CY23EP05
2.5 V or 3.3 V,10–220 MHz, Low Jitter,
5 Output Zero Delay Buffer
2.5 V or 3.3 V,10–220 MHz, Low Jitter, 5 Output Zero Delay Buffer
Features
Functional Description
■
10 MHz to 220 MHz maximum operating range
■
Zero input-output propagation delay, adjustable by loading on
CLKOUT pin
■
Multiple low-skew outputs
❐ 30 ps typical output-output skew
❐ One input drives five outputs
The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to
distribute low-jitter high-speed clocks and is available in a 8-pin
SOIC package. It accepts one reference input, and drives out five
low-skew clocks. The –1H version operates up to 220 (200) MHz
frequencies at 3.3 V (2.5 V), and has a higher drive strength than
the –1 devices. All parts have on-chip PLLs which lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
■
22 ps typical cycle-to-cycle jitter
■
13 ps typical period jitter
■
Standard and high drive strength options
■
Available in space-saving 150-mil SOIC package
■
3.3 V or 2.5 V operation
■
Industrial temperature available
The CY23EP05 PLL enters a power-down mode when there are
no rising edges on the REF input (< ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 A of current draw.
The CY23EP05 is available in different configurations, as shown
in the Ordering Information table. The CY23EP05-1 is the base
part. The CY23EP05-1H is the high-drive version of the –1, and
its rise and fall times are much faster than the –1.
These parts are not intended for 5 V input-tolerant applications.
For a complete list of related documentation, click here.
Logic Block Diagram
CLKOUT
PLL
REF
CLK1
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation
Document Number: 38-07759 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 5, 2016
CY23EP05
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 3
Zero Delay and Skew Control.......................................... 3
Absolute Maximum Conditions....................................... 4
Operating Conditions....................................................... 4
Electrical Specifications (3.3 V DC) ................................ 4
Electrical Specifications (2.5 V DC) ................................ 5
Thermal Resistance.......................................................... 5
Electrical Specifications (3.3 V and 2.5 V AC) ............... 6
Switching Waveforms ...................................................... 8
Test Circuits...................................................................... 9
Supplemental Parametric Information.......................... 10
Ordering Information...................................................... 14
Ordering Code Definitions ......................................... 14
Document Number: 38-07759 Rev. *F
Package Drawing and Dimensions ...............................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC®Solutions .......................................................
Cypress Developer Community.................................
Technical Support .....................................................
15
16
16
16
17
18
18
18
18
18
18
Page 2 of 18
CY23EP05
Pin Configuration
Figure 1. 8-pin SOIC pinout (Top View)
Top View
REF
CLK2
CLK1
GND
1
8
2
7
3
6
4
5
CLKOUT
CLK4
VDD
CLK3
Pin Description
Pin No.
Signal
1
REF [1]
Input reference frequency
Description
2
CLK2 [2]
Buffered clock output
3
CLK1 [2]
Buffered clock output
4
GND
5
CLK3 [2]
Ground
Buffered clock output
6
VDD
3.3 V or 2.5 V supply
7
CLK4 [2]
Buffered clock output
8
CLKOUT [2, 3]
Buffered clock output, internal feedback on this pin
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve zero delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load of
5 pF (internal load) plus any additional load externally connected
to this pin. For applications requiring zero input-output delay, the
total load on each output pin (including CLKOUT) must be the
same. For example, if there is no external load on the CLKOUT
pin, add 5 pF to each of the remaining outputs to match the
internal load on the CLKOUT pin. If input-output delay adjustments are required, the CLKOUT load may be changed to vary
the delay between the REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information refer to the application note titled
“AN1234 - Understanding Cypress’s Zero Delay Buffers”.
Notes
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document Number: 38-07759 Rev. *F
Page 3 of 18
CY23EP05
Absolute Maximum Conditions
DC input voltage ......................................VSS – 0.5 V to 4.6 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage to ground potential ................–0.5 V to 4.6 V
Storage temperature .................................. –65 °C to 150 °C
Junction temperature ................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015 ............................ > 2000 V
Operating Conditions
Min
Typ
Max
Unit
VDD3.3
Parameter
3.3 V supply voltage
Description
3.0
3.3
3.6
V
VDD2.5
2.5 V supply voltage
2.3
2.5
2.7
V
TA
Operating temperature (ambient temperature) – Commercial
0
–
70
°C
Operating temperature (ambient temperature) – Industrial
CL[4]
–40
–
85
°C
Load capacitance, < 100 MHz, 3.3 V
–
–
30
pF
Load capacitance, < 100 MHz, 2.5 V with high drive
–
–
30
pF
Load capacitance, < 133.3 MHz, 3.3 V
–
–
22
pF
Load capacitance, < 133.3 MHz, 2.5 V with high drive
–
–
22
pF
Load capacitance, < 133.3 MHz, 2.5 V with standard drive
–
–
15
pF
Load capacitance, > 133.3 MHz, 3.3 V
–
–
15
pF
Load capacitance, > 133.3 MHz, 2.5 V with high drive
–
–
15
pF
[5]
CIN
Input capacitance
–
–
5
pF
BW
Closed-loop bandwidth, 3.3 V
–
1–1.5
–
MHz
Closed-loop bandwidth, 2.5 V
–
0.8
–
MHz
Output impedance, 3.3 V high drive
–
29
–
ROUT
tPU
Output impedance, 3.3 V standard drive
–
41
–
Output impedance, 2.5 V high drive
–
37
–
Output Impedance, 2.5 V standard drive
–
41
–
0.01
–
50
ms
Min
Typ
Max
Unit
3.0
3.3
3.6
V
Power-up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
Electrical Specifications (3.3 V DC)
Parameter
Description
Test Conditions
VDD
Supply voltage
VIL
Input LOW voltage
–
–
0.8
V
VIH
Input HIGH voltage
2.0
–
VDD + 0.3
V
IIL
Input leakage current
0 < VIN < VIL
–10
–
10
A
IIH
Input HIGH current
VIN = VDD
–
–
100
A
VOL
Output LOW voltage
IOL = 8 mA (Standard Drive)
–
–
0.4
V
IOL = 12 mA (High Drive)
–
–
0.4
V
Notes
4. Applies to Test Circuit #1.
5. Applies to both REF Clock and internal feedback path on CLKOUT.
Document Number: 38-07759 Rev. *F
Page 4 of 18
CY23EP05
Electrical Specifications (3.3 V DC) (continued)
Parameter
VOH
Description
Output HIGH voltage
IDD (PD mode) Power down supply current
IDD
Supply current
Test Conditions
Min
Typ
Max
Unit
IOH = –8 mA (Standard Drive)
2.4
–
–
V
IOH = –12 mA (High Drive)
2.4
–
–
V
REF = 0 MHz (Commercial)
–
–
12
A
REF = 0 MHz (Industrial)
–
–
25
A
Unloaded outputs, 66-MHz REF
–
–
30
mA
Min
Typ
Max
Unit
2.3
2.5
2.7
V
Electrical Specifications (2.5 V DC)
Parameter
Description
Test Conditions
VDD
Supply voltage
VIL
Input LOW voltage
–
–
0.7
V
VIH
Input HIGH voltage
1.7
–
VDD + 0.3
V
IIL
Input leakage current
0 < VIN < VDD
–10
–
10
A
IIH
Input HIGH current
VIN = VDD
–
–
100
A
VOL
Output LOW voltage
IOL = 8 mA (standard drive)
–
–
0.5
V
IOL = 12 mA (high drive)
–
–
0.5
V
IOH = –8 mA (standard drive)
VDD – 0.6
–
–
V
IOH = –12 mA (high drive)
VDD – 0.6
–
–
V
REF = 0 MHz (commercial)
–
–
12
A
REF = 0 MHz (industrial)
–
–
25
A
Unloaded outputs, 66-MHz REF
–
–
45
mA
VOH
Output HIGH voltage
IDD (PD mode) Power Down supply current
IDD
Supply current
Thermal Resistance
Parameter[6]
Description
Theta JA
Thermal resistance
(junction to ambient)
Theta JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
8-pin SOIC
Unit
145
°C/W
62
°C/W
Note
6. These parameters are guaranteed by design and are not tested.
Document Number: 38-07759 Rev. *F
Page 5 of 18
CY23EP05
Electrical Specifications (3.3 V and 2.5 V AC)
Parameter
1/t1
TIDC
Description
Maximum frequency [7]
(input/output)
Input duty cycle
t2 t1
Output duty cycle
t3,t4
Rise, fall time (3.3 V) [8]
t3, t4
[8]
Rise, fall time (2.5
V)[8]
[8]
t5
Output to output skew
t6
Delay, REF rising edge to
CLKOUT rising edge [8]
t7
Part to part skew
[8]
Min
Typ
Max
Unit
3.3 V high drive
Test Conditions
10
–
220
MHz
3.3 V standard drive
10
–
167
MHz
2.5 V high drive
10
–
200
MHz
2.5 V standard drive
10
–
133
MHz
< 133.3 MHz
25
–
75
%
> 133.3 MHz
40
–
60
%
< 133.3 MHz
47
–
53
%
> 133.3 MHz
45
–
55
%
Std drive, CL = 30 pF, < 100 MHz
–
–
1.6
ns
Std drive, CL = 22 pF, < 133.3 MHz
–
–
1.6
ns
Std drive, CL = 15 pF, < 167 MHz
–
–
0.6
ns
High drive, CL = 30 pF, < 100 MHz
–
–
1.2
ns
High drive, CL = 22 pF, < 133.3 MHz
–
–
1.2
ns
High drive, CL = 15 pF, > 133.3 MHz
–
–
0.5
ns
Std drive, CL = 15 pF, < 133.33 MHz
–
–
1.5
ns
High drive, CL = 30 pF, < 100 MHz
–
–
2.1
ns
High drive, CL = 22 pF, < 133.3 MHz
–
–
1.3
ns
High drive, CL = 15 pF, > 133.3 MHz
–
–
1.2
ns
All outputs equally loaded
–
30
100
ps
PLL enabled at 3.3 V
–100
–
100
ps
PLL enabled at 2.5 V
–200
–
200
ps
Measured at VDD/2.
Any output to any output, 3.3 V
supply
–150
–
150
ps
Measured at VDD/2.
Any output to any output, 2.5 V
supply
–300
–
300
ps
Notes
7. For the given maximum loading conditions. See CL in Operating Conditions Table.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07759 Rev. *F
Page 6 of 18
CY23EP05
Electrical Specifications (3.3 V and 2.5 V AC) (continued)
Parameter
Description
[9]
tLOCK
PLL lock time
TJCC [9, 10]
Cycle-to-cycle jitter, peak
TPER [9, 10]
Period jitter, peak
Test Conditions
Min
Typ
Max
Unit
Stable power supply, valid clocks
presented on REF and CLKOUT
pins
–
–
1.0
ms
3.3 V supply, > 66 MHz, < 15 pF
–
22
55
ps
3.3 V supply, > 66 MHz, < 30 pF,
standard drive
–
45
125
ps
3.3 V supply, > 66 MHz, < 30 pF,
high drive
–
45
100
ps
2.5 V supply, > 66 MHz, < 15 pF,
standard drive
–
40
100
ps
2.5 V supply, > 66 MHz, < 15 pF,
high drive
–
35
80
ps
2.5 V supply, > 66 MHz, < 30 pF,
high drive
–
52
125
ps
3.3 V supply, 66–100 MHz, < 15 pF
–
18
60
ps
3.3 V supply, > 100 MHz, < 15 pF
–
13
35
ps
3.3 V supply, > 66 MHz, < 30 pF,
standard drive
–
28
75
ps
3.3 V supply, > 66 MHz, < 30 pF,
high drive
–
26
70
ps
2.5 V supply, > 66 MHz, < 15 pF,
standard drive
–
25
60
ps
2.5 V supply, 66–100 MHz, < 15 pF,
high drive
–
22
60
ps
2.5 V supply, > 100 MHz, < 15 pF,
high drive
–
19
45
ps
Notes
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
10. Typical jitter is measured at 3.3 V or 2.5 V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application notes, “Understanding Data Sheet Jitter Specifications for Cypress Products.”
Document Number: 38-07759 Rev. *F
Page 7 of 18
CY23EP05
Switching Waveforms
Figure 2. Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
Figure 3. All Outputs Rise/Fall Time
2.0 V(1.8 V)
0.8 V(0.6 V)
OUTPUT 2.0 V(1.8 V)
0.8 V(0.6 V)
3.3 V(2.5 V)
0V
t4
t3
Figure 4. Output-Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
t5
Figure 5. Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
CLKOUT
t6
Figure 6. Part-Part Skew
VDD/2
Any output, Part 1 or 2
VDD/2
Any output, Part 1 or 2
t7
Document Number: 38-07759 Rev. *F
Page 8 of 18
CY23EP05
Test Circuits
Figure 7. Test Circuit
Test Circuit # 1
V DD
CLK
0.1 F
OUTPUTS
C LOAD
V DD
0.1 F
Document Number: 38-07759 Rev. *F
GND
GND
Page 9 of 18
CY23EP05
Supplemental Parametric Information
Delay REF Input to CLKn (ps)
Figure 8. 2.5 V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading Difference between CLKOUT
and CLKn
1500
1250
1000
750
500
250
0
-250
-500
-750
-1000
-1250
-1500
2.5V Standard Drive
2.5V High Drive
-20
-10
0
10
20
Load CLKOUT- Load CLKn (pF)
Data is shown for 66 MHz. Delay is a weak function of frequency.
Figure 9. 3.3 V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading Difference between CLKOUT
and CLKn
Delay REF Input to CLKn (ps)
1000
3.3V Standard Drive
3.3V High Drive
800
600
400
200
0
-200
-400
-600
-800
-1000
-20
-10
0
10
20
Load CLKOUT- Load CLKn (pF)
Data is shown for 66 MHz. Delay is a weak function of frequency.
Document Number: 38-07759 Rev. *F
Page 10 of 18
CY23EP05
Supplemental Parametric Information (continued)
Figure 10. 2.7 V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature
70
60
50
40
30
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
20
15pF, -45C, High Drive
15pF, 90C, High Drive
10
30pF, -45C, High Drive
30pF, 90C, High Drive
0
33
66
100
133
166
200
Frequency (MHz)
Note that the 30 pF data above 100 MHz is beyond the data sheet specification of 22 pF.
Figure 11. 3.6 V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature
100
80
60
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
30pF, -45C, Standard Drive
30pF, 90C, Standard Drive
15pF, -45C, High Drive
15pF, 90C, High Drive
30pF, -45C, High Drive
30pF, 90C, High Drive
40
20
0
33
66
100
133
166
200
233
Frequency (MHz)
Note that the 30-pF high-drive data above 100 MHz is beyond the data sheet specification of 22 pF.
Document Number: 38-07759 Rev. *F
Page 11 of 18
CY23EP05
Supplemental Parametric Information (continued)
Figure 12. Typical 3.3 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
350
15 pF, Standard Drive
15 pF, High Drive
30 pF, Standard Drive
30 pF, High Drive
300
250
200
150
100
50
0
0
50
100
150
200
250
Frequency (MHz)
Figure 13. Typical 2.5 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
400
15 pF, Standard Drive
15 pF, High Drive
30 pF, High Drive
350
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
Figure 14. Typical 3.3 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
250
15 pF, Standard Drive
15 pF, High Drive
30 pF, Standard Drive
30 pF, High Drive
200
150
100
50
0
0
50
100
150
250
200
Frequency (MHz)
Figure 15. Typical 2.5 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
250
15 pF, Standard Drive
15 pF, High Drive
30 pF, High Drive
200
150
100
50
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
Document Number: 38-07759 Rev. *F
Page 12 of 18
CY23EP05
Supplemental Parametric Information (continued)
Figure 16. 100 MHz (top) and 156.25 MHz (bottom) Typical Phase-noise Data versus VDD and Drive Strength [11]
-90
SSB Phase Noise (dBc/Hz)
-100
3.3V High Drive
3.3V Standard Drive
-110
-120
2.5V High Drive
2.5V Standard Drive
-130
100 MHz
-140
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Offset Frequency (Hz)
-90
SSB Phase Noise (dBc/Hz)
-100
3.3V High Drive
3.3V Standard Drive
-110
-120
2.5V High Drive
-130
2.5V Standard Drive
156.25 MHz
-140
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Offset Frequency (Hz)
Note
11. Typical jitter is measured at 3.3 V or 2.5 V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application notes, “Understanding Data Sheet Jitter Specifications for Cypress Products.”
Document Number: 38-07759 Rev. *F
Page 13 of 18
CY23EP05
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY23EP05SXC-1
8-pin SOIC
Commercial
CY23EP05SXC-1T
8-pin SOIC – Tape and Reel
Commercial
CY23EP05SXI-1
8-pin SOIC
Industrial
CY23EP05SXI-1T
8-pin SOIC – Tape and Reel
Industrial
CY23EP05SXC-1H
8-pin SOIC
Commercial
CY23EP05SXC-1HT
8-pin SOIC – Tape and Reel
Commercial
CY23EP05SXI-1H
8-pin SOIC
Industrial
CY23EP05SXI-1HT
8-pin SOIC – Tape and Reel
Industrial
Ordering Code Definitions
CY 23EP05 S
X
X - XX X
X = blank or T
blank = Tube; T = Tape and Reel
Output Drive: XX = 1 or 1 H
1 = Standard Drive; 1H = High Drive
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
S = 8-pin SOIC
Base part number (Enhanced performance 5 output zero delay buffer)
Company ID: CY = Cypress
Document Number: 38-07759 Rev. *F
Page 14 of 18
CY23EP05
Package Drawing and Dimensions
Figure 17. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07759 Rev. *F
Page 15 of 18
CY23EP05
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
AC
Alternating Current
DC
Direct Current
dBc
decibels relative to carrier
PCI
Peripheral Component Interconnect
C
degree Celsius
PLL
Phase-Locked Loop
Hz
hertz
SDRAM
Synchronous Dynamic Random Access Memory
MHz
megahertz
SOIC
Small-Outline Integrated Circuit
A
microampere
mA
milliampere
W
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07759 Rev. *F
Symbol
Unit of Measure
Page 16 of 18
CY23EP05
Document History Page
Document Title: CY23EP05, 2.5 V or 3.3 V,10–220 MHz, Low Jitter, 5 Output Zero Delay Buffer
Document Number: 38-07759
Revision
ECN
Orig. of
Change
Submission
Date
**
349620
RGL
See ECN
New data sheet
*A
401073
RGL
See ECN
Updated Delay vs. Load graph with standard drive data
Added Phase-noise graph
Description of Change
*B
413826
RGL
See ECN
Minor Change: typo – changed from CY23EP05SXC-T to CY23EP05SXC-1T
*C
3273677
CXQ
06/07/2011
1) Added typical column to the Operating Conditions table.
Included 3.3 V and 2.5 V typical specs for the two VDD rows.
2) All BW, ROUT, and Theta JA specs are moved to typical column with only
dashes left in the Min and Max columns. Removed the “(typical)” note from the
description cells for these specs.
3) All other specs just have a dash for the new typical column cells.
4) Changed Iil spec in Electrical Specifications (3.3 V DC) and Electrical Specifications (2.5 V DC) tables from +/– 10 µA max to –10 µA min and 10 µA max.
5) Added typical column to the DC Electrical Specifications tables. Typical
column is all kept dashes except for the first row VDD (3.3 V or 2.5 V
respectively).
6) Changed t7 spec from +/– 150 ps max to –150 ps min and 150 ps max (same
for the 300 ps spec).
7) Updated package drawing to latest revision.
8) Added Ordering Code Definitions, Acronyms, Units sections.
*D
4402737
AJU
06/09/2014
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *D to *F.
Updated in new template.
Completing Sunset Review.
*E
4578443
AJU
11/25/2014
Added related documentation hyperlink in page 1.
*F
5260402
PSR
05/05/2016
Updated Zero Delay and Skew Control section.
Added Thermal Resistance.
Updated the Cypress logo, copyright information, Sales, Solutions, and Legal
Information based on the new template.
Document Number: 38-07759 Rev. *F
Page 17 of 18
CY23EP05
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
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Interface
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© Cypress Semiconductor Corporation, 2005-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners
Document Number: 38-07759 Rev. *F
Revised May 5, 2016
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