CY23S08
3.3 V Zero Delay Buffer
3.3 V Zero Delay Buffer
Features
input-to-output propagation delay is less than 350 ps and
output-to-output skew is less than 250 ps.
■
Zero input output propagation delay, adjustable by capacitive
load on FBK input
■
Multiple configurations (see Available CY23S08
Configurations on page 4)
■
Multiple low-skew outputs
❐ 45-ps typical output-output skew (-1)
❐ Two banks of four outputs that can be tristated by two select
inputs
■
10 MHz to 140 MHz operating range
■
65-ps typical cycle-to-cycle jitter (-1, -1H)
■
Advanced 0.65-m complementary metal oxide semiconductor
(CMOS) technology
■
Space-saving 16-pin small outline integrated circuit (SOIC)
package
■
3.3-V operation
■
Spread Aware
The CY23S08 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in Select Input
Decoding on page 4. If all output clocks are not required, Bank
B can be tristated. The select inputs also enable the input clock
to be directly applied to the output for chip and system testing
purposes.
The CY23S08 PLL enters a power-down state when there are no
rising edges on the REF input. In this mode, all outputs are
tristated and the PLL is turned off, resulting in less than 50 A of
current draw. The PLL shuts down in two additional cases as
shown in Select Input Decoding on page 4.
Multiple CY23S08 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY23S08 is available in five different configurations, as
shown in Available CY23S08 Configurations on page 4. The
CY23S08-1 is the base part, where the output frequencies equal
the reference if there is no counter in the feedback path. The
CY23S08-1H is the high-drive version of the -1, and rise and fall
times on this device are much faster.
Functional Description
The CY23S08 is a 3.3-V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
The CY23S08-2 enables you to obtain 2X and 1X frequencies on
each output bank. The exact configuration and output
frequencies depends on which output drives the feedback pin.
The CY23S08-2H is the high drive version of the -2, and rise and
fall times on this device are much faster.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback must be driven into
the FBK pin, and obtained from one of the outputs. The
The CY23S08-4 enables you to obtain 2X clocks on all outputs.
Therefore, the part is versatile, and can be used in a variety of
applications.
For a complete list of related documentation, click here.
Logic Block Diagram
/2
PLL
FBK
MUX
REF
CLKA1
CLKA2
Extra Divider (–4)
CLKA3
S2
S1
CLKA4
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –2H)
Cypress Semiconductor Corporation
Document Number: 38-07265 Rev. *Q
•
198 Champion Court
CLKB4
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 17, 2016
CY23S08
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Select Input Decoding ................................................. 4
Available CY23S08 Configurations ............................. 4
Spread Aware .............................................................. 4
Maximum Ratings ............................................................. 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 8
Test Circuits ...................................................................... 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Document Number: 38-07265 Rev. *Q
Package Drawings and Dimensions ............................. 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC® Solutions ...................................................... 14
Cypress Developer Community ................................. 14
Technical Support ..................................................... 14
Page 2 of 14
CY23S08
Pinouts
Figure 1. 16-pin SOIC pinout (Top View)
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
14
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Pin Definitions
Pin
1
2
3
Signal
REF
[1]
CLKA1
[2]
CLKA2
[2]
Description
Input reference frequency, 5-V tolerant input
Clock output, Bank A
Clock output, Bank A
4
VDD
3.3-V supply
5
GND
Ground
6
CLKB1 [2]
Clock output, Bank B
7
CLKB2 [2]
Clock output, Bank B
[3]
8
S2
9
S1 [3]
Select input, bit 2
Select input, bit 1
10
CLKB3
[2]
Clock output, Bank B
11
CLKB4 [2]
Clock output, Bank B
12
GND
13
VDD
Ground
3.3-V supply
14
CLKA3
[2]
Clock output, Bank A
15
CLKA4 [2]
Clock output, Bank A
16
FBK
PLL feedback input
Notes
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Document Number: 38-07265 Rev. *Q
Page 3 of 14
CY23S08
Functional Overview
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Tristate
Tristate
PLL
Y
0
1
Driven
Tristate
PLL
N
1
0
Driven
Driven
Reference
Y
1
1
Driven
Driven
PLL
N
Available CY23S08 Configurations
Device
CY23S08-1
Feedback From
Bank A or Bank B
Bank A Frequency
Reference
Bank B Frequency
Reference
CY23S08-1H
Bank A or Bank B
Reference
Reference
CY23S08-2
Bank A
Reference
Reference/2
CY23S08-2H
Bank A
Reference
Reference/2
CY23S08-2
Bank B
2 X Reference
Reference
CY23S08-2H
Bank B
2 X Reference
Reference
CY23S08-4
Bank A or Bank B
2 X Reference
2 X Reference
Spread Aware
Many systems designed now use the Spread Spectrum frequency timing generation (SSFTG) technology. Cypress is one of the
pioneers of SSFTG development, and designed this product so as not to filter off the Spread Spectrum feature of the Reference input,
assuming it exists. When a zero delay buffer does not pass through the SS feature, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, see Cypress’s application note EMI Suppression Techniques with Spread
Spectrum Frequency Timing Generator (SSFTG) ICs.
Note
4. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08-2.
Document Number: 38-07265 Rev. *Q
Page 4 of 14
CY23S08
Maximum Ratings
Storage temperature ................................ –65 °C to +150 °C
Supply voltage to ground potential ..............–0.5 V to +7.0 V
DC input voltage (except Ref) ............ –0.5 V to VDD + 0.5 V
DC input voltage REF .......................................... –0.5 to 7 V
Max soldering temperature (10 sec.) ........................ 260 °C
Junction temperature ................................................ 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015) ........................... >2000 V
Operating Conditions
Parameter [5]
Description
VDD
Supply voltage
TA
Ambient operating temperature, Commercial
Ambient operating temperature, Industrial
CL
CIN
Min
Max
Unit
3.0
3.6
V
0
70
°C
–40
85
°C
Load capacitance, below 100 MHz
–
30
pF
Load capacitance, from 100 MHz to 140 MHz
–
15
pF
–
7
pF
Min
Max
Unit
–
0.8
V
Input capacitance
[6]
Electrical Characteristics
For CY23S08SXC-xx Commercial Temperature Devices
Parameter
Description
VIL
Input Low voltage
VIH
Input High voltage
IIL
Input Low current
IIH
Input High current
VOL
Output Low
VOH
Output High voltage[7]
voltage[7]
Test Conditions
2.0
–
V
VIN = 0 V
–
50.0
A
VIN = VDD
–
100.0
A
IOL = 8 mA (-1, -2, -4)
IOL = 12 mA (-1H, -2H)
–
0.4
V
2.4
–
V
IOH = –8 mA (-1, -2, -4)
IOH = –12 mA (-1H, -2H)
IDD (PD mode) Power-down supply current
REF = 0 MHz
–
12.0
A
IDD
Unloaded outputs, 100-MHz REF;
Select inputs at VDD or GND
–
45.0
mA
–
70.0
(-1H, -2H)
mA
Unloaded outputs, 66 MHz REF (-1, -2, -4)
–
32.0
mA
Unloaded outputs, 33 MHz REF (-1, -2, -4)
–
18.0
mA
Supply current
Thermal Resistance
Parameter [8]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
16-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
108
°C/W
37
°C/W
Notes
5. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. These parameters are guaranteed by design and are not tested.
Document Number: 38-07265 Rev. *Q
Page 5 of 14
CY23S08
Switching Characteristics
For CY23S08SXC-xx Commercial Temperature Devices
Parameter [9]
t1
t1
t1
t1
t1
Description
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Duty cycle[10] = t2 t1
(-1, -2, -4, -1H, -2H)
Test Conditions
30 pF load, –1, –1H, –2 devices
30 pF load, –4 devices
20 pF load, –1H device
15 pF load, –1, –2 devices
15 pF load, –4 devices
Measured at VDD/2,
FOUT = 66.66 MHz, 30-pF load
Min
10
15
10
10
15
40.0
Typ
–
–
–
–
–
50.0
Max
100
100
133.3
140.0
140.0
60.0
Unit
MHz
MHz
MHz
MHz
MHz
%
Duty Cycle[10] = t2 t1
(-1, -2, -4, -1H, -2H)
Measured at VDD/2,
FOUT < 66.66 MHz, 15 pF load
45.0
50.0
55.0
%
t3
Rise Time[10] (-1, -2, -4)
–
–
2.20
ns
t3
Rise Time[10] (-1, -2, -4)
–
–
1.50
ns
t3
Rise Time[10] (-1H, -2H)
–
–
1.50
ns
t4
Fall Time[10] (-1, -2, -4)
–
–
2.20
ns
t4
Fall Time[10] (-1, -2, -4)
–
–
1.50
ns
t4
Fall Time[10] (-1H, 2H)
–
–
1.25
ns
t5
Output-to-output skew on same
Bank (-1) [10]
Output-to-output skew on same
Bank (-1H, -2, -2H) [10]
Output-to-output skew on same
Bank (-4) [10]
Output-to-output skew (-1H, -2H)
Output Bank A to output Bank B
Skew (-1, -2)
Output Bank A to output Bank B
Skew (-4)
Output Bank A to output Bank B
Skew (-1H)
Measured between 0.8 V and 2.0 V,
30 pF load
Measured between 0.8 V and 2.0 V,
15 pF load
Measured between 0.8 V and 2.0 V,
30 pF load
Measured between 0.8 V and 2.0 V,
30 pF load
Measured between 0.8 V and 2.0 V,
15 pF load
Measured between 0.8 V and 2.0 V,
30 pF load
All outputs equally loaded
–
45
200
ps
All outputs equally loaded
–
105
150
ps
All outputs equally loaded
–
70
100
ps
All outputs equally loaded
All outputs equally loaded
–
–
–
–
200
300
ps
ps
All outputs equally loaded
–
–
215
ps
All outputs equally loaded
–
–
250
ps
Notes
9. All parameters are specified with loaded outputs.
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07265 Rev. *Q
Page 6 of 14
CY23S08
Switching Characteristics (continued)
For CY23S08SXC-xx Commercial Temperature Devices
Parameter [9]
Description
Test Conditions
t6
Delay, REF rising edge to FBK
rising edge [11]
Measured at VDD/2
t7
Device-to-device skew[11]
t8
Output slew rate [11]
tJ
Cycle-to-cycle jitter [11] (-1, -1H)
Measured at VDD/2 on the FBK pins
of devices
Measured between 0.8 V and 2.0 V
on -1H, -2H device using Test Circuit
#2
Measured at 66.67 MHz, loaded
outputs, 15, 30 pF loads; 133 MHz,
15 pF load
Measured at 66.67 MHz, loaded
outputs, 15 pF load
Measured at 66.67 MHz, loaded
outputs, 30 pF load
Measured at 66.67 MHz, loaded
outputs, 15, 30 pF loads
Stable power supply, valid clocks
presented on REF and FBK pins
Cycle-to-cycle jitter [11] (-2)
Cycle-to-cycle jitter [11] (-2)
tJ
Cycle-to-cycle jitter [11] (-4)
tLOCK
PLL lock time [11]
Min
Typ
Max
Unit
–250
–
275
ps
–
–
700
ps
1
–
–
V/ns
–
65
125
ps
–
85
300
ps
–
–
400
ps
–
–
200
ps
–
–
1.0
ms
Note
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07265 Rev. *Q
Page 7 of 14
CY23S08
Switching Waveforms
Figure 2. Duty Cycle Timing
t1
t2
1.4 V
1.4 V
1.4 V
Figure 3. All Outputs Rise and Fall Time
OUTPUT
2.0 V
0.8 V
2.0 V
0.8 V
3.3 V
0V
t4
t3
Figure 4. Output-Output Skew
OUTPUT
1.4 V
1.4 V
OUTPUT
t5
Figure 5. Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
FBK
t6
Figure 6. Device-Device Skew
VDD/2
FBK, Device 1
VDD/2
FBK, Device 2
t7
Document Number: 38-07265 Rev. *Q
Page 8 of 14
CY23S08
Test Circuits
Figure 7. Test Circuit 1
VDD
0.1 F
CLK OUT
OUTPUTS
C LOAD
V DD
0.1 F
GND
GND
Test Circuit for all parameters except t8
Figure 8. Test Circuit 2
Test Circuit # 2
V DD
0.1 F
1 K
OUTPUTS
1 K
CLK out
10 pF
V DD
0.1 F
GND
GND
Test Circuit for t8, Output slew rate on –1H device
Document Number: 38-07265 Rev. *Q
Page 9 of 14
CY23S08
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY23S08SXI-1H
16-pin SOIC (150 Mils)
Industrial (–40 °C to 85 °C)
CY23S08SXI-1HT
16-pin SOIC (150 Mils) – Tape and reel
Industrial (–40 °C to 85 °C)
Ordering Code Definitions
CY
23S
08
S
X
I
-
1
H
X
X = blank or T
blank = Tube; T = Tape and Reel
High Output Drive Strength
Configuration Type
Temperature Grade:
I = Industrial
Pb-free
Package Type:
S = 16-pin SOIC
Number of Outputs
Base Part Number for Spread Aware Zero Delay Buffers
Company ID: CY = Cypress
Document Number: 38-07265 Rev. *Q
Page 10 of 14
CY23S08
Package Drawings and Dimensions
Figure 9. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Document Number: 38-07265 Rev. *Q
Page 11 of 14
CY23S08
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
OE
Output Enable
°C
degree Celsius
PLL
Phase-Locked Loop
k
kilohm
RMS
Root Mean Square
MHz
megahertz
SOIC
Small Outline Integrated Circuit
µA
microampere
SSFTG
Spread Spectrum Frequency Timing Generation
µF
microfarad
TSSOP
Thin Shrunk Small Outline Package
µs
microsecond
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07265 Rev. *Q
Symbol
Unit of Measure
Page 12 of 14
CY23S08
Document History Page
Document Title: CY23S08, 3.3 V Zero Delay Buffer
Document Number: 38-07265
Revision
ECN
Orig. of
Change
Submission
Date
**
110530
SZV
12/02/01
*A
122863
RBI
12/20/02
Added power up requirements to operating conditions information.
*B
130951
RGL
11/26/03
Corrected the Switching Characteristics parameters to reflect the W152 device
and new characterization.
*C
204201
RGL
See ECN
Corrected the Block Diagram
*D
231100
RGL
See ECN
Fixed Typo in table 2.
*E
378878
RGL
See ECN
Removed “Preliminary”
Added Industrial Temp and Pb Free Devices
Added typical char data
*F
391564
RGL
See ECN
Changed output-to-output skew typical value from 90ps to 45ps
Added cycle-to-cycle jitter (-2) typical value of 85ps
*G
1442823
WWZ /
AESA
See ECN
Updated ordering info with status update. Added new Pb-free part numbers.
*H
2600345
WWZ /
PYRS
11/03/08
Updated max frequency number from 133 MHz to 140 MHz on page 1 and
page 4 load capacitance description
*I
2658081
KVM /
PYRS
02/16/09
Removed references to SOIC in the pinout drawing and pin description table
on page 2.
Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering
Information Table.
Added CY23S08ZXC-1HT to the Ordering Information Table.
Updated Ordering Information Table to remove obsolete devices.
Removed Status column.
*J
2761988
KVM
09/10/09
Added industrial temperature range to Operating Conditions table.
Added numerical values to Operating Range column of Ordering Information
table.
Removed references to –3 device.
*K
2904767
CXQ
04/05/10
Removed the following parts from Ordering Information: CY23S08SXC-2,
CY23S08SXC-2T, CY23S08SXI-4, CY23S08SXI-4T.
Updated Package Diagrams.
*L
3011498
CXQ
08/19/2010
Updated package spec 51-85091.
Added Ordering code definition,
Added Acronyms and Units of Measure.
Completing Sunset Review.
*M
3056348
CXQ
10/12/2010
Removed pruned parts from Ordering Information.
Removed 16-pin TSSOP package diagram.
*N
3211161
CXQ
03/30/2011
Removed following pruned parts form Ordering information table.
CY23S08SXC-1
CY23S08SXC-1T
*O
4201668
CINM
11/25/2013
Updated Package Drawings and Dimensions:
spec 51-85068 – Changed revision from *C to *E.
Updated to new template.
*P
4580603
TAVA
11/26/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*Q
5274556
PSR
05/17/2016
Added Thermal Resistance.
Updated to new template.
Document Number: 38-07265 Rev. *Q
Description of Change
Change from Spec number: 38-01107 to 38-07265
Page 13 of 14
CY23S08
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-07265 Rev. *Q
Revised May 17, 2016
Page 14 of 14