NUP4012PXV6 Quad Transient Voltage Suppressor Array ESD Protection Diodes with Ultra−Low (0.7 pF) Capacitance http://onsemi.com The four−line voltage transient suppressor array is designed to protect voltage−sensitive components that require ultra−low capacitance from ESD and transient voltage events. This device features a common anode design which protects four independent data lines in a single SOT−563 low profile package. Excellent clamping capability, low capacitance, low leakage, and fast response time make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs. 1 6 2 5 3 4 Features • • • • • • • Low Capacitance (0.7 pF Typical) Protects up to Four Data Lines SOT−563 1.6 mm x 1.6 mm Low Profile of 0.55 mm for Slim Design Ultra D1, D2, D3, and D4 Pins = 5.2 V Minimum Protection ESD Rating: IEC61000−4−2: Level 4 This is a Pb−Free Device SOT−563 CASE 463A MARKING DIAGRAM P7 M G G Typical Applications • • • • USB 2.0 High−Speed Interface Cell Phones MP3 Players SIM Card Protection P7 M G = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) MAXIMUM RATINGS (TJ = 25°C, unless otherwise specified) Symbol Value Unit TJ Operating Junction Temperature Range Rating −40 to 125 °C TSTG Storage Temperature Range −55 to 150 °C Device TL Lead Solder Temperature – Maximum (10 seconds) 260 °C NUP4012PXV6T1G ESD IEC 61000−4−2 Contact 8000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION Package Shipping† SOT−563 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2009 August, 2009− Rev. 1 1 Publication Order Number: NUP4012PXV6/D NUP4012PXV6 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IF Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM VC VBR VRWM Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C I Parameter IPP Uni−Directional TVS Max. Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified) Parameter Conditions Reverse Working Voltage (D1, D2, D3, and D4) (Note 1) Breakdown Voltage (D1, D2, D3, and D4) IT = 1 mA, (Note 2) Reverse Leakage Current (D1, D2, D3, and D4) Symbol Min Typ Max Unit VRWM − − 4.0 V VBR 5.2 5.5 − V @ VRWM IR − − 1.0 mA Capacitance (D1, D2, D3, and D4) VR = 0 V, f = 1 MHz (Line to GND) CJ − 0.7 0.9 pF Clamping Voltage @ IPP = 1 A (Note 3) VC − − 9.5 V Clamping Voltage Per IEC61000−4−2 (Note 4) VC Figures 1 and 2 V 1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 2. VBR is measured at pulse test current IT. 3. Surge current waveform per Figure 5. 4. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 NUP4012PXV6 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 3 80 NUP4012PXV6 PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A−01 ISSUE F D −X− 5 6 1 e 2 A 4 E −Y− 3 b L DIM A b C D E e L HE HE C 5 PL 6 0.08 (0.003) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. M X Y MILLIMETERS MIN NOM MAX 0.50 0.55 0.60 0.17 0.22 0.27 0.08 0.12 0.18 1.50 1.60 1.70 1.10 1.20 1.30 0.5 BSC 0.10 0.20 0.30 1.50 1.60 1.70 INCHES NOM MAX 0.021 0.023 0.009 0.011 0.005 0.007 0.062 0.066 0.047 0.051 0.02 BSC 0.004 0.008 0.012 0.059 0.062 0.066 MIN 0.020 0.007 0.003 0.059 0.043 SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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