FAN4800A/C, FAN4801/1S/2/2L PFC/PWM Controller Combination Features Description Pin-to-Pin Compatible with ML4800 and FAN4800 and CM6800 and CM6800A PWM Configurable for Current-Mode or Feed-Forward Voltage-Mode Operation Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM in one IC The highly integrated FAN4800A/C and FAN4801/1S/2/2L are specially designed for power supplies that consist of boost PFC and PWM. They require very few external components to achieve versatile protections / compensation. They are available in 16-pin DIP and SOP packages. Low Operating Current fRTCT=4•fPFC=2•fPWM for FAN4800C and FAN4802/2L The PWM can be used in either current or voltage mode. In voltage mode, feed-forward from the PFC output bus can reduce the secondary output ripple. Innovative Switching-Charge Multiplier Divider Compared with older productions, ML4800 and FAN4800, FAN4800A/C and FAN4801/1S/2/2L have lower operation current that save power consumption in external devices. FAN4800A/C and FAN4801/1S/2/2L have accurate 49.9% maximum duty of PWM that makes the hold-up time longer. Specifically, the brownout protection and PFC soft-start functions are not in ML4800 and FAN4800. Average-Current-Mode for Input-Current Shaping PFC Over-Voltage and Under-Voltage Protections PFC Feedback Open-Loop Protection Peak Current Limiting for PFC Cycle-by-Cycle Current Limiting for PWM Power-On Sequence Control and Soft-Start To start evaluating FAN4800A/C, FAN4801/1S/2/2L for replacing existing FAN4800 and ML4800 boards, five things must be done before the fine-tuning procedure: Brownout Protection Interleaved PFC/PWM Switching FAN4801/1S/2/2L Improve Efficiency at Light Load fRTCT=4•fPFC=4•fPWM for FAN4800A and FAN4801/1S 1. Change RAC resister from the old value to a higher resister: between 6MΩ to 8MΩ. 2. Change RT/CT pin from the existing values to RT=6.8KΩ and CT=1000pF to have fPFC=64KHz, fPWM=64KHz. 3. VRMS pin needs to be 1.224V at VIN=85 VAC for universal input application from line input from 85VAC to 270 VAC. Both poles for the Vrms of FAN4801/1S/2/2L don’t need to substantially slower than FAN4800; about 5 to 10 times. 4. At full load, the average VEA needs to ~4.5V and the ripple on the VEA needs to be less than 400mV. 5. Soft-Start pin, the soft-start current has been reduced to half from the FAN4800 capacitor. Applications Desktop PC Power Supply Internet Server Power Supply LCD TV, Monitor Power Supply UPS Battery Charger DC Motor Power Supply Related Resources Monitor Power Supply Complete design instructions are detailed in application note AN-6078SC (available in Chinese only). Telecom System Power Supply Distributed Power © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 www.fairchildsemi.com 1 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination April 2009 Operating Temperature Range Eco Status FAN4800ANY -40°C to +105°C Green FAN4800CNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) FAN4800AMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape and Reel FAN4800CMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape and Reel FAN4801NY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube FAN4801SNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube FAN4802NY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube FAN4802LNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube FAN4801MY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape and Reel FAN4801SMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape and Reel FAN4802MY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape and Reel FAN4802LMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape and Reel Part Number Packing Method Package 16-pin Dual In-Line Package (DIP) Tube Tube For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Part Number PFC:PWM Frequency Ratio Brown Out / In Range In / Out FAN4800ANY 1:1 1.05V / 1.9V NA FAN4800AMY 1:1 1.05V / 1.9V NA FAN4800CNY 1:2 1.05V / 1.9V NA FAN4800CMY 1:2 1.05V / 1.9V NA FAN4801NY 1:1 1.05V / 1.9V 1.95V / 2.45V FAN4801SNY 1:1 1.05V / 1.9V 2.8V / 3.35V FAN4802NY 1:2 1.05V / 1.9V 1.95V / 2.45V FAN4802LNY 1:2 0.9V / 1.65V 1.95V / 2.45V FAN4801MY 1:1 1.05V / 1.9V 1.95V / 2.45V FAN4801SMY 1:1 1.05V / 1.9V 2.8V / 3.35V FAN4802MY 1:2 1.05V / 1.9V 1.95V / 2.45V FAN4802LMY 1:2 0.9V / 1.65V 1.95V / 2.45V © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Ordering Information www.fairchildsemi.com 2 IEA VEA IAC FBPFC ISENSE VREF VDD VRMS VDD SS OPFC FBPWM OPWM RT/CT GND RAMP ILIMIT VREF FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Application Diagram FAN4800A/C FAN4801/1S/2/2L Secondary Figure 1. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Typical Application Current Mode www.fairchildsemi.com 3 IEA VEA IAC FBPFC ISENSE VREF VDD VRMS VDD SS OPFC FBPWM OPWM RT/CT GND RAMP ILIMIT FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Application Diagram VREF FAN4800A/C FAN4801/1S/2/2L VREF Secondary Figure 2. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Typical Application Voltage Mode www.fairchildsemi.com 4 Figure 3. Figure 4. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 FAN4800A/C Function Block Diagram FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Block Diagram FAN4801/1S/2/2L Function Block Diagram www.fairchildsemi.com 5 F – Fairchild Logo Z – Plant Code X – 1-Digit Year Code Y – 1-Digit Week Code TT – 2-Digit Die Run Code T – Package Type (N:DIP, M:SOP) P – Y: Green Package M – Manufacture Flow Code Figure 5. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Marking Information Top Mark www.fairchildsemi.com 6 Figure 6. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 IEA Output of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulse width for PFC gate drive. 2 IAC Input AC Current. For normal operation, this input provides current reference for the multiplier. The suggested maximum IAC is 100µA. 3 ISENSE 4 VRMS 5 SS 6 FBPWM 7 RT/CT Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. 8 RAMP PWM RAMP Input. In current mode, this pin functions as the current sense input; when in voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp). 9 ILIMIT Peak Current Limit Setting for PWM. The peak current limits setting for PWM. 10 GND 11 OPWM PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally clamped under 15V to protect the MOSFET. 12 OPFC PFC Gate Drive. The totem pole output drive for PWM MOSFET. This pin is internally clamped under 15V to protect the MOSFET. 13 VDD Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively. The operating current is lower than 10mA. 14 VREF Reference Voltage. Buffered output for the internal 7.5V reference. 15 FBPFC 16 VEA PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of multiplier and PFC ILIMIT comparator. Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier. PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10µA constant current source. The voltage on FBPWM is clamped by SS during startup. In the event of a protection condition occurring and/or PWM disabled, the SS pin is quickly discharged. FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Pin Configuration PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. Ground. Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 www.fairchildsemi.com 7 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Parameter Min. DC Supply Voltage Max. Unit 30 V VH SS, FBPWM, RAMP, OPWM, OPFC -0.3 30.0 V VL IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA -0.3 7.0 V 7.5 V 0 VVREF+0.3 V -5.0 0.7 V VVREF VREF VIEA IEA VN ISENSE IAC Input AC Current 1 mA IREF VREF Output Current 5 mA IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A IPWM-OUT Peak PWM OUT Current, Source or Sink 0.5 A Power Dissipation TA < 50°C 800 mW PD RΘ j-a Thermal Resistance (Junction-to-Air) TJ DIP 80.80 °C/W SOP 104.10 °C/W +125 °C Operating Junction Temperature -40 TSTG Storage Temperature Range -55 TL Lead Temperature(Soldering) Electrostatic Discharge Capability ESD Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 +150 °C +260 °C 4.5 kV 1000 V Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage to the device. FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Min. Operating Ambient Temperature © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 -40 Typ. Max. Unit +105 °C www.fairchildsemi.com 8 VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units 30 80 µA 2.0 2.6 5.0 mA 11 12 V 1.9 V VDD Section IDD ST Startup Current VDD=VTH-ON-0.1V; OPFC OPWM Open IDD-OP Operating Current VDD=13V; OPFC OPWM Open VTH-ON Turn-On Threshold Voltage 10 Hysteresis 1.5 VDD OVP 27 ΔVTH VDD-OVP ΔVDD-OVP VDD OVP Hysteresis 28 29 1 V V Oscillator fOSC-RT/CT RT/CT Frequency RT=6.8kΩ, CT=1000pF PFC & PWM Frequency 240 256 268 60 64 67 120 128 134 kHz fOSC FAN4800C,FAN4802/02L PWM Frequency RT=6.8kΩ, CT=1000pF fDV Voltage Stability 11V ≦ VDD ≦ 22V 2 % fDT Temperature Stability -40°C ~ +105°C 2 % fTV Total Variation (3) (PFC & PWM) Line, Temperature 70 kHz fRV Ramp Voltage 6.5 15 mA 50 75 kHz (3) 58 Valley to Peak IDischarge Discharge Current fRANGE Frequency Range tPFCD PFC Dead Time 2.8 VRAMP=0V, VRT/CT=2.5V (3) kHz V RT=6.8kΩ, CT=1000pF 400 600 800 ns 7.4 7.5 7.6 V 30 50 mV 25 mV 0.5 % 7.35 7.65 V 25 mV VREF VVREF Reference Voltage IREF=0mA, CREF=0.1µF ΔVVREF1 Load Regulation of Reference Voltage CREF=0.1µF, IREF=0mA to 3.5mA VVDD=14V, Rise/Fall Time > 20µs ΔVVREF2 Line Regulation of Reference Voltage CREF=0.1µF, VVDD=11V to 22V ΔVVREF-DT (3) Temperature Stability -40°C ~ +105°C (3) ΔVVREF-TV Total Variation Line, Load, Temp (3) ΔVVREF-LS Long-Term Stability TJ=125°C, 0 ~ 1000HRs 5 Maximum Current VVREF > 7.35V 5 IREF-MAX. (3) IOS 0.4 Output Short Circuit FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics mA 25 mA PFC OVP Comparator VPFC-OVP ΔVPFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V PFC OVP Hysteresis 200 250 300 mV 0.2 0.3 0.4 V Voltage Level on FBPFC to Enable OPWM During Startup 2.3 2.4 2.5 V Hysteresis 1.15 1.25 1.35 V Low-Power Detect Comparator VEAOFF VEA Voltage OFF OPFC VIN OK Comparator VRD-FBPFC ΔVRD-FBPFC © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 www.fairchildsemi.com 9 VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units 6 V 2.55 V 90 µmho Voltage Error Amplifier FBPFC Input Voltage Range Vref Reference Voltage AV (3) Gmv IFBPFC-L IFBPFC-H IBS Open-Loop Gain (3) 0 at T=25°C 2.45 2.50 35 42 Transconductance VNONINV=VINV, VVEA=3.75V at T=25°C 50 70 Maximum Source Current VFBPFC=2V, VVEA=1.5V 40 50 Maximum Sink Current VFBPFC=3V, VVEA=6V -50 Input Bias Current -1 VVEA-H Output High Voltage on VVEA 5.8 VVEA-L Output Low Voltage on VVEA dB µA -40 µA 1 µA 6.0 0.1 V 0.4 V 0.7 V 100 µmho 10 mV 7.4 8.0 V 0.1 0.4 Current Error Amplifier VISENSE GmI Input Voltage Range (3) (ISENSE Pin) -1.5 Transconductance VNONINV=VINV, VIEA=3.75V 78 VOFFSET Input Offset Voltage VVEA=0V, IAC Open -10 VIEA-H Output High Voltage VIEA-L Output Low Voltage IL Source Current IH Sink Current AI 6.8 VISENSE=-0.6V, VIEA=1.5V 35 VISENSE=+0.6V, VIEA=4.0V Open-Loop Gain (3) 88 50 -50 40 V µA -35 50 µA dB Tri-Fault Detect (3) tFBPFC_OPEN Time to FBPFC Open VPFC-UVP PFC Feedback UnderVoltage Protection VFBPFC=VPFC-UVP to FBPFC OPEN, 470pF from FBPFC to GND 0.4 2 4 ms 0.5 0.6 V 100 µA FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics (Continued) Gain Modulator IAC GAIN BW Vo(gm) Input for AC Current GAIN Modulator Bandwidth (3) (4) (3) Output Voltage=5.7kΩ × (3) (ISENSE-IOFFSET) © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Multiplier Linear Range 0 IAC=17.67µA, VRMS=1.080V VFBPFC=2.25V, at T=25°C 7.50 9.00 10.50 IAC=20µA, VRMS=1.224V VFBPFC=2.25V, at T=25°C 6.30 7.00 7.70 IAC=25.69µA, VRMS=1.585V VFBPFC=2.25V, at T=25°C 3.80 4.20 4.60 IAC=51.62µA, VRMS=3.169V VFBPFC=2.25V, at T=25°C 0.95 1.05 1.16 IAC=62.23µA, VRMS=3.803V VFBPFC=2.25V, at T=25°C 0.66 0.73 0.80 IAC=40µA 2 IAC=20µA, VRMS=1.224V VFBPFC=2.25V, at T=25°C 0.74 0.82 kHz 0.90 V www.fairchildsemi.com 10 VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units -1.25 -1.15 -1.05 V PFC ILIMIT Comparator VPFC-ILIMIT Peak Current Limit Threshold Voltage, Cycle-by-Cycle Limit IAC=17.67µA, VRMS=1.08V VFBPFC=2.25V, at T=25°C 200 Gate Output Clamping Voltage VDD=22V 13 VGATE-L Gate Low Voltage VDD=15V; IO=100mA VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 tr Gate Rising Time VDD=15V; CL=4.7nF; O/P=2V to 9V 40 70 120 ns tf Gate Falling Time VDD=15V; CL=4.7nF; O/P=9V to 2V 40 60 110 ns DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 DPFC-MIN Minimum Duty Cycle VIEA>4.5V ΔVpk PFC ILIMIT-Gain Modulator Output mV PFC Output Driver VGATE-CLAMP 15 17 V 1.5 V V % 0 % Brown Out VRMS-UVP VRMS Threshold Low VRMS-UVP VRMS Threshold High ΔVRMS-UVP tUVP Hysteresis FAN4800A/C, FAN4801/1S/2 1.00 1.05 1.10 V FAN4802L 0.85 0.90 0.95 V FAN4800A/C, FAN4801/1S/2 1.85 1.90 1.95 V FAN4802L 1.60 1.65 1.70 V FAN4800A/C, FAN4801/1S/2 750 850 950 mV FAN4802L 650 750 850 mV 340 410 480 ms 9.5 10.0 10.5 Under-Voltage Protection Delay Time FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics (Continued) Soft-Start VSS-MAX Maximum Voltage ISS Soft-Start Current VDD=15V 10 V µA PWM ILIMIT Comparator VPWM-ILIMIT tPD tPWM-Bnk Threshold Voltage 0.95 Delay to Output 1.00 1.05 250 Leading-Edge Blanking Time V ns 170 250 350 ns Range (FAN4801/1S/2/2L) VRMS-L RMS AC Voltage LOW When VRMS=1.95V at 132VRMS 1.90 1.95 2.00 V VRMS-H RMS AC Voltage HIGH When VRMS=2.45V at 150VRMS 2.40 2.45 2.50 V VEA LOW When VVEA=1.95V at 30% Loading, When VVEA=2.80V at 60% Loading 1.90 1.95 2.00 2.75 2.80 2.85 2.40 2.45 2.50 3.30 3.35 3.40 18 20 22 VEA-L VEA-H Itc VEA LOW (FAN4801S) VEA HIGH VEA HIGH (FAN4801S) When VVEA=2.45V at 40% Loading, When VVEA=3.35V at 70% Loading Two-Level Current FBPFC Two-Level Current © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 V V µA www.fairchildsemi.com 11 VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications. Symbol Parameter Conditions Min. Typ. Max. Units 13 15 17 V 1.5 V PWM Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22V VGATE-L Gate Low Voltage VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 tr Gate Rising Time VDD=15V; CL=4.7nF 30 60 120 ns tf Gate Falling Time VDD=15V; CL=4.7nF 30 50 110 ns Maximum Duty Cycle 49.0 49.5 50.0 % PWM Comparator Level Shift 1.3 1.5 1.8 V DPWM-MAX VPWM-LS VDD=15V; IO=100mA Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 2 -1 -1 4. Gain=K × 5.3 × (VRMS ) ; K=( ISENSE － IOFFSET) × [IAC × (VEA － 0.7V)] ; VEA (MAX.)=5.6V. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 V FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Electrical Characteristics (Continued) www.fairchildsemi.com 12 20.0 2.96 18.0 2.94 16.0 2.92 2.90 IDD-OP(uA) IDD-ST(uA) 14.0 12.0 10.0 8.0 6.0 2.86 2.84 4.0 2.82 2.0 2.80 0.0 2.78 -40℃ -25℃ -10℃ 5℃ Figure 7. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ IDD-ST vs. Temperature 11.4 2.0 11.3 1.9 △VTH(V) 11.0 95℃ 110℃ 125℃ IDD-OP vs. Temperature 1.7 1.6 1.5 10.9 1.4 1.3 10.8 -40℃ -25℃ -10℃ 5℃ Figure 9. 20℃ 35℃ 50℃ 65℃ 80℃ -40℃ -25℃ -10℃ 95℃ 110℃ 125℃ VTH-ON vs. Temperature 28.04 65.0 28.02 64.9 FOSC-FAN4801/1S(kHz) 27.96 27.94 27.92 27.90 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVTH vs. Temperature 64.7 64.6 64.5 64.4 64.3 27.88 27.86 -40℃ -25℃ -10℃ 5℃ Figure 11. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 64.2 -40℃ 110℃ 125℃ VDD-OVP vs. Temperature -25℃ -10℃ Figure 12. 655 129.8 650 129.6 645 129.4 640 tPFCD(ns) 130.0 129.2 129.0 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ fOSC-FAN4801/1S vs. Temperature 630 625 128.6 620 128.4 5℃ 635 128.8 Figure 13. 20℃ 64.8 27.98 -40℃ -25℃ -10℃ 5℃ Figure 10. 28.00 VDD-OVP(V) 20℃ 35℃ 50℃ 65℃ 80℃ 1.8 11.1 FOSC-FAN4802/2L(kHz) 5℃ Figure 8. 11.2 VTH-ON (V) 2.88 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Typical Characteristics 615 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ fOSC-FAN4802/2L vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 5℃ Figure 14. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ tPFCD vs. Temperature www.fairchildsemi.com 13 7.520 6 7.515 5 7.510 △ VVREF1(mV) VVREF(V) 7.505 7.500 7.495 7.490 4 3 2 7.485 1 7.480 7.475 0 -40℃ -25℃ -10℃ 5℃ Figure 15. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ VVREF vs. Temperature Figure 16. 0.18 0.14 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVVREF1 vs. Temperature 20.5 IREF-MAX.(mA) △ VVREF2(mV) 35℃ 21.0 0.16 0.12 0.10 0.08 0.06 20.0 19.5 19.0 0.04 0.02 18.5 0.00 -0.02 18.0 -40℃ -25℃ -10℃ Figure 17. 5℃ -40℃ -25℃ -10℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVVREF2 vs. Temperature Figure 18. 2.742 252.2 2.740 252.0 △ VPFC-OVP(mV) VPFC-OVP(V) 20℃ 21.5 0.20 2.738 2.736 2.734 2.732 -40℃ -25℃ -10℃ Figure 19. 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ IREF-MAX. vs. Temperature 251.8 251.6 251.4 251.2 -40℃ -25℃ -10℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VPFC-OVP vs. Temperature Figure 20. 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVPFC-OVP vs. Temperature 1.275 1.270 △ VRD-FBPFC(V) 2.398 2.396 2.394 2.392 2.390 1.265 1.260 1.255 1.250 1.245 2.388 Figure 21. 20℃ 35℃ 250.8 5℃ 2.400 -40℃ -25℃ -10℃ 5℃ 251.0 2.730 VRD-FBPFC(V) 5℃ FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Typical Characteristics 1.240 5℃ -40℃ -25℃ -10℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VRD-FBPFC vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Figure 22. 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVRD-FBPFC vs. Temperature www.fairchildsemi.com 14 74 2.502 2.500 73 Gmv(umho) Vref(V) 2.498 2.496 2.494 73 72 2.492 72 2.490 2.488 71 -40℃ -25℃ -10℃ 5℃ Figure 23. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ VREF vs. Temperature 4.5 94 4.0 92 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ GmV vs. Temperature 90 3.0 Gm I(umho) VOFFSET(mV) -10℃ Figure 24. 3.5 2.5 2.0 1.5 88 86 84 82 1.0 80 0.5 0.0 78 -40℃ -25℃ -10℃ 5℃ Figure 25. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ VOFFSET vs. Temperature Figure 26. 7.10 6.1 7.05 6.0 7.00 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ GmI vs. Temperature 5.9 Rmul(kΩ) 6.95 GAIN2 -25℃ FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Typical Characteristics 6.90 6.85 5.8 5.7 5.6 6.80 5.5 6.75 6.70 5.4 -40℃ -25℃ -10℃ 5℃ Figure 27. 20℃ 35℃ 50℃ 65℃ 80℃ -40℃ -25℃ -10℃ 95℃ 110℃ 125℃ GAIN2 vs. Temperature Figure 28. -1.1775 295 -1.1780 290 -1.1785 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Rmul vs. Temperature 285 -1.1790 △ Vpk(mV) VPFC-ILIMIT(V) 280 -1.1795 -1.1800 -1.1805 275 270 265 -1.1810 -1.1815 260 -1.1820 255 250 -1.1825 -40℃ -25℃ -10℃ Figure 29. 5℃ 5℃ 20℃ 35℃ 50℃ -40℃ -25℃ -10℃ 65℃ 80℃ 95℃ 110℃ 125℃ VPFC-ILIMIT vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Figure 30. 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVpk vs. Temperature www.fairchildsemi.com 15 10.1 1.010 10.0 1.009 9.9 9.8 1.007 ISS(uA) VPWM-ILIMIT (V) 1.008 1.006 1.005 9.5 9.3 1.003 9.2 1.002 9.1 -40℃ -25℃ -10℃ 5℃ Figure 31. -40℃ -25℃ -10℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VPWM-ILIMIT vs. Temperature 5℃ 1.048 867.5 1.047 867.0 1.046 866.5 △ VRMS-UVP(mV) 1.044 1.043 1.042 1.041 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ISS vs. Temperature 866.0 865.5 865.0 864.5 864.0 863.5 1.040 863.0 1.039 862.5 1.038 862.0 -40℃ -25℃ -10℃ 5℃ Figure 33. -40℃ -25℃ -10℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VRMS-UVP vs. Temperature 5℃ 2.446 1.939 2.445 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ΔVRMS-UVP vs. Temperature Figure 34. 1.940 2.444 1.938 2.443 VRMS-H(V) 1.937 1.936 1.935 1.934 2.442 2.441 2.440 2.439 1.933 2.438 1.932 2.437 2.436 1.931 -40℃ -25℃ -10℃ 5℃ 2.435 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ Figure 35. VRMS-L vs. Temperature 5℃ Figure 36. 1.942 2.436 1.940 2.434 1.938 2.432 VEA-H(V) VEA-L(V) 20℃ 35℃ Figure 32. 1.045 VRMS-UVP(V) 9.6 9.4 1.004 VRMS-L(V) 9.7 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Typical Characteristics 1.936 1.934 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VRMS-H vs. Temperature 2.430 2.428 1.932 2.426 1.930 2.424 1.928 -40℃ -25℃ -10℃ -40℃ -25℃ -10℃ Figure 37. 5℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VEA-L vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Figure 38. 110 ℃ 125 ℃ VEA-H vs. Temperature www.fairchildsemi.com 16 14.4 14.6 14.3 14.5 14.2 VGATE-CLAMP-PWM(V) VGATE-CLAMP-PFC(V) 14.7 14.4 14.3 14.2 14.1 14.1 14.0 13.9 13.8 14.0 13.7 13.9 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 13.6 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ Figure 39. VGATE-CLAMP-PFC vs. Temperature Figure 40. 96.06 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VGATE-CLAMP-PWM vs. Temperature 49.80 96.04 49.75 DPWM-MAX(%) DPFC-MAX(%) 96.02 96.00 95.98 95.96 95.94 49.70 49.65 49.60 49.55 95.92 95.90 49.50 95.88 -40℃ -25℃ -10℃ -40℃ -25℃ -10℃ Figure 41. 5℃ 20℃ 35℃ 50℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 65℃ 80℃ 95℃ 110℃ 125℃ DPFC-MAX vs. Temperature Figure 42. 110 ℃ 125 ℃ DPWM-MAX vs. Temperature 1.460 21.0 20.8 1.455 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Typical Characteristics VPWM-LS(V) 20.6 Itc(uA) 20.4 20.2 20.0 1.450 1.445 1.440 19.8 1.435 19.6 19.4 1.430 -40℃ -25℃ -10℃ 5℃ Figure 43. 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ Itc vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 Figure 44. 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VPWM-LS vs. Temperature www.fairchildsemi.com 17 The FAN4800A/C and FAN4801/1S/2/2L consist of an average current controlled, continuous boost Power Factor Correction (PFC) front-end and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the line regulation of PWM. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This proprietary leading/trailing edge modulation results in a higher usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitor. IGAINMOD = I AC × (VEA − 0.7) VRMS 2 ×K (1) Note that the output current of the gain modulator is limited around 159μA and the maximum output voltage of the gain modulator is limited to 159μA x 5.7K=0.906V. This 0.906V also determines the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE=IGAINMOD – IOFFSET and IOFFSET can only be measured when VEA is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 31μA ~ 48μA. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800A, FAN4801/1S operates at the same frequency as the PFC; and FAN4800C, FAN4802/2L operates at double with PFC. Selecting RAC for IAC Pin In addition to power factor correction, a number of protection features are built into this series. They include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout (UVLO). The IAC pin is the input of the gain modulator and also a current mirror input and requires current input. Selecting a proper resistor RAC provides a good sine wave current derived from the line voltage and helps program the maximum input power and minimum input line voltage. RAC=VIN peak x 56KΩ. For example, if the minimum line voltage is 75VAC, the RAC=75 x 1.414 x 56KΩ=6MΩ. Gain Modulator Current Amplifier Error, IEA The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current, which results in a negative voltage being impressed upon the ISENSE pin. 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, required in high-power, switching-power conversion environments. The gain modulator responds linearly to this current. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS (except at unusually low values of VRMS, where special gain contouring takes over to limit power dissipation of the circuit components under brownout conditions). 3. The output of the voltage error amplifier, VEA. The gain modulator responds linearly to variations in this voltage. PFC Cycle-By-Cycle Current Limiter As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is less than -1.15V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is: © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Functional Description www.fairchildsemi.com 18 Error Amplifier Compensation To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards, the FAN4800A/C, FAN4801/1S/2/2L includes TriFault Detect. This feature monitors FBPFC for certain PFC fault conditions. The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 45 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current-loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: As the reference voltage increases from 0V, it creates a differentiated voltage on IEA, which prevents the PFC from immediately demanding a full duty cycle on its boost converter. Complete design is referred in application note AN-6078SC. In a feedback path failure, the output of the PFC could exceed safe operating limits. With such a failure, FBPFC exceeds its normal operating area. Should FBPFC go too LOW, too HIGH, or OPEN, TriFault Detect senses the error and terminates the PFC output drive. TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function. PFC Over-Voltage Protection There is an RC filter between RSENSE and ISENSE pin. There are two reasons to add a filter at the ISENSE pin: In the FAN4800A/C, FAN4801/1S/2/2L, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the highvoltage DC output of the PFC is fed to FBPFC. When the voltage on FBPFC exceeds 2.75V, the PFC output driver is shut down. The PWM section continues to operate. The OVP comparator has 250mV of hysteresis and the PFC does not restart until the voltage at FBPFC drops below 2.50V. VDD OVP can also serve as a redundant PFC OVP protection. VDD OVP threshold is 28V with 1V hysteresis. 1. Protection: During startup or inrush current conditions, there is a large voltage across RSENSE, which is the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. 2. To reduce L, the boost inductor: The ISENSE filter also can reduce the boost inductor value since the ISENSE filter behaves like an integrator before the ISENSE pin, which is the input of the current error amplifier, IEA. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100Ω and 50Ω because IOFFSET x RFILTER can generate a negative offset voltage of IEA. Selecting an RFILTER equal to 50Ω keeps the offset of the IEA less than 3mV. Design the pole of ISENSE filter at fPFC/6, one sixth of the PFC switching frequency, so the boost inductor can be reduced six times without disturbing the stability. The capacitor of the ISENSE filter, CFILTER, is approximately 100nF. Selecting PFC Rsense RSENSE is the sensing resistor of the PFC boost converter. During the steady state, line input current x RSENSE equals IGAINMOD x 5.7KΩ. At full load, the average VEA needs to around 4.5V and ripple on the VEA needs to be less than 400mV. Choose the resistance of the sensing resistor: RSENSE = ( 4.5 − 0.7) × 5.7KΩ × I AC × Gain × VIN × 2 2 × (5.6 − 0.7) × Line Input Power V REF (2) C V2 C I2 CV1 where 5.6 is VEA maximum output. C I1 R V1 PFC Output VEA PFC Soft-Start PFC startup is controlled by VEA level. Before FBPFC voltage reaches 2.4V, the VEA level is around 2.8V. At 90VAC, the PFC soft-start time is 90ms. FBPFC The AC UVP comparator monitors the AC input voltage. The FAN4800A/C, FAN4801/1S/2 disables OPFC when the VRMS is less than 1.05V and continues 500ms. The VRMS threshold low voltage of FAN4802L is 0.9V, which is different from the FAN4802. IEA Rmul 1 GMi 2.5V R F2 R SENSE GMv 15 RI1 16 R F1 PFC Brownout © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination TriFault Detect™ IAC 2 VRMS 4 RFILTER ISENSE 3 Gain Modulator I MO V(t) Rmul C FILTER Figure 45. Compensation Network Connection for the Voltage and Current Error Amplifiers www.fairchildsemi.com 19 Pulse Width Modulator (PWM) To improve the efficiency, the system can reduce PFC switching loss at low line and light load by reducing the PFC output voltage. The two-level PFC output of FAN4801/1S/2/2L can be programmable. The operation of the PWM section is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In currentmode applications, the PWM ramp (RAMP) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage. It is thereby representative of the current flowing in the converter’s output stage. ILIMIT, which provides cycle-bycycle current limiting, is typically connected to RAMP in such applications. For voltage-mode operation and certain specialized applications, RAMP can be connected to a separate RC timing network to generate a voltage ramp against which FBPWM is compared. Under these conditions, the use of voltage feed-forward from the PFC bus can assist in line regulation accuracy and response. As in current-mode operation, the ILIMIT input is used for output stage over-current protection. No voltage error amplifier is included in the PWM stage, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM’s RAMP input that allows FBPWM to command a 0% duty cycle for input voltages below typical 1.5V. As Figure 46 shows, FAN4801/1S/2/2L detect VEA pin and VRMS pin to determine the system operates low line and light load or not. At the second-level PFC, there is a current of 20µA through RF2 from FBPFC pin. So the second-level PFC output voltage can be calculated as. Output ≅ RF 1 + RF 2 × (2.5V − 20 μA × RF 2 ) RF 2 (3) For example, if the second-level PFC output voltage is expected as 300V and normal voltage is 387V, according to the equation, RF2 is 28kΩ RF1 is 4.3MΩ. The programmable range of second level PFC output voltage is 340V ~ 300V. VEA PFC Output 16 VDD RF1 20µA FBPFC 15 gmv 2.5V RF2 PWM Cycle-By-Cycle Current Limiter The ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. When the ILIMIT triggers the cycle-by-cycle bi-cycle current, it limits the PWM duty cycle mode and the power dissipation is reduced during the dead-short condition. Range VRMS 4 Figure 46. Two-Level PFC Scheme Oscillator (RT/CT) VIN OK Comparator The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if the voltage on FBPFC is less than its nominal 2.4V. Once the voltage reaches 2.4V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. 1 (4) tRT / CT + tDEAD The dead time of the oscillator is derived from the following equation: fRT / CT = ⎛ V −1 ⎞ ⎟ tRT / CT = CT × RT × In ⎜⎜ REF ⎟ ⎝ VREF − 3.8 ⎠ FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Two-Level PFC Function PWM Soft-Start (SS) (5) PWM startup is controlled by selection of the external capacitor at soft-start. A current source of 10µA supplies the charging current for the capacitor and startup of the PWM begins at 1.5V. at VREF=7.5V and tRT/CT=CT x RT x 0.56. The dead time of the oscillator is determined using: 2.8V × CT = 360 × CT (6) 7.78mA The dead time is so small (tRT/CT>>tDEAD) that the operating frequency can typically be approximated by: tDEAD = fRT / CT = 1 tRT / CT © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 (7) www.fairchildsemi.com 20 Leading/Trailing Modulation When the PWM section is used in current mode, RAMP is generally used as the sampling point for a voltage, representing the current in the primary of the PWM’s output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP is the input for a ramp voltage generated by a second set of timing components (RRAMP, CRAMP) that have a minimum value of 0V and a peak value of approximately 6V. In voltage mode, feed forward from the PFC output bus is an excellent way to derive the timing ramp for the PWM stage. Conventional PWM techniques employ trailing-edge modulation, in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. In the case of leading-edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off-time of the switch. Generating VDD After turning on the FAN4800A/C, FAN4801/1S/2/2L at 11V, the operating voltage can vary from 9.3V to 28V. The threshold voltage of the VDD OVP comparator is 28V and its hysteresis is 1V. When VDD reaches 28V, OPFC is LOW, and the PWM section is not disturbed. There are two ways to generate VDD: use auxiliary power supply around 15V or use bootstrap winding to self-bias the FAN4800A/C, FAN4801/1S/2/2L system. The bootstrap winding can be taped from the PFC boost choke or the transformer of the DC-to-DC stage. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination PWM Control (RAMP) www.fairchildsemi.com 21 19.68 18.66 16 A 9 6.60 6.09 1 8 (0.40) TOP VIEW 0.38 MIN 5.33 MAX 8.13 7.62 3.42 3.17 3.81 2.92 2.54 0.35 0.20 0.58 A 0.35 1.78 1.14 15 0 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Physical Dimensions 8.69 17.78 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1 Figure 47. 16-Pin Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 www.fairchildsemi.com 22 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination Physical Dimensions (Continued) Figure 48. 16-Pin Small Outline Package (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 www.fairchildsemi.com 23 FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination © 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.2 www.fairchildsemi.com 24