SG6932 PFC / Forward PWM Controller Features Description Interleaved PFC/PWM Switching The highly integrated SG6932 is designed for power supplies with boost PFC and forward PWM. It requires very few external components to achieve versatile protections and compensation. It is available in 16-pin DIP and SOP packages. Average Current Mode for Input-current Shaping Low Operating Current Innovative Switching-Charge Multiplier-divider Multi-vector Control for Improved PFC Output Transient Response PFC Over-voltage and Under-voltage Protections PFC and PWM Feedback Open-loop Protection Cycle-by-cycle Current Limiting for PFC/PWM Slope Compensation for PWM Selectable PWM Maximum Duty Cycle: 50%, 65% Brownout Protection Power-on Sequence Control and Soft-start Applications Switch-mode Power Supplies with Active PFC Servo-system Power Supplies The proprietary interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is continuously decreased to reduce power consumption. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a lowbandwidth PFC loop; in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG6932 shuts off to prevent extra-high voltage on output. For the forward PWM stage, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode (CCM) operation. Hiccup operation during output overloading is guaranteed. The soft-start and programmable maximum duty cycle ensure safe operation. SG6932 provides complete protection functions, such as brownout protection and RI open/short latch off. PC-ATX Power Supplies Ordering Information Part Number Operating Temperature Range Package Eco Status Packing Method SG6932DZ -40°C to +85°C 16-pin Dual In-Line Package (DIP) RoHS Tube SG6932SZ -40°C to +85°C 16-pin Small Outline Package (SOP) RoHS Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com SG6932 — PFC / Forward PWM Controller May 2008 SG6932 — PFC / Forward PWM Controller Application Diagram Figure 1. Typical Application © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 2 SG6932 — PFC / Forward PWM Controller Block Diagram Figure 2. Function Block Diagram © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 3 T: D=DIP, S=SOP P : Z =Lead Free + ROHS Compatible XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location SG6932TP XXXXXXXXYWWV Figure 3. Top Mark SG6932 — PFC / Forward PWM Controller Marking Information Pin Configuration VRMS 1 16 IAC RI 2 15 VEA IEA 3 14 FBPFC IPFC 4 13 SS IMP 5 12 VDD ISENSE 6 11 OPFC FBPWM 7 10 GND IPWM 8 9 OPWM Figure 4. Pin Configuration (Top View) © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 4 Pin # Name Description 1 VRMS Line-Voltage Detection. The pin is used for PFC multiplier and brownout protection. 2 RI Oscillator Setting. One resistor connected between RI and ground determines the switching frequency. A resistor with resistance between 12 ~ 47kΩ is recommended. The switching frequency is equal to [1560 / RI]kHz, where RI is in kΩ. For example, if RI is 24kΩ, the switching frequency is 65kHz. 3 IEA Output of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulsewidth for PFC gate drive. 4 IPFC Inverting Input of PFC Current Amplifier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. 5 IMP Non-inverting Input of PFC Current Amplifier and Output of Multiplier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. 6 ISENSE Peak Current Limit Setting for PFC. 7 FBPWM PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. It is internally pulled HIGH through a 6.5kΩ resistor. An external opto-coupler from the secondary feedback circuit is usually connected to this pin. 8 IPWM PWM Current Sense. The current sense input for the PWM stage. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. 9 OPWM PWM Gate Drive. The totem-pole output drive for PWM MOSFET. clamped under 18V to protect the MOSFET. 10 GND Ground. The power ground. 11 OPFC PFC Gate Drive. The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. 12 VDD Supply. The power supply pin. The threshold voltages for start-up and turn-off are 14V and 10V, respectively. The operating current is lower than 10mA. 13 SS PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 50µA constant current source. The voltage on FBPWM is clamped by SS during startup. In the event of a protection condition occurring and/or PWM being disabled, the SS pin is quickly discharged. The voltage of SS pin can be used to select 50% or 65% maximum duty cycle. 14 FBPFC Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. 15 VEA Error Amplifier Output for PFC Voltage Feedback Loop. A compensation network (usually a capacitor) is connected between this pin and ground. A large capacitor value results in a narrow bandwidth and improves the power factor. 16 IAC Input AC Current. For normal operation, this input is used to provide current reference for the multiplier. The suggested maximum IAC is 360µA. © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 SG6932 — PFC / Forward PWM Controller Pin Definitions This pin is internally www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are given with respect to GND pin. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage to the device. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 25 V IAC Input AC Current 2 mA VHIGH OPWM, OPFC, IAC -0.5 25.0 V VLOW Others -0.5 7.0 V 0.8 W PD TJ TSTG Power Dissipation (TA<50°C) Operating Junction Temperature -40 +125 °C Storage Temperature Range -55 +150 °C θJC Thermal Resistance (Junction-to-Case) TL Lead Temperature (Wave Soldering, 10 Seconds) ESD DIP 33.64 SOP 41.95 °C/W +260 °C Electrostatic Discharge Capability, Human Body Model: JESD22-A114 4.5 KV Electrostatic Discharge Capability, Machine Model: JESD22-A115 250 V SG6932 — PFC / Forward PWM Controller Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Min. Operating Ambient Temperature © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 -40 Typ. Max. Unit +85 °C www.fairchildsemi.com 6 VDD=15V, TA= 25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VDD-OP Continuously Operating Voltage 20 V IDD ST Start-Up Current VDD – 0.16V 10 20 μA IDD-OP Operating Current VDD = 15V; OPFC OPWM open 6 10 mA VTH-ON Start Threshold Voltage 14 15 V 13 VDD-min Minimum Operating Voltage VDD-OVP VDD OVP1 (Turn Off PWM with Delay) tVDD-OVP Delay Time of VDD OVP1 RI=24kΩ 9 10 11 V 23.4 24.5 25.5 V 25 μs 8 Oscillator VRI RI Voltage fOSC PWM Frequency RI RI=24kΩ RI Range 1.176 1.200 1.224 V 62 65 68 kHz 47 kΩ 12 RIOPEN RI Pin Open Protection If RI > RIOPEN, PWM Turned Off 200 kΩ RISHORT RI Pin Short Protection If RI > RISHORT, PWM Turned Off 2 kΩ SG6932 — PFC / Forward PWM Controller Electrical Characteristics VRMS for UVP and ON/OFF VRMS-UVP-1 RMS AC Voltage Under-Voltage Threshold to Turn Off PFC (with TUVP Delay) for UVP Mode1 VRMS-UVP-2 Recovery Level on VRMS for UVP tUVP Under-Voltage Protection to Turn Off PFC Delay Time (No Delay for Start-up) RI=24kΩ 0.75 0.80 0.85 VRMS- VRMS- VRMS- UVP-1 UVP-1 V +0.19 UVP-1 V +0.17 +0.21 150 195 240 ms 2.95 3.00 3.05 V PFC Stage Voltage Error Amplifier VREF Reference Voltage AV Open-Loop Gain 60 dB Zo Output Impedance 110 kΩ OVPFBPFC PFC Over-Voltage Protection △ OVPFBPFC PFC Feedback Voltage Protection Hysteresis VFBPFC-H Clamp-High Feedback Voltage GFBPFC-H Clamp-High Gain VFBPFC-L Clamp-Low Feedback Voltage GFBPFC-L Clamp-Low Gain 3.20 3.25 3.30 V 60 90 120 mV 3.10 3.15 3.20 V 2.75 2.85 0.5 mA/V 2.90 V 6.5 mA/V IFBPFC-L Maximum Source Current 1.5 2.0 mA IFBPFC-H Maximum Sink Current 70 110 μA UVPVFB PFC Feedback Under-Voltage Protection 0.35 0.40 VOFF-FBPFC Voltage Level on FBPFC to Disable OPWM 2.15 2.20 0.45 2.25 V V Continued on following page… © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 7 VDD=15V, TA= 25°C unless otherwise noted. Symbol VFBHIGH VRD-FBPFC tUVP_PFC Parameter Conditions Min. Typ. Max. Units 6 7 8 V Voltage Level on FBPFC to Enable OPWM During Start-up 2.6 2.7 2.8 V Debounce Time of PFC UVP 40 70 120 μs Output High Voltage on VEA Current Error Amplifier VOFFSET AI BW CMRR Input Offset Voltage ((-) > (+)) 8 mV Open-loop Gain 60 dB 1.5 MHz 70 dB Unit Gain Bandwidth Common-Mode Rejection Ratio VOUT-HIGH Output HIGH Voltage VOUT-LOW Output LOW Voltage IMR1, IMR2 Reference Current Source IL Maximum Source Current IH Maximum Sink Current VCM=0~1.5V 3.2 RI=24kΩ (IMR=20+IRI•0.8) V 50 0.2 V 70 μA 3 mA 0.25 mA SG6932 — PFC / Forward PWM Controller Electrical Characteristics (Continued) Peak Current Limit IP Constant Current Output RI=24kΩ Vpk Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (Vsense < Vpk) 90 100 110 VRMS=1.05V 0.15 0.20 0.25 VRMS=3V 0.35 0.40 0.45 tpkD Propagation Delay tBnk Leading-Edge Blanking Time 270 350 μA V 200 ns 450 ns 360 μA Multiplier IAC Input AC Current Multiplier Linear Range Maximum Multiplier Current Output RI=24kΩ IMO-1 Multiplier Current Output (Low-Line, High-Power) VRMS=1.05V; IAC=90μA; VEA=7.5V; RI=24kΩ 200 230 IMO-2 Multiplier Current Output (High-Line, High-Power) VRMS=3V; IAC=264μA; VEA=7.5V; RI=24kΩ 65 85 VIMP Voltage of IMP Open 3.4 3.9 4.4 V 16 18 V 1.5 V IMO-max 0 230 μA 280 μA μA PFC Output Driver VZ-PFC Output Voltage Maximum (Clamp) VDD=20V VOL-PFC Output Voltage Low VDD=15V; IO=100mA VOH-PFC Output Voltage High VDD=13V; IO=100mA 8 tR-PFC Rising Time VDD=15V; CL=5nF; O/P= 2V to 9V 40 70 120 ns tF-PFC Falling Time VDD=15V; CL=5nF; O/P= 9V to 2V 40 60 110 ns 97 % DCMAX Maximum Duty Cycle 93 V Continued on following page… © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 8 VDD=15V, TA= 25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 2.2 2.7 3.2 V/V 4 5 7 kΩ PWM Open-Loop Protection Voltage 4.2 4.5 4.8 V Interval of PWM Open-Loop Protection Reset RI=24kΩ 500 600 700 ms PWM Open-Loop Protection Delay Time RI=24kΩ 80 95 120 ms 1.9 2.1 2.3 V PWM Stage FBPWM AV FB to current Comparator Attenuation ZFB Input Impedance FBOPEN-LOOP tOPEN-PWMHiccup tOPEN-PWM VN Frequency Reduction Threshold on FBPWM PWM Current Sense tPD-PWM VLIMIT Propagation Delay to Output – VLIMIT Loop VDD=15V, OPWM Drops to 9V Peak Current Limit Threshold Voltage 60 0.65 0.70 120 ns 0.75 V tBnk-PWM Leading-Edge Blanking Time 270 350 450 ns △VSLOPE Slope Compensation △VS=△VSLOPE(ton/t) △VS : Compensation Voltage Added to Current Sense 0.40 0.45 0.55 V 16 18 V 1.5 V SG6932 — PFC / Forward PWM Controller Electrical Characteristics (Continued) Output Driver VZ-PWM Output Voltage Maximum (Clamp) VDD=20V VOL-PWM Output Voltage Low VDD=15V; IO=100mA VOH-PWM Output Voltage High VDD=13V; IO=100mA 8 tR-PWM Rising Time VDD=15V; CL=5nF; O/P=2V to 9V 30 60 120 ns tF-PWM Falling Time VDD=15V; CL=5nF; O/P=9V to 2V 30 50 110 ns V Maximum Duty Cycle DCSS=6V Maximum Duty Cycle for SS=6V RI=24kΩ 62 66 % DCSS=5V Maximum Duty Cycle for SS=5V RI=24kΩ 46 50 % Constant Current Output for Soft-Start RI=24kΩ 44 56 μA 5 V Soft Start ISS VDC-MAX-50% Voltage of SS for 50% Maximum Duty Cycle VDC-MAX-65% Voltage of SS for 65% Maximum Duty Cycle RD Discharge Resistance © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 50 6 V 470 Ω www.fairchildsemi.com 9 11.0 18.0 10.8 16.0 10.6 14.0 10.4 VTH-MIN(V) IDD ST (µA) 20.0 12.0 10.0 8.0 10.2 10.0 9.8 6.0 9.6 4.0 9.4 2.0 9.2 9.0 0.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ -40℃ 125℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) Figure 6. Minimum Operation Voltage (VDD-MIN) vs. Temperature Figure 5. Startup (IDD-ST) vs. Temperature 15.0 14.8 Start-up Current (µA) 14.6 VTH-ON(V) 14.4 14.2 14.0 13.8 13.6 13.4 13.2 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 13.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 1 2 3 4 125℃ 5 6 7 8 9 10 11 12 13 14 15 VDD Voltage (V) Temperature (℃) Figure 7. Start Threshold Voltage (VTH-ON) vs. Temperature Figure 8. Startup Current vs. VDD Voltage 70.0 25.5 25.3 60.0 25.1 VDD-OVP (V) 50.0 Duty Cycle (%) SG6932 — PFC / Forward PWM Controller Typical Characteristics 40.0 30.0 24.9 24.7 24.5 24.3 24.1 20.0 23.9 10.0 23.7 23.5 0.0 -40℃ 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 FB Voltage (V) -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Figure 10. VDD OVP Threshold vs. Temperature Figure 9. Duty Cycle vs. FB Voltage © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 -25℃ www.fairchildsemi.com 10 3.30 3.29 3.28 3.26 FOSC (KHz) OVPPFC (V) 3.27 3.25 3.24 3.23 3.22 3.21 3.20 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 68.0 67.5 67.0 66.5 66.0 65.5 65.0 64.5 64.0 63.5 63.0 62.5 62.0 -40℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Figure 12. PWM Frequency (fOSC) vs. Temperature 100.0 100.0 90.0 90.0 80.0 80.0 70.0 70.0 TF (nS) TR(nS) Figure 11. PFC Over-voltage Protection vs. Temperature 60.0 60.0 50.0 50.0 40.0 40.0 30.0 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ -40℃ 125℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) Figure 13. Rising Time vs. Temperature Figure 14. Falling Time vs. Temperature 3.05 50.0 3.04 49.5 3.03 49.0 DCMAX (%) 3.02 VREF (V) 35℃ Temperature (℃) SG6932 — PFC / Forward PWM Controller Typical Characteristics (Continued) 3.01 3.00 2.99 2.98 48.5 48.0 47.5 47.0 2.97 46.5 2.96 46.0 2.95 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ -40℃ 125℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Figure 16. Maximum Duty Cycle (SS=5V) vs. Temperature Figure 15. Reference Voltage vs. Temperature © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 -25℃ Temperature (℃) Temperature (℃) www.fairchildsemi.com 11 120.0 66.0 110.0 65.5 100.0 90.0 TR-PWM (nS) DCMAX (%) 65.0 64.5 64.0 63.5 80.0 70.0 60.0 63.0 50.0 62.5 40.0 30.0 62.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ -40℃ 125℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Figure 18. Rising Time vs. Temperature 4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 110.0 100.0 90.0 TF-PWM (nS) FBOPEN-LOOP (V) Figure 17. Maximum Duty Cycle (SS=6V) vs. Temperature 80.0 70.0 60.0 50.0 40.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 30.0 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Figure 19. PWM Open-Loop Protection Voltage vs. Temperature Figure 20. Fall Time vs. Temperature 55 120 54 115 53 110 52 105 ISS (uA) TOPEN-PWM (mS) 35℃ Temperature (℃) SG6932 — PFC / Forward PWM Controller Typical Characteristics (Continued) 100 95 51 50 49 48 90 47 85 46 45 80 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ Temperature (℃) 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Figure 21. PWM Open-Loop Protection Delay Time vs. Temperature Figure 22. Constant Current Output for Soft-start vs. Temperature 0.75 0.74 0.73 VLIMIT (V) 0.72 0.71 0.70 0.69 0.68 0.67 0.66 0.65 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Figure 23. Peak Current Limit Threshold Voltage vs. Temperature © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 12 The highly integrated SG6932 is designed for power supplies with boost PFC and forward PWM. It requires very few external components to achieve versatile protections and compensation. Switching Frequency / Current Sources The switching frequency can be programmed by the resistor RI connected between the RI and GND pins. The relationship is: The proprietary interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is linearly decreased to reduce power consumption. fPWM = 1560 (kHz ) R I (kΩ ) (1) For example, a 24kΩ resistor RI results in a 65kHz switching frequency. Accordingly, constant current IT flows through RI: The PFC function is implemented by average-currentmode control. The proprietary switching charge multiplier-divider provides a high degree of noise immunity for the PFC circuit. This enables the PFC circuit to operate over a much wider region. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop; in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop; is broken, the SG6932 shuts off PFC to prevent extrahigh voltage on output. IT = 1.2V (mA) RI (kΩ ) (2) IT is used to generate internal current reference. Line Voltage Detection (VRMS) Figure 25 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier and brownout protection. For brownout protection, when the VRMS voltage drops below 0.8V, OPFC turns off. For the forward PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-mode operation. Hiccup operation during output overloading is guaranteed. To prevent the power supply from drawing large current during startup, the start-up for PWM stage is delayed 4ms after the PFC output voltage reaches its set value. SG6932 provides complete protection functions, such as brownout protection and built-in latch for overvoltage and RI open/short. SG6932 — PFC / Forward PWM Controller Functional Description 0.47µF~4.7µF IAC Signal Figure 24 shows the IAC pin connected to input voltage by a resistor and the current, IAC, is the input for PFC multiplier. For the linear range of IAC 0~360μA, the range input voltage should be connected to a resistance over 1.2MΩ. Figure 25. Line-Voltage Detection on VRMS Pin Interleave Switching The SG6932 uses interleaved switching to synchronize the PFC and PWM stages. This reduces switching noise and spreads the EMI emissions. Figure 26 shows off-time (tOFF) inserted between the turn-off of the PFC gate drives and the turn-on of the PWM. OPFC OPWM TtOFF OFF Figure 24. Input Voltage Detection © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 Figure 26. Interleaved Switching www.fairchildsemi.com 13 The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching charge multiplier-divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 27 shows the control loop for the average-current-mode control circuit. The transconductance error amplifier has output impedance RO (>90kΩ) and a capacitor CEA (1μF ~ 10μF) connected to ground (as shown in Figure 28). This establishes a dominant pole f1 for the voltage loop: f1 = 1 2π × RO × CEA (5) The average total input power can be expressed as: PIN = VIN(rms ) × IIN(rms ) ∝ VRMS × IMO I × VEA ∝ VRMS × AC VRMS2 ∝ VRMS × (6) VIN × VEA R AC VRMS2 ∝ VEA From Equation 6, VEA, the output of the voltage error amplifier, actually controls the total input power and the power delivered to the load. SG6932 — PFC / Forward PWM Controller PFC Operation Multi-vector Error Amplifier Figure 27. Control Loop of PFC Stage The voltage-loop error amplifier is transconductance, which has high output impedance (> 90kΩ). A capacitor CEA (1μF ~ 10μF) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. The current source output from the switching charge multiplier-divider can be expressed as: I × VEA ( μA) IMO = K × AC VRMS2 (3) IMP, the current output from IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical, fixed-current sources. R2 and R3 are also identical and are used to pull HIGH the operating point of the IMP and IPFC pins when the voltage across RS goes negative with respect to ground. Figure 28 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds ±5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If RA is opened, SG6932 shuts off immediately to prevent extra-high voltage on the output capacitor. Through the differential amplification of the signal across RS, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulsewidth for PFC is determined. Through the average-current-mode control loop, the input current IS is proportional to IMO: IMO × R2 = IS × RS 3.15V (4) + According to Equation 4, the minimum value of R2 and maximum of RS can be determined because IMO should not exceed the specified maximum value. 2.85V RA There are different considerations in determining the value of the sense resistor RS. The value of RS should be small enough to reduce power consumption, but large enough to maintain the resolution. A current transformer (CT) may be used to improve the efficiency of high-power converters. FBPFC RB 3V + K IACxVEA 2 V RMS VEA C EA To achieve good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 3. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 SG69XX - Figure 28. Multi-Vector Error Amplifier www.fairchildsemi.com 14 Forward PWM and Slope Compensation SG6932 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 29 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on the ISENSE pin goes below VPK. The PWM stage is designed for forward power converters. Peak-current-mode control is used to optimize system performance. Slope compensation is added to stabilize the current loop. The SG6932 inserts a synchronized, positively sloped ramp at each switching cycle. The positively sloped ramp is represented by the voltage signal Vs-comp. In this example, the voltage of the ramp signal is 0.55V. The VRMS voltage determines the VPK voltage. The relationship between VPK and VRMS is shown in Figure 29. The amplitude of the constant current, IP, is determined by the internal current reference, IT, according to the following equation: IP = 2 × IT = 2 × 1.2(V ) RI 0.55V FBPWM (7) + IPWM Therefore, the peak current of the IS is given by (VRMS<1.05V): (I × RP ) − 0.2(V) IS _ peak = P RS + 0.7V SG69XX (8) Figure 31. Slope Compensation Limited Power Control SG6932 — PFC / Forward PWM Controller Cycle-by-Cycle Current Limiting Every time the output of power supply is shorted or overloaded, the FBPWM voltage increases. If the FB voltage is higher than a designed threshold of 4.2V for longer than 95ms, the PWM output is turned off. Gate Drivers SG6932 output stages are fast totem-pole gate drivers. The output driver is clamped by an internal 18V Zener diode to protect the power MOSFET. Figure 29. Current Limit Power-On Sequence and Soft-Start Protections The SG6932 is enabled whenever the line voltage is higher than the brownout threshold. Once the SG6932 is active, the PFC stage is enabled first. The PWM stage is enabled following a 4ms delay time after FBPFC voltage exceeds 2.7V. During start-up of PWM stage, the SS pin charges an external capacitor with a constant current source. The voltage on FBPWM is clamped by SS during start-up. In the event of a protection condition occurring and/or PWM being disabled, the SS pin is quickly discharged. The SG6932 provides full protection functions to prevent the power supply and the load from being damaged. The protection features include: PFC Feedback Over-Voltage Protection. When the PFC feedback voltage exceeds the over-voltage threshold, SG6932 inhibits the PFC switching signal. This protection prevents the PFC power converter from operating abnormally while the FBPFC pin is open. Second PFC Over-Voltage Protection (OVP_PFC). The PFC stage over-voltage input. The comparator disables the PFC output driver if this input exceeds 3.25V. This pin can be connected to the FBPFC pin or the PFC boost output through a divider network. This pin provides an extra input for PFC over-voltage protection. 3V 2.7V FBPFC PFC Feedback Under-Voltage Protection. The SG6932 stops the PFC switching signal whenever the PFC feedback voltage drops below the under-voltage threshold. This protection feature prevents the PFC power converter from experiencing abnormal conditions while the FBPFC pin is shorted to ground. OPFC 4ms OPWM VDD Over-Voltage Protection. The PFC and PWM stages are disabled whenever the VDD voltage exceeds the over-voltage threshold. Figure 30. Power-On Sequence © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 RI Pin Open / Short Protection. The RI pin is used to set the switching frequency and internal current reference. The PFC and PWM stages of SG6932 are disabled whenever the RI pin is short or open. www.fairchildsemi.com 15 The ground in the output capacitor CO is the major ground reference for power switching. To provide a good ground reference and reduce the switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance. SG6932 has a single ground pin, which prevents high sink currents in the output being returned separately. Good high-frequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG6932. A resistor (5 ~ 20Ω) is recommended, connected in series from the output to the gate of the MOSFET. The IPFC pin is connected directly to RS through R3 to improve noise immunity. Do not incorrectly connect to the ground trace 2. The IMP and ISENSE pins should also be connected directly via the resistors R2 and RP to another terminal of RS. Isolating the interference between the PFC and PWM stages is also important. Figure 32 shows an example of the PCB layout. The ground trace 1 is connected from the ground pin to the decoupling capacitor, which should be low impedance and as short as possible. The ground trace 2 provides a signal ground and should be connected directly to the decoupling capacitor CDD and/or to the ground pin. The ground trace 3 is independently tied from the decoupling capacitor to the PFC output capacitor CO. SG6932 — PFC / Forward PWM Controller PCB Layout Figure 32. PCB Layout © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 16 SG6932 — PFC / Forward PWM Controller Reference Circuit Figure 33. Reference Circuit © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 17 SG6932 — PFC / Forward PWM Controller Physical Dimensions 19.68 18.66 16 A 9 6.60 6.09 1 8 (0.40) TOP VIEW 0.38 MIN 5.33 MAX 8.13 7.62 3.42 3.17 3.81 2.92 2.54 0.35 0.20 0.58 A 0.35 1.78 1.14 15 0 8.69 17.78 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1 Figure 34. 16-pin Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 18 SG6932 — PFC / Forward PWM Controller Physical Dimensions (Continued) Figure 35. 16-Pin Small Outline Package (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 19 SG6932 — PFC / Forward PWM Controller © 2007 Fairchild Semiconductor Corporation SG6932 • Rev. 1.1.3 www.fairchildsemi.com 20