CY7C1021BNV33 64 K × 16 Static RAM 64 K × 16 Static RAM Features Functional Description[1] ■ 3.3 V operation (3.0 V–3.6 V) The CY7C1021BNV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. ■ High speed ❐ tAA = 15 ns ■ CMOS for optimum speed/power ■ Low Active Power ❐ 576 mW (max) ■ Low CMOS Standby Power ❐ 1.80 mW (max) ■ Automatic power-down when deselected ■ Independent control of upper and lower bits ■ Available in 44-pin TSOP II and 400-mil SOJ ■ Available in a 48-ball Mini BGA package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BNV33 is available in 400-mil-wide SOJ, standard 44-pin TSOP Type II, and 48-ball mini BGA packages. Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06433 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 8, 2011 [+] Feedback CY7C1021BNV33 Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 A8 A9 A10 A11 A12 A13 A14 A15 COLUMN DECODER BHE WE CE OE BLE Selection Guide -15 Maximum Access Time (ns) 15 Maximum Operating Current (mA) 160 Maximum CMOS Standby Current (mA) 0.5 Document #: 001-06433 Rev. *C Page 2 of 17 [+] Feedback CY7C1021BNV33 Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 Switching Waveforms ...................................................... 9 Read Cycle No. 1 ........................................................ 9 Read Cycle No. 2 (OE Controlled) .............................. 9 Write Cycle No. 1 (CE Controlled) ............................. 10 Write Cycle No. 2 (BLE or BHE Controlled) .............. 10 Write Cycle No. 2 (WE Controlled, OE LOW) ........... 11 Document #: 001-06433 Rev. *C Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 Page 3 of 17 [+] Feedback CY7C1021BNV33 Pin Configurations SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 37 36 35 34 33 32 31 30 29 28 27 13 14 15 16 17 18 19 20 21 22 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Mini BGA Top View Document #: 001-06433 Rev. *C 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O6 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A9 A10 A11 H A8 NC Page 4 of 17 [+] Feedback CY7C1021BNV33 DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied .......................................... –55 °C to +125 °C Supply Voltage on VCC to Relative GND[2] ...–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State[2] .................................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Operating Range Range Ambient Temperature VCC –40 °C to +85 °C 3.3 V 10% Industrial Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH VIL IIX Input Load Current IOZ Output Leakage Current ICC ISB1 ISB2 -15 Min Max Unit 2.4 – V – 0.4 V Input HIGH Voltage 2.2 VCC + 0.3 V V Input LOW Voltage[2] –0.3 0.8 V GND < VI < VCC –1 +1 A GND < VI < VCC, Output Disabled –1 +1 A VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC – 160 mA Automatic CE Power Down Current —TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 mA Automatic CE Power Down Current —CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 500 A Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz Max Unit 6 pF 8 pF Notes 2. Minimum voltage is –2.0 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06433 Rev. *C Page 5 of 17 [+] Feedback CY7C1021BNV33 AC Test Loads and Waveforms R 317 3.3 V R 317 3.3 V OUTPUT 3.0 V OUTPUT 30 pF R2 351 INCLUDING JIG AND SCOPE (a) 5 pF INCLUDING JIG AND SCOPE (b) OUTPUT Equivalent to: THÉVENIN EQUIVALENT Document #: 001-06433 Rev. *C R2 351 167 GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 10% 90% 10% Fall Time: 1 V/ns 1.73 V 30 pF Page 6 of 17 [+] Feedback CY7C1021BNV33 Switching Characteristics[4] Over the Operating Range Parameter Description -15 Min Max Unit READ CYCLE tRC Read Cycle Time 15 – ns tAA Address to Data Valid – 15 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 15 ns tDOE OE LOW to Data Valid – 7 ns tLZOE OE LOW to Low Z 0 – ns – 7 ns 3 – ns Z[5, 6] tHZOE OE HIGH to High tLZCE CE LOW to Low Z[6] Z[5, 6] tHZCE CE HIGH to High – 7 ns tPU CE LOW to Power-Up 0 – ns tPD CE HIGH to Power-Down – 15 ns tDBE Byte Enable to Data Valid – 7 ns tLZBE Byte Enable to Low Z 0 – ns Byte Disable to High Z – 7 ns tWC Write Cycle Time 15 – ns tSCE CE LOW to Write End 10 – ns tAW Address Set-Up to Write End 10 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 10 – ns tSD Data Set-Up to Write End 8 – ns tHD Data Hold from Write End 0 – ns tLZWE WE HIGH to Low Z[6] 3 – ns – 7 ns 9 – ns tHZBE WRITE CYCLE[7] Z[5, 6] tHZWE WE LOW to High tBW Byte Enable to End of Write Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 6. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 001-06433 Rev. *C Page 7 of 17 [+] Feedback CY7C1021BNV33 Data Retention Characteristics Over the Operating Range (L version only) Parameter Description Conditions[8] Min Max Unit 2.0 – V – 100 A Chip Deselect to Data Retention Time 0 – ns Operation Recovery Time 15 – ns VDR VCC for Data Retention ICCDR Data Retention Current tCDR[9] tR[10] VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 8. No input may exceed VCC + 0.5 V. 9. Tested initially and after any design or process changes that may affect these parameters. 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Document #: 001-06433 Rev. *C Page 8 of 17 [+] Feedback CY7C1021BNV33 Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Notes 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06433 Rev. *C Page 9 of 17 [+] Feedback CY7C1021BNV33 Switching Waveforms(continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06433 Rev. *C Page 10 of 17 [+] Feedback CY7C1021BNV33 Switching Waveforms(continued) Write Cycle No. 2 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE H X L L L X BLE BHE X X X High Z High Z Power-Down Standby (ISB) H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L I/O0–I/O7 I/O8–I/O15 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 001-06433 Rev. *C Page 11 of 17 [+] Feedback CY7C1021BNV33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) Ordering Code Package Diagram Package Type 15 CY7C1021BNV33L-15BAI 51-85096 48-ball Mini BGA (7 mm × 7 mm) CY7C1021BNV33L-15VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021BNV33L-15ZXI 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 02 1 BN V33 L - 15 XX I Temperature Range: I = Industrial Package Type: XX = BA or VX or ZX BA = 48-ball Mini BGA VX = 44-pin Molded SOJ (Pb-free) ZX = 44-pin TSOP Type II (Pb-free) Speed: 15 ns L = Low power V33 = Voltage range (3 V to 3.6 V) BN = 0.25 µm Technology 1 = Data width × 16-bits 02 = 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact local sales representative regarding availability of these parts. Document #: 001-06433 Rev. *C Page 12 of 17 [+] Feedback CY7C1021BNV33 Package Diagrams Figure 1. 48-ball FBGA (7 mm × 7 mm × 1.2 mm), 51-85096 51-85096 *I Figure 2. 44-pin (400-Mil) Molded SOJ, 51-85082 51-85082 *C Document #: 001-06433 Rev. *C Page 13 of 17 [+] Feedback CY7C1021BNV33 Package Diagrams(continued) Figure 3. 44-pin TSOP Type II, 51-85087 51-85087 *C Document #: 001-06433 Rev. *C Page 14 of 17 [+] Feedback CY7C1021BNV33 Acronyms Document Conventions Acronym Description Units of Measure BGA ball grid array CMOS complementary metal oxide semiconductor ns nano seconds Symbol Unit of Measure CE chip enable µs micro seconds FBGA Fine-Pitch Ball Grid Array ohms I/O input/output V Volts OE output enable µA micro Amperes SOJ small outline J-lead mA milli Amperes SRAM static random access memory mm milli meter TTL transistor-transistor logic MHz Mega Hertz TSOP thin small-outline package pF pico Farad WE write enable °C degree Celcius % percent mW milli Watts W Watts Document #: 001-06433 Rev. *C Page 15 of 17 [+] Feedback CY7C1021BNV33 Document History Page Document Title: CY7C1021BNV33 64 K × 16 Static RAM Document Number: 001-06433 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 423847 See ECN NXR New Data Sheet *A 2897061 03/22/10 AJU Removed obsolete parts from ordering information table Updated package diagrams *B 3109897 12/14/2010 AJU Added Ordering Code Definitions *C 3103073 03/08/2011 PRAS Document #: 001-06433 Rev. *C Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. Page 16 of 17 [+] Feedback CY7C1021BNV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06433 Rev. *C Revised March 8, 2011 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback