CY7C1081DV33 64-Mbit (4 M × 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 12 ns The CY7C1081DV33 is a high-performance CMOS static RAM organized as 4,194,304 words by 16 bits. ■ Low active power ❐ ICC = 300 mA at 12 ns ■ Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 100 mA ■ Operating voltages of 3.3 ± 0.3 V To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A21). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A21). ■ 2.0-V data retention ■ Automatic power-down when deselected ■ Transistor-transistor logic (TTL)-compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 48-ball fine ball grid array (FBGA) package To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1HIGH or CE2 LOW), the outputs are disabled (OE HIGH), both byte high enable and byte low enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Logic Block Diagram 4M × 16 RAM ARRAY SENSE AMPS A(10:0) ROW DECODER DATAIN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE A(21:11) OE CE2 CE1 BLE Cypress Semiconductor Corporation Document #: 001-53992 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 22, 2012 CY7C1081DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 Data Retention Characteristics ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Document #: 001-53992 Rev. *D Ordering Information ...................................................... 10 Ordering Code Definition ........................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 Page 2 of 12 CY7C1081DV33 Selection Guide Description Maximum access time –12 Unit 12 ns Maximum operating current 300 mA Maximum CMOS standby current 100 mA Pin Configuration Figure 1. 48-Ball FBGA (Top View) Document #: 001-53992 Rev. *D 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC I/O12 A21 A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O3 I/O15 A20 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 H Page 3 of 12 CY7C1081DV33 Maximum Ratings Current into outputs (LOW) ......................................... 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Static discharge voltage............. ...............................>2001 V (MIL-STD-883, Method 3015) Storage temperature ................................ –65 C to +150 C Latch-up current ...................................................... >140 mA Ambient temperature with power applied ........................................... –55 C to +125 C Operating Range Supply voltage on VCC relative to GND [1] ....–0.5 V to +4.6 V DC voltage applied to outputs in high-Z state[1] ................................... –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 °C to +85 °C 3.3 V 0.3 V 12 ns [1] DC input voltage ............................... –0.5 V to VCC + 0.5 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage voltage[1] –12 Unit Min Max 2.4 – V – 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V VIL Input LOW IIX Input leakage current GND < VIN < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC operating supply current VCC = Max, f = fmax = 1/tRC, IOUT = 0 mA CMOS levels – 300 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fmax – 120 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0, – 100 mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 32 pF 40 pF FBGA Unit 55 C/W 23.04 C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Note 1. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document #: 001-53992 Rev. *D Page 4 of 12 CY7C1081DV33 Figure 2. AC Test Loads and Waveforms[2] HIGH-Z CHARACTERISTICS: R1 317 3.3 V 50 VTH = 1.5 V OUTPUT Z0 = 50 OUTPUT 30 pF* INCLUDING JIG AND SCOPE (b) (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R2 351 5 pF* ALL INPUT PULSES 3.0 V 90% 90% 10% GND RISE TIME: > 1 V/ns 10% (c) FALL TIME: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit 2 – – V – – 100 mA VDR VCC for data retention ICCDR Data retention current tCDR[3] Chip deselect to data retention time 0 – – ns tR[4] Operation recovery time 12 – – ns VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR > 2 V 3.0 V tR CE1 CE2 Notes 2. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins to include reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document #: 001-53992 Rev. *D Page 5 of 12 CY7C1081DV33 AC Switching Characteristics Over the Operating Range [5] Parameter –12 Description Min Max Unit Read Cycle tpower VCC(typ) to the first access [6] 100 – s tRC Read cycle time 12 – ns tAA Address to data valid – 12 ns tOHA Data hold from address change 3 – ns tACE CE1 LOW and CE2 HIGH to Data Valid – 12 ns tDOE OE LOW to data valid – 7 ns tLZOE OE LOW to low-Z 1 – ns – 7 ns 3 – ns – 7 ns 0 – ns – 12 ns tHZOE OE HIGH to high-Z tLZCE [7] CE1 LOW and CE2 HIGH to low-Z tHZCE [7] CE1 HIGH and CE2 LOW to high-Z tPU [7] CE1 LOW and CE2 HIGH to power-up [8] [8] tPD CE1 HIGH and CE2 LOW to power-down tDBE Byte enable to data valid – 7 ns tLZBE Byte enable to low-Z 1 – ns Byte disable to high-Z – 7 ns tWC Write cycle time 12 – ns tSCE CE1 LOW and CE2 HIGH to write end 9 – ns tAW Address setup to write end 9 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 9 – ns tSD Data setup to write end 7 – ns tHD Data hold from write end tHZBE Write Cycle [9, 10] 0 – ns WE HIGH to low-Z [7] 3 – ns tHZWE WE LOW to high-Z [7] – 7 ns tBW Byte enable to end of write 9 – ns tLZWE Notes 5. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms[2], unless specified otherwise. 6. tpower is the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms[2]. 8. These parameters are guaranteed by design and are not tested. 9. The internal memory write time is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-53992 Rev. *D Page 6 of 12 CY7C1081DV33 Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled) [11, 12] tRC ADDRESS tAA tOHA PREVIOUS DATA VALID DATA I/O DATAOUT VALID Figure 5. Read Cycle 2 (OE Controlled) [12, 13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA I/O HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATAOUT VALID tPD tPU 50% ICC 50% ISB Notes 11. Device is continuously selected. OE, CE1 = VIL, BHE or BHE or both = VIL, and CE2 = VIH. 12. WE is HIGH for read cycle. 13. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 14. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. Document #: 001-53992 Rev. *D Page 7 of 12 CY7C1081DV33 Switching Waveforms (continued) Figure 6. Write Cycle 1 (CE Controlled) [15, 16, 17] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD DATA I/O tHD DATAIN VALID Figure 7. Write Cycle 2 (WE Controlled, OE LOW) [15, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD DATAIN VALID tLZWE Notes 15. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. 16. Data I/O is high impedance if OE or BHE, BLE or both = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-53992 Rev. *D Page 8 of 12 CY7C1081DV33 Switching Waveforms (continued) Figure 8. Write Cycle 3 (BLE or BHE Controlled) [18] tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD DATAIN VALID DATA I/O Truth Table CE1 CE2 OE WE BLE BHE I/O0 – I/O7 I/O8 – I/O15 Mode Power H X X X X X High-Z High-Z Power down Standby (ISB) X L X X X X High-Z High-Z Power down Standby (ISB) L H L H L L Data Out Data Out Read all bits Active (ICC) L H L H L H Data Out High-Z Read lower bits only Active (ICC) L H L H H L High-Z Data Out Read upper bits only Active (ICC) L H X L L L Data In Data In Write all bits Active (ICC) L H X L L H Data In High-Z Write lower bits only Active (ICC) L H X L H L High-Z Data In Write upper bits only Active (ICC) L H H H X X High-Z High-Z Selected, Outputs disabled Active (ICC) Note 18. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. Document #: 001-53992 Rev. *D Page 9 of 12 CY7C1081DV33 Ordering Information Speed (ns) 12 Ordering Code CY7C1081DV33-12BAXI Package Diagram 001-50044 Package Type 48-Ball FBGA (8 × 9.5 × 1.4 mm) (Pb-free) Operating Range Industrial Ordering Code Definition CY 7 C 1 08 1 D V33 - xx xxx x Temperature Range: x = I I = Industrial Package Type: xxx = BAX BAX = 48-ball FBGA (Pb-free) Speed: xx = 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 1 = Data width × 16 bits 08 = 64-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 001-53992 Rev. *D Page 10 of 12 CY7C1081DV33 Package Diagram Figure 9. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044) 001-50044 *C Acronyms Document Conventions Acronym Description Units of Measure CMOS complementary metal oxide semiconductor FBGA fine ball grid array °C degrees Celsius I/O input/output A microampere SRAM static random access memory mA milliampere TTL transistor-transistor logic MHz megahertz ns nanosecond pF picofarad V volt ohm W watt Document #: 001-53992 Rev. *D Symbol Unit of Measure Page 11 of 12 CY7C1081DV33 Document History Page Document Title: CY7C1081DV33, 64-Mbit (4 M × 16) Static RAM Document Number: 001-53992 Revision ECN Submission Date Orig. of Change ** 2746867 07/31/2009 VKN/AESA *A 3100499 12/02/2010 PRAS Updated Note 14. Changed datasheet status from Preliminary to Final. Updated Package Diagram and Sales, Solutions, and Legal Information. Added Acronyms, Document Conventions and Ordering Code Definition. Description of Change New datasheet *B 3178249 21/02/2011 PRAS Post to external web *C 3246293 05/04/2011 PRAS Modified Figure 44-B all FBGA pin configuration. *D 3720094 08/22/2012 TAVA Minor Text edits. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-53992 Rev. *D Revised August 22, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 12 of 12