CYPRESS CY7C1020CV26

CY7C1020CV26
512 Kb (32 K × 16) Static RAM
Features
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
■
Temperature range
❐ Automotive: –40°C to 125°C
■
High speed
❐ tAA = 15 ns
■
Optimized voltage range: 2.5V to 2.7V
■
Automatic power down when deselected
■
Independent control of upper and lower bits
■
CMOS for optimum speed and power
■
Package offered: 44-pin TSOP II
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory appears on I/O9 to I/O16. See
the Truth Table on page 7 for a complete description of read
and write modes.
Functional Description
The CY7C1020CV26 is a high performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
The input/output pins (I/O1 through I/O16) are placed in a high
impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020CV26 is available in a standard 44-pin TSOP
Type II.
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-05406 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 14, 2010
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CY7C1020CV26
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View)
Selection Guide
CY7C1020CV26-15
Unit
Maximum Access Time
Description
15
ns
Maximum Operating Current
100
mA
5
mA
Maximum CMOS Standby Current
Document #: 38-05406 Rev. *C
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CY7C1020CV26
DC Input Voltage[1] .................................. –0.5V to VCC+0.5V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65C to +150C
Ambient Temperature with
Power Applied ............................................ –55C to +125C
Supply Voltage on VCC to Relative GND[1] .....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[1] ...................................... –0.5V to VCC+0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... > 200 mA
Operating Range
Range
Automotive
Ambient
Temperature
VCC
–40C to +125C
2.5V to 2.7V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Minimum,
IOH = –1.0 mA
VOL
Output LOW Voltage
VCC = Minimum,
IOL = 1.0 mA
VIH
Input HIGH Voltage
Voltage[1]
CY7C1020CV26
Min
Max
2.3
Unit
V
0.4
V
2.0
VCC + 0.3
V
VIL
Input LOW
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–5
+5
A
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
–5
+5
A
IOS[2]
Output Short Circuit Current
VCC = Maximum, VOUT = GND
–300
mA
ICC
VCC Operating Supply Current
VCC = Maximum, IOUT = 0 mA,
f = fMAX = 1/tRC
100
mA
ISB1
Automatic CE Power Down
Current —TTL Inputs
Maximum VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
40
mA
ISB2
Automatic CE Power Down
Current —CMOS Inputs
Maximum VCC,
CE > VCC – 0.3V, VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
5
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25C, f = 1 MHz,
VCC = 2.6V
Max
Unit
8
pF
8
pF
Notes
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05406 Rev. *C
Page 3 of 11
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CY7C1020CV26
Figure 2. AC Test Loads and Waveforms[4]
ALL INPUT PULSES
R 1830 
2.6V
2.5V
OUTPUT
R2
1976 
30 pF
GND
90%
90%
10%
10%
Fall Time:1 V/ns
Rise Time: 1 V/ns
(a)
(b)
AC Switching Characteristics Over the Operating Range
Parameter
Description
CY7C1020CV26
Min
Max
Unit
READ CYCLE
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
15
ns
tDOE
OE LOW to Data Valid
7
ns
Z[5]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[5, 6]
Z[5]
tLZCE
CE LOW to Low
tHZCE
CE HIGH to High Z[5, 6]
tPU[7]
tPD[7]
CE LOW to Power Up
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
ns
15
3
ns
0
ns
7
3
ns
ns
7
0
CE HIGH to Power Down
ns
ns
ns
15
ns
7
ns
0
ns
7
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
10
ns
tAW
Address Setup to Write End
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
10
ns
tSD
Data Setup to Write End
8
ns
tHD
Data Hold from Write End
0
ns
[5]
tLZWE
WE HIGH to Low Z
tHZWE
WE LOW to High Z[5, 6]
tBW
Byte Enable to End of Write
3
ns
4
10
ns
ns
Notes
4. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.5V and transmission line loads as in
(a) of AC Test Loads.
5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
7. This parameter is guaranteed by design and is not tested.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Document #: 38-05406 Rev. *C
Page 4 of 11
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CY7C1020CV26
Switching Waveforms
Figure 3. Read Cycle No. 1[9, 10]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
IICC
CC
IISB
SB
Notes
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05406 Rev. *C
Page 5 of 11
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CY7C1020CV26
Switching Waveforms
Figure 5. Write Cycle No. 1 (CE Controlled)[12, 13]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Figure 6. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
12. Data I/O is high impedance if OE or BHE and BLE = VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document #: 38-05406 Rev. *C
Page 6 of 11
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CY7C1020CV26
Switching Waveforms
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read – All bits
Active (ICC)
L
H
Data Out
High Z
Read – Lower bits only
Active (ICC)
H
L
High Z
Data Out
Read – Upper bits only
Active (ICC)
L
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High Z
Write – Lower bits only
Active (ICC)
H
L
High Z
Data In
Write – Upper bits only
Active (ICC)
L
X
L
I/O1–I/O8
I/O9–I/O16
Mode
Power
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05406 Rev. *C
Page 7 of 11
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CY7C1020CV26
Ordering Information
Speed
(ns)
15
Ordering Code
Package
Name
CY7C1020CV26-15ZSXE
Z44
Package Type
44-pin TSOP Type II (Pb-free)
Operating
Range
Automotive
Ordering Code Definitions
CY 7 C 1 02 0
C V26 - 15 ZSX E
Temperature Range:
E = Automotive
Package Type:
ZSX = 44-pin TSOP Type II (Pb-free)
Speed: XX = 15 ns
V26 = Voltage range (2.5 V to 2.7 V)
C = 0.16 µm Technology
0 = Data width × 16-bits
02 = 512-Kbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document #: 38-05406 Rev. *C
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CY7C1020CV26
Package Diagrams
Figure 8. 44-Pin TSOP II
51-85087 *C
Document #: 38-05406 Rev. *C
Page 9 of 11
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CY7C1020CV26
Document History Page
Document Title: CY7C1020CV26 512 Kb (32 K × 16) Static RAM
Document Number: 38-05406
REV.
ECN NO.
Submission
Date
Orig. of
Change
**
128060
07/30/03
EJH
Customized data sheet to meet special requirements for CG5988AF
Automotive temperature range: –40°C / +125°C
*A
352999
See ECN
SYT
Removed ‘CG5988AF’ from the Datasheet
Edited the features section for better structure on Page 1
Edited the title to include the mention of ‘512Kb’
*B
2903127
04/01/2010
VIVG
Updated template.
Updated package diagram.
Added Sales, Solutions, and Legal Information.
*C
3109992
12/14/2010
AJU
Added Ordering Code Definitions.
Document #: 38-05406 Rev. *C
Description of Change
Page 10 of 11
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CY7C1020CV26
Sales, Solutions, and Legal Information
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05406 Rev. *C
Revised December 14, 2010
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