CYPRESS CY7C1021D

CY7C1021D
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
Functional Description
■
Temperature Ranges:
❐ Industrial: –40 °C to 85 °C
The CY7C1021D is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected. The input and output pins (IO0
through IO15) are placed in a high impedance state when the
device is deselected (CE HIGH), outputs are disabled (OE
HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during
a write operation (CE LOW and WE LOW).
■
Pin and Function Compatible with CY7C1021B
■
High Speed
❐ tAA = 10 ns
■
Low Active Power
❐ ICC = 80 mA at 10 ns
■
Low CMOS Standby Power
❐ ISB2 = 3 mA
■
2.0 V Data Retention
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Independent Control of Upper and Lower Bits
■
Available in Pb-free 44-pin 400-Mil Wide Molded SOJ and
44-pin TSOP II Packages
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A15).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the Truth Table on page 10 for a
complete description of read and write modes.
Logic Block Diagram
64K x 16
RAM Array
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
IO0–IO7
IO8–IO15
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05462 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 7, 2011
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CY7C1021D
Contents
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Switching Characteristics ................................................ 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document #: 38-05462 Rev. *J
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY7C1021D
Pin Configuration
Figure 1. 44-pin SOJ / 44-pin TSOP II (Top View) [1]
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
NC
Selection Guide
Description
-10 (Industrial)
Unit
Maximum Access Time
10
ns
Maximum Operating Current
80
mA
Maximum CMOS Standby Current
3
mA
Note
1. NC pins are not connected on the die.
Document #: 38-05462 Rev. *J
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CY7C1021D
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Operating Range
Supply Voltage on
VCC to Relative GND[2] ................................–0.5 V to +6.0 V
Range
DC Voltage Applied to Outputs
in High Z State [2] ................................ –0.5 V to VCC + 0.5 V
Industrial
Ambient
Temperature
VCC
Speed
–40 C to +85 C
5 V  10%
10 ns
Electrical Characteristics
Over the Operating Range
Parameter
Description
-10 (Industrial)
Test Conditions
VOH
Output HIGH Voltage
IOH = –4.0 mA
VOL
Output LOW Voltage
IOL = 8.0 mA
VIH
Input HIGH Voltage
[2]
Unit
Min
Max
2.4
–
V
–
0.4
V
2.2
VCC + 0.5 V
V
0.5
0.8
V
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
1
+1
A
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
1
+1
A
ICC
VCC Operating Supply Current
VCC = Max, IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
–
80
mA
83 MHz
–
72
mA
66 MHz
–
58
mA
40 MHz
–
37
mA
ISB1
Automatic CE Power Down
Current —TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax
–
10
mA
ISB2
Automatic CE Power Down
Current —CMOS Inputs
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or
VIN < 0.3 V, f = 0
–
3
mA
Note
2. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
Document #: 38-05462 Rev. *J
Page 4 of 16
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CY7C1021D
Capacitance
Parameter [3]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
TA = 25C, f = 1 MHz, VCC = 5.0 V
Unit
8
pF
8
pF
Thermal Resistance
Parameter [3]
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
44-pin SOJ
44-pin TSOP II Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
59.52
53.91
C/W
36.75
21.24
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
ALL INPUT PULSES
3.0 V
Z = 50 
90%
OUTPUT
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
90%
10%
10%
GND
1.5 V
Rise Time: 3 ns
(a)
(b)
Fall Time: 3 ns
High-Z characteristics:
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
R2
255
5 pF
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document #: 38-05462 Rev. *J
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CY7C1021D
Switching Characteristics
Over the Operating Range
Parameter [5]
Description
-10 (Industrial)
Min
Max
Unit
Read Cycle
tpower [6]
VCC(typical) to the first access
100
–
s
tRC
Read Cycle Time
10
–
ns
tAA
Address to Data Valid
–
10
ns
tOHA
Data Hold from Address Change
3
–
ns
tACE
CE LOW to Data Valid
–
10
ns
tDOE
OE LOW to Data Valid
–
5
ns
0
–
ns
–
5
ns
3
–
ns
–
5
ns
OE LOW to Low Z
tLZOE
[7]
OE HIGH to High Z
tHZOE
tLZCE
CE LOW to Low Z
[7, 8]
[7]
[7, 8]
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-Up
0
–
ns
tPD
CE HIGH to Power-Down
–
10
ns
tDBE
Byte Enable to Data Valid
–
5
ns
tLZBE
Byte Enable to Low Z
0
–
ns
Byte Disable to High Z
–
5
ns
tWC
Write Cycle Time
10
–
ns
tSCE
CE LOW to Write End
7
–
ns
tHZBE
Write Cycle
[9]
tAW
Address Setup to Write End
7
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Setup to Write Start
0
–
ns
tPWE
WE Pulse Width
7
–
ns
tSD
Data Setup to Write End
6
–
ns
tHD
Data Hold from Write End
0
–
ns
WE HIGH to Low Z
[7]
3
–
ns
tHZWE
WE LOW to High Z
[7, 8]
–
5
ns
tBW
Byte Enable to End of Write
7
–
ns
tLZWE
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance
state.
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates
the write.
Document #: 38-05462 Rev. *J
Page 6 of 16
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CY7C1021D
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR [10]
Chip Deselect to Data Retention Time
tR
[11]
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Operation Recovery Time
Min
Max
Unit
2.0
–
V
–
3
mA
0
–
ns
tRC
–
ns
Data Retention Waveform
DATA RETENTION MODE
4.5 V
VCC
VDR > 2 V
4.5 V
tR
tCDR
CE
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [12, 13]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Notes
10. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
12. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
13. WE is HIGH for read cycle.
Document #: 38-05462 Rev. *J
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CY7C1021D
Switching Waveforms (continued)
Figure 4. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05462 Rev. *J
Page 8 of 16
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CY7C1021D
Switching Waveforms (continued)
Figure 5. Write Cycle No. 1 (CE Controlled) [16, 17]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Figure 6. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
16. Data I/O is high impedance if OE or BHE and/or BLE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document #: 38-05462 Rev. *J
Page 9 of 16
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CY7C1021D
Switching Waveforms (continued)
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
IO0–IO7
IO8–IO15
H
X
X
X
X
High Z
High Z
L
L
H
L
L
Data Out
Data Out
L
H
Data Out
H
L
L
L
X
L
Mode
Power
Power Down
Standby (ISB)
Read – All bits
Active (ICC)
High Z
Read – Lower bits only
Active (ICC)
High Z
Data Out
Read – Upper bits only
Active (ICC)
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High Z
Write – Lower bits only
Active (ICC)
H
L
High Z
Data In
Write – Upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05462 Rev. *J
Page 10 of 16
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CY7C1021D
Ordering Information
Speed
(ns)
10
Package
Diagram
Package Type
Operating
Range
CY7C1021D-10VXI
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
Industrial
CY7C1021D-10ZSXI
51-85087 44-pin TSOP Type II (Pb-free)
Ordering Code
Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7 C 1 02 1
D - 10 XX
X
I
Temperature Range: I
I = Industrial
Pb-free
Package Type: XX = V or ZS
V = 44-pin Molded SOJ
ZS = 44-pin TSOP Type II
Speed: 10 ns
D = C9, 90 nm Technology
1 = Data width × 16-bits
02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document #: 38-05462 Rev. *J
Page 11 of 16
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CY7C1021D
Package Diagrams
Figure 8. 44-pin Molded SOJ (400-Mil) V44.4, 51-85082
51-85082 *C
Document #: 38-05462 Rev. *J
Page 12 of 16
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CY7C1021D
Package Diagrams (continued)
Figure 9. 44-pin TSOP Z44-II, 51-85087
51-85087 *C
Document #: 38-05462 Rev. *J
Page 13 of 16
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CY7C1021D
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
I/O
input/output
MHz
Mega Hertz
OE
output enable
µA
micro Amperes
SOJ
small outline J-lead
µs
micro seconds
SRAM
static random access memory
mA
milli Amperes
TSOP
thin small outline package
mm
milli meter
TTL
transistor-transistor logic
ms
milli seconds
WE
write enable
ns
nano seconds

ohms
%
percent
pF
pico Farad
V
Volts
W
Watts
%
percent
Document #: 38-05462 Rev. *J
Symbol
Unit of Measure
Page 14 of 16
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CY7C1021D
Document History Page
Document Title: CY7C1021D, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05462
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
201560
SWI
See ECN
Advance Information data sheet for C9 IPP
*A
233695
RKF
See ECN
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B
263769
RKF
See ECN
Added Data Retention Characteristics Table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C
307601
RKF
See ECN
Reduced Speed bins to –10 and –12 ns
*D
520647
VKN
See ECN
Converted from Preliminary to Final
Removed Commercial Operating range
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Added Automotive Product Information
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
802877
VKN
See ECN
Changed Commercial operating range ICC spec from 60 mA to 80 mA for
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to
37 mA for 40MHz
Changed Automotive operating range ICC spec from 100 mA to 120 mA for
83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
*F
2751755
08/14/09
*G
2898399
03/24/2010
AJU
Updated Package Diagrams
*H
3109897
12/14/2010
AJU
Added Ordering Code Definitions.
*I
3245199
04/30/2011
PRAS
*J
3086499
06/07/2011
AJU
Document #: 38-05462 Rev. *J
VKN/PYRS For 12 ns speed, changed ICC spec from 120 mA to 90 mA
For 12 ns speed, changed ISB1 spec from 50 mA to 10 mA and ISB2 spec from
15 mA to 10 mA
Dislodged Automotive information to new datasheet (001-68372).
Removed the Note “Automotive Product Information is Preliminary.” in page 3.
Added Acronyms and Units of Measure.
Updated in new template.
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Page 15 of 16
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CY7C1021D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05462 Rev. *J
Revised June 7, 2011
Page 16 of 16
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