Click Here & Upgrade PDF Complete \\\ Expanded Features Unlimited Pages Documents SPICE Device Model Si4920DY Vishay Siliconix Dual N-Channel 30-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71008 18-May-04 www.vishay.com 1 Click Here & Upgrade Expanded Features Unlimited Pages PDF Complete SPICE Device Model Si4920DY Vishay Siliconix Documents SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250 µA 2 ID(on) VDS ≥ 5 V, VGS = 10 V 238 VGS = 10 V, ID = 6.9 A 0.020 0.020 VGS = 4.5 V, ID = 5.8 A 0.023 0.026 25 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistance Forward Transconductance a a a Diode Forward Voltage rDS(on) gfs VDS = 15 V, ID = 6.9 A 23 VSD IS = 1.7 A, VGS = 0 V 0.72 V A Ω S V Dynamicb Total Gate Charge Qg 29 VDS = 15 V, VGS = 10 V, ID = 6.9 A 30 Gate-Source Charge Qgs 7.5 7.5 Gate-Drain Charge Qgd 3.5 3.5 Turn-On Delay Time td(on) 10 12 13 10 15 60 32 15 32 50 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω IF = 1.7 A, di/dt = 100 A/µs nC Ns Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2% b. Guaranteed by design, not subject to production testing www.vishay.com 2 Document Number: 71008 18-May-04 Click Here & Upgrade PDF Complete \\\ Expanded Features Unlimited Pages Documents SPICE Device Model Si4920DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71008 18-May-04 www.vishay.com 3