SPICE Device Model SUP/SUB70N03-09BP Vishay Siliconix N-Channel 30-V (D-S), 175°C MOSFET PWM Optimized CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71701 02-Oct-01 www.vishay.com 1 SPICE Device Model SUP/SUB70N03-09BP Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbo l Test Condition Simulate d Data Measured Data VGS(th) VDS = VGS, ID = 250µA 1.5 ID(on) VDS = 5 V, VGS = 10V 604 VGS = 10V, ID = 30A 0.007 0.007 VGS = 4.5V, ID = 20A 0.010 0.010 Unit Static Gate Threshold Voltage a On-State Drain Current Drain-Source On-State a Resistance rDS(on) VGS = 10V, ID = 30A, TJ = 125°C VGS = 10V, ID = 30A, TJ = 175°C a Forward Transconductance V A Ω 0.0085 0.0095 gfs VDS = 15V, ID = 30A 45 45 S a VSD IS = 70A, VGS = 0 V 0.92 1.1 V Input Capacitance Ciss 1484 1500 Output Capacitance Coss 465 530 Reverse Transfer Capacitance Crss 153 240 15 15.5 Forward Voltage Dynamic b Total Gate Charge c Qg c Gate-Source Charge Gate-Drain Charge c Turn-On Delay Time Rise Time Fall Time Qgd c c Turn-Off Delay Time Qgs td(on) tr c c Reverse Recovery Time td(off) tf trr VGS = 0V, VDS = 25V, f = 1 MHz VDS = 15V, VGS = 5V, ID = 70A VDD = 15V, RL = 0.21Ω ID ≅ 70A, VGEN = 10V, RG = 2.5Ω IF = 70A, di/dt = 100 A/µs 5 5 6 6 10 10 13 8 26 25 34 9 20 30 pf nC ns Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 71701 02-Oct-01 SPICE Device Model SUP/SUB70N03-09BP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71701 02-Oct-01 www.vishay.com 3