SPICE Device Model SUP/SUB85N04-03 Vishay Siliconix N-Channel 40-V (D-S) 175°C MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71615 18-Apr-01 www.vishay.com 1 SPICE Device Model SUP/SUB85N04-03 Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250 µA 1.9 ID(on) VDS = 5 V, VGS = 10 V 1410 VGS = 10V, ID = 30A 0.0026 0.0029 0.0044 Unit Static Gate Threshold Voltage a On-State Drain Current a Drain-Source On-State Resistance a rDS(on) VGS = 4.5V, ID = 20A 0.0040 VGS = 10V, ID = 30A, TJ = 125°C 0.0037 VGS = 10V, ID = 30A, ,TJ = 175°C 0.0043 V A Forward Transconductance gfs VDS = 15V, ID = 30 A 87 Forward Voltage a VSD IS = 85A, VGS = 0 V 0.92 1.1 6809 6860 1347 1320 Ω S V Dynamic b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 823 800 Total Gate Chargeb Qg 165 165 Gate-Source Chargeb Qgs 25 25 b VGS = 0V, VDS = 25V, f = 1 MHz VDS = 30V, VGS = 10V, ID = 85A Gate-Drain Charge Qgd 55 55 Turn-On Delay Time b td(on) 57 15 103 90 Rise Time b Turn-Off Delay Time tr b td(off) Fall Time b tf Reverse Recovery Time trr VDD = 30V, RL = 0.35Ω ID ≅ 85A, VGEN = 10V, RG = 2.5 Ω IF = 85A, di/dt = 100 A/µs 120 95 193 125 65 60 pf nC ns Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71615 18-Apr-01 SPICE Device Model SUP/SUB85N04-03 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°c UNLESS OTHERWISE NOTED) Document Number: 7xxxx dd-Mon-yr www.vishay.com 3