SPICE Device Model SUD50N03-10P Vishay Siliconix N-Channel 30-V (D-S), 175°°C MOSFET PWM Optimized CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Model Subcircuit Schematic) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71725 21-Oct-98 www.vishay.com 1 SPICE Device Model SUD50N03-10P Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit VGS(th) VDS = VGS, ID = 250 µA 1.59 V ID(on) VDS = 5 V, VGS = 10 V 593 A VGS = 10 V, ID = 25 A 0.0076 Static Gate Threshold Voltage a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance a Diode Forward Voltage Dynamic rDS(on) VGS = 4.5 V, ID = 15 A 0.012 VGS = 10 V, ID = 15 A, Tj = 125°C 0.012 VGS = 10 V, ID = 15 A, Tj = 175°C 0.014 Ω gfs VDS = 15 V, ID = 15 A 34 S VSD IS = 50 A, VGS = 0 V 0.91 V b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 2699 VGS = 0 V, VDS = 25 V, f = 1 MHz 652 Total Gate Chargec Qg Gate-Source Chargec Qgs Gate-Drain Chargec Qgd Turn-On Delay Timec td(on) 17 tr 7.5 Rise Timec Turn-Off Delay Timec c td(off) Fall Time tf Source-Drain Reverse Recovery Time trr pf 282 45 VDS = 15 V, VGS = 10 V, ID = 50 A 8.5 nC 9.5 VDD = 15 V, RL = 0.3 Ω ID ≅ 50 A, VGEN = 10 V, RG = 2.5 Ω 34 ns 11 IF = 50 A, di/dt = 100 A/µs 45 Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2% b. Guaranteed by design, not subject to production testing c. Independent of operating temperature www.vishay.com 2 Document Number: 71725 21-Oct-98 SPICE Device Model SUD50N03-10P Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71725 21-Oct-98 www.vishay.com 3