TI SM470R1B1MHFQS

SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
16/32-BIT RISC FLASH MICROCONTROLLER
FEATURES
1
•
•
2
•
•
•
•
•
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
•
High-Performance Static CMOS Technology
SM470R1x 16/32-Bit RISC Core ( ARM7TDMI™)
– 60-MHz System Clock (Pipeline Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
Integrated Memory
– 1M-Byte Program Flash
– Two Banks With 16 Contiguous Sectors
– 64K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial Temperature Range
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
Twelve Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Three Serial Communication Interfaces
(SCIs)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Two High-End CAN Controllers (HECC)
– 32-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Five Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
12-Channel, 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55-µs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
Flexible Interrupt Handling
Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
46 Dedicated General-Purpose I/O (GIO) Pins
and 47 Additional Peripheral I/Os
Sixteen External Interrupts
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1 (1) (JTAG) Test-Access Port
Available in KGD and HFQ Packages
•
•
•
•
•
•
•
•
•
(1)
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
(2)
2
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/220°C)
Temperature Range (2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures.
Custom temperature ranges available
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
ORDERING INFORMATION (1)
TA
–55°C to 220°C
(1)
(2)
PACKAGE
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
KGD
SM470R1B1MKGDS1
SM470R1B1MKGDS1
CQFP-HFQ
TBD
TBD
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DIE LAYOUT
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
Table 1. Bare Die Information
DIE SIZE
DIE PAD SIZE
DIE PAD
COORDINATES (1)
DIE
THICKNESS
DIE PAD
COMPOSITION
BACKSIDE
FINISH
BACKSIDE
POTENTIAL
208.858 x 211.890 mils/
5304.99 x 5382.01 µm
65.1 x 65.1(µm)
See Table 2
11 mils
AlCu
Silicon with
backgrind
Ground
(1)
Pads 12, 22, 26, 136, 143, 146, 149 and 152 are test pads, no connections required. It is highly recommended to leave them open.
Copyright © 2009–2011, Texas Instruments Incorporated
3
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 2. Bond Pad Coordinates
PAD NO.
PAD SIZE (µm)
Y MIN
X MAX
Y MAX
X
Y
1
178.955
10.08
244.055
75.18
65.1
65.1
2
368.2
10.08
433.3
75.18
65.1
65.1
3
557.445
10.08
622.545
75.18
65.1
65.1
4
664.335
10.08
729.435
75.18
65.1
65.1
5
853.58
10.08
918.68
75.18
65.1
65.1
6
1042.825
10.08
1107.925
75.18
65.1
65.1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
7
4
BOND PAD COORDINATES (µm)
X MIN
1149.715
10.08
1214.815
75.18
65.1
65.1
1338.96
10.08
1404.06
75.18
65.1
65.1
1445.85
10.08
1510.95
75.18
65.1
65.1
1552.74
10.08
1617.84
75.18
65.1
65.1
1659.63
10.08
1724.73
75.18
65.1
65.1
1766.52
10.08
1831.62
75.18
65.1
65.1
1866.2
10.08
1931.3
75.18
65.1
65.1
1965.88
10.08
2030.98
75.18
65.1
65.1
2065.56
10.08
2130.66
75.18
65.1
65.1
2165.24
10.08
2230.34
75.18
65.1
65.1
2272.13
10.08
2337.23
75.18
65.1
65.1
2396.1
10.08
2461.2
75.18
65.1
65.1
2520.07
10.08
2585.17
75.18
65.1
65.1
2626.96
10.08
2692.06
75.18
65.1
65.1
2733.85
10.08
2798.95
75.18
65.1
65.1
2840.74
10.08
2905.84
75.18
65.1
65.1
2947.63
10.08
3012.73
75.18
65.1
65.1
3054.52
10.08
3119.62
75.18
65.1
65.1
3243.765
10.08
3308.865
75.18
65.1
65.1
3350.655
10.08
3415.755
75.18
65.1
65.1
3539.9
10.08
3605
75.18
65.1
65.1
3646.79
10.08
3711.89
75.18
65.1
65.1
3746.47
10.08
3811.57
75.18
65.1
65.1
3846.15
10.08
3911.25
75.18
65.1
65.1
3953.04
10.08
4018.14
75.18
65.1
65.1
4142.285
10.08
4207.385
75.18
65.1
65.1
4331.53
10.08
4396.63
75.18
65.1
65.1
4431.21
10.08
4496.31
75.18
65.1
65.1
4530.89
10.08
4595.99
75.18
65.1
65.1
4630.57
10.08
4695.67
75.18
65.1
65.1
4730.25
10.08
4795.35
75.18
65.1
65.1
4829.93
10.08
4895.03
75.18
65.1
65.1
39
4936.82
10.08
5001.92
75.18
65.1
65.1
40
5150.04
178.955
5215.14
244.055
65.1
65.1
41
5150.04
368.2
5215.14
433.3
65.1
65.1
42
5150.04
557.445
5215.14
622.545
65.1
65.1
43
5150.04
666.26
5215.14
731.36
65.1
65.1
44
5150.04
855.505
5215.14
920.605
65.1
65.1
45
5150.04
1044.75
5215.14
1109.85
65.1
65.1
46
5150.04
1153.565
5215.14
1218.665
65.1
65.1
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 2. Bond Pad Coordinates (continued)
PAD NO.
BOND PAD COORDINATES (µm)
X MIN
Y MIN
X MAX
PAD SIZE (µm)
Y MAX
X
Y
47
5150.04
1262.38
5215.14
1327.48
65.1
65.1
48
5150.04
1371.195
5215.14
1436.295
65.1
65.1
49
5150.04
1480.01
5215.14
1545.11
65.1
65.1
50
5150.04
1669.255
5215.14
1734.355
65.1
65.1
51
5150.04
1778.07
5215.14
1843.17
65.1
65.1
52
5150.04
1886.885
5215.14
1951.985
65.1
65.1
54
55
56
57
58
59
60
61
62
63
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
53
5150.04
1995.7
5215.14
2060.8
65.1
65.1
5150.04
2184.945
5215.14
2250.045
65.1
65.1
5150.04
2293.76
5215.14
2358.86
65.1
65.1
5150.04
2402.575
5215.14
2467.675
65.1
65.1
5150.04
2511.39
5215.14
2576.49
65.1
65.1
5150.04
2700.635
5215.14
2765.735
65.1
65.1
5150.04
2809.45
5215.14
2874.55
65.1
65.1
5150.04
2998.695
5215.14
3063.795
65.1
65.1
5150.04
3187.94
5215.14
3253.04
65.1
65.1
5150.04
3296.755
5215.14
3361.855
65.1
65.1
5150.04
3486
5215.14
3551.1
65.1
65.1
5150.04
3675.245
5215.14
3740.345
65.1
65.1
5150.04
3784.06
5215.14
3849.16
65.1
65.1
5150.04
3973.305
5215.14
4038.405
65.1
65.1
5150.04
4082.12
5215.14
4147.22
65.1
65.1
5150.04
4190.935
5215.14
4256.035
65.1
65.1
5150.04
4299.75
5215.14
4364.85
65.1
65.1
5150.04
4408.565
5215.14
4473.665
65.1
65.1
5150.04
4517.38
5215.14
4582.48
65.1
65.1
5150.04
4626.195
5215.14
4691.295
65.1
65.1
5150.04
4735.01
5215.14
4800.11
65.1
65.1
5150.04
4843.825
5215.14
4908.925
65.1
65.1
5150.04
4952.64
5215.14
5017.74
65.1
65.1
4981.165
5148.85
5046.265
5213.95
65.1
65.1
4862.935
5148.85
4928.035
5213.95
65.1
65.1
4738.965
5148.85
4804.065
5213.95
65.1
65.1
4614.995
5148.85
4680.095
5213.95
65.1
65.1
4496.765
5148.85
4561.865
5213.95
65.1
65.1
4378.535
5148.85
4443.635
5213.95
65.1
65.1
4189.29
5148.85
4254.39
5213.95
65.1
65.1
4000.045
5148.85
4065.145
5213.95
65.1
65.1
3881.815
5148.85
3946.915
5213.95
65.1
65.1
85
3757.845
5148.85
3822.945
5213.95
65.1
65.1
86
3639.615
5148.85
3704.715
5213.95
65.1
65.1
87
3450.37
5148.85
3515.47
5213.95
65.1
65.1
88
3332.14
5148.85
3397.24
5213.95
65.1
65.1
89
3213.91
5148.85
3279.01
5213.95
65.1
65.1
90
3095.68
5148.85
3160.78
5213.95
65.1
65.1
91
2906.435
5148.85
2971.535
5213.95
65.1
65.1
92
2717.19
5148.85
2782.29
5213.95
65.1
65.1
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Copyright © 2009–2011, Texas Instruments Incorporated
5
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 2. Bond Pad Coordinates (continued)
PAD NO.
PAD SIZE (µm)
Y MIN
X MAX
Y MAX
X
Y
93
2598.96
5148.85
2664.06
5213.95
65.1
65.1
94
2480.73
5148.85
2545.83
5213.95
65.1
65.1
95
2362.5
5148.85
2427.6
5213.95
65.1
65.1
96
2244.27
5148.85
2309.37
5213.95
65.1
65.1
97
2126.04
5148.85
2191.14
5213.95
65.1
65.1
98
1936.795
5148.85
2001.895
5213.95
65.1
65.1
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
99
100
1747.55
5148.85
1812.65
5213.95
65.1
65.1
1629.32
5148.85
1694.42
5213.95
65.1
65.1
1511.09
5148.85
1576.19
5213.95
65.1
65.1
1321.845
5148.85
1386.945
5213.95
65.1
65.1
1203.615
5148.85
1268.715
5213.95
65.1
65.1
1085.385
5148.85
1150.485
5213.95
65.1
65.1
967.155
5148.85
1032.255
5213.95
65.1
65.1
843.185
5148.85
908.285
5213.95
65.1
65.1
719.215
5148.85
784.315
5213.95
65.1
65.1
595.245
5148.85
660.345
5213.95
65.1
65.1
471.275
5148.85
536.375
5213.95
65.1
65.1
347.305
5148.85
412.405
5213.95
65.1
65.1
223.335
5148.85
288.435
5213.95
65.1
65.1
10.08
4979.975
75.18
5045.075
65.1
65.1
65.1
10.08
4868.5
75.18
4933.6
65.1
10.08
4757.025
75.18
4822.125
65.1
65.1
10.08
4645.55
75.18
4710.65
65.1
65.1
10.08
4534.075
75.18
4599.175
65.1
65.1
10.08
4410.105
75.18
4475.205
65.1
65.1
10.08
4286.135
75.18
4351.235
65.1
65.1
10.08
4162.165
75.18
4227.265
65.1
65.1
10.08
4038.195
75.18
4103.295
65.1
65.1
10.08
3912.825
75.18
3977.925
65.1
65.1
10.08
3801.35
75.18
3866.45
65.1
65.1
10.08
3689.875
75.18
3754.975
65.1
65.1
10.08
3578.4
75.18
3643.5
65.1
65.1
10.08
3466.925
75.18
3532.025
65.1
65.1
65.1
10.08
3355.45
75.18
3420.55
65.1
10.08
3243.975
75.18
3309.075
65.1
65.1
10.08
3132.5
75.18
3197.6
65.1
65.1
10.08
3021.025
75.18
3086.125
65.1
65.1
10.08
2909.55
75.18
2974.65
65.1
65.1
131
10.08
2720.305
75.18
2785.405
65.1
65.1
132
10.08
2608.83
75.18
2673.93
65.1
65.1
133
10.08
2497.355
75.18
2562.455
65.1
65.1
134
10.08
2385.88
75.18
2450.98
65.1
65.1
135
10.08
2274.405
75.18
2339.505
65.1
65.1
65.1
127
128
129
130
6
BOND PAD COORDINATES (µm)
X MIN
136
10.08
2162.93
75.18
2228.03
65.1
137
10.08
2051.455
75.18
2116.555
65.1
65.1
138
10.08
1862.21
75.18
1927.31
65.1
65.1
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 2. Bond Pad Coordinates (continued)
PAD NO.
BOND PAD COORDINATES (µm)
PAD SIZE (µm)
X MIN
Y MIN
X MAX
Y MAX
X
Y
139
10.08
1672.965
75.18
1738.065
65.1
65.1
140
10.08
1561.49
75.18
1626.59
65.1
65.1
141
10.08
1372.245
75.18
1437.345
65.1
65.1
65.1
142
10.08
1260.77
75.18
1325.87
65.1
143
10.08
1149.295
75.18
1214.395
65.1
65.1
144
10.08
1037.82
75.18
1102.92
65.1
65.1
146
147
148
149
150
151
152
司
公
限
有 2
件
技 83 器
科 16 元
子 29 子
电 -8 电
创 55 温
德 07 高
鸿话油
圳电石
深系理
联代
业
专
145
10.08
926.345
75.18
991.445
65.1
65.1
10.08
814.87
75.18
879.97
65.1
65.1
10.08
703.395
75.18
768.495
65.1
65.1
10.08
514.15
75.18
579.25
65.1
65.1
10.08
402.675
75.18
467.775
65.1
65.1
10.08
291.2
75.18
356.3
65.1
65.1
10.08
179.725
75.18
244.825
65.1
65.1
4.9
5154.1
69.93
5219.13
65.03
65.03
Copyright © 2009–2011, Texas Instruments Incorporated
7
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
HFQ PACKAGE
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Figure 1. SM470R1B1M 84-Pin CQFP-HFQ (Top View)
Pin Assignments
The SM470R1B1M 84-pin HFQ ceramic quad flatpack (CQFP) pin assignments are shown in Figure 1.
Features
The reduced pin count version of SM470R1B1M has the following features.
• Communication interfaces
– Two serial peripheral interface
– Two serial communication interface
– Two high-end CAN controllers
– Two inter- integrated circuit (I2C) modules
• 4-channel, 10-bit multi-buffered ADC
• High-end timer lite (HET) controlling seven programmable I/O channels
• Eight general purpose I/O’s
8
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
DESCRIPTION
The SM470R1B1M (1) devices are members of the Texas Instruments SM470R1x family of general-purpose
16/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high
performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a
high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The SM470R1B1M utilizes the big-endian
format where the most significant byte of a word is stored at the lowest numbered byte and the least significant
byte at the highest numbered byte.
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High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The B1M RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The B1M devices contain the following:
• ARM7TDMI 16/32-Bit RISC CPU
• SM470R1x system module (SYS) with 470+ enhancements
• 1M-byte flash
• 64K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Digital watchdog (DWD) timer
• Analog watchdog (AWD) timer
• Enhanced real-time interrupt ( RTI) module
• Interrupt expansion module (IEM)
• Memory security module (MSM)
• JTAG security module
• Two serial peripheral interface (SPI) modules
• Three serial communications interface (SCI) modules
• Two high-end CAN controllers (HECC)
• Five inter-integrated circuit (I2C) modules
• 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
• High-end timer lite (HET) controlling 12 I/Os
• External clock prescale (ECP)
• Expansion bus module (EBM)
• Up to 93 I/O pins
The functions performed by the 470+ system module (SYS) include:
• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)
The enhanced real-time interrupt (RTI) module on the B1M has the option to be driven by the oscillator clock.
The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral
select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the
SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
(1)
Throughout the remainder of this document, the SM470R1B1M will be referred to as either the full device name or as B1M.
Copyright © 2009–2011, Texas Instruments Incorporated
9
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz or 30
MHz, depending on the input voltage. When in pipeline mode, the flash operates with a system clock frequency
of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed information on the flash, see the
F05 Flash section of this data sheet.
The memory security module (MSM) and the JTAG security module prevent unauthorized access and visibility to
on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.
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The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the
CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). These CAN peripherals are ideal for applications
operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or
multiplexed wiring. The I2C module is a multi-master communication module providing an interface between the
B1M microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and
400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the
specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional
information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number
SPNU223).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For
more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide
(literature number SPNU199).
The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).
NOTE
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions
and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module
(EBM) Reference Guide (literature number SPNU222).
10
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
Device Characteristics
Table 3 identifies all the characteristics of the B1M device except the SYSTEM and CPU, which are generic.
Table 3. Device Characteristics
DEVICE DESCRIPTION
SM470R1B1M
COMMENTS
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CHARACTERISTICS
MEMORY
For the number of memory selects on this device, see Table 5, SM470R1B1M Memory Selection Assignment.
INTERNAL MEMORY
Pipeline/Non-Pipeline
1M-Byte flash
64K-Byte SRAM
Memory Security Module (MSM)
JTAG Security Module
Flash is pipeline-capable.
The B1M RAM is implemented in one 64K array selected by two
memory-select signals (see Table 5, SM470R1B1M Memory
Selection Assignment ).
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 8, Interrupt Priority. And for the 1K peripheral address ranges and their
peripheral selects, see Table 6, B1M Peripherals, System Module, and Flash Base Addresses.
CLOCK
Expansion Bus
ZPLL
Zero-pin PLL has no external loop filter pins.
EBM
Expansion bus module with 42 pins. Supports 8- and 16-bit
memories. See Table 9 for details.
46 I/O
Port A has 8 external pins; Port B has only 1 external pin; Port C has
5 external pins; Port D has 6 external pins; Ports E, F, and G each
have 8 external pins; and Port H has 2 external pins.
GENERAL-PURPOSE I/Os
ECP
YES
SCI
3 (3-pin)
CAN (HECC and/or SCC)
2 HECC
SPI (5-pin, 4-pin or 3-pin)
2 (5-pin)
I2C
5
HET with XOR Share
12 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 12-channel
64-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
84
PACKAGES
HFQ
Copyright © 2009–2011, Texas Instruments Incorporated
Two high-end CAN controllers
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This
HR sharing is independent of whether or not the odd pin is available
externally. If an odd pin is available externally and shared, then the
odd pin can only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (literature number SPNU199).
Both the logic and registers for a full 16-channel MibADC are
present.
11
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Functional Block Diagram
External
Pins
FLASH
(1M Byte)
2 Banks
16 Sectors
VCCP
FLTP2
OSCIN
Memory
Security
Module
(MSM)
RAM
(64K Bytes)
ZPLL
OSCOUT
Crystal
External
Pins
PLLDIS
ADIN[11:0]
CPU Address Data Bus
TDI
TDO
TMS
TMS2
RST
AWD
TEST
PORRST
CLKOUT
TMS470R1x CPU
HET
64 Words
ICE Breaker
Expansion Address/Data Bus
TCK
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TRST
MibADC
64−Word
FIFO
TMS470R1x System Module
with Enhanced RTI Module(A)
DMA Controller
16 Channels
Interrupt Expansion
Module (IEM)
SCC
I2C4SDA
I2C4SCL
I2C5SDA
I2C5SCL
Digital
Watchdog
(DWD)
I2C4
Analog
Watchdog
(AWD)
HECC1
HECC2
SCI1
SCI2
I2C5
I2C3
I2C2
SCI3
SPI2
SPI1
ECP
GIO/EBM
12
ADREFHI
ADREFLO
VCCAD
VSSAD
HET[0:8;18,20,22]
CAN1HTX
CAN1HRX
CAN2HTX
CAN2SRX
SCI1CLK
SCI1TX
SCI1RX
SCI2CLK
SCI2TX
SCI2RX
I2C3SDA
I2C3SCL
I2C2SDA
I2C2SCL
I2C1SDA
I2C1SCL
GIOH[5,0]
GIOF[7:0]
GIOG[7:0]
GIOD[5:0]
GIOE[7:0]/INT[15:8]
GIOB[0]
GIOC[4:0]
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOA[1]/INT[1]/ECLK
SPI1CLK
SPI1SIMO
SPI1SOMI
SPI1SCS
SPI1ENA
SPI2CLK
SPI2SOMI
SPI2SIMO
SPI2SCS
SPI2ENA
SCI3CLK
SCI3TX
A.
SCI3RX
I2C1
ADEVT
The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 4. Terminal Functions
TERMINAL
PAD
NO.
HFQ
PIN
NO. (4)
HET[0]
76
42
HET[1]
75
NC
HET[2]
74
41
HET[3]
69
38
NAME
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
HIGH-END TIMER (HET)
HET[5]
HET[6]
HET[7]
HET[8]
HET[18]
HET[20]
HET[22]
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HET[4]
Timer input capture or output
compare. The HET[8:0,18,20,22]
applicable pins can be programmed
as general-purpose input/output
(GIO) pins. All are high-resolution
pins.
The high-resolution (HR) SHARE
feature allows even HR pins to share
the next higher odd HR pin
structures. This HR sharing is
independent of whether or not the
odd pin is available externally. If an
odd pin is available externally and
shared, then the odd pin can only be
used as a general-purpose I/O. For
more information on HR SHARE, see
the TMS470R1x High-End Timer
(HET) Reference Guide (literature
number SPNU199).
68
37
66
36
9
6
11
NC
3.3 V
2 mA -z
13
7
16
NC
19
NC
20
NC
86
49
5-V tolerant
4 mA
87
50
3.3 V
2 mA -z
57
29
5-V tolerant
4 mA
58
30
3.3 V
2 mA -z
IPD (20 µA)
HIGH-END CAN CONTROLLER (HECC)
CAN1HRX
CAN1HTX
CAN2HRX
CAN2HTX
HECC1 receive pin or GIO pin
IPU (20 µA)
HECC1 transmit pin or GIO pin
IPU (20 µA)
HECC2 transmit pin or GIO pin
HECC2 receive pin or GIO pin
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT[0]
144
83
GIOA[1]/INT[1]/ECLK
140
80
GIOA[2]/INT[2]
138
79
GIOA[3]/INT[3]
137
78
GIOA[4]/INT[4]
130
73
GIOA[5]/INT[5]
101
58
GIOA[6]/INT[6]
81
46
GIOA[7]/INT[7]
82
47
GIOB[0]/EBDMAREQ0
46
NC
GIOC[0]/EBOE
139
NC
GIOC[1]/EBWR[0]
131
NC
GIOC[2]/EBWR[1]
129
NC
GIOC[3]/EBCS[5]
123
NC
GIOC[4]/EBCS[6]
122
NC
(1)
(2)
(3)
(4)
5-V tolerant
3.3 V
4 mA
General-purpose input/output pins.
GIOA[7:0]/INT[7:0] are
interrupt-capable pins.
GIOA[1]/INT[1]/ECLK pin is
multiplexed with the external
clock-out function of the external
clock prescale (ECP) module.
2 mA -z
GIOB[0], GIOC[4:0], GIOD[5:0],
GIOE[7:0:], GIOF[7:0], GIOG[7:0],
and GIOH[5,0] are multiplexed with
the expansion bus module.
See Table 9.
IPD (20 µA)
PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
Any pins marked as NC are physically connected to ground internal to the package. Care must be used to keep these pins in a high
impedance input state.
Copyright © 2009–2011, Texas Instruments Incorporated
13
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 4. Terminal Functions (continued)
TERMINAL
PAD
NO.
HFQ
PIN
NO. (4)
GIOD[0]/EBADDR[0]
45
NC
GIOD[1]/EBADDR[1]
42
NC
GIOD[2]/EBADDR[2]
38
NC
GIOD[3]/EBADDR[3]
33
NC
GIOD[4]/EBADDR[4]
30
NC
GIOD[5]/EBADDR[5]
25
NC
GIOE[0]/EBDATA[0]
47
NC
GIOE[1]/EBDATA[1]
50
NC
GIOE[2]/EBDATA[2]
61
NC
GIOE[3]/EBDATA[3]
64
NC
GIOE[4]/EBDATA[4]
67
NC
GIOE[5]/EBDATA[5]
70
NC
GIOE[6]/EBDATA[6]
73
NC
GIOE[7]/EBDATA[7]
80
NC
GIOF[0]/INT[8]/
EBADDR[6]/EBDATA[8]
83
GIOF[1]/INT[9]/
EBADDR[7]/EBDATA[9]
85
GIOF[2]/INT[10]/
EBADDR[8]/EBDATA[10]
92
GIOF[3]/INT[11]/
EBADDR[9]/EBDATA[11]
93
GIOF[4]/INT[12]/
EBADDR[10]/EBDATA[12]
96
NAME
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
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GIOF[5]/INT[13]/
EBADDR[11]/EBDATA[13]
99
GIOF[6]/INT[14]/
EBADDR[12]/EBDATA[14]
102
GIOF[7]/INT[15]/
EBADDR[13]/EBDATA[15]
103
GIOG[0]/EBADDR[14]/
EBADDR[6]
21
GIOG[1]/EBADDR[15]/
EBADDR[7]
10
GIOG[2]/EBADDR[16]/
EBADDR[8]
8
GIOG[3]/EBADDR[17]/
EBADDR[9]
6
GIOG[4]/EBADDR[18]/
EBADDR[10]
3
GIOG[5]/EBADDR[19]/
EBADDR[11]
150
GIOG[6]/EBADDR[20]/EBADD
R[12]
148
GIOG[7]/EBADDR[21]/
EBADDR[13]
145
GIOH[0]/EBADDR[22]/
EBADDR[14]
144
GIOH[5]/EBHOLD
128
14
NC
NC
NC
NC
NC
3.3 V
NC
NC
2 mA -z
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0],
GIOE[7:0:], GIOF[7:0], GIOG[7:0],
and GIOH[5,0] are multiplexed with
the expansion bus module.
GIOF[7:0]/INT[15:8] are
interrupt-capable pins.
See Table 9.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 4. Terminal Functions (continued)
TERMINAL
NAME
PAD
NO.
HFQ
PIN
NO. (4)
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
59
ADEVT
104
ADIN[0]
120
NC
ADIN[1]
119
NC
ADIN[3]
ADIN[4]
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADREFHI
ADREFLO
VCCAD
VSSAD
IPD (20 µA)
MibADC event input. Can be
programmed as a GIO pin.
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ADIN[2]
2 mA -z
118
NC
117
NC
116
NC
111
NC
110
63
109
NC
108
62
107
61
106
60
105
NC
112
113
3.3 V
MibADC analog input pins
64
65
3.3 VREF
MibADC module high-voltage
reference input
GND REF
MibADC module low-voltage
reference input
MibADC analog supply voltage
114
66
3.3-V PWR
115
67
GND
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
SPI1ENA
SPI1SCS
SPI1SIMO
SPI1SOMI
4
2
1
3
SPI1 clock. SPI1CLK can be
programmed as a GIO pin.
2
SPI1 chip enable. Can be
programmed as a GIO pin.
1
5-V tolerant
4 mA
4
SPI1 data stream. Slave in/master
out. Can be programmed as a GIO
pin.
5
SPI1 data stream. Slave out/master
in. Can be programmed as a GIO pin.
5
7
SPI1 slave chip select. Can be
programmed as a GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK
SPI2ENA
SPI2SCS
59
63
65
31
SPI2 clock. Can be programmed as a
GIO pin.
34
SPI2 chip enable. Can be
programmed as a GIO pin.
35
5-V tolerant
4 mA
SPI2 slave chip select. Can be
programmed as a GIO pin.
33
SPI2 data stream. Slave in/master
out. Can be programmed as a GIO
pin.
32
SPI2 data stream. Slave out/master
in. Can be programmed as a GIO pin.
SPI2SIMO
62
SPI2SOMI
60
I2C1SDA
90
NC
I2C1SCL
91
NC
INTER-INTEGRATED CIRCUIT 1 (I2C1)
Copyright © 2009–2011, Texas Instruments Incorporated
5-V tolerant
4 mA
I2C1 serial data pin or GIO pin
I2C1 serial clock pin or GIO pin
15
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 4. Terminal Functions (continued)
TERMINAL
NAME
PAD
NO.
HFQ
PIN
NO. (4)
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
INTER-INTEGRATED CIRCUIT 2 (I2C2)
I2C2SDA
97
55
I2C2SCL
98
56
5-V tolerant
I2C2 serial data pin or GIO pin
4 mA
I2C2 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 3 (I2C3)
I2C3SCL
32
NC
31
NC
5-V tolerant
I2C3 serial data pin or GIO pin
4 mA
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I2C3SDA
I2C3 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 4 (I2C4)
I2C4SDA
I2C4SCL
44
23
43
22
5-V tolerant
I2C4 serial data pin or GIO pin
4 mA
I2C4 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 5 (I2C5)
I2C5SDA
I2C5SCL
41
NC
40
NC
5-V tolerant
I2C5 serial data pin or GIO pin
4 mA
I2C5 serial clock pin or GIO pin
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN
OSCOUT
PLLDIS
36
19
35
18
100
57
Crystal connection pin or external
clock input
1.8 V
2 mA
External crystal connection pin
IPD (20 µA)
3.3 V
Enable/disable the ZPLL. The ZPLL
can be bypassed and the oscillator
becomes the system clock. If not in
bypass mode, TI recommends that
this pin be connected to ground or
pulled down to ground by an external
resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1CLK
SCI1RX
SCI1TX
51
26
3.3 V
2 mA -z
49
25
5-V tolerant
4 mA
48
24
3.3 V
2 mA -z
IPD (20 µA)
SCI1 clock. SCI1CLK can be
programmed as a GIO pin.
SCI1 data receive. SCI1RX can be
programmed as a GIO pin.
IPU (20 µA)
SCI1 data transmit. SCI1TX can be
programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2CLK
SCI2RX
SCI2TX
54
NC
3.3 V
2 mA -z
53
NC
5-V tolerant
4 mA
52
NC
3.3 V
2 mA -z
IPD (20 µA)
SCI2 clock. SCI2CLK can be
programmed as a GIO pin.
SCI2 data receive. SCI2RX can be
programmed as a GIO pin.
IPU (20 µA)
SCI2 data transmit. SCI2TX can be
programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)
SCI3CLK
SCI3RX
SCI3TX
27
14
3.3 V
2 mA -z
24
13
5-V tolerant
4 mA
23
12
3.3 V
2 mA -z
IPD (20 µA)
SCI3 clock. SCI3CLK can be
programmed as a GIO pin.
SCI3 data receive. SCI3RX can be
programmed as a GIO pin.
IPU (20 µA)
SCI3 data transmit. SCI3TX can be
programmed as a GIO pin.
SYSTEM MODULE (SYS)
CLKOUT
84
48
3.3 V
PORRST
121
68
3.3 V
16
Bidirectional pin. CLKOUT can be
programmed as a GIO pin or the
output of SYSCLK, ICLK, or MCLK.
8 mA
IPD (20 µA)
Input master chip power-up reset.
External VCC monitor circuitry must
assert a power-on reset.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 4. Terminal Functions (continued)
TERMINAL
NAME
RST
PAD
NO.
124
HFQ
PIN
NO. (4)
69
TYPE (1)
3.3 V
(2)
CURRENT
OUTPUT
4 mA
DESCRIPTION
IPU (20 µA)
Bidirectional reset. The internal
circuitry can assert a reset, and an
external system reset can assert a
device reset.
On this pin, the output buffer is
implemented as an open drain (drives
low only).
To ensure an external reset is not
arbitrarily generated, TI recommends
that an external pullup resistor be
connected to this pin.
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INTERNAL
PULLUP/
PULLDOWN (3)
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
39
21
3.3 V
Analog watchdog reset. The AWD pin
provides a system reset if the WD
KEY is not written in time by the
system, providing an external RC
network circuit is connected. If the
user is not using AWD, TI
recommends that this pin be
connected to ground or pulled down
to ground by an external resistor.
For more details on the external RC
network circuit, see the TMS470R1x
System Module Reference Guide
(literature number SPNU189).
8 mA
TEST/DEBUG (T/D)
TCK
79
45
43
TDI
IPD (20 µA)
Test clock. TCK controls the test
hardware (JTAG).
IPU (20 µA)
Test data in. TDI inputs serial data to
the test instruction register, test data
register, and programmable test
address (JTAG).
IPD (20 µA)
Test data out. TDO outputs serial
data from the test instruction register,
test data register, identification
register, and programmable test
address (JTAG).
IPD (20 µA)
Test enable. Reserved for internal
use only. TI recommends that this pin
be connected to ground or pulled
down to ground by an external
resistor.
IPU (20 µA)
Serial input for controlling the state of
the CPU test access port (TAP)
controller (JTAG).
IPU (20 µA)
Serial input for controlling the second
TAP. TI recommends that this pin be
connected to VCCIO or pulled up to
VCCIO by an external resistor.
IPD (20 µA)
Test hardware reset to TAP1 and
TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI
recommends that this pin be pulled
down to ground by an external
resistor.
3.3 V
77
8 mA
44
TDO
78
8 mA
72
TEST
127
11
TMS
18
8 mA
10
TMS2
3.3 V
17
8 mA
84
TRST
151
FLASH
FLTP2
135
77
Copyright © 2009–2011, Texas Instruments Incorporated
NC
NC
Flash test pad 2. For proper
operation, this pin must not be
connected [no connect (NC)].
17
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 4. Terminal Functions (continued)
TERMINAL
NAME
VCCP
PAD
NO.
HFQ
PIN
NO. (4)
134
76
14
8
34
17
56
28
95
54
126
71
133
75
28
15
72
40
89
52
141
81
15
9
37
20
55
27
94
53
125
70
132
74
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
3.3-V PWR
DESCRIPTION
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
1.8-V PWR
Core logic supply voltage
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VCC
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
3.3-V PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
VSS
GND
Core supply ground reference
SUPPLY GROUND DIGITAL I/O
VSSIO
18
29
16
71
39
88
51
142
82
GND
Digital I/O supply ground reference
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
B1M Device-Specific Information
Memory
Figure 2 shows the memory map of the B1M device.
Memory (4G Bytes)
0xFFFF_FFFF
IEM
MSM
Reserved
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0xFFF8_0000
0xFFF7_FFFF
SYSTEM with PSA, CIM, RTI,
DEC, DMA, MMC, DWD
System Module Control
Registers
(512K Bytes)
Peripheral Control Registers
(512K Bytes)
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
Reserved
HET
Reserved
SPI1
SCI3
SCI2
SCI1
Reserved
MibADC
ECP
Reserved
EBM
GIO
Reserved
HECC2
Reserved
HECC1
Reserved
HECC2 RAM
Reserved
HECC1 RAM
Reserved
SCC
Reserved
SCC RAM
I2C4
I2C3
I2C2
I2C1
I2C5
SPI2
Reserved
Reserved
Flash Control Registers
Reserved
MPU Control Registers
Reserved (1 MByte)
0xFFE0_0000
0x7FFF_FFFF
RAM
(64K Bytes)
Program
and
Data Area
FLASH
(1M Bytes)
2 Banks
16 sectors
HET RAM
(1K Bytes)
0x0000_0024
0x0000_0023
Exception, Interrupt, and
Reset Vectors
0x0000_0000
Reserved
FIQ
IRQ
Reserved
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
0xFFFF_FFFF
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_F700
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F600
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EF00
0xFFF7_ED00
0xFFF7_EC00
0xFFF7_EA00
0xFFF7_E800
0xFFF7_E600
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_DB00
0xFFF7_DA00
0xFFF7_D900
0xFFF7_D800
0xFFF7_D500
0xFFF7_D400
0xFFF0_0000
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
A.
Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B.
The CPU registers are not part of the memory map.
Figure 2. SM470R1B1M Memory Map
Copyright © 2009–2011, Texas Instruments Incorporated
19
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers, see
the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number
SPNU189).
For the memory selection assignments and the memory selected, see Table 5.
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Table 5. SM470R1B1M Memory Selection Assignment
MEMORY
SELECT
0 (fine)
1 (fine)
2 (fine)
3 (fine)
4 (fine)
5 (coarse)
6 (coarse)
(1)
(2)
MEMORY
SELECTED
(ALL INTERNAL)
FLASH/ROM
FLASH/ROM
RAM
RAM
MEMORY
SIZE (1)
1M
64 K (2)
MPU
MSM
MEMORY BASE ADDRESS
REGISTER
NO
YES
MFBAHR0 and MFBALR0
NO
YES
MFBAHR1 and MFBALR1
YES
YES
MFBAHR2 and MFBALR2
STATIC MEM
CTL REGISTER
YES
YES
MFBAHR3 and MFBALR3
HET RAM
1K
NO
NO
MFBAHR4 and MFBALR4
SMCR1
CS[5]/GIOC[3]
512K x 8 (512KB)
256K x 16
(512KB)
NO
NO
MCBAHR2 and MCBALR2
SMCR5
CS[6]/GIOC[4]
512K x 8 (512KB)
256K x 16
(512KB)
NO
NO
MCBAHR3 and MCBALR3
SMCR6
x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.
JTAG security module
The B1M device includes a JTAG security module to provide maximum security to the memory contents. The
visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory. For the
B1M, the visible unlock code is in the OTP sector at address 0x0000_01F8.
memory security module
The B1M device also includes a memory security module (MSM) to provide additional security and flexibility to
the memory contents' protection. The password for unlocking the MSM is located in the four words just before
the flash protection keys.
RAM
The B1M device contains 64K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This B1M RAM is implemented in one 64K-byte array
selected by two memory-select signals. This B1M configuration imposes an additional constraint on the memory
map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the
multiples of the size of the physical RAM (i.e., 64K bytes for the B1M device). The B1M RAM is addressed
through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).
20
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the Flash read and Flash program and erase sections.
flash protection keys
The B1M device provides flash protection keys. These four 32-bit protection keys prevent
program/erase/compaction operations from occurring until after the four protection keys have been matched by
the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B1M are
located in the last 4 words of the first 64K sector.
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flash read
The B1M flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and
read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system
clock frequency of 30 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In
other words, the B1M device powers up and comes out of reset in non-pipeline mode.
Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will override pipeline
mode.
Copyright © 2009–2011, Texas Instruments Incorporated
21
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
flash program and erase
The B1M device flash contains two 512K-byte memory arrays (or banks), for a total of 1M-byte of flash, and
consists of sixteen sectors. These sixteen sectors are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
OTP
2K Bytes
0x0000_0000
0x0000_007FF
0
64K Bytes
0x0000_0000
0x0000_FFFF
1
64K Bytes
0x0001_0000
0x0001_FFFF
0x0002_0000
0x0002_FFFF
2
64K Bytes
MEMORY ARRAYS
(OR BANKS)
BANK0
(512K Bytes)
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3
64K Bytes
0x0003_0000
0x0003_FFFF
4
64K Bytes
0x0004_0000
0x0004_FFFF
5
64K Bytes
0x0005_0000
0x0005_FFFF
6
64K Bytes
0x0006_0000
0x0006_FFFF
7
64K Bytes
0x0007_0000
0x0007_FFFF
0
64K Bytes
0x0008_0000
0x0008_FFFF
1
64K Bytes
0x0009_0000
0x0009_FFFF
2
64K Bytes
0x000A_0000
0x000A_FFFF
3
64K Bytes
0x000B_0000
0x000B_FFFF
4
64K Bytes
0x000C_0000
0x000C_FFFF
5
64K Bytes
0x000D_0000
0x000D_FFFF
6
64K Bytes
0x000E_0000
0x000E_FFFF
7
64K Bytes
0x000F_0000
0x000F_FFFF
BANK1
(512K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and
read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution cannot occur from any sector within a bank that is being programmed or erased.
NOTE
When the OTP sector is enabled, the rest of flash memory is disabled. The OTP memory
can only be read or programmed from code executed out of RAM.
HET RAM
The B1M device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
22
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
peripheral selects and base addresses
The B1M device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the
SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 6.
Table 6. B1M Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
0 x FFFF_FFCC
0 x FFFF_FFFF
N/A
0 x FFFF_FF70
0 x FFFF_FFCB
N/A
DWD
0xFFFF_FF60
0 x FFFF_FF6F
N/A
PSA
0 x FFFF_FF40
0 x FFFF_FF5F
N/A
CIM
0 x FFFF_FF20
0 x FFFF_FF3F
N/A
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SYSTEM
RESERVED
RTI
0 x FFFF_FF00
0 x FFFF_FF1F
N/A
DMA
0 x FFFF_FE80
0 x FFFF_FEFF
N/A
DEC
0 x FFFF_FE00
0 x FFFF_FE7F
N/A
RESERVED
0xFFFF_FD80
0xFFFF_FDFF
N/A
MMC
0 x FFFF_FD00
0 x FFFF_FD7F
N/A
IEM
0 x FFFF_FC00
0 x FFFF_FCFF
N/A
RESERVED
0 x FFFF_Fb00
0 x FFFF_FBFF
N/A
RESERVED
0 x FFFF_Fa00
0 x FFFF_FAFF
N/A
DMA CMD BUFFER
0 x FFFF_F800
0 x FFFF_F9FF
N/A
MSM
0xFFFF_F700
0xFFFF_F7FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F6FF
N/A
RESERVED
0 x FFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F700
0xFFF7_F7FF
SCI3
0xFFF7_F600
0xFFF7_F6FF
SCI2
0XFFF7_F500
0XFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MibADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_EE00
0xFFF7_EEFF
EBM
0xFFF7_ED00
0xFFF7_EDFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
0xFFF7_EB00
0xFFF7_EBFF
0xFFF7_EA00
0xFFF7_EAFF
0xFFF7_E900
0xFFF7_E9FF
0xFFF7_E800
0xFFF7_E8FF
0xFFF7_E700
0xFFF7_E7FF
HECC2
HECC1
HECC2 RAM
HECC1 RAM
0xFFF7_E600
0xFFF7_E6FF
0xFFF7_E500
0xFFF7_E5FF
0xFFF7_E400
0xFFF7_E4FF
RESERVED
0xFFF7_E100
0xFFF7_E3FF
SCC
0xFFF7_E000
0xFFF7_E0FF
Copyright © 2009–2011, Texas Instruments Incorporated
PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
PS[5]
PS[6]
PS[7]
23
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 6. B1M Peripherals, System Module, and Flash Base Addresses (continued)
CONNECTING MODULE
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
RESERVED
0xFFF7_DD00
0xFFF7_DFFF
SCC RAM
0xFFF7_DC00
0xFFF7_DCFF
I2C4
0xFFF7_DB00
0xFFF7_DBFF
I2C3
0xFFF7_DA00
0xFFF7_DAFF
I2C2
0xFFF7_D900
0xFFF7_D9FF
I2C1
0xFFF7_D800
0xFFF7_D8FF
PERIPHERAL SELECTS
PS[8]
PS[9]
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24
RESERVED
0xFFF7_D600
0xFFF7_D7FF
I2C5
0xFFF7_D500
0xFFF7_D5FF
SPI2
0xFFF7_D400
0xFFF7_D4FF
RESERVED
0xFFF7_CC00
0xFFF7_D3FF
PS[10]
PS[11] – PS[12]
RESERVED
0xFFF7_C800
0xFFF7_CBFF
PS[13]
RESERVED
0xFFF7_C000
0xFFF7_C7FF
PS[14] – PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
FLASH CONTROL REGISTERS
0xFFE8_8000
0xFFE8_BFFF
N/A
RESERVED
0xFFF8_4024
0xFFF8_7FFF
N/A
MPU CONTROL REGISTERS
0xFFE8_4000
0xFFE8_4023
N/A
RESERVED
0xFFF8_0000
0xFFF8_3FFF
N/A
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
direct-memory access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the B1M memory
map (except for restricted memory locations like the system control registers area). The DMA manages up to 16
channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA controller
is connected to both the CPU and peripheral buses, enabling these data transfers to occur in parallel with CPU
activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the B1M device, the DMA controller
configuration is 32 control packets and 16 channels.
For the B1M DMA request hardwired configuration, see Table 7.
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Table 7. DMA Request Lines Connections (1)
MODULES
DMA REQUEST INTERRUPT SOURCES
Expansion Bus DMA request
EBDMAREQ[0]
DMAREQ[0]
SPI1/I2C4
SPI1 end-receive/I2C4 read
SPI1DMA0/I2C4DMA0
DMAREQ[1]
SPI1/I2C4
SPI1 end-transmit/I2C4 write
SPI1DMA1/I2C4DMA1
DMAREQ[2]
ADC EV/I2C1 read
MibADCDMA0/I2C1DMA0
DMAREQ[3]
MibADC/SCI1/I2C5
ADC G1/SCI1 end-receive/I2C5 read
MibADCDMA1/SCI1DMA0/I2C5DMA0
DMAREQ[4]
MibADC/SCI1/I2C5
ADC G2/SCI1 end-transmit/I2C5 write
MibADCDMA2/SCI1DMA1/I2C5DMA1
DMAREQ[5]
I2C1 write
I2C1DMA1
DMAREQ[6]
SCI3/SPI2
SCI3 end-receive/SPI2 end-receive
SCI3DMA0/SPI2DMA0
DMAREQ[7]
SCI3/SPI2
DMAREQ[8]
MibADC/I2C1
I2C1
SCI3 end-transmit/SPI2 end-transmit
SCI3DMA01SPI2DMA1
I2C2
I2C2 read end-receive
I2C2DMA0
DMAREQ[9]
I2C2
I2C2 write end-transmit
I2C2DMA1
DMAREQ[10]
I2C3
I2C3 read
I2C3DMA0
DMAREQ[11]
I2C3
I2C3 write
I2C3DMA1
DMAREQ[12]
SCI2
SCI2 end-receive
SCI2DMA0
DMAREQ[14]
SCI2
SCI2 end-transmit
SCI2DMA1
DMAREQ[15]
Reserved
(1)
DMA CHANNEL
EBM
DMAREQ[13]
For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a
given application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
• Non-request mode (used when transferring from memory to memory)
• Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
Copyright © 2009–2011, Texas Instruments Incorporated
25
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
interrupt priority (IEM to CIM)
Interrupt requests originating from the B1M peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.) are
assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register
mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS
module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
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The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
• Fast interrupt request (FIQ)
• Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order in
the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 8.
Table 8. Interrupt Priority (IEM and CIM)
MODULES
INTERRUPT SOURCES
IEM CHANNEL
SPI1
SPI1 end-transfer/overrun
0
0
RTI
COMP2 interrupt
1
1
RTI
COMP1 interrupt
2
2
RTI
TAP interrupt
3
3
SPI2
SPI2 end-transfer/overrun
4
4
GIO
GIO interrupt A
5
5
Reserved
6
6
HET
HET interrupt 1
7
7
I2C1
I2C1 interrupt
8
8
SCI1/SCI2
SCI1
SCI1 or SCI2 error interrupt
9
9
SCI1 receive interrupt
10
10
Reserved
I2C2
HECC1
SCC
11
11
I2C2 interrupt
12
12
HECC1 interrupt A
13
13
SCC interrupt A
14
14
15
15
Reserved
MibADC
MibADC end event conversion
16
16
SCI2
SCI2 receive interrupt
17
17
DMA
DMA interrupt 0
18
18
I2C3
I2C3 interrupt
19
19
SCI1
SCI1 transmit interrupt
20
20
SW interrupt (SSI)
21
21
22
22
HET interrupt 2
23
23
HECC1 interrupt B
24
24
SCC
SCC interrupt B
25
25
SCI2
SCI2 transmit interrupt
26
26
MibADC end Group 1 conversion
27
27
DMA
DMA Interrupt 1
28
28
GIO
GIO interrupt B
29
29
MibADC end Group 2 conversion
30
30
SCI3 error interrupt
31
31
System
Reserved
HET
HECC1
MibADC
MibADC
SCI3
26
DEFAULT CIM INTERRUPT
LEVEL/CHANNEL
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Table 8. Interrupt Priority (IEM and CIM) (continued)
MODULES
INTERRUPT SOURCES
Reserved
DEFAULT CIM INTERRUPT
LEVEL/CHANNEL
IEM CHANNEL
32–37
HECC2 interrupt A
31
38
HECC2
HECC2 interrupt B
31
39
SCI3
SCI3 receive interrupt
31
40
SCI3
SCI3 transmit interrupt
31
41
I2C4
I2C4 interrupt
31
42
I2C5
I2C5 interrupt
31
43
31
44–47
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31
HECC2
Reserved
For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)
Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
Copyright © 2009–2011, Texas Instruments Incorporated
27
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
expansion bus module (EBM)
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The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output
pins and expansion bus interface pins. This module supports the multiplexing of the GIO and the expansion bus
interface functions. The module also supports 8- and 16- bit expansion bus memory interface mappings as well
as mapping of the following expansion bus signals:
• 27-bit address bus (EBADDR[26:0] for x8, 19-bit address bus (EBADDR[18:0] for x16
• 8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])
• 2 write strobes (EBWR[1:0])
• 2 memory chip selects (EBCS[6:5])
• 1 output enable (EBOE)
• 1 external hold signal for interfacing to slow memories (EBHOLD)
• 1 DMA request line (EBDMAREQ[0])
Table 9 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of these
pins varies depending on the memory mode.
Table 9. Expansion Bus Mux Mapping (1)
EXPANSION BUS MODULE PINS
GIO
(1)
(2)
x8
(2)
x16 (2)
GIOB[0]
EBDMAREQ[0]
EBDMAREQ[0]
GIOC[0]
EBOE
EBOE
GIOC[2:1]
EBWR[1:0]
EBWR[1:0]
GIOC[4:3]
EBCS[6:5]
EBCS[6:5]
GIOD[5:0]
EBADDR[5:0]
EBADDR[5:0]
GIOE[7:0]
EBDATA[7:0]
EBDATA[7:0]
GIOF[7:0]
EBADDR[13:6]
EBDATA[15:8]
GIOG[7:0]
EBADDR[21:14]
EBADDR[13:6]
GIOH[5]
EBHOLD
EBHOLD
I2C5SDA
EBADDR[26]
EBADDR[18]
I2C5SCL
EBADDR[25]
EBADDR[17]
I2C4SCL
EBADDR[24]
EBADDR[16]
I2C4SDA
EBADDR[23]
EBADDR[15]
GIOH[0]
EBADDR[22]
EBADDR[14]
For more detailed information, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222) and
the TMS470R1x General Purpose Input/Output Reference Guide (literature number SPNU192).
X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.
Table 10 lists the names of the expansion bus interface signals and their functions.
Table 10. Expansion Bus Pins
PIN
EBDMAREQ
EBOE
Expansion bus pin enable
EBWR
Expansion bus write strobe EBWR[1] controls EBDATA[15:8] and EBWR[0]
controls EBDATA[7:0]
EBCS
EBADDR
28
DESCRIPTION
Expansion bus DMA request
Expansion bus chip select
Expansion bus address pins
EBDATA
Expansion bus data pins
EBHOLD
Expansion bus hold: An external device may assert this signal to add wait
states to an expansion bus transaction.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The B1M MibADC module can function in two modes: compatibility mode, where its programmer's model is
compatible with the SM470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts or by the DMA.
MibADC event trigger enhancements
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The MibADC includes two major enhancements over the event-triggering capability of the SM470R1x ADC.
• Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
• The trigger source and polarity can be selected individually for both group1 and the event group from the
options identified in Table 11.
Table 11. MibADC Event Hookup Configuration
EVENT #
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] OR EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
Reserved
EVENT4
11
Reserved
For group1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in
the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
Copyright © 2009–2011, Texas Instruments Incorporated
29
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
JTAG Interface
There are two main test access ports (TAPs) on the device:
• SM470R1x CPU TAP
• Device TAP for factory test
Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 3.
TMS470R1x CPU
TCK
TCK
TRST
TRST
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TMS
TMS
TDI
TDI
TDO
TDO
Factory Test
TCK
TRST
TMS2
TMS
TDI
TDO
Figure 3. JTAG Interface
30
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
documentation support
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Extensive documentation supports all of the SM470 microcontroller family generation of devices. The types of
documentation available include data sheets with design specifications; complete user's guides for all devices
and development support tools; and hardware and software applications. Useful reference documentation
includes:
• Bulletin
– TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)
• User's Guides
– TMS470R1x System Module Reference Guide (literature number SPNU189)
– TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
– TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
– TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
– TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
– TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199)
– TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
– TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206)
– TMS470R1x Zero Pin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number
SPNU212)
– TMS470R1x Digital Watchdog Timer Reference Guide (literature number SPNU244)
– TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211)
– TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
– TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
– TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222)
– TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)
– TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245)
– TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246)
– TMS470 Peripherals Overview Reference Guide (literature number SPNU248)
• Errata Sheet
– TMS470R1B1M TMS470 Microcontrollers Silicon Errata (literature number SPNZ139)
Copyright © 2009–2011, Texas Instruments Incorporated
31
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS470R1B1M). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications
SM
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TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Figure 4 illustrates the numbering and symbol nomenclature for the SM470R1x family.
32
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SM
470 R1 B
1M
KGD
S
1
1 = KGD revision
PREFIX
TMS = Fully Qualified Device
FAMILY
470 = TMS470 RISC − Embedded
Microcontroller Family
PACKAGE TYPE
KGD = Known Good Die
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ARCHITECTURE
R1 = ARM7TDM1 CPU
TEMPERATURE RANGE
S = −55°C − 220°C
DEVICE TYPE B
With 1024K−Bytes Flash Memory:
60−MHZ Frequency
1.8-V Core, 3.3-V I/O
Flash Program Memory
ZPLL Clock
64K−Byte Static RAM
1K−Byte HET RAM (64 Instructions)
AWD
DWD
RTI
10−Bit, 12−Input MibADC
Two SPI Modules
Three SCI Modules
Two High−End CAN HECC
HET, 16 Channels
ECP
IEM
DMA
Five I2C Modules
EMB
MSM
REVISION CHANGE
Blank = Original
FLASH MEMORY
1M = 1024K−Bytes Flash Memory
Figure 4. SM470R1x Family Nomenclature
Copyright © 2009–2011, Texas Instruments Incorporated
33
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 12). The B1M device identification code register
value is 0xnA5F.
Figure 5. SM470 Device ID Bit Allocation Register [offset = 0xFFFF_FFF0h]
31
16
Reserved
15
12
0
TF
11
R/F
10
9
PART NUMBER
3
2
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
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1
VERSION
LEGEND:
For bits 3-15: R = Read only, -K = Value constant after RESET.
For bits 0-2: R = Read only, -1 = Value after RESET.
Table 12. SM470 Device ID Bit Allocation Register Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
Reads are undefined and writes have no effect.
15-12
VERSION
Silicon version (revision) bits
These bits identify the silicon version of the device.
TF
Technology family bit
This bit distinguishes the technology family core power supply:
11
10
34
R/F
0
3.3 V for F10/C10 devices
1
1.8 V for F05/C05 devices
ROM/flash bit
This bit distinguishes between ROM and flash devices:
0
Flash device
1
ROM device
9-3
PART NUMBER
Device-specific part number bits
These bits identify the assigned device-specific part number. The assigned device-specific part
number for the B1M device is 1001011.
2-0
1
Mandatory High
Bits 2, 1, and 0 are tied high by default.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
Absolute Maximum Ratings
over operating free-air temperature range, A version (unless otherwise noted) (1)
Supply voltage range:
VCC
(2)
–0.3 V to 2.5 V
(2)
–0.3 V to 4.1 V
Supply voltage range:
VCCIO, VCCAD, VCCP (flash pump)
Input voltage range:
All 5 V tolerant input pins
–0.3 V to 6.0 V
All other input pins
–0.3 V to 4.1 V
IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST , TEST, and
TCK
±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11]
±10 mA
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Input clamp current:
Operating free-air
temperature range, TA:
A version
Storage temperature range, Tstg:
(1)
(2)
–55°C to 220°C
–55°C to 220°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to their associated grounds.
Device Recommended Operating Conditions (1)
MIN
VCC
Digital logic supply voltage (Core)
NOM
MAX
SYSCLK = 48 MHz
(pipeline mode enabled)
1.71
2.05
SYSCLK = 60 MHz
(pipeline mode enabled)
1.81
2.05
UNIT
V
VCCIO
Digital logic supply voltage (I/O)
3
3.6
V
VCCAD
ADC supply voltage
3
3.6
V
VCCP
Flash pump supply voltage
3
3.6
V
VSS
Digital logic supply ground
VSSAD
ADC supply ground (1)
–0.1
0.1
V
TA
Operating free-air temperature
–55
220
°C
(1)
0
V
All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
Copyright © 2009–2011, Texas Instruments Incorporated
35
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
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Figure 6. SM470R1B1M-HT Life Expectancy Curve
Notes:
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package
interconnect life).
36
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Minimum and maximum parameters are characterized for operation at TA = 220°C unless otherwise noted, but may not be
production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature
performance. (1)
PARAMETER
Vhys
Input hysteresis
VIL
Low-level input
voltage
All inputs (3)
High-level input
voltage
All inputs
Input threshold
voltage
AWD only (4)
OSCIN with digital input
only
Low-level output voltage (5)
VOH
High-level output voltage (5)
IIC
Input clamp current (I/O pins) (6)
Input current
(3.3 V input pins)
2
VCCIO + 0. 3
1.35
1.8
0.7 VCC
VCC + 0.3
IOL = 50 µA
IOH = IOH MIN
IOH = 50 µA
–2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
IIL Pulldown
VI = VSS
–1
1
VI = VCCIO
5
100
IIL Pullup
VI = VSS
–100
–5
IIH Pullup
VI = VCCIO
–1
1
All other pins
No pullup or pulldown
–1
1
VI = VSS
–1
1
VI = VCCIO
1
5
VI = 5 V
5
25
VI = 5.5 V
25
50
RST
All other 3.3 V I/O
VOL = VOL MAX
(7)
RST
V
V
V
V
IIH Pulldown
CLKOUT, TDI, TDO,
TMS, TMS2
High-level output
current
0.2
0.8 VCCIO
5 V tolerant
IOH
0.2 VCCIO
VCCIO – 0.2
VI < VSSIO – 0. 3 or
VI > VCCIO + 0. 3
UNIT
V
0.8
CLKOUT, AWD, TDI,
TDO, TMS, TMS2
Low-level output
current
MAX
–0 .3
IOL = IOL MAX
Input current (5 V tolerant input pins)
IOL
TYP (2)
0.15
VOL
II
MIN
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VIH
TEST CONDITIONS
mA
µA
µA
8
4
mA
2
4
–8
VOH = VOH MIN
–4
All other 3.3 V I/O (7)
–2
5 V tolerant
–4
mA
Source currents (out of the device) are negative while sink currents (into the device) are positive.
The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal VCC,
VCCIO, or VCCAD, room temperature.
This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST Timings section.
These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
Parameter does not apply to input-only or output-only pins.
Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal
Functions table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the
resulting value will always be low.
Copyright © 2009–2011, Texas Instruments Incorporated
37
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum parameters are characterized for operation at TA = 220°C unless otherwise noted, but may not be
production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature
performance. (1)
PARAMETER
TEST CONDITIONS
VCC Digital supply current (operating mode)
ICC
VCC Digital supply current (standby mode)
ICCIO
MAX
UNIT
SYSCLK = 48 MHz,
ICLK = 24 MHz, VCC = 2.05 V
110
mA
SYSCLK = 60 MHz,
ICLK = 30 MHz, VCC = 2.05 V
125
mA
OSCIN = 5 MHz, VCC = 2.05 V
1.30
mA
700
µA
All frequencies, VCC = 2.05 V
(10)
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 V
20
mA
VCCIO Digital supply current (standby mode) (9)
No DC load, VCCIO = 3.6 V (10)
250
µA
VCCIO Digital supply current (halt mode) (9)
No DC load, VCCIO = 3.6 V (10)
225
µA
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
15
mA
All frequencies, VCCAD = 3.6 V
10
µA
All frequencies, VCCAD = 3.6 V
10
µA
SYSCLK = 48 MHz, VCCP = 3.6 V
read operation
45
mA
SYSCLK = 60 MHz, VCCP = 3.6 V
read operation
55
mA
VCCP = 3.6 V program and erase
70
mA
VCCP = 3.6 V standby mode
operation (8)
10
µA
VCCP = 3.6 V halt mode
operation (8)
10
µA
ICCAD VCCAD supply current (standby mode)
VCCAD supply current (halt mode)
ICCP
(9)
TYP (2)
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VCC Digital supply current (halt mode) (8)
(8) (9)
MIN
VCCP pump supply current
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
(8) For flash banks/pumps in sleep mode.
(9) For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.
(10) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO – 0.2 V.
38
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Parameter Measurement Information
IOL
Tester Pin
Electronics
50 Ω
V LOAD
Output
Under
Test
CL
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I OH
Where:
IOL
=
IOH
=
VLOAD =
CL
=
IOL MAX for the respective pin (A)
IOH MIN for the respective pin(A)
1.5 V
150-pF typical load-circuit capacitance(B)
A.
For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range"
table.
B.
All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 7. Test Load Circuit
Copyright © 2009–2011, Texas Instruments Incorporated
39
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Timing Parameter Symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Compaction, CMPCT
RD
Read
CO
CLKOUT
RST
Reset, RST
ER
Erase
RX
SCInRX
ICLK
Interface clock
S
Slave mode
M
Master mode
SCC
SCInCLK
OSC, OSCI
OSCIN
SIMO
SPInSIMO
OSCO
OSCOUT
SOMI
SPInSOMI
Program, PROG
SPC
SPInCLK
Ready
SYS
System clock
Read margin 0, RDMRGN0
TX
SCInTX
access time
r
rise time
cycle time (period)
su
setup time
delay time
t
transition time
fall time
v
valid time
hold time
w
pulse duration (width)
P
R
R0
R1
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CM
Read margin 1, RDMRGN1
Lowercase subscripts and their meanings are:
a
c
d
f
h
The following additional letters are used with these meanings:
H
L
V
40
High
X
Unknown, changing, or don't care level
Low
Z
High impedance
Valid
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
External Reference Resonator/Crystal Oscillator Clock Option
The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 8 (a). The oscillator is a
single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to
the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes. Please note that external crystal mode is guaranteed to function only within
the temperature ranges of -40°C to 150°C. Above this recommended temperature range it is strongly
recommended to use an external clock signal as shown in Figure 8 (b).
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An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 8b.
OSCIN
C1
(A)
OSCIN
OSCOUT
Crystal
"
C2
(A)
!External
Clock Signal
(toggling 0 - VCC)
(b)
(a)
A.
OSCOUT
The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 8. Crystal/Clock Connection
Copyright © 2009–2011, Texas Instruments Incorporated
41
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled (1)
MIN
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
tw(OSCIL)
TYP
MAX UNIT
4
10 MHz
100
ns
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
f(OSCRST)
OSC FAIL frequency (2)
Switching Characteristics over Recommended Operating Conditions for Clocks (1) (2)
PARAMETER
f(SYS)
f(CONFIG)
f(ICLK)
f(ECLK)
tc(SYS)
tc(CONFIG)
tc(ICLK)
tc(ECLK)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
42
kHz
Not production tested.
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
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(1)
(2)
ns
53
System clock frequency (6)
TEST CONDITIONS (5)
MIN
External clock output frequency for ECP module
Cycle time, system clock
Cycle time, ECP module external clock output
UNIT
60 (7)
MHz
Pipeline mode disabled
24
MHz
24
MHz
Pipeline mode enabled
30
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
30
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
16.7
ns
Pipeline mode disabled
41.6
ns
Cycle time, system clock - flash config mode
Cycle time, interface clock
MAX
Pipeline mode enabled
System clock frequency - flash config mode
Interface clock frequency
(3) (4)
41.6
ns
Pipeline mode enabled
33.3
ns
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
33.3
ns
Pipeline mode disabled
41.6
ns
Not production tested.
f(SYS) = M × f(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f(SYS) = f(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
f(ECLK) = f(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
Only ZPLL mode is available. FM mode must not be turned on.
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
Flash Vread must be set to 5 V to achieve maximum system clock frequency.
Operating VCC range for this system clock frequency is 1.81 to 2.05 V.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
Switching Characteristics over Recommended Operating Conditions for External Clocks (1) (2)
(3)
(4)
(see Figure 9 and Figure 10)
PARAMETER
TEST CONDITIONS
MIN
SYSCLK or MCLK (5)
tw(COL)
ICLK: X is even or 1 (6)
Pulse duration, CLKOUT low
0.5tc(ICLK) – tf
ICLK: X is odd and not 1 (6)
tw(COH)
Pulse duration, CLKOUT high
0.5tc(SYS) – tr
ICLK: X is even or 1 (6)
0.5tc(ICLK) – tr
tw(EOH)
(6)
Pulse duration, ECLK low
Pulse duration, ECLK high
N is even and X is even or odd
0.5tc(ECLK) – tf
N is odd and X is even
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
N is odd and X is even
0.5tc(ECLK) – tr
N is odd and X is odd and not 1
(1)
(2)
(3)
(4)
(5)
(6)
ns
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
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tw(EOL)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK (5)
ICLK: X is odd and not 1
MAX
0.5tc(SYS) – tf
ns
ns
0.5tc(ECLK) – 0.5tc(SYS) – tr
Not production tested.
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
tw(COH)
CLKOUT
tw(COL)
Figure 9. CLKOUT Timing Diagram
tw(EOH)
ECLK
tw(EOL)
Figure 10. ECLK Timing Diagram
Copyright © 2009–2011, Texas Instruments Incorporated
43
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
RST AND PORRST TIMINGS
Timing Requirements for PORRST (1)
(see Figure 11)
MIN
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and become
active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and become
active during power down
0.6
1.5
1.1
2.75
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VIL(PORRST)
tsu(PORRST)r
tsu(VCCIO)r
th(PORRST)r
tsu(PORRST)f
th(PORRST)rio
th(PORRST)d
tsu(PORRST)fio
tsu(VCCIO)f
V
V
V
V
Low-level input voltage after VCCIO > VCCIOPORH
VIL
(1)
MAX UNIT
0.2 VCCIO
V
0.5
V
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
Setup time, VCCIO >VCCIOPORL before VCC > VCCPORL
0
ms
Hold time, PORRST active after VCC > VCCPORH
1
ms
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
µs
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
Hold time, PORRST active after VCC < VCCPORL
0
ms
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
Not production tested.
V CCP /VCCIO
V CC
V CCIOPORH
th(PORRST)rio
V CCPORH
V CCIOPORH
V CCIO
V CC
tsu(PORRST)f
th(PORRST)r
V CCIOPORL
V CC
VCCP/VCCIO
PORRST
th(PORRST)r
tsu(VCCIO)r
V CCPORL
V CCIOPORL
th(PORRST)d
tsu(PORRST)r
V IL
V CCPORH
tsu(PORRST)fio
tsu(PORRST)f
V CCPORL
V IL(PORRST)
tsu(VCCIO)f
VIL
VIL
V IL
V IL(PORRST)
NOTE: VCCIO > 1.1 V before VCC > 0.6 V
Figure 11. PORRST Timing Diagram
Switching Characteristics over Recommended Operating Conditions for RST (1)
PARAMETER
tv(RST)
tfsu
(2)
MIN
Valid time, RST active after PORRST inactive
4112tc(OSC)
Valid time, RST active (all others)
8tc(SYS)
Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump
stabilization time)
836tc(OSC)
MAX UNIT
ns
ns
(1)
(2)
Not production tested.
Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.
44
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
JTAG SCAN INTERFACE TIMING (JTAG CLOCK SPECIFICATION 10-MHz AND 50-pF LOAD ON
TDO OUTPUT) (1)
MIN
MAX UNIT
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
th(TCKr
-TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
th(TCKf
-TDO)
Hold time, TDO after TCKf
10
td(TCKf
-TDO)
Delay time, TDO valid after TCK fall (TCKf)
(1)
ns
45
ns
Not production tested.
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Figure 12. JTAG Scan Timings
Copyright © 2009–2011, Texas Instruments Incorporated
45
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
OUTPUT TIMINGS
Switching Characteristics for Output Timings versus Load Capacitance ©L) (1)
(see Figure 13)
PARAMETER
CL = 15 pF
tr
tr
tr
tf
tr
tf
(1)
MAX
0.5
2.5
CL = 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
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tf
Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
MIN
Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Rise time, RST
Rise time, 4mA, 5 V tolerant pins
CL = 150 pF
13
32
CL = 15 pF
3
10
CL = 50 pF
3.5
12
7
21
CL = 100 pF
Fall time, 4mA, 5 V tolerant pins
Rise time, all other output pins
Fall time, all other output pins
CL = 150 pF
9
28
CL = 400 pF
18
40
CL = 15 pF
2
8
CL = 50 pF
2.5
9
CL = 100 pF
8
25
CL = 150 pF
11
35
CL = 400 pF
20
45
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
UNIT
ns
ns
ns
ns
ns
ns
ns
Not production tested.
tr
tf
80%
Output
20%
VCC
80%
20%
0
Figure 13. CMOS-Level Outputs
46
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
INPUT TIMINGS
Timing Requirements for Input Timings (1) (2)
(see Figure 14)
MIN
tpw
(1)
(2)
Input minimum pulse width
MAX UNIT
tc(ICLK) + 10
ns
Not production tested.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
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Input
80%
V CC
80%
20%
20%
0
Figure 14. CMOS-Level Inputs
FLASH TIMINGS
Timing Requirements for Program Flash (1) (2)
MIN
TYP
MAX
UNIT
4
16
200
µs
8
32
s
tprog(16-bit)
Half word (16-bit) programming time
tprog(Total)
1M-byte programming time (3)
terase(sector)
Sector erase time, TA = –40°C to 150°C
twec
Write/erase cycles at TA = –40°C to 85°C
tfp(RST)
Flash pump settling time from RST to SLEEP
167tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
167tc(SYS)
ns
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
84tc(SYS)
ns
(1)
(2)
(3)
1.7
50000
s
cycles
Not production tested.
For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
The 1M-byte programming time includes overhead of state machine.
Copyright © 2009–2011, Texas Instruments Incorporated
47
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SPIn MASTER MODE TIMING PARAMETERS
SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2)
NO.
1
2 (6)
3 (6)
5 (6)
6 (6)
7 (6)
(1)
(2)
(3)
(4)
(5)
(6)
(see Figure 15)
MIN
MAX
100
256tc(ICLK)
0.5tc(SPC)M + 5
tc(SPC)M
Cycle time, SPInCLK (5)
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
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4 (6)
(3) (4)
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M – 5 – tf
tc(SPC)M – 5 – tr
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
UNIT
10
10
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t c(SPC)M ≥(PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 15. SPIn Master Mode External Timing (CLOCK PHASE = 0)
48
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SPIn Master Mode External Timing Parameters (1)
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (2)
NO.
1
2 (6)
3 (6)
5
6
7
(1)
(2)
(3)
(4)
(5)
(6)
(6)
(6)
(6)
(see Figure 16)
MIN
(5)
MAX
tc(SPC)M
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
4
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4 (6)
(3) (4)
UNIT
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t c(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 16. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Copyright © 2009–2011, Texas Instruments Incorporated
49
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SPIn SLAVE MODE TIMING PARAMETERS
SPIn Slave Mode External Timing Parameters (1)
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (2)
NO.
1
2 (7)
3 (7)
5
6
7
(1)
(2)
(3)
(4)
(5)
(6)
(7)
50
(7)
(7)
(7)
(see Figure 17)
MIN
MAX
100
256tc(ICLK)
tc(SPC)S
Cycle time, SPInCLK (6)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
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4
(7)
(3) (4) (5)
UNIT
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t c(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
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4
55
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 17. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
SPIn Slave Mode External Timing Parameters (1)
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (2)
NO.
1
tc(SPC)S
2 (7)
3 (7)
4 (7)
5
6
7
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(7)
(7)
(7)
Cycle time, SPInCLK (6)
(3) (4) (5)
(see Figure 18)
MIN
MAX
100
256tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid
(clock polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
6
UNIT
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
If the SPI is in slave mode, the following must be true: tc(SPC) ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t c(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
Copyright © 2009–2011, Texas Instruments Incorporated
51
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
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4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 18. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
52
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SCIn ISOSYNCHRONOUS MODE TIMINGS - INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode (1) (2)
(3) (4)
(see Figure 19)
(BAUD + 1)
IS EVEN OR BAUD = 0
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224 tc(ICLK)
3tc(ICLK)
(224 – 1) tc(ICLK)
ns
Cycle time,
SCInCLK
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) + 0.5tc(ICLK) – tf
0.5tc(SCC) + 0.5tc(ICLK)
ns
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) – 0.5tc(ICLK) – tr
0.5tc(SCC) – 0.5tc(ICLK)
ns
10
ns
tw(SCCH)
td(SCCH-TXV)
Delay time,
SCInCLK high to
SCInTX valid
Valid time,
SCInTX data after
SCInCLK low
tv(TX)
tsu(RX-SCCL)
tv(SCCL-RX)
(1)
(2)
(3)
(4)
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tc(SCC)
10
tc(SCC) – 10
tc(SCC) – 10
ns
Setup time,
SCInRX before
SCInCLK low
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
Valid time,
SCInRX data
after SCInCLK
low
–tc(ICLK) + tf + 20
–tc(ICLK) + tf + 20
ns
Not production tested.
BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
tc(SCC)
tw(SCCL)
tw(SCCH)
SCICLK
tv(TX)
td(SCCHĆTXV)
Data Valid
SCITX
tsu(RXĆSCCL)
SCIRX
B.
tv(SCCLĆRX)
Data Valid
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 19. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Copyright © 2009–2011, Texas Instruments Incorporated
53
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
SCIn ISOSYNCHRONOUS MODE TIMINGS - EXTERNAL CLOCK
Timing Requirements for External Clock SCIn Isosynchronous Mode (1) (2)
(3)
(see Figure 20)
MIN
MAX
UNIT
tc(SCC)
Cycle time, SCInCLK (4)
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + t r
ns
tv(TX)
Valid time, SCInTX data after SCInCLK low
tv(SCCL-RX)
(1)
(2)
(3)
(4)
ns
2tc(SCC) – 10
ns
0
ns
2tc(ICLK) + 10
ns
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tsu(RX-SCCL)
8tc(ICLK)
Setup time, SCInRX before SCInCLK low
Valid time, SCInRX data after SCInCLK low
Not production tested.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK).
tc(SCC)
tw(SCCH)
tw(SCCL)
SCICLK
tv(TX)
td(SCCHĆTXV)
Data Valid
SCITX
tsu(RXĆSCCL)
SCIRX
C.
tv(SCCLĆRX)
Data Valid
Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 20. SCIn Isosynchronous Mode Timing Diagram for External Clock
54
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
I2C TIMING
I2C Signals (SDA and SCL) Switching Characteristics (5) (6) Assumes testing over recommended operating
conditions.
I2C Signals (SDA and SCL) Switching Characteristics (1) (2)
STANDARD MODE
PARAMETER
MIN
MAX
150
FAST MODE
MIN
MAX
75
150
UNIT
tc(I2CCLK)
Cycle time, I2C module clock
75
tc(SCL)
Cycle time, SCL
10
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
µs
4
0.6
µs
Pulse duration, SCL low
4.7
1.3
µs
Pulse duration, SCL high
4
0.6
µs
250
100
ns
tw(SCLL)
tw(SCLH)
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
tr(SCL)
tr(SDA)
tf(SCL)
tf(SDA)
tsu(SCLH-SDAH)
tw(SP)
Cb
(5)
(6)
(1)
(2)
(3)
(4)
(4)
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th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START
condition)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
For I2C bus devices
Pulse duration, SDA high between STOP and START conditions
0
3.45
(3)
4.7
ns
µs
2.5
0
0.9
µs
µs
1.3
Rise time, SCL
1000
20+0.1Cb
(4)
300
ns
Rise time, SDA
1000
20+0.1Cb
(4)
300
ns
300
ns
300
Fall time, SCL
300
20+0.1Cb
(4)
Fall time, SDA
300
20+0.1Cb
(4)
Setup time, SCL high before SDA high (for STOP condition)
4.0
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
400
ns
µs
0.6
50
ns
400
pF
Not production tested.
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
Not production tested.
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum th(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
C b = The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Copyright © 2009–2011, Texas Instruments Incorporated
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SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
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SDA
tw(SDAH)
tw(SP)
tsu(SDA−SCLH)
tr(SCL)
tw(SCLL)
tsu(SCLH−SDAH)
tw(SCLH)
SCL
tf(SCL)
tc(SCL)
th(SCLL−SDAL)
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th(SDA−SCLL)
tsu(SCLH−SDAL)
th(SCLL−SDAL)
Stop
Start
Repeated
Stop
D.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
E.
The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL
signal.
F.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH).
G.
Cb = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Figure 21. I2C Timings
STANDARD CAN CONTROLLER (SCC) MODE TIMINGS
Dynamic Characteristics for the CANSTX and CANSRX Pins (1)
PARAMETER
td(CANSTX)
td(CANSRX)
(1)
(2)
56
Delay time, transmit shift register to CANSTX pin (2)
Delay time, CANSRX pin to receive shift register
MIN
MAX
UNIT
15
ns
5
ns
Not production tested.
These values do not include the rise/fall times of the output buffer.
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
EXPANSION BUS MODULE TIMING
Expansion Bus Timing Parameters (1)
–55°C ≤ TA ≤ 220°C, 3.0 V ≤ V CC ≤ 3.6 V (see Figure 22 and Figure 23)
MIN
MAX
td(COH-EBADV)
Delay time, CLKOUT high to EBADDR valid
21.4
ns
th(COH-EBADIV)
Hold time, EBADDR invalid after CLKOUT high
12.4
ns
td(COH-EBOE)
Delay time, CLKOUT high to EBOE fall
11.4
ns
th(COH-EBOEH)
Hold time, EBOE rise after CLKOUT high
11.4
ns
Delay time, CLKOUT low to write strobe (EBWR) low
11.3
ns
Hold time, EBWR high after CLKOUT low
11.6
ns
th(COL-EBWRH)
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Cycle time, CLKOUT
td(COL-EBWR)
20.8
UNIT
tc(CO)
ns
tsu(EBRDATV-COH)
Setup time, EBDATA valid before CLKOUT high (READ) (2)
th(COH-EBRDATIV)
Hold time, EBDATA invalid after CLKOUT high (READ)
(–14.7)
ns
td(COL-EBWDATV)
Delay time, CLKOUT low to EBDATA valid (WRITE) (3)
16.1
ns
th(COL-EBWDATIV)
Hold time, EBDATA invalid after CLKOUT low (WRITE)
14.7
ns
td(COH-EBCS0)
Delay, CLKOUT high to EBCS0 fall
13.6
ns
Hold, EBCS0 rise after CLKOUT high
13.2
ns
15.2
ns
SECONDARY TIMES
th(COH-EBCS0H)
tsu(COH-EBHOLDL)
tsu(COH-EBHOLDH)
(1)
(2)
(3)
Setup time, EBHOLD low to CLKOUT high (2)
Setup time, EBHOLD high to CLKOUT high
(2)
10.9
ns
10.5
ns
Not production tested.
Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
Valid after CLKOUT goes low for write cycles.
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SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
tc(CO)
CLKOUT
th(COH-EBADIV)
td(COH-EBADV)
Valid
EBADDR
th(COH-EBRDATIV)
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tsu(EBRDATV-COH)
Valid
EBDATA
th(COH-EBOEH)
td(COH-EBOE)
EBOE
td(COH-EBCS0)
th(COH-EBCS0H)
EBCS0
tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)
EBHOLD
1 Hold State
Figure 22. Expansion Memory Signal Timing - Reads
58
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
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tc(CO)
CLKOUT
th(COH-EBADIV)
td(COH-EBADV)
Valid
EBADDR
th(COL-EBWDATIV)
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td(COL-EBWDATV)
Valid
EBDATA
th(COL-EBWRH)
td(COL-EBWR)
EBWR
td(COH-EBCS0)
td(COH-EBCS0)
EBCS0
tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)
EBHOLD
1 Hold State
Figure 23. Expansion Memory Signal Timing - Writes
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HIGH-END TIMER (HET) TIMINGS
Minimum PWM Output Pulse Width:
This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
Minimum Input Pulses that Can Be Captured:
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The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
NOTE
Once the input pulse width is greater than LRP, the resolution of the measurement is still
HRP. (That is, the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
60
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
MULTI-BUFFERED A-TO-D CONVERTER (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on V
SS and V CC , from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to AD
REFLO unless otherwise noted.
Resolution
10 bits (1024 values)
Monotonic
Assured
00h to 3FFh [00 for VAI ≤ AD REFLO ; 3FF for VAI ≥ AD REFHI ]
Output conversion code
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Table 13. MibADC Recommended Operating Conditions (1)
ADREFHI
A-to-D high-voltage reference source
ADREFLO
A-to-D low-voltage reference source
VAI
Analog input voltage
IAIC
Analog input clamp current (2)
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
(1)
(2)
MIN
MAX
UNIT
VSSAD
VCCAD
V
VSSAD
VCCAD
V
VSSAD – 0.3
VCCAD + 0.3
V
–2
2
mA
For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 14. Operating Characteristics over Full Ranges of Recommended Operating Conditions (1) (2) (3)
PARAMETER
RI
Analog input resistance
DESCRIPTION/CONDITIONS
MAX UNIT
500
Ω
10
pF
Sampling
30
pF
250
Analog input capacitance
See Figure 24.
IAIL
Analog input leakage current
See Figure 24.
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which
specified accuracy is maintained
ADREFHI - ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value. See Figure 25.
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the MibADC. MibADC transfer
characteristics, excluding the quantization
error. See Figure 26.
E TOT
Total error/Absolute accuracy
Maximum value of the difference between an
analog value and the ideal midstep value.
See Figure 27.
(3)
(4)
TYP
Conversion
See Figure 24.
CI
(1)
(2)
MIN
(4)
–1
3
1
µA
5
mA
3.6
V
±1.5
LSB
±2
LSB
±2.5
LSB
Not production tested.
INL and DNL values are valid for a max ADCCLK frequency of 15 MHz. For frequencies greater than 15 MHz missing codes are
expected at higher temperature.
VCCAD = ADREFHI
1 LSB = (ADREFHI - ADREFLO)/210 for the MibADC
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SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
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External
Rs
MibADC
Input Pin
Ri
Sample Switch
Sample
Capacitor
Parasitic
Capacitance
V src
R leak
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Ci
Figure 24. MibADC Input Equivalent Circuit
Table 15. Multi-Buffer ADC Timing Requirements (1)
MIN
µs
µs
Delay time, conversion time
0.55
µs
Delay time, total sample/hold and conversion time
1.55
µs
td(SH)
Delay time, sample and hold time
td©)
td(SHC)
(1)
(2)
MAX UNIT
1
Cycle time, MibADC clock
(2)
NOM
0.067
tc(ADCLK)
Not production tested.
This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
The differential nonlinearity error shown in Figure 25 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
!
!
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 25. Differential Nonlinearity (DNL)
62
Copyright © 2009–2011, Texas Instruments Incorporated
SM470R1B1M-HT
SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
www.ti.com
The integral nonlinearity error shown in Figure 26 (sometimes referred to as linearity error) is the deviation of the
values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
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At Transition
011/100
(ć 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (ć 1/4 LSB)
0 ... 000
0
A.
1
2
3
4
5
Analog Input Value (LSB)
6
7
1 LSB = (ADREFHI - ADREFLO)/210
Figure 26. Integral Nonlinearity (INL) Error
The absolute accuracy or total error of an MibADC as shown in Figure 27 is the maximum value of the difference
between an analog value and the ideal midstep value.
A.
1 LSB = (ADREFHI - ADREFLO)/210
Figure 27. Absolute Accuracy (Total) Error
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SPNS155D – SEPTEMBER 2009 – REVISED JUNE 2011
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REVISION HISTORY
Changes from Revision C (August 2010) to Revision D
Page
•
Changed GIOA[6]/INT[6] HFQ pin from 48 to 46 ............................................................................................................... 13
•
Changed VSSIO HFQ pin from 18 to 16 ................................................................................................................................ 18
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64
Copyright © 2009–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2011
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PACKAGING INFORMATION
Orderable Device
(1)
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SM470R1B1MHFQS
ACTIVE
CFP
HFQ
84
1
TBD
Call TI
N / A for Pkg Type
SM470R1B1MKGDS1
ACTIVE
XCEPT
KGD
0
36
TBD
Call TI
N / A for Pkg Type
(3)
Samples
(Requires Login)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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IMPORTANT NOTICE
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