TI TMS470PLF111

TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
z
z
– Class II Serial Interface B (C2SIb)
– Normal 10.4 Kbps and 4X Mode 41.6 Kbps
– Inter-Integrated Circuit (I2C) Module
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
High-Performance Static CMOS Technology
TMS470 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
z
Integrated Memory
– 128K-Byte Program Flash
– One Bank With 10 Contiguous Sectors
– 32K-Byte Program Flash with ECC
– One Bank with 4 Contiguous Sectors
– 8K-Byte Static RAM (SRAM)
z
High-End Timer (HET)
– 29 Programmable I/O Channels:
– 25 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
z
Operating Features
– Low-Power Modes: Doze and Sleep
– Industrial/Automotive Temperature Ranges
z
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (ECLK)
z
System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Real-Time Interrupt (RTI) Timer
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Vectored Interrupt Module (VIM) with 32
Channels
– System Integrity and Failure Detection
– ICE Breaker
– Cyclic Redundancy Checker (CRC) with
Parallel Signature Analysis (PSA)
z
16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample/Conversion Time
– Calibration Mode and Self-Test Features
z
34 Dedicated General-Purpose I/O (GIO) Pins
and 48 Additional Peripheral I/Os
z
32 External Interrupts
On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1(1) (JTAG) Test-Access
Port
z
z
Frequency-Modulated Zero-Pin Phase-Locked
Loop (FMZPLL)-Based Clock Module With
Prescaler
– Multiply-by-8 Internal FMZPLL Option
Six Communication Interfaces:
– Serial Peripheral Interface (SPI)
– 255 Programmable Baud Rates
– Two Local Interconnect Network Interfaces
(LINs)
– Supports the Serial Communication
Interface (SCI)
– Standard CAN Controller (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
z
z
144-Pin Pb-Free/Green Plastic Low-Profile
Quad Flatpack (PGE Suffix)
z
Development System Support Tools Available
– Code Composer Studio™ Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
1
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
74
73
75
78
77
76
82
81
80
79
85
84
83
86
94
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95
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100
102
101
72
109
110
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64
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111
112
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36
34
35
32
33
30
31
24
25
26
27
28
29
22
23
21
18
19
20
16
17
LIN1RX
LIN1TX
VSS
OSCIN
OSCOUT
VCC
SPI1CLK
SPI1SIMOI
SPI1SOMI
SPI1SCS[1]
SPI1SCS[0]
VCCIO
VSS
GIOB[7]
GIOB[6]
GIOB[5]
GIOB[4]
GIOB[3]
GIOB[2]
GIOB[1]
GIOB[0]
TCK
TRST
TDO
REGDIS
AWD
TDI
TMS
HET[21]
HET[22]
HET[23]
VCC
VSS
HET[24]
HET[25]
HET[26]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
143
144
1
GIOA[5]
GIOA[4]
GIOA[3]
GIOA[2]
GIOA[0]
GIOA[1]
VCCIOR
VSS
HET[27]
HET[28]
GIOD[0]
GIOD[1]
ECLK
GIOD[2]
GIOD[3]
GIOD[7]
GIOD[6]
CANSRX
CANSTX
RST
HET[9]
HET[10]
HET[11]
VCCP
VSS
FLTP2
VCC
VSS
HET[12]
HET[13]
HET[14]
HET[15]
HET[16]
HET[17]
GIOD[5]
GIOD[4]
106
105
104
103
108
107
LIN2TX
LIN2RX
GIOE[0]
GIOE[1]
VSS
VCCIOR
C2SILPN
C2SITX
C2SIRX
VSS
VCC
GIOC[0]
GIOC[1]
GIOC[2]
GIOC[3]
VSS
VCCIOR
GIOC[4]
GIOC[5]
GIOC[6]
GIOC[7]
ADIN1[0]
ADIN1[1]
ADIN1[2]
ADIN1[3]
ADIN1[4]
ADIN1[5]
VSSAD
ADIN1[6]
ADIN1[7]
ADIN1[8]
ADIN1[9]
ADIN1[10]
ADIN1[11]
ADIN1[12]
ADIN1[13]
TMS470PLF111 144-PIN PGE PACKAGE (TOP VIEW)
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
ADIN1[14]
ADIN1[15]
VCCAD
ADREFHI
ADREFLO
VSSAD
ADEVT
TEST
PORRST
I2C1SDA
I2C1SCL
VSS
VCC
GIOA[6]
GIOA[7]
VSS
VCCIOR
SPI1SCS[2]
HET[8]
HET[7]
HET[6]
HET[5]
VSS
VCC
VSS
VCCIO
HET[4]
HET[3]
HET[2]
HET[1]
HET[0]
HET[20]
VSS
VCCIO
HET[19]
HET[18]
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
description
The TMS470PLF111(1) devices are members of the Texas Instruments TMS470 family of general-purpose16/
32-bit reduced instruction set computer (RISC) microcontrollers. The PLF111 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high
instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The TMS470PLF111 utilizes the bigendian format where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The PLF111 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The real-time interrupt (RTI) module on the PLF111 has the option to be driven by the oscillator clock. The
digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires.
The PLF111 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information
on the flash, see the flash section of this data sheet. The flash on the PLF111 device can be protected by means
of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to
correct single bit errors and detect double bit errors for each 64-bits of data. This is achieved by maintaining
an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory
space.
The PLF111 device has six communication interfaces: SPI, two LINs, CAN (SCC), C2SI, and I2C. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The LIN is the local interconnect network interface which also supports the SCI - a full-duplex,
serial I/O interface intended for asynchronous communication between the CPU and other peripherals using
the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol
that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per
second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., automotive
and industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the
PLF111 to transmit and receive messages on a class II network following an SAE Standard J1850 Class B Data
Communication Network Interface standard. The I2C module is a multi-master communication module providing
an interface between the PLF111 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C
supports both 100 Kbps and 400 Kbps speeds.
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. The PLF111 HET peripheral contains the XOR-share feature. This feature allows two adjacent
HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard
HET.
The PLF111 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can
be grouped by software for sequential conversion sequences. There are three separate groupings, all three of
which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode.
1 Throughout the remainder of this document, the TMS470PLF111 shall be referred to as either the full device name or PLF111.
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3
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
description (continued)
The frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module contains a phase-locked loop,
a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the
FMZPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMZPLL
provides the input to the global clock module (GCM). The GCM module subsequently provides system clock
(HCLK), real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2) and peripheral interface
clock (VCLK) to all other PLF111 device modules.
The PLF111 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK). The ECLK frequency is a user-programmable ratio of the peripheral interface clock
(VCLK) frequency.
4
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
device characteristics
The PLF111 device is a derivative of the F05 Platform Architecture. Table 1, Device Characteristics, identifies
all the characteristics of the PLF111 device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470PLF111
COMMENTS FOR PLF111
MEMORY
For device memory mapping, please see page 13.
Pipeline/Non-Pipeline
INTERNAL
MEMORY
1 Bank 128K-Byte Flash
Flash is pipeline-capable
1 Bank 32K-Byte Flash with ECC
8K-Byte SRAM
CRC, 1-channel
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority Table (Table 6, Interrupt Priority (VIM)). For the peripheral
address ranges, see Table 3, Peripheral Memory and Table 4, Peripheral Select Map with Address Range.
CLOCK
FMZPLL
Frequency-modulated zero-pin PLL has no external loop filter pins.
GENERAL-PURPOSE
I/Os
34 I/O
Ports A, B, C and D each have eight (8) external pins with external
interrupt capability. Port E has only two (2) external pins.
ECP
YES
LIN
2 (2-pin)
CAN
(HECC and/or SCC)
SCC
SPI
1
C2SIb
1
I2C
1
HET with
XOR Share
29 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 16-channel
64-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
5V
PINS
144
PACKAGE
PGE
POST OFFICE BOX 1443
Also supports SCI mode of operation
Three chip select pins.
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This HR
sharing is independent of whether or not the odd pin is available
externally. If an odd pin is available externally and shared, then the odd
pin can only be used as a general-purpose I/O.
Both the logic and registers for a full 16-channel MibADC are present.
• HOUSTON, TEXAS 77251-1443
5
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
functional block diagram
External Pins
External Pins
ECLK
System
Module
VCCP
FLTP2
RST
PORRST
ICE
Breaker
ADIN[15:0]
TMS470 CPU
MibADC
64-Word
FIFO
FLASH
128K Bytes
+
32K Bytes
with ECC
RAM
(8K Bytes)
ADEVT
ADREFHI
ADREFLO
VCCAD
VSSAD
CPU Bus
TRST
TCK
TDI
TDO
TMS
TEST
HET
64 Words
Peripheral
Bridge
SCC
HET [28:0]
CANSTX
VIM
OSCOUT
OSCIN
FMZPLL
Peripheral Bus (VBUS)
CANSRX
Cyclic
Redundancy
Checker
(CRC) w/
PSA
GCM
LIN1
LIN1TX
LIN1RX
LIN2
I2C
LIN2TX
LIN2RX
I2CSDA
I2CSCL
SPISIMO
SPI
SPISOMI
SPICLK
SPISCS[2:0]
C2SITX
VCCIOR
RTI1, DWD,
AWD
6
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GIO
GIOA[7:0]/INT[7:0]
GIOB[7:0]/INT[15:8]
GIOC[7:0]/INT[23:16]
GIOD[7:0]/INT[31:24]
GIOE[1:0]
VREG
AWD
REGDIS
C2SI
• HOUSTON, TEXAS 77251-1443
C2SIRX
C2SILPN
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
Terminal Functions
TERMINAL
NAME
PIN
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
42
HET[1]
43
HET[2]
44
HET[3]
45
HET[4]
46
HET[5]
51
HET[6]
52
HET[7]
53
HET[8]
54
HET[9]
129
HET[10]
130
HET[11]
131
HET[12]
137
HET[13]
138
HET[14]
139
HET[15]
140
HET[16]
141
HET[17]
142
HET[18]
37
HET[19]
38
HET[20]
41
HET[21]
29
HET[22]
30
HET[23]
31
HET[24]
34
HET[25]
35
HET[26]
36
HET[27]
117
HET[28]
118
CANSRX
126
CANSTX
127
Timer input capture or output compare. The HET[28:0] applicable pins
can be programmed as general-purpose input/output (GIO) pins. All
are high-resolution pins.
5V
2mA
20 μA
Programmable The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent
IPD
of whether or not the odd pin is available externally. If an odd pin is
available externally and shared, then the odd pin can only be used as
a general-purpose I/O.
STANDARD CAN CONTROLLER (SCC)
5V
2mA
4mA
20 uA IPU
SCC receive pin or GIO pin
SCC transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIB)
C2SILPN
102
C2SIRX
100
C2SITX
101
2mA
5V
2mA
4mA
C2SI module loopback enable pin or GIO pin
20 μA
Programmable C2SI module receive data input pin or GIO pin
IPU/IPD
C2SI module transmit data output pin or GIO pin
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.).
Programmable IPU’s/IPD’s are disabled by default, except for I2C1SDA and I2C1SCL.
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7
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
GIOA[0]/INT[0]
113
GIOA[1]/INT[1]
114
GIOA[2]/INT[2]
112
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
GENERAL-PURPOSE I/O (GIO)
GIOA[3]/INT[3]
111
GIOA[4]/INT[4]
110
GIOA[5]/INT[5]
109
GIOA[6]/INT[6]
59
GIOA[7]/INT[7]
58
GIOB[0]/INT[8]
21
GIOB[1]/INT[9]
20
GIOB[2]/INT[10]
19
GIOB[3]/INT[11]
18
GIOB[4]/INT[12]
17
GIOB[5]/INT[13]
16
GIOB[6]/INT[14]
15
GIOB[7]/INT[15]
14
GIOC[0]/INT[16]
97
GIOC[1]/INT[17]
96
GIOC[2]/INT[18]
95
GIOC[3]/INT[19]
94
GIOC[4]/INT[20]
91
GIOC[5]/INT[21]
90
GIOC[6]/INT[22]
89
GIOC[7]/INT[23]
88
GIOD[0]/INT[24]
119
GIOD[1]/INT[25]
120
GIOD[2]/INT[26]
122
GIOD[3]/INT[27]
123
GIOD[4]/INT[28]
144
GIOD[5]/INT[29]
143
GIOD[6]/INT[30]
125
GIOD[7]/INT[31]
124
GIOE[0]
106
5V
2mA
General-purpose input/output pins.
20 μA
Programmable
GIOA[7:0]/INT[7:0], GIOB[7:0]/INT[15:8], GIOC[7:0]/INT[23:16],
IPD/IPU
and GIOD[7:0]/INT[31:24] are interrupt-capable pins.
GIOE[1]
105
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
Programmable IPU’s/IPD’s are disabled by default, except for I2C1SDA and I2C1SCL.
8
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
ADEVT
66
ADIN[0]
87
ADIN[1]
86
ADIN[2]
85
ADIN[3]
84
ADIN[4]
83
ADIN[5]
82
ADIN[6]
80
ADIN[7]
79
ADIN[8]
78
ADIN[9]
77
5V
2mA
20 uA
Programmable
MibADC event input. Can be programmed as a GIO pin.
Pull-up/pulldown
5V
MibADC analog input pins
ADIN[10]
76
ADIN[11]
75
ADIN[12]
74
ADIN[13]
73
ADIN[14]
72
ADIN[15]
71
ADREFHI
69
5V REF
MibADC module high-voltage reference input
ADREFLO
68
GND REF
MibADC module low-voltage reference input
VCCAD
70
5V REF
VSSAD
67
81
MibADC analog supply voltage
GND REF
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE (SPI)
SPISCS[0]
11
SPISCS[1]
10
SPISCS[2]
55
SPICLK
7
SPISIMO
8
SPISOMI
9
LIN1RX
1
LIN1TX
2
LIN2RX
107
LIN2TX
108
5V
2mA
5V
4mA
SPI slave chip select. Can be programmed as a GIO pin.
20 uA
Programmable
Pull-up/pull- SPI clock. SPICLK can be programmed as a GIO pin.
down
SPI data stream. Slave in/master out. Can be programmed as a GIO pin.
SPI data stream. Slave out/master in. Can be programmed as a GIO pin.
BUFFERED LOCAL INTERCONNECT NETWORK 1 (LIN1)
5V
2mA
LIN1/SCI1 data receive.Ccan be programmed as a GIO pin.
20 uA
Programmable
Pull-up/pull- LIN1/SCI1 data transmit. Can be programmed as a GIO pin.
down
BUFFERED LOCAL INTERCONNECT NETWORK 2 (LIN2)
5V
2mA
LIN2/SCI2 data receive. Can be programmed as a GIO pin.
20 uA
Programmable
Pull-up/pull- LIN2/SCI2 data transmit. Can be programmed as a GIO pin.
down
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
Programmable IPU’s/IPD’s are disabled by default, except for I2C1SDA and I2C1SCL.
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9
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
INTER-INTEGRATED CIRCUIT (I2C)
I2CSDA
62
I2CSCL
63
OSCIN
4
OSCOUT
5
5V
2mA
I2C serial data pin or GIO pin
20 μA
Programmable
I2C serial clock pin or GIO pin
Pull-up
FREQUENCY-MODULATED ZERO-PIN PHASE-LOCKED LOOP (FMZPLL)
1.8-V
Crystal connection pin or external clock input
8mA
External crystal connection pin
SYSTEM MODULE (SYS)
ECLK
121
5V
PORRST
64
5V
RST
REGDIS
128
25
5V
8mA
4mA
5V
20 uA
Programmable Bidirectional pin. ECLK can be programmed as a GIO pin or the output of
Pull-up/pull- VCLK.
down
IPD (100 μA)
Input master chip power-up reset. External VCC monitor circuitry must
assert a power-on reset.
IPU (100 μA)
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low
only).
To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
IPD (100 μA)
Enables/disables the internal voltage regulator. Pulling this pin high
disables the internal voltage regulator. Pulling this pin low enables the
internal voltage regulator. Low power modes are not supported if the
internal voltage regulator is disabled.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
26
5V
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC network
circuit is connected. If the user is not using AWD, TI recommends that this
pin be connected to ground or pulled down to ground by an external
resistor.
8mA
For more details on the external RC network circuit, see the application
note Analog Watchdog Resistor, Capacitor and Discharge Interval
Selection Constraints (literature number SPNA005).
TEST/DEBUG (T/D)
TCK
22
5V
IPD (100 μA)
Test clock. TCK controls the test hardware (JTAG).
TDI
27
5V
IPU (100 μA)
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
TDO
24
TEST
65
5V
IPD (100 μA)
Test enable. Reserved for internal use only. TI recommends that this pin
be connected to ground or pulled down to ground by an external resistor.
TMS
28
5V
IPU (100 μA)
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG).
TRST
23
5V
IPD (100 μA)
Test hardware reset to TAP. IEEE Standard 1149-1 (JTAG) Boundary-Scan
Logic.
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test address
(JTAG).
8mA
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
Programmable IPU’s/IPD’s are disabled by default, except for I2C1SDA and I2C1SCL.
10
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
FLASH
FLTP2
134
5V
Flash test pad 2. For proper operation, this pin must not be connected
[no connect (NC)].
VCCP
132
5V PWR
Flash external pump voltage (5 V). This pin is required for both Flash read
and Flash program and erase operations.
SUPPLY VOLTAGE CORE (1.8 V)
6
32
VCC
49
60
1.8-V
PWR
98
135
VREG output voltage / Core logic supply voltage
The functionality of the Vcc pins are dependant upon the state of the
REGDIS pin. If REGDIS pin is HIGH, the internal VREG is disabled and
core logic voltage should be supplied through these pins. If REGDIS pin
is LOW, the internal VREG is enabled and the VREG output voltage is
output on these pins.
SUPPLY VOLTAGE DIGITAL I/O AND REGULATOR (5 V)
12
VCCIO
39
Digital I/O supply voltage
47
56
VCCIOR
5-V
PWR
92
Digital I/O and internal regulator supply voltage
103
115
SUPPLY GROUND CORE
3
33
50
VSS
61
GND
Core supply ground reference
99
133
136
SUPPLY GROUND DIGITAL I/O
13
40
48
VSSIO
57
GND
Digital I/O supply ground reference
93
104
116
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
Programmable IPU’s/IPD’s are disabled by default, except for I2C1SDA and I2C1SCL.
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11
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
PLF111 DEVICE-SPECIFIC INFORMATION
memory map
Figure 1 shows the memory map of the PLF111 device.
Memory (4G Bytes)
0xFFFF_FFFF
System Module Control Registers
(512K Bytes)
0xFFF8_0000
0xFFF7_FFFF
Peripheral Control Registers
(512K Bytes)
0xFF00_0000
0xFEFF_FFFF
CRC/PSA
(16M Bytes)
0xFE00_0000
Reserved
0x0800_1FFF
RAM
8K Bytes
0x0800_0000
0x0040_7FFF
0x0040_0000
FLASH ECC
32K Bytes
1 Bank
0x0001_FFFF
FLASH
128K Bytes
1 Bank
Reserved
FIQ
IRQ
0x0000_0024
0x0000_0023
0x0000_0000
Reserved
Data Abort
Exception, Interrupt, and
Reset Vectors
Prefetch Abort
Software Interrupt
• HOUSTON, TEXAS 77251-1443
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
Reset
0x0000_0000
Figure 1. TMS470PLF111 Memory Map
POST OFFICE BOX 1443
0x0000_001C
Undefined Instruction
A. The CPU registers are not a part of the memory map.
12
0x0000_0023
0x0000_0020
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
memory selects
Memories in the PLF111 device are located at fixed addresses. Tables below detail the mapping of the memory
regions.
Table 2. Memory Frame Assignment
MEMORY FRAME NAME BASE ADDRESS ENDING ADDRESS MEMORY TYPE ACTUAL MEMORY SIZE
nCS0
CSRAM0
0x0000 0000
0x0001 FFFF
Flash
128KBytes
0x0040 0000
0x0040 7FFF
Flash-ECC
32KBytes
0x0800 0000
0x0800 1FFF
Internal RAM
8KBytes
Table 3. Peripheral Memory
PERIPHERAL
MEMORY NAME
ADDRESS RANGE
BASE ADDRESS ENDING ADDRESS
PERIPHERAL
MEMORY CHIP
SELECT
PERIPHERAL MEMORY
POWERDOWN
CONTROL REGISTER
CAN (SCC) RAM
0xFF1E 0000
0xFF1F FFFF
PCS[15]
PCSPWRDWNSET0[15]
ADC RAM
0xFF3E 0000
0xFF3F FFFF
PCS[31]
PCSPWRDWNSET0[31]
HET RAM
0xFF46 0000
0xFF47 FFFF
PCS[35]
PCSPWRDWNSET1[3]
Table 4. Peripheral Select Map with Address Range
PERIPHERAL
NAME
ADDRESS RANGE
BASE ADDRESS ENDING ADDRESS
PERIPHERAL
SELECT
PERIPHERAL POWERDOWN
CONTROL REGISTER
SPI
0xFFF7 F400
0xFFF7 F5FF
PS[2]
PSPWRDWNSET0[9:8]
LIN2
0xFFF7 E600
0xFFF7 E6FF
PS[6]
PSPWRDWNSET0[26]
LIN1
0xFFF7 E500
0xFFF7 E5FF
PS[6]
PSPWRDWNSET0[25]
SCC
0xFFF7 DC00
0xFFF7 DCFF
PS[8]
PSPWRDWNSET1[0]
I2C
0xFFF7 D400
0xFFF7 D4FF
PS[10]
PSPWRDWNSET1[8]
C2SI
0xFFF7 D000
0xFFF7 D0FF
PS[11]
PSPWRDWNSET1[12]
MibADC
0xFFF7 C000
0xFFF7 C1FF
PS[15]
PSPWRDWNSET1[29:28]
GIO
0xFFF7 BC00
0xFFF7 BDFF
PS[16]
PSPWRDWNSET2[1:0]
HET
0xFFF7 B800
0xFFF7 B8FF
PS[17]
PSPWRDWNSET2[4]
Table 5. System Peripheral Registers
FRAME NAME
BASE ADDRESS ENDING ADDRESS
CRC/PSA
0xFE00 0000
VIM RAM
0xFFF8 2000
0xFEFF FFFF
0xFFF8 2FFF
Flash wrapper
0xFFF8 7000
0xFFF8 7FFF
PCR Registers
0xFFFF E000
0xFFFF E0FF
RTI
0xFFFF FC00
0xFFFF FCFF
VIM Registers
0xFFFF FE00
0xFFFF FEFF
System Registers
0xFFFF FF00
0xFFFF FFFF
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13
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
memory
F05 flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions.
The PLF111 flash memory and internal static RAM memory locations can be swapped by configuring the SYS
module BMMCR1 register.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
flash protection keys
The PLF111 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the PLF111 are located in the
last 4 words of the first 8K sector.
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz (versus a system
clock frequency of 24 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the Flash can be read with no wait
states when memory addresses are sequential (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a "0"). In other words, the
PLF111 device powers up and comes out of reset in non-pipeline mode with a default number of wait
states set to 1.
14
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
memory (continued)
flash program and erase
The PLF111 device flash contains one 128K-byte memory array (or bank) and consists of ten sectors. These
ten sectors are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
16K Bytes
0x0000_4000
0x0000_7FFF
3
16K Bytes
0x0000_8000
0x0000_BFFF
4
16K Bytes
0x0000_C000
0x0000_FFFF
5
16K Bytes
0x0001_0000
0x0001_3FFF
6
16K Bytes
0x0001_4000
0x0001_7FFF
7
16K Bytes
0x0001_8000
0x0001_BFFF
8
8K Bytes
0x0001_C000
0x0001_DFFF
9
8K Bytes
0x0001_E000
0x0001_FFFF
MEMORY ARRAYS
(OR BANKS)
BANK0
(128K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
The PLF111 device also contains flash ECC memory. The flash ECC bank (BANK1) is 16 bits wide and cannot
be reused for program storage and execution. Only sectors 0 and 1 are used for ECC. The bank is sized as
follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
8K Bytes
0x0040_0000
0x0040_1FFF
1
8K Bytes
0x0040_2000
0x0040_3FFF
2
8K Bytes
0x0040_4000
0x0000_5FFF
3
8K Bytes
0x0040_6000
0x0000_7FFF
MEMORY ARRAYS
(OR BANKS)
BANK1
(32K Bytes)
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
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15
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
interrupt priority (VIM)
The vectored interrupt module (VIM) provides a fully programmable priority scheme. Interrupt requests originating from the PLF111 peripheral modules (i.e., SPI; LIN1 or LIN2; RTI; etc.) are assigned to channels within
the 32-channel VIM where, via programmable register mapping, the interrupt priority of the channels can be
changed. Programming multiple interrupt sources to the same VIM channel effectively shares the VIM channel
between sources.
The VIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the VIM to be of either type:
z
Fast interrupt request (FIQ)
z
Normal interrupt request (IRQ)
The VIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order
in the VIM (0 [highest] and 31 [lowest] priority). For VIM default mapping, channel priorities, and their associated
modules, see Table 6, Interrupt Priority (VIM).
Table 6. Interrupt Priority (VIM)
MODULES
INTERRUPT SOURCES
System
System error
0
System
SW interrupt (SSI)
1
RTI
RTI compare interrupt 0
2
RTI
RTI compare interrupt 1
3
RTI
RTI compare interrupt 2
4
RTI
RTI compare interrupt 3
5
RTI
RTI overflow interrupt 0
6
RTI
RTI overflow interrupt 1
RESERVED
7
8
GIO
GIO interrupt A
9
GIO
GIO interrupt B
10
HET
HET level 0 interrupt
11
HET
HET level 1 interrupt
12
SPI1
SPI1 level 0 interrupt
13
SPI1
SPI1 level 1 interrupt
14
LIN2
LIN2 level 0 interrupt
15
LIN2
LIN2 level 1 interrupt
16
SCC
SCC level 0 interrupt
17
SCC
SCC level 1 interrupt
18
ADC
ADC level 0 interrupt
19
ADC
ADC level 1 interrupt
20
I2C
I2C level 0 interrupt
21
I2C
I2C level 1 interrupt
22
FLASH ECC
Flash ECC interrupt
23
C2SIb interrupt
25
RESERVED
C2SIb
16
DEFAULT VIM
INTERRUPT REQUEST
MAPPING
24
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
interrupt priority (VIM) (continued)
Table 6, Interrupt Priority (VIM). Interrupt Priority (VIM) (Continued)
MODULES
INTERRUPT SOURCES
DEFAULT VIM
INTERRUPT REQUEST
MAPPING
LIN1
LIN1 level 0 interrupt
26
LIN1
LIN1 level 1 interrupt
27
RESERVED
28
RESERVED
29
RESERVED
30
RESERVED
31
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17
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The PLF111 MibADC module stores its digital results in one of three FIFO buffers. There is one FIFO buffer
for each conversion group [event, group1 (G1), and group2 (G2)], and the total MibADC FIFO on the device is
divided amongst these three regions. The size of the individual group buffers are software programmable.
MibADC buffers can be serviced by interrupts.
MibADC event trigger capability
z
All three conversion groups can be configured for event-triggered operation, providing up to three eventtriggered groups.
z
The trigger source and polarity can be selected individually for group 1, group 2 and the event group from
the options identified in Table 7, MibADC Event Hookup Configuration.
Table 7. MibADC Event Hookup Configuration
SOURCE SELECT BITS FOR G1, G2, OR EVENT
(G1SRC[1:0], G2SRC[1:0], or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
000
ADEVT
EVENT2
001
HET1
EVENT3
010
HET3
EVENT4
011
Reserved
EVENT5
100
Reserved
EVENT6
101
Reserved
EVENT7
110
Reserved
EVENT8
111
Reserved
EVENT #
18
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470 family.
These support tools include:
z
Code Composer Studio™ Integrated Development Environment (IDE)
– Fully integrated suite of software development tools
– Includes Compiler/Assembler/Linker, Debugger, and Simulator
– Supports Real-Time analysis, data visualization, and open API
z
Optimizing C compiler
– Supports high-level language programming
– Full implementation of the standard ANSI C language
– Powerful optimizer that improves code-execution speed and reduces code size
– Extensive run-time support library included
– TMS470 control registers easily accessible from the C program
– Interfaces C functions and assembly functions easily
– Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
z
Assembly language tools (assembler and linker)
– Provides extensive macro capability
– Allows high-speed operation
– Allows extensive control of the assembly process using assembler directives
– Automatically resolves memory references as C and assembly modules are combined
For more information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio is a trademark of Texas Instruments.
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19
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470 family.
TMS 470 P L F 1 1 1 PGE I
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
Device Voltage:
Program Memory Types:
Architecture:
Device Family:
Pin Compatibility:
Program Memory Class:
470 = TMS470 ARM7TDMI CPU RISC-Embedded MCU Family
L = 5V
C
F
L
B
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
P = Platform architecture
1 = Body
1 = First Pinout
2 = Second Pinout
1 = 0
<= 64K Bytes
1
<= 128K Bytes
2
<= 256K Bytes
3
<= 384K Bytes
5
<= 512K Bytes
7
<= 768K Bytes
A - E<= 1M - 4M Bytes
Operating Free-Air
Temperature Ranges:
I =
T =
Q =
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
Package: PGE = 144-Pin Pb-Free/Green Plastic Low-Profile Quad Flatpack
(LQFP)
Figure 2. TMS470 Family Nomenclature
20
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
device identification code register
The device identification code register identifies the coprocessor status, an assigned device-specific part number, the technology family (TF), the I/O voltage, whether or not parity is supported, the levels of flash and RAM
erro detection, and the device version. The PLF111 device identification code register value is 0x0006_3405.
Table 8. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
24
FFFF_FFF0 CP15
14
13
12
11
TF
I/O
VOLT
PP
R-K
R-K
R-K
10
9
22
21
20
19
18
17
BIT 16
PART NUMBER
TF
R-K
R-K
R-K
BIT 15
23
8
FLASH ECC
RAM
ECC
R-K
R-K
7
6
5
4
3
2
1
BIT 0
VERSION
1
0
1
R-K
R-1
R-0
R-1
LEGEND:
R = Read only, -K = Value constant after RESET
Device ID Bit Allocation Register Field Descriptions
Bit
31
Name
Value
Description
This bit indicates the presence of coprocessor (CP15)
CP15
0
No coprocessor present in the device
1
Coprocessor present in the device
30–17
PART
NUMBER
These bits indicate the assigned device-specific part number.
The assigned device-specific part number for the PLF111 device is
00000000000011 (0x3).
16–13
TF
Technology family bit
These bits indicate the technology family (C05, F05, F035, C035).
0001
12
11
F05
I/O voltage bit
This bit identifies the core power supply:
I/O
VOLT
0
3.3 V
1
5V
Peripheral parity bit
This bit indicates whether parity is supported:
PP
0
No parity on peripheral
1
Parity on peripheral
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21
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
Device ID Bit Allocation Register Field Descriptions (Continued)
Bit
10–9
8
Name
Value
Description
Flash ECC bits
These bits indicate the level of error detection and correction on the flash
memory:
FLASHECC
00
No error detection/correction
01
Program memory with parity
10
Program memory with ECC
11
Reserved
RAM ECC bits
This bit indicates the presence of error detection and correction on the
CPU RAM:
RAMECC
0
RAM ECC not present
1
RAM ECC present
7–3
VERSION
These bits identify the silicon version of the device.
2–0
101
Bits 2:0 are set to 101 by default to indicate a platform device.
22
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
device part numbers
Table 9, Device Part Number lists all the available TMS470PLF111 devices.
Table 9. Device Part Number
DEVICE PART
NUMBER
PROGRAM MEMORY
ROM
FLASH
EEPROM
PACKAGE TYPE
100-PIN
LQFP
−40°C TO 85°C
X
TMS470PLF111PGEI
X
X
TMS470PLF111PGET
X
X
TMS470PLF111PGEQ
X
X
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TEMPERATURE RANGES
144-PIN
LQFP
• HOUSTON, TEXAS 77251-1443
−40°C TO 105°C
−40°C TO 125°C
X
X
23
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, A version
(unless otherwise noted)(1)
Supply voltage ranges: VCC (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (flash pump)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input voltage range: All input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input clamp current: ADIN[0:15] IIK (VI < 0 or VI > VCCAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10 mA
All other pins IIK (VI < 0 or VI > VCCIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature ranges, TA: I version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 All voltage values are with respect to their associated grounds.
device recommended operating conditions(3)
MIN
NOM
MAX
UNIT
VCCIOR
Digital I/O and internal regulator supply voltage
4.75
5
5.25
V
VCC
Voltage regulator output voltage, internal regulator enabled
1.81
1.91
2.05
V
VCCAD
MibADC supply voltage
4.75
5
5.25
V
VCCP
Flash pump supply voltage
4.75
5
5.25
V
VSS
Digital logic supply ground
VSSAD
MibADC supply ground
TA
TJ
0
Operating free-air temperature
− 0.1
0.1
V
I version
− 40
85
°C
T version
− 40
105
°C
Q version
− 40
125
°C
− 40
150
°C
Operating junction temperature
3 All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
24
V
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
electrical characteristics over recommended operating free-air temperature range(1)
PARAMETER
TEST CONDITIONS
Vhys
Input hysteresis
VIL
Low-level input voltage
All inputs(2)
VIH
High-level input voltage
All inputs
VOH
High-level output voltage(4)
IIC
Input clamp current (I/O pins)(5)(9)
100μA IPU/IPD
All other pins
IOL
Low-level output
current
0.3VCCIOR
V
0.7VCCIOR
VCCIOR + 0.5
V
0.2 VCCIOR
0.2
IOH = IOH MAX
0.8 VCCIOR
IOH = 50 μA
VCCIOR − 0.2
−2
IIL Pulldown
VI = VSS
−1
1
IIH Pulldown
VI = VCCIOR
5
40
IIL Pullup
VI = VSS
–40
–5
2
IIH Pullup
VI = VCCIOR
−1
1
IIL Pulldown
VI = VSS
−1
1
IIH Pulldown
VI = VCCIOR
23
88
IIL Pullup
VI = VSS
−204
−69
IIH Pullup
VI = VCCIOR
−1
1
−1
1
TDO, ECLK, AWD
8
RST, SPICLK,
SPISIMO, SPISOMI, VOL = VOL MAX
CANSTX, C2SITX
4
mA
μA
mA
2
All other output pins
High-level output
current
V
V
VI < VSSIO − 0.3 or VI > VCCIOR + 0.3
No IPU/IPD
UNIT
VSS − 0.5
IOL = 50 μA
TDO, ECLK, AWD
IOH
MAX
V
IOL = IOL MAX
Low-level output voltage(4)
II
TYP
0.5
VOL
20μA IPU/IPD
MIN
VOH = VOH MIN
−8
RST, SPICLK,
SPISIMO, SPISOMI,
CANSTX, C2SITX
−4
All other output pins
−2
mA
CI
Input capacitance
6
pF
CO
Output capacitance
7
pF
1 Source currents (out of the device) are negative while sink currents (into the device) are positive.
2 This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 40.
3 VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
4 Parameter does not apply to input-only or output-only pins.
5 I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
6 For flash banks/pumps in sleep mode.
7 The PLF111 device will enter low power mode only if the internal regulator is enabled. Low power modes are not supported when internal
regulator is disabled.
8 Based on resistor of 5.3Ω and capacitor of 1μF in series with VCCP.
9 The following pins do not have clamping diodes: nPORRST, REGDIS, TCK, nTRST and TEST. The application must not exceed an input
current of +-2mA with an absolute maximum rating of +-20mA.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
electrical characteristics over recommended operating free-air temperature range(1) (continued)
MODE
Operating
PARAMETER
MAX
UNIT
VCCIOR regulator/IO supply current/Vcc
digital supply current
HCLK = 48MHz, VCLK = 48 MHz, PLL enabled
VCCIOR = 5.25 V
Internal regulator enabled
TEST CONDITIONS
92
mA
VCCIOR regulator/IO supply current/Vcc
digital supply current
HCLK = 24MHz, VCLK = 24 MHz, PLL enabled
VCCIOR = 5.25 V
Internal regulator enabled
62
mA
VCCIOR regulator/IO supply current/Vcc
digital supply current
HCLK = 8MHz, VCLK = 8 MHz, PLL disabled
VCCIOR = 5.25 V
Internal regulator enabled
42
mA
VCCAD supply current
VCCAD = 5.25 V
18
mA
VCCP pump supply current
VCCP = 5.25 V, read operation
10
mA
VCCP pump supply current
VCCP = 5.25 V, peak program and erase
operation
30
mA
18
mA
15
mA
VCCP = 5.25 V, peak program and erase
VCCP pump supply current
operation(8)
VCCP = 5.25 V, average program and erase
VCCP pump supply current
Doze(7)
Sleep(7)
operation (8)
MIN
TYP
VCCIOR regulator/IO supply current/Vcc
digital supply current
I version (85°C)
OSCIN = 8 MHz, VCCIOR = 5.25 V
660
uA
VCCIOR regulator/IO supply current/Vcc
digital supply current
Q version (125°C)
OSCIN = 8 MHz, VCCIOR = 5.25 V
850
uA
VCCAD supply current
VCCAD = 5.25 V(6)
10
uA
(6)
VCCP pump supply current
VCCP = 5.25 V
10
uA
VCCIOR regulator/IO supply current/Vcc
digital supply current
I version (85°C)
VCC = 2.05 V
110
uA
VCCIOR regulator/IO supply current/Vcc
digital supply current
Q version (125°C)
VCC = 2.05 V
350
uA
VCCAD supply current
VCCAD = 5.25 V(6)
10
uA
10
uA
VCCP pump supply current
VCCP = 5.25 V
(6)
1Source currents (out of the device) are negative while sink currents (into the device) are positive.
2This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 40.
3VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
4Parameter does not apply to input-only or output-only pins.
5I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
6For flash banks/pumps in sleep mode.
7The PLF111 device will enter low power mode only if the internal regulator is enabled. Low power modes are not supported when internal
regulator is disabled.
8 Based on the condition that a parallel capacitor of 1uF is placed on the VCCP line and series resistor of 5.3 Ohm is placed in the VCCP line
9The following pins do not have clamping diodes: nPORRST, REGDIS, TCK, nTRST and TEST. The application must not exceed an input current
of +-2mA with an absolute maximum rating of +-20mA.
26
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SPNS113 – OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin(A)
IOH
= IOH MIN for the respective pin(A)
VLOAD = 1.5 V
CL
= 150-pF typical load-circuit capacitance(B)
NOTES: A. For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
Compaction, CMPCT
VCLK
M
OSC
VBUS Interface clock
Master mode
OSCIN
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
28
H
High
X
L
V
Low
Valid
Z
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
device clock
HCLK (to SYSTEM)
GCM
FMzPLL
GCLK (to CPU)
/2 option
OSCIN
1
/1..8
X8
RTICLK1 (to RTI1)
/1..4
0
VCLK (to Peripherals)
VCLK2 (to HET)
HET
VCLK2
HRP
HET Loop Resolution Clock
LRP
/20
/1..64
5
..2
HET High Resolution Clock
VCLK
VCLK
/1,2,..256
/2,3..224
/1,2..256
/1,2..63
/1,2..256
/1,2..65536
/1,2,..1024
SPI Baud
Rate
Prop_seg
Phase_seg2
SPI
SCI Baud
Rate
SCI, LIN
ADCLK
C2SI Baud
Rate
ADC
C2SI
I2C Baud
Rate
I2C
ECLK
External Clock
Phase_seg1
CAN Baud Rate
CAN (SCC)
Figure 4. TMS470 Platform Clock Domains Block Diagram
Table 10. GCM Clock Source Assignments
GCM SOURCE NUMBER
CLOCK SOURCE
0
OSCIN
1
FMzPLL output
2
RESERVED
3
RESERVED
4
RESERVED
5
RESERVED
6
RESERVED
7
RESERVED
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8 V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 5b.
OSCIN
C1(A)
OSCOUT
Crystal
OSCIN
C2(A)
External
Clock Signal
(toggling 0–1.8 V)
(a)
(b)
A. The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 5. Crystal/Clock Connection
30
OSCOUT
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SPNS113 – OCTOBER 2006
FMZPLL and clock specifications
input frequency increase for FMzPLL
DIVCLK
OSCIN
To GCM
FMzPLL
/2
CSVSTAT.CLKSR2V
CDIS.CLKSR2OFF
PLLCTL1.OSCDIV
GHVSRC.GHVSRC[2:0]
Figure 6. FMZPLL Clock Input Circuitry
The FMzPLL has an input frequency (DIVCLK) range from 4MHz to 10MHz. In order to allow for input OSCIN
frequencies higher than 10Mhz, the oscillator input must be divided down by 2 through a software programmable
register bit PLLCTL1.OSCDIV. DIVCLK can be either OSCIN/1 or OSCIN/2. This is selectable via the OSC_DIV
bit in the PLLCTL1 register. The default value for this bit is divide-by-1.
After reset, the system clock and CPU clock are driven by OSCIN, and CLKSR2OFF switches off DIVCLK to
the PLL. Software must ensure that CLKSR2OFF (CSDIS) is only set to 1 if DIVCLK does not exceed the
10MHz maximum input frequency of the FMzPLL. If CLKSR2OFF is set to one, the PLL will start its locking
process. Once the PLL is locked it will signal this with the CLKSR2V bit (CSVSTAT) and the software can then
switch to the PLL output clock with the GHVSRC[2:0] bits (GHVSRC). This is shown in Figure 6. For more
information, please see the System Architecture specification.
The FMZPLL only supports a multiplication factor of 8 only.
timing requirements for input clocks(1)
MIN
TYP
MAX
UNIT
20
MHz
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
Pulse duration, OSCIN high
15
tw(OSCIH)
f(OSCRST)
(2)
4
ns
600
OSC FAIL frequency
kHz
1 Frequency modulation mode of the FMzPLL is not supported.
2 Causes a device reset (specifically a clock reset) by setting the OSC RST bit in SYSESR and the OSC FAIL flag bit in GLBSTAT as defined in
the TMS470 Platform Architecture documentation.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
FMZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for clocks(1)(2)(3)
TEST CONDITIONS(4)
PARAMETER
MIN
Pipeline mode enabled
MAX
UNIT
48
MHz
f(HCLK)
System clock frequency(5)
24
MHz
f(VCLK)
Peripheral VBUS clock frequency
48
MHz
f(VCLK2)
HET clock frequency
48
MHz
f(ECLK)
External clock output frequency for ECP module
48
MHz
f(DIVCLK)
FMzPLL clock in frequency
10
MHz
tc(HCLK)
Cycle time, system clock
tc(VCLK)
Pipeline mode disabled
Pipeline mode enabled
20.8
ns
Pipeline mode disabled
41.6
ns
Cycle time, peripheral VBUS clock
20.8
ns
tc(VCLK2)
Cycle time, HET clock
20.8
ns
tc(ECLK)
Cycle time, ECP module external clock output
20.8
ns
tc(DIVCLK)
Cycle time, FMzPLL clock in
100
ns
1 f(HCLK) = M * f(OSC) / R, where M = 8, and R = {1,2,3,4,5,6,7,8}.
f(VCLK) = f(HCLK) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the peripheral VBUS clock divider ratio.
2 f(ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCTRL.[15:0] register bits in the ECP module.
3 Frequency modulation mode of the FMzPLL is not supported.
4 Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
5 Flash Vread must be set to 5Vand must always be set at 5V.
32
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
sequence to wake up from doze mode
In doze mode, the HCLK, GCLK, VCLK, and VCLK2 are all turned off. Also, the main oscillator is the only clock
source running while in doze mode. Please see the TMS470 Platform Architecture Specification (SPNU230)
for more details on the doze mode. Doze mode is not supported if the internal voltage regulator is disabled.
The RTICLK1 is still active, which allows the RTI module to generate periodic wake up interrupts, if required.
The other wakeup options are: external interrupts via GIO pins, CAN message, SCI/LIN, C2SI and I2C. The
sequence for waking up from doze mode is described below:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Wakeup request is received/generated. Figure 7 shows the CAN module generating the wakeup interrupt.
This wakeup event causes the core VREG to wake up.
Since the main oscillator is running already it is used as the clock source upon wakeup.
The software runs using the main oscillator as the clock source. Also, now the PLL can be enabled.
Once the PLL has acquired LOCK, the software can switch over to using the PLL output clock for normal
operation.
Ready for Normal Operation/CAN Message
8 MHz
CrystalOscillator
with PLL
Wake-up
CPU
On-Chip
VREG
ON
OFF
e.g. CAN
Module
CPU
Wake-up
VREG
Update Status and Prepare for
Normal Operation
Figure 7. Wake Up From Doze Mode
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
sequence to wake up from sleep mode
In sleep mode, ALL the clocks are turned off: HCLK, GCLK, VCLK, VCLK2, and RTICLK1. All the clock sources
are also disabled. Please refer to the TMS470 Platform Architecture Specification (SPNU230) for more details
on sleep mode. Sleep mode is not supported if the internal voltage regulator is disabled.
The wakeup options are: external interrupts via GIO pins, CAN, SCI/LIN, C2SI and I2C. The sequence for
waking up from the sleep mode is described below:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Wakeup request is received/generated. Figure 8 shows the CAN module generating the wakeup interrupt
based on a message received.
This wakeup event causes the on-chip VREG to wake up.
Once the on-chip VREG wakes up, the CPU and the main oscillator start to wake up.
Once the main oscillator output is valid, the software runs using the main oscillator as the clock source.
The software can prepare for normal operation. Also, now the PLL can be enabled.
Once the PLL has acquired LOCK, the software can switch over to using the PLL output clock for normal
operation.
Startup to Normal Operation
~2ms, depending on xtal
Ready for Normal Operation/CAN Message
8 MHz
CrystalOscillator
with PLL OFF
Wake-up
oscillator
ON
On-Chip
VREG
Wake-up
CPU
OFF
Wake-up
VREG
e.g. CAN
Module
CPU
Start Oscillator
Update Status and Prepare
for Normal Operation
Figure 8. Wake Up From Sleep Mode
34
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summary of wakeup from low power modes
MODE
Doze
CLOCK
SOURCE
ACTIVE
Oscillator
ACTIVE
CLOCKS
WAKEUP
OPTIONS
WAKEUP
CLOCK
SOURCE
GIO interrupts, CAN Rx,
RTICLK1 SCI/LIN Rx, C2SI Rx, RTI, Oscillator
I2C SDA
WAKEUP TIMES
VREG wakeup(1) + flash pump sleep(2) + flash pump standby(3)
GIO interrupts, CAN Rx,
VREG wakeup + Osc. startup + 1024 Osc. cycles + flash pump sleep
SCI/LIN Rx, C2SI Rx, I2C Oscillator
+ flash pump standby
SDA
1 VREG wakeup = thalt-normal. See page 39.
2 Flash pump sleep = minimum time for which the flash pump is in sleep mode before it enters standby mode = 2μs. The flash pump sleep2standby
counter must be programmed such that the (counter value X wakeup clock source period) is at least 2μs.
3 Flash pump standby = minimum time for which the flash pump is in standby mode before it enters active mode = 1μs. The flash pump
standby2active counter must be programmed such that the (counter value X wakeup clock source period) is at least 1μs.
4 Low power modes are not supported if the internal voltage regulator is disabled.
Sleep
None
None
Note: The flash banks will wake up in parallel with the flash pump. The flash banks can wake up faster than
the flash pump and therefore the overall flash module wake up time is determined by the pump wake up time.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
FMZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 9)(1)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
3
tw(EOL)
Pulse duration, ECLK low
0.5tc(ECLK) – tf
ns
4
tw(EOH)
Pulse duration, ECLK high
0.5tc(ECLK) – tr
ns
1 f(ECLK) = f(VCLK)/N where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCTRL.[15:0] register bits in the system module.
4
ECLK
3
Figure 9. ECLK Timing Diagram
36
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
power-up sequence
The power up sequence starts with the input voltage rising above VCCIOR_min and the release of reset. The
oscillator must first start and its amplitude grow to an acceptable level. Simultaneously, the flash pump and
banks power up. Code can be executed from RAM any time after SYSTEM_RST is released; however, an
access to flash will be held off until the flash is ready.
VCCIOR_min
VCCIOR
150 us
>0
PORRST
osc startup time
2 - 3(A) ms
1024 OSC
OSC_VALID
8 OSC
PLL_RST
8 VCLK
SYSTEM_RST
FLASH_PUMP_RST
min 2 μs
Sleep
Bank Power Up
Active
Sleep-to-StdbyStdby-to-Active
min 2 μs
Sleep
Pump Power Up
1
2
3
4
min 1 μs
Sleep-to-Stdby
5
6
7
8
Stdby-to-Active
9
Active
10
NOTE A: Oscillator startup time is highly influenced by the crystal, load capacitor values, temperature and voltage.
Figure 10. Power-Up Sequencing
Step 1.
Step 2.
Step 3.
Power is turned on and VCCIOR starts to rise. The PORRST signal must be released (driven HIGH) no
earlier than 150μs after the VCCIOR reaches 4.75V. OSC clock is still unstable. The oscillator start up time
is typically 2-3ms from the time VCCIOR_min is reached.
Once the oscillator starts up, the PLL wrapper counts an additional 1024 OSC clocks before asserting
OSC_VALID.
After OSC_VALID is active, the global clock module (GCM) starts generating all domain clocks (GCLK,
HCLK, VCLK, VCLK2). The PLL wrapper counts 8 OSC clocks before deasserting PLL_RST.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
power-up sequence (continued)
Step 4.
Step 5.
Step 6.
Step 7.
Step 8.
Step 9.
Step 10.
38
After PLL_RST is deasserted, all flip flops will be in their reset state. The System module counts eight
VCLK cycles and then releases the SYSTEM_RST to the rest of the device. The external RST pin is
equivalent to the internal SYSTEM_RST signal. Asserting external RST will synchronously extend the
internal SYSTEM_RST.
Flash bank(s) are now in standby mode. This transition occurs only when waking up from low power
modes. The flash banks are already in an active state on power up.
Flash bank(s) are now in active mode. No read access to bank yet -- only DC current.
Reset to flash pumps is released.
Flash pump module is now in standby mode.
Flash pump module is now in active mode. no read access to bank yet -- only DC current.
Flash wrapper generates the BANK_RDY signal and the flash access can now proceed.
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SPNS113 – OCTOBER 2006
internal voltage regulator specifications
PARAMETER
MIN
DESCRIPTION
(1)
tD(VCCIOR)0-3
Delay time, 5V input supply to ramp from 0V to 4.75V
tV(PORRST)L
Valid time, PORRST active after 5V input supply becomes ≥ 4.75V
VCCIORmin(PORRST)f Minimum input voltage, when PORRST must be made active during power down or brown out
Cmin(VCC)core
Capacitance distributed over all core VCC pins for voltage regulator stability
ESR(max)core
Total combined ESR of stabilization capacitors on core Vcc pins
MAX
UNIT
25
us
150
us
4.75
V
10
uF
0
0.25
Ω/pin
1 Ramping at minimum tD(VCCIOR)0-3 with large load capacitance Cmin can cause large transient currents (approximately 1.9 A).
4.75V
VCCIORmin(PORRST)f
tV(PORRST)L
VCCP/VCCIOR
tD(VCCIOR)0-3
PORRST
Figure 11. PORRST Timing Requirements
VREG recommended operation conditions
TEST CONDITIONS
MIN
MAX
UNIT
Normal mode, regulator active
0
100
mA
3
mA
PARAMETER
ICC
VCC load rating
Halt mode, regulator active
VREG halt-mode timing characterisitics(2)(3)
PARAMETER
MIN
MAX
UNIT
tnormal-halt
transition time between normal mode and halt mode
70
nS
thalt-normal
transition time between halt mode and normal mode
20
μS
2 These times only reflect VREG transition times. Times for other components are not included.
3 Device low power modes are not supported when the VREG is disabled
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
RST and PORRST timings
switching characteristics over recommended operating conditions for RST(1)
PARAMETER
MIN
tv(RST)
Valid time, RST active after PORRST inactive
tfsu
Flash start up time, from RST inactive to fetch of first instruction from Flash (Flash
pump stabilization time)
MAX
UNIT
1048tc(OSC)
ns
5
μs
1 Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.
40
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
MAX
UNIT
1
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
ns
TCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 12. JTAG Scan Timings
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41
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 13)
MIN
PARAMETER
tr
tf
tr
tf
tr
tf
Rise time, 8mA buffers
Fall time, 8mA buffers
Rise time, 4mA buffers
Fall time, 4mA buffers
Rise time, 2mA buffers
Fall time, 2mA buffers
0.5
2.5
CL= 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL= 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
tf
80%
Output
20%
VCC
80%
20%
Figure 13. CMOS-Level Outputs
42
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0
ns
ns
ns
ns
ns
ns
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
input timings for general purpose input output pins
timing requirements for input timings(1)(2)((see Figure 14)
MIN
tpw
tc(VCLK) + 10
Input minimum pulse width
MAX
UNIT
ns
1 tc(VCLK) = peripheral VBUS clock cycle time = 1/f(VCLK)
2 Applicable to peripheral pins in GPIO mode only.
tpw
Input
80%
20%
VCC
80%
20%
0
Figure 14. CMOS-Level Inputs
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
flash timings
timing requirements for program flash(1)
MIN
Flash pump stabilization time
tacc_delay
Flash bank stabilization time
tprog(16-bit)
From sleep mode to
standby mode
2
From standby mode to
active mode
1
1.9
From standby mode to
active mode
0.1
Total programming
terase(sector)
Sector erase time(2)
UNIT
us
4
time(2)(3)
tprog(Total)
MAX
us
From sleep mode to
standby mode
Half word (16-bit) programming time(2)
TYP
16
200
μs
1.3
15
s
2
15
s
100
cycles
85°C(2)
twec
Write/erase cycles at TA =
tfp(RST)
Flash pump settling time from RST to SLEEP
143tc(HCLK)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
143tc(HCLK)
ns
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
72tc(HCLK)
ns
1 For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
2 Flash program/erase is specified only at a temperature range of -40C to 85C.
3The total programming time includes overhead of state machine, but does not include data transfer time.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)(1)(2)(3)(see Figure 15)
MIN
NO.
1
2(5)
3(5)
Cycle time, SPInCLK
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
125
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tv(SPCH-SIMO)M Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M – 5 – tf
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
6
tv(SPCH-SOMI)M Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
ns
ns
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
UNIT
256tc(VCLK)
tw(SPCL)M
6(5)
7(5)
MAX
tc(SPC)M
4(5)
5(5)
(4)
ns
ns
6
Setup time CS active until SPICLK high (clock polarity = 0)
C2TDELAY*tc(VCLK)
+ 2*tc(VCLK) tf(SPICS) + tr(SPICLK)
ns
Setup time CS active until SPICLK low (clock polarity = 1)
C2TDELAY*tc(VCLK)
+ 2*tc(VCLK) tf(SPICS) + tf(SPICLK)
ns
8(5) tC2TDELAY
Hold time SPICLK low CS until inactive (clock polarity = 0)
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK)
+ tc(VCLK) - tf(SPICLK)
+ tr(SPICS)
ns
Hold time SPICLK high until CS inactive (clock polarity = 1)
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK)
+ tc(VCLK) - tr(SPICLK)
+ tr(SPICS)
ns
9(5) tT2CDELAY
1 The MASTER bit is set and the CLOCK PHASE bit is cleared.
2 tc(VCLK) = interface clock cycle time = 1/f(VCLK)
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 100 ns, where PS is the prescale value.
For PS values of 0:tc(SPC)M = 2tc(VCLK) ≥ 100 ns.
5 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPInSOMI
Figure 15. SPIn Master Mode External Timing (CLOCK PHASE = 0)
SPInCLK
SPInSIMO
Master Out Data Is Valid
8
9
SPInCSn
Figure 16. SPI Master Mode Chip Select timing (CLOCK PHASE = 1; CLOCK POLARITY = 0)
SPInCLK
SPInSIMO
Master Out Data Is Valid
8
9
SPInCSn
Figure 17. SPI Master Mode Chip Select timing (CLOCK PHASE = 1; CLOCK POLARITY = 1)
46
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)(1)(2)(3) (see Figure 18)
NO.
1
2(5)
3(5)
4(5)
5(5)
6(5)
7(5)
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
(4)
MIN
MAX
125
256tc(VCLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)
6
UNIT
ns
1 The MASTER bit is set and the CLOCK PHASE bit set.
2 tc(VCLK) = interface clock cycle time = 1/f(VCLK)
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 100 ns, where PS is the prescale value.
For PS values of 0:tc(SPC)M = 2tc(VCLK) ≥ 100 ns.
5 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 18. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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SPNS113 – OCTOBER 2006
SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)(1)(2)(3)(4)(see Figure 19)
NO
1
2(6)
3(6)
(5)
MIN
MAX
100
256tc(VCLK)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid (clock
polarity = 0)
0.5tc(VCLK)
1.5tc(VCLK)
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid (clock
polarity = 1)
0.5tc(VCLK)
1.5tc(VCLK)
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S –1.5tc(VCLK)-tf
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
tc(SPC)S –1.5tc(VCLK)-tr
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
4(6)
5(6)
6(6)
7(6)
UNIT
ns
1 The MASTER bit is cleared and the CLOCK PHASE bit is cleared.
2 If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value.
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 tc(VCLK) = interface clock cycle time = 1/f(VCLK)
5 When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 100 ns, where PS is the prescale value.
For PS values of 0:tc(SPC)S = 2tc(VCLK) ≥ 100 ns.
6 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 19. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
50
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SPNS113 – OCTOBER 2006
SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)(1)(2)(3)(4)(see Figure 20)
NO
1
2(6)
3(6)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
(5)
MIN
MAX
100
256tc(VCLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S –0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S –0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S –0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S –0.25tc(VCLK)
0.5tc(SPC)S + 0.25tc(VCLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(VCLK)
1.5tc(VCLK)
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid (clock
polarity = 1)
0.5tc(VCLK)
1.5tc(VCLK)
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S –1.5tc(VCLK)-tf
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
tc(SPC)S –1.5tc(VCLK)-tr
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 1)
6
4(6)
5(6)
6(6)
7(6)
UNIT
ns
1 The MASTER bit is cleared and the CLOCK PHASE bit is set.
2 If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value.
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 tc(VCLK) = interface clock cycle time = 1/f(VCLK)
5 When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 100 ns, where PS is the prescale value.
For PS values of 0:tc(SPC)S = 2tc(VCLK) ≥ 100 ns.
6 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 20. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
NOTE :
52
Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
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SPNS113 – OCTOBER 2006
I2C timing
Table 11, I2C Signals (SDA and SCL) Switching Characteristics(1) below assumes testing over recommended
operating conditions.
Table 11. I2C Signals (SDA and SCL) Switching Characteristics(1)
STANDARD
FAST MODE
MODE
UNIT
MIN MAX
MIN MAX
PARAMETER
tc(I2CCLK)
Cycle time, I2C module clock
75
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START condition)
4.7
0.6
μs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START condition)
4
0.6
μs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
μs
tw(SCLH)
Pulse duration, SCL high
4
0.6
μs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
th(SDA-SCLL)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
For I2C bus devices
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
tw(SP)
Cb
150
0 3.45(2)
0
4.7
1.3
4.0
0.6
0
Pulse duration, spike (must be suppressed)
(3)
75
400
Capacitive load for each bus line
150
ns
ns
0.9
μs
μs
μs
50
ns
400
pF
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
2 The maximum th(SDA-SCLL) for I2C bus devices needs only be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
3 Cb = The total capacitance of one bus line in pF.
SDA
tsu(SDA-SCLH)
tw(SDAH)
tw(SCLL)
tr(SCL)
tw(SP)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
Stop
tf(SCL)
th(SDA-SCLL)
Start
th(SCLL-SDAL)
tsu(SCLH-SDAL)
Repeated
Start
Stop
NOTE:A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
NOTE:The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
NOTE:A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
NOTE:Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
Figure 21. I2C Timings
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53
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
standard CAN controller (SCC) mode timings
dynamic characteristics for the CANSTX and CANSRX pins
MIN
PARAMETER
td(CANSTX)
Delay time, transmit shift register to CANSTX pin(1)
td(CANSRX)
Delay time, CANSRX pin to receive shift register
1 These values do not include rise/fall times of the output buffer.
54
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MAX
UNIT
15
ns
5
ns
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
high-end timer (HET) timings
dynamic characteristics for the HET pins
MIN
PARAMETER
topw(HET)
tipw(HET)
Output pulse width, this is the minimum pulse width that can be generated(1)
Input pulse width, this is the minimum pulse width that can be captured
(2)
MAX
UNIT
1/f(VCLK2)
ns
1/f(VCLK2)
ns
1 topw(HET) = HRP(min) = hr(min) / SYSCLK
2 tipw(HET) = LRP(min) = hr(min) * lr(min) / SYSCLK
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55
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . .00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions(1)
ADREFHI
ADREFLO
MIN
MAX
UNIT
A-to-D high -voltage reference source
VSSAD
VCCAD
V
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
VAI
Analog input voltage
IAIC
Analog input clamp current(2)
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
−2
2
mA
1 For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
2 Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions(3)(4)
PARAMETER
MAX
UNIT
50
100
Ω
250
500
Ω
See Figure 22
24
pF
See Figure 22
7
pF
DESCRIPTION/CONDITIONS
RMUX
Analog input mux-on resistance
See Figure 22
RADC
ADC sample switch on-resistance
See Figure 22
CMUX
Input mux capacitance
CADC
ADC sample switch-on capacitance
IAIL
Analog input leakage current
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
EINL
ETOT
–1
1
μA
5
mA
V
Difference between the actual step width and the
ideal value. (See Figure 23)
±1.5
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error.
(See Figure 24)
±2.0
LSB
Total error/Absolute accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 25)
±2
LSB
4 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
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4.75
TYP
5.25
3 VCCAD = ADREFHI
56
MIN
TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
multi-buffered A-to-D converter (MibADC) (continued)
Input
switch
AIN0
Input
switch
AIN1
Input
switch
AIN15
Rmux
Rmux
Sample
switch
Rmux
Cmux
Radc
Cadc
Figure 22. MibADC Input Equivalent Circuit
multi-buffer adc timing requirements
MIN
NOM
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
1
μs
td(C)
Delay time, conversion time
0.55
μs
Delay time, total sample/hold and conversion time
1.55
μs
0
ns
td(SHC)(1)
td(PU-ADV)
(1)
0.05
Delay time, ADC stable after exiting power-down mode
1 This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors.
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ...
0.
.. 100
0 ...
0.
.. 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ...
0.
.. 010
0 ...
0.
.. 001
Differential Linearity
Error (–1/2 LSB)
1 LSB
0 ...
0.
.. 000
0
1
2
3
4
Analog Input Value (LSB)
5
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 23. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 24 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 24. Integral Nonlinearity (INL) Error
58
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 25 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 25. Absolute Accuracy (Total) Error
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°-7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 11
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
60
PARAMETER
°C/W
RΘJA
98
RΘJB
43
RΘJC
22
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
List of Figures
TMS470PLF111 144-Pin PGE Package (TOP VIEW)
Functional Block Diagram
Figure 1. TMS470PLF111 Memory Map
Figure 2. TMS470 Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. TMS470 Platform Clock Domains Block Diagram
Figure 5. Crystal/Clock Connection
Figure 6. FMZPLL Clock Input Circuitry
Figure 7. Wake Up From Doze Mode
Figure 8. Wake Up From Sleep Mode
Figure 9. ECLK Timing Diagram
Figure 10. Power-Up Sequencing
Figure 11. PORRST Timing Requirements
Figure 12. JTAG Scan Timings
Figure 13. CMOS-Level Outputs
Figure 14. CMOS-Level Inputs
Figure 15. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 16. SPI Master Mode Chip Select timing (CLOCK PHASE = 1; CLOCK POLARITY = 0)
Figure 17. SPI Master Mode Chip Select timing (CLOCK PHASE = 1; CLOCK POLARITY = 1)
Figure 18. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 19. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 20. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 21. I2C Timings
Figure 22. MibADC Input Equivalent Circuit
Figure 23. Differential Nonlinearity (DNL)
Figure 24. Integral Nonlinearity (INL) Error
Figure 25. Absolute Accuracy (Total) Error
Mechanical Data
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TMS470PLF111
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS113 – OCTOBER 2006
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
62
Device Characteristics
Memory Frame Assignment
Peripheral Memory
Peripheral Select Map with Address Range
System Peripheral Registers
Interrupt Priority (VIM)
MibADC Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Number
GCM Clock Source Assignments
I2C Signals (SDA and SCL) Switching Characteristics
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