TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (64-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
Integrated Memory
– 256K-Byte Program Flash
– One Bank With 10 Contiguous Sectors
– 16K-Byte Static RAM (SRAM)
Operating Features
– Core Supply Voltage (VCC): 1.81 V - 2.06 V
– Core Supply Voltage (VCC): 1.70 V - 2.06 V
When Used At or Below 56MHz, 85C Ambient
Temp, and 115C Junction Temp
– I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
– 9 Programmable I/O Channels:
– 7 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 128-Instruction Capacity
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External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
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16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
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10 Dedicated General-Purpose I/O (GIO) Pins
and 37 Additional Peripheral I/Os
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Eight External Interrupts
Flexible Interrupt Handling
Compatible ROM Device (Planned)
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On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1† (JTAG) Test-Access Port
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100-Pin Plastic Low-Profile Quad Flatpack
Development System Support Tools Available
– Code Composer Studio™ Integrated Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
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Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
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Six Communication Interfaces:
– Serial Peripheral Interface (SPI)
– 255 Programmable Baud Rates
– Two Serial Communication Interfaces (SCIs)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Two Standard CAN Controllers (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Multi-Buffered Serial Peripheral Interface
(MibSPI)
– 64-Word Buffer
– Eight Chip Selects
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High-End Timer (HET)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
† The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
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1
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
TDO
TDI
PLLDIS
HET[8]
TCK
VSSIO
VCCIO
CLKOUT
CAN1STX
CAN1SRX
SCI1TX
SCI1CLK
SCI1RX
VCC
VSS
ADEVT
ADIN[7]
ADIN[6]
ADIN[5]
ADIN[15]
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
TMS470R1VF4B8 100-PIN PZ PACKAGE (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2
ADIN[11]
76
50
HET[18]
ADIN[14]
77
49
HET[19]
ADIN[10]
78
48
HET[20]
ADIN[13]
79
47
HET[21]
ADIN[9]
80
46
SPI2SCS
ADIN[12]
ADIN[8]
81
45
SPI2ENA
82
44
SPI2SOMI
ADREFHI
83
43
SPI2SIMO
ADREFLO
84
42
SPI2CLK
VCCAD
85
41
VCC
VSSAD
86
40
VSS
TMS
87
39
CAN2SRX
TMS2
88
38
VSS
89
37
CAN2STX
VCC
33
SCI2TX
FLTP2
94
32
SCI2RX
FLTP1
95
31
GIOA[3]/INT[3]
VCCP
96
30
GIOA[2]/INT[2]
MIBSPICS[2]
97
29
GIOA[1]/INT[1]/ECLK
MIBSPICS[3]
98
28
GIOA[0/INT[0]]
MIBSPICS[4]
99
27
TEST
MIBSPICS[5]
100
26
TRST
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GIOA[4]/INT[4]
GIOA[5]/INT[5]
GIOA[6]/INT[6]
PORRST
VCC
VSS
MIBSPICS[7]
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MIBSPICS[6]
9
HET[13]
8
HET[12]
7
GIOD[0]
6
GIOD[1]
5
GIOD[2]
4
VCCIO
3
VSSIO
2
RST
1
VCC
93
OSCIN
HET[30]
VCC
OSCOUT
34
VSS
92
MIBSPICLK
HET[31]
VSS
MIBSPISOMI
VSS
35
MIBSPISIMO
36
91
MIBSPIENA
90
MIBSPICS[0]
VCC
MIBSPICS[1]
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
description
The TMS470R1VF4B8† device is a member of the Texas Instruments TMS470R1x family of general-purpose16/
32-bit reduced instruction set computer (RISC) microcontrollers. The VF4B8 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high
instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF4B8 utilizes the bigendian format where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF4B8 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF4B8 device contains the following:
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ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements
256K-byte flash
16K-byte SRAM
Zero-pin phase-locked loop (ZPLL) clock module
Digital watchdog (DWD) timer
Real-time interrupt (RTI) module
Multi-buffered serial peripheral interface (MibSPI) module
Serial peripheral interface (SPI) module
Two serial communications interface (SCI) modules
Two standard CAN controllers (SCC)
10-bit multi-buffered analog-to-digital converter (MibADC), with 16 input channels
High-end timer (HET) controlling 9 I/Os
External Clock Prescale (ECP)
Up to 47 I/O pins
The functions performed by the 470+ system module (SYS) include: address decoding; memory protection;
memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal
interrupt sources; device clock control; and parallel signature analysis (PSA). The enhanced real-time interrupt
(RTI) module on the VF4B8 has the option to be driven by the oscillator clock. The digital watchdog (DWD) is
a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires.
This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt
priority, and a device memory map. For a more detailed functional description of the SYS module, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
The VF4B8 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 64 MHhz. For more detailed
information on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
† Throughout the remainder of this document, the TMS470R1VF4B8 device shall be referred to by either the full device name or VF4B8.
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3
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
description (continued)
The VF4B8 device has six communication interfaces: a MibSPI, an SPI, two SCIs, and two SCCs. The MibSPI
is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length to be
shifted into and out of the device at a programmed bit-transfer rate. The SPI provides a convenient method of
serial interaction for high-speed communications between similar shift-register type devices.The SCI is a fullduplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals
using the standard Non-Return-to-Zero (NRZ) format. The SCC uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit
per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. For more information on the MibSPI peripheral, see the TMS470R1x Multi-Buffered Serial Peripheral Interface (MibSPI) Reference Guide (literature number SPNU217). For more detailed functional information on the SPI, SCI, and SCC
peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199). The VF4B8 HET peripheral contains the XOR-share feature.
This feature allows two adjacent HET high-resolution channels to be sired together, making it possible to output
smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
The VF4B8 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK† to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF4B8 device modules. For
more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL)
Clock Module Reference Guide (literature number SPNU212).
The VF4B8 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
† ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal
reference.
4
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
device characteristics
The VF4B8 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all
the characteristics of the VF4B8 device except the SYSTEM and CPU, which are generic. The COMMENTS
column aids the user in software-programming and references device-specific information.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VF4B8
COMMENTS FOR VF4B8
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
Pipeline/Non-Pipeline
INTERNAL
MEMORY
Flash is pipeline-capable
The VF4B8 RAM is implemented in one 16K array selected by two
memory-select signals (see the Memory Selection Assignment table,
Table 2).
256K-Byte flash
16K-Byte SRAM
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority Table (Table 4). And for the 1K peripheral address ranges and
their peripheral selects, see the Peripherals, System Module, and Flash Base Addresses table (Table 3).
CLOCK
ZPLL
Zero-pin PLL has no external loop filter pins.
GENERAL-PURPOSE
I/Os
10 I/O
Port A has seven (7) external pins, and Port D has three (3) external pins.
ECP
YES
SCI
1 (2-pin)
1 (3-pin)
CAN
(HECC and/or SCC)
2 SCC
SPI
(5-pin, 4-pin or 3-pin)
1 (5-pin)
MibSPI
1 (12-pin)
HET with
XOR Share
9 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 16-channel
64-word FIFO
Standard CAN controllers
Eight chip selects
Master mode only
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent
of whether or not the odd pin is available externally. If an odd pin is
available externally and shared, then the odd pin can only be used as
a general-purpose I/O. For more information on HR SHARE, see
theTMS470R1x High-End Timer (HET) Reference Guide (literature
number SPNU199).
Both the logic and registers for a full 16-channel MibADC are present.
1.81V − 2.06V
CORE VOLTAGE
1.70 − 2.06V
I/O VOLTAGE
3.0V − 3.6V
PINS
100
PACKAGES
PZ
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When operating at or below 56MHz, 85C ambient temperature, and
115C junction temperature.
• HOUSTON, TEXAS 77251-1443
5
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
functional block diagram
External Pins
OSCIN
VCCP
FLTP1
FLTP2
FLASH
(256K Bytes)
10 Sectors
RAM
(16K Bytes)
ZPLL
OSCOUT
Crystal
External Pins
PLLDIS
ADIN[15:0]
CPU Address/Data Bus
MibADC
with
64-Word
FIFO
TRST
TCK
ADREFHI
ADREFLO
VCCAD
TMS470R1x
CPU
VSSAD
TDI
HET with
XOR Share
(128-Word)
TMS
TMS470R1x SYSTEM MODULE
TMS2
RST
Digital
Watchdog
(DWD)
PORRST
Expansion Address/Data Bus
TDO
TEST
ADEVT
SCC1
HET [8,12,13,18:21]
HET [30:31]
CAN1STX
CAN1SRX
SCC2
CAN2STX
CAN2SRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
CLKOUT
SCI2
SCI2TX
SCI2RX
GIOD[0:2]
6
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MIBSPI
MIBSPISCS[0:7]
MIBSPIENA
MIBSPISIMO
MIBSPISOMI
MIBSPICLK
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
SPI2
• HOUSTON, TEXAS 77251-1443
GIO
GIOA[2:6]/INT[2:6]
GIOA[0]/INT[0]
ECP
GIOA[1]/INT[1]/
ECLK
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
Terminal Functions
TERMINAL
NAME
PIN
NO.
INPUT
OUTPUT
VOLTAGE†‡ CURRENT†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
HIGH-END TIMER (HET)
HET[8]
55
HET[12]
17
HET[13]
16
HET[18]
50
HET[19]
49
HET[20]
48
HET[21]
47
HET[30]
34
HET[31]
35
CAN1SRX
59
CAN1STX
60
CAN2SRX
39
CAN2STX
38
GIOA[0]/INT[0]
28
GIOA[1]/INT[1]/
ECLK
29
GIOA[2]/INT[2]
30
GIOA[3]/INT[3]
31
GIOA[4]/INT[4]
25
GIOA[5]/INT[5]
24
Timer input capture or output compare. These pins can be programmed
as general-purpose input/output (GIO) pins.
HET[8,12,13,18,19,20,21] are high-resolution pins, and HET[30:31] are
standard-resolution pins.
3.3-V
2mA
IPD (20 μA)
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent
of whether or not the odd pin is available externally. If an odd pin is
available externally and shared, then the odd pin can only be used as
a general-purpose I/O. For more information on HR SHARE, see the
TMS470R1x High-End Timer (HET) Reference Guide (literature
number SPNU199).
STANDARD CAN CONTROLLER 1 (SCC1)
3.3-V
2mA
SCC1 receive pin or GIO pin
IPU (20 μA)
SCC1 transmit pin or GIO pin
STANDARD CAN CONTROLLER 2 (SCC2)
3.3-V
2mA
SCC1 receive pin or GIO pin
IPU (20 μA)
SCC1 transmit pin or GIO pin
GENERAL-PURPOSE I/O (GIO)
GIOA[6]/INT[6]
23
GIOD[0]
15
GIOD[1]
14
GIOD[2]
13
4mA
IPD (20 μA)
3.3-V
2mA
3.3-V
2mA
General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin.
GIOA[7:0]/INT[7:0] are interrupt-capable pins. If pins GIOA[6:2] are
not externally pulled up or down, they need to be driven as output
LOW for reduced power consumption in low power mode.
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out
function of the external clock prescale (ECP) module.
General-purpose input/output pins.If pins GIOD[2:0] are not
externally pulled up or down, they need to be driven as output
LOW for reduced power consumption in low power mode.
† PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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7
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
INPUT
OUTPUT
VOLTAGE†‡
CURRENT
†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
ADEVT
66
ADIN[0]
75
ADIN[1]
74
ADIN[2]
73
ADIN[3]
72
ADIN[4]
71
ADIN[5]
69
ADIN[6]
68
ADIN[7]
67
ADIN[8]
82
ADIN[9]
80
ADIN[10]
78
ADIN[11]
76
ADIN[12]
81
ADIN[13]
79
ADIN[14]
77
ADIN[15]
70
2mA
IPD (20 μA)
3.3-V
MibADC event input. Can be programmed as a GIO pin.
MibADC analog input pins
ADREFHI
83
3.3-V REF
MibADC module high-voltage reference input
ADREFLO
84
GND REF
MibADC module low-voltage reference input
VCCAD
85
3.3-V PWR
MibADC analog supply voltage
VSSAD
86
GND
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK
42
SPI2ENA
45
SPI2SCS
46
4mA
SPI2 clock. SPI1CLK can be programmed as a GIO pin.
SPI2 chip enable. Can be programmed as a GIO pin.
2mA
SPI2 slave chip select. Can be programmed as a GIO pin.
IPD (20 μA)
3.3-V
SPI2SIMO
43
4mA
SPI2 data stream. Slave in/master out. Can be programmed as a GIO
pin.
SPI2SOMI
44
4mA
SPI2data stream. Slave out/master in. Can be programmed as a GIO
pin.
MIBSPICLK
5
MIBSPISIMO
3
MIBSPISOMI
4
MIBSPIENA
1
MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE (MIBSPI)
MibSPI clock. SPI1CLK can be programmed as a GIO pin.
3.3-V
4mA
IPD (20 μA)
2mA
MibSPI data stream. Slave in/master out. Can be programmed as a GIO
pin.
MibSPI data stream. Slave out/master in. Can be programmed as a GIO
pin.
MibSPI chip enable. Can be programmed as a GIO pin.
† PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
8
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
MIBSPISCS[0]
2
MIBSPISCS[1]
91
MIBSPISCS[2]
97
MIBSPISCS[3]
98
MIBSPISCS[4]
99
MIBSPISCS[5]
100
MIBSPISCS[6]
18
MIBSPISCS[7]
19
OSCIN
8
OSCOUT
7
INPUT
VOLTAGE†‡
OUTPUT
CURRENT
†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE (MIBSPI) (CONTINUED)
3.3-V
MibSPI slave chip select. Can be programmed as a GIO pin. If pins
MIBSPISCS[4:0] are not externally pulled up or down, they need
to be driven as output LOW for reduced power consumption in
low power mode.
2mA
MibSPI slave chip select. If pins MIBSPISCS[7:5] are not externally
pulled up or down, they need to be driven as output LOW for
reduced power consumption in low power mode.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
PLLDIS
51
SCI1CLK
61
SCI1RX
63
SCI1TX
62
SCI2RX
32
SCI2TX
33
1.8-V
Crystal connection pin or external clock input
1.8-V O
External crystal connection pin
IPD (100 μA)
3.3-V
Enable/disable the ZPLL. The ZPLL can be bypassed and the
oscillator becomes the system clock. If not in bypass mode, TI
recommends that this pin be connected to ground or pulled down to
ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
IPD (20 μA)
3.3-V
2mA
IPU (20 μA)
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
3.3-V
2mA
IPU (20 μA)
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
CLKOUT
58
3.3-V
PORRST
22
3.3-V
8mA
IPD (20 μA)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the
output of SYSCLK, ICLK, or MCLK.
IPD (20 μA)
Input master chip power-up reset. External VCC monitor circuitry must
assert a power-on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an
external system reset can assert a device reset.
RST
10
3.3-V
4mA
IPU (100 μA)
On this pin, the output buffer is implemented as an open drain (drives
low only).
To ensure an external reset is not arbitrarily generated, TI
recommends that an external pullup resistor be connected to this pin.
† PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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9
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
INPUT
OUTPUT
VOLTAGE†‡
CURRENT†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
TEST/DEBUG (T/D)
TCK
54
3.3-V
IPD (20 μA)
Test clock. TCK controls the test hardware (JTAG).
IPU (20 μA)
Test data in. TDI inputs serial data to the test instruction register, test
data register, and programmable test address (JTAG).
IPD (20 μA)
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test
address (JTAG).
TDI
52
TDO
53
TEST
27
IPD (100 μA)
Test enable. Reserved for internal use only. TI recommends that this
pin be connected to ground or pulled down to ground by an external
resistor.
TMS
87
IPU (100 μA)
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG).
TMS2
88
IPU (100 μA)
Serial input for controlling the second TAP. TI recommends that this
pin be connected to VCCIO or pulled up to VCCIO by an external resistor.
TRST
26
IPD (100 μA)
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that this pin be pulled down to
ground by an external resistor.
8mA
3.3-V
4mA
FLASH
FLTP1
95
NC
Flash test pad 1. For proper operation, this pin must not be
connected [no connect (NC)].
FLTP2
94
NC
Flash test pad 2. For proper operation, this pin must not be
connected [no connect (NC)].
VCCP
96
3.3-V PWR
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
9
21
37
VCC
41
1.8-V
PWR
Core logic supply voltage
65
90
93
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
12
57
3.3-V
PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
6
20
36
VSS
40
GND
Core supply ground reference
64
89
92
SUPPLY GROUND DIGITAL I/O
VSSIO
11
56
GND
Digital I/O supply ground reference
† PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
VF4B8 DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF4xB device.
Memory (4G Bytes)
0xFFFF_FFFF
SYSTEM with PSA, CIM, RTI, DEC,
DWD, and MMC
0xFFFF_FFFF
Reserved
0xFFFF_FC00
System Module Control Registers
(512K Bytes)
Reserved
0xFFF8_0000
0xFFF7_FFFF
Peripheral Control Registers
(512K Bytes)
HET
Reserved
Reserved
Flash Control Registers
SCI2
Reserved
SCI1
MPU Control Registers
MibADC
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
0xFFFF_FD00
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
GIO/ECP
Reserved
SCC1/SCC2
0xFFE0_0000
0xFFF7_F400
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E000
SCC1/SCC2 RAM
0xFFF7_DC00
Reserved
0x7FFF_FFFF
0xFFF7_D800
MibSPI
0xFFF7_D600
RAM
(16K Bytes)
SPI2
0xFFF7_D400
Reserved
0xFFF7_D000
Program
and
Data Area
Reserved
0xFFF7_C000
Reserved
FLASH
(256K Bytes)
10 Sectors
0xFFF0_0000
Reserved
FIQ
IRQ
HETRAM
(1.5K Bytes)
0x0000_0024
0x0000_0023
0x0000_0000
Reserved
Data Abort
Exception, Interrupt, and
Reset Vectors
Prefetch Abort
Software Interrupt
Undefined Instruction
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
Reset
0x0000_0000
NOTES: A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. TMS470R1VF4B8 Memory Map
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11
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. The decoded block size for the flash memory on this device is 0x00200000 For more
information on how to control and configure these memory select registers, see the bus structure and memory
sections of the TMS470R1x System Module Reference Guide (literature number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. TMS470R1VF4B8 Memory Selection Assignment
MEMORY
SIZE
STATIC MEM
CTL REGISTER
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH
1 (fine)
FLASH
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
1.5K
NO
MFBAHR4 and MFBALR4
SMCR1
1 (coarse)
MibSPI RAM
0.5K
NO
MCBAHR1 and MCBALR1
SMCR4
256K
16K†
MPU
MEMORY BASE ADDRESS REGISTER
NO
MFBAHR0 and MFBALR0
NO
MFBAHR1 and MFBALR1
YES
MFBAHR2 and MFBALR2
YES
MFBAHR3 and MFBALR3
† The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the
memory-base address register.
RAM
The VF4B8 device contains 16K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF4B8 RAM is implemented in one 16K array selected
by two memory-select signals. This VF4B8 configuration imposes an additional constraint on the memory map
for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples
of the size of the physical RAM (i.e., 16K for the VF4B8 device). The VF4B8 RAM is addressed through memory
selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
F05 flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections below.
flash protection keys
The VF4B8 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the VF4B8 are located in the
last 4 words of the first 16K sector. For more detailed information on the flash protection keys and the FMPKEY
control register, see the Optional Quadruple Protection Keys and Programming the Protection Keys portions
of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
12
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
FLASH read
The VF4B8 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
Note: The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 64 MHz, versus a system
clock frequency of 24 MHz in normal mode. Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
Note: After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a "0"). In other words, the
VF4B8 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will override pipeline mode.
flash program and erase
The VF4B8 device flash contains one 256K-byte memory array (or bank), and consists of ten sectors. These
ten sectors are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
16K Bytes
0x0000_0000
0x0000_3FFF
1
16K Bytes
0x0000_4000
0x0000_7FFF
2
32K Bytes
0x0000_8000
0x0000_FFFF
3
32K Bytes
0x0001_0000
0x0001_7FFF
4
32K Bytes
0x0001_8000
0x0001_FFFF
5
32K Bytes
0x0002_0000
0x0002_7FFF
6
32K Bytes
0x0002_8000
0x0002_FFFF
7
32K Bytes
0x0003_0000
0x0003_7FFF
8
16K Bytes
0x0003_8000
0x0003_BFFF
9
16K Bytes
0x0003_C000
0x0003_FFFF
MEMORY ARRAY
(OR BANK)
BANK0
(256K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
Note: The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution cannot occur from any sector within a bank that is being programmed or erased.
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
HET RAM
The VF4B8 device contains HET RAM. The HET RAM has a 128-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
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13
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
peripheral selects and base addresses
The VF4B8 device uses ten of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 3.
Table 3. VF4B8 Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
14
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0xFFFF_FD00
0xFFFF_FFFF
N/A
RESERVED
0xFFF8_0000
0xFFFF_FCFF
N/A
RESERVED
0xFFF7_FE00
0xFFF7_FFFF
RESERVED
0xFFF7_FD00
0xFFF7_FDFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
RESERVED
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F600
0xFFF7_F7FF
SCI2
0XFFF7_F500
0XFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MIBADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_ED00
0xFFF7_EEFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
RESERVED
0xFFF7_EA00
0xFFF7_EBFF
RESERVED
0xFFF7_E800
0xFFF7_E9FF
RESERVED
0xFFF7_E600
0xFFF7_E7FF
RESERVED
0xFFF7_E400
0xFFF7_E5FF
RESERVED
0xFFF7_E300
0xFFF7_E3FF
SCC2
0xFFF7_E200
0xFFF7_E2FF
RESERVED
0xFFF7_E100
0xFFF7_E1FF
SCC1
0xFFF7_E000
0xFFF7_E0FF
RESERVED
0xFFF7_DF00
0xFFF7_DFFF
SCC2 RAM
0xFFF7_DE00
0xFFF7_DEFF
RESERVED
0xFFF7_DD00
0xFFF7_DDFF
SCC1 RAM
0xFFF7_DC00
0xFFF7_DCFF
RESERVED
0xFFF7_D800
0xFFF7_DBFF
RESERVED
0xFFF7_D700
0xFFF7_D7FF
MIBSPI
0xFFF7_D600
0xFFF7_D6FF
RESERVED
0xFFF7_D500
0xFFF7_D5FF
0xFFF7_D4FF
PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
PS[5]
PS[6]
PS[7]
PS[8]
PS[9]
PS[10]
SPI2
0xFFF7_D400
RESERVED
0xFFF7_D000
0xFFF7_D3FF
PS[11]
RESERVED
0xFFF7_CC00
0xFFF7_CFFF
PS[12]
RESERVED
0xFFF7_C800
0xFFF7_CBFF
PS[13]
RESERVED
0xFFF7_C400
0xFFF7_C7FF
PS[14]
RESERVED
0xFFF7_C000
0xFFF7_C3FF
PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
FLASH CONTROL REGISTERS
0xFFE8_8000
0xFFE8_807F
N/A
MPU CONTROL REGISTERS
0xFFE8_4000
0xFFE8_4023
N/A
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
interrupt priority (CIM)
The interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device modules
(i.e, MibSPI, SPI2, SCI1, SCI2, SCC1, SCC2, etc.)
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
z
Fast interrupt request (FIQ)
z
Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order
in the CIM (0 [highest] and 31 [lowest] priority). For channel priorities, and their associated modules, see Table 4.
Table 4. Interrupt Priority (CIM)
MODULES
INTERRUPT SOURCES
Reserved
DEFAULT CIM INTERRUPT
LEVEL/CHANNEL
0
RTI
COMP2 interrupt
1
RTI
COMP1 interrupt
2
RTI
TAP interrupt
3
SPI2
SPI2 end-transfer/overrun
4
GIO
GIO interrupt A
5
HET interrupt 1
7
Reserved
HET
MibSPI
SCI1/SCI2
SCI1
6
MibSPI interrupt A
8
SCI1 or SCI2 error interrupt
9
SCI1 receive interrupt
10
Reserved
11
Reserved
12
SCC2
SCC2 interrupt A
13
SCC1
SCC1 interrupt A
14
MibSPI
MibSPI interrupt B
15
MibADC
MibADC end event conversion
16
SCI2 receive interrupt
17
SCI2
Reserved
18
Reserved
SCI1
19
SCI1 transmit interrupt
20
SW interrupt (SSI)
21
HET interrupt 2
23
SCC2
SCC2 interrupt B
24
SCC1
SCC1 interrupt B
25
SCI2
SCI2 transmit interrupt
26
MibADC end Group 1 conversion
27
GIO interrupt B
29
MibADC end Group 2 conversion
30
System
Reserved
HET
MibADC
22
Reserved
GIO
MibADC
28
Reserved
31
For more detailed functional information on the CIM, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
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15
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF4B8 MibADC module can function in two modes: compatibility mode, where its programmer’s model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
z
Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
z
The trigger source and polarity can be selected individually for both group 1 and the event group from the
options identified in Table 5.
Table 5. MibADC Event Hookup Configuration
EVENT #
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
HET19
EVENT4
11
Reserved
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
16
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MibSPI
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (one to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The MibSPI
is normally used for communication between the microcontroller and external peripherals or another microcontroller. Typical applications include interface to external I/O or peripheral expansion via devices such as shift
registers, display drivers, and analog-to-digital converters.
Slave mode is not supported by the MibSPI on this device.
Table 6 shows the trigger sources for MibSPI.
Table 6. MibSPI Event Hookup Configuration
EVENT #
SOURCE SELECT BITS FOR
TRIGGER SOURCES (TRGSRC[3:0])
SIGNAL PIN NAME
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[2]
EVENT2
0011
GIOA[3]
EVENT3
0100
GIOA[4]
EVENT4
0101
HET[20]
EVENT5
0110
HET[21]
EVENT6
0111
HET[22]
EVENT7
1000
HET[23]
EVENT8
1001
HET[25]
EVENT9
1010
HET[26]
EVENT10
1011
HET[27]
EVENT11
1100
ADEVT
EVENT12
1101
N/C
EVENT13
1110
N/C
EVENT14
1111
Internal Tick Counter
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17
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
z
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
z
Optimizing C compiler
–
–
–
–
–
–
–
z
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
TMS470R1x CPU Simulator
–
–
–
z
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
Assembly language tools (assembler and linker)
–
–
–
–
z
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kit
–
Allows high-speed JTAG communication to the TMS470R1x emulator or target board
For more information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
18
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documentation includes:
z
z
Users Guides
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
–
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
–
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
–
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
–
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
–
TMS470R1x System Module Reference Guide (literature number SPNU189)
–
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
–
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
–
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
–
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
–
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
–
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature number SPNU206)
–
TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide
(literature number SPNU212)
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
–
TMS470R1x Multi-Buffered Serial Peripheral Interface (MibSPI) Reference Guide (literature number
SPNU217)
Application Reports:
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
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19
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 44 8 PZ A
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
4B = ’4B Devices Containing the Following Modules:
– ZPLL Clock
– 16K-Byte Static RAM
– 1.5K-Byte HET RAM (128 Instructions)
– Digital Watchdog (DWD)
– 10-Bit, 9-Input Multi-buffered Analog-to-Digital
Converter (MibADC)
– Serial Peripheral Interface (SPI) Module
– Multi-Buffered Serial Peripheral Interface (MibSPI) Module
– Two Serial Communications Interface (SCI) Modules
– Two standard Controller Area Networks (CAN) [SCCs]
– High-End Timer (HET)
– External Clock Prescaler (ECP)
8 = 0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
Package:
A =
T =
Q =
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
PZ = 100-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure 2. TMS470R1x Family Nomenclature
20
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 7). The VF4B8 device identification code
register value is 0x1A2F.
Table 7. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
6
5
4
3
2
1
BIT 0
Reserved
FFFF_FFF0
BIT 15
LEGEND:
For bits 3–15:
For bits 0–2:
14
13
12
11
10
9
8
7
VERSION
TF
R/F
PART NUMBER
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
R = Read only, -K = Value constant after RESET
R = Read only, -1 = Value after RESET
Bits 31:16
Reserved. Reads are undefined and writes have no effect.
Bits 15:12
VERSION. Silicon version (revision) bits
These bits identify the silicon version of the device.
Bit 11
TF. Technology Family (TF) bit
This bit distinguishes the technology family core power supply:
0 = 3.3 V for F10/C10 devices
1 = 1.8 V for F05/C05 devices
Bit 10
R/F. ROM/flash bit
This bit distinguishes between ROM and flash devices:
0 = Flash device
1 = ROM device
Bits 9:3
PART NUMBER. Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF4B8 device is: 1000101.
Bits 2:0
"1" Mandatory High. Bits 2,1, and 0 are tied high by default.
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
device part numbers
Table 8 lists all the available TMS470R1VF4B8 devices.
Table 8. Device Part Number
DEVICE PART
NUMBER
PROGRAM MEMORY
PACKAGE TYPE
TEMPERATURE RANGES
FLASH
EEPROM
100-PIN
LQFP
−40°C TO 85°C
TMS470R1VF4B8PZA
X
X
X
TMS470R1VF4B8PZT
X
X
TMS470R1VF4B8PZQ
X
X
22
ROM
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−40°C TO 105°C
−40°C TO 125°C
X
X
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, A version
(unless otherwise noted)†
Supply voltage ranges: VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (flash pump) (see Note 1) . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input voltage range: All input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:15], PORRST, TRST, TEST and TCK . . . . . . . . . . . . . . . ±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 125°C
Operating junction temperature range, TJ A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 115°C
T version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 130°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to their associated grounds.
device recommended operating conditions‡
MIN
VCC
ZPLLVCC
VCCIO
Digital logic and flash supply voltage
(Core)
ZPLL supply voltage
When operating at or below 56MHz, 85C
ambient temp, and 115C juntion temp
Digital logic supply voltage (I/O)
‡
VCCAD
ADC supply voltage
VCCP
Flash pump supply voltage
VSS
Digital logic supply ground
VSSAD
MibADC supply ground
TA
TJ
When operating at or below 56MHz, 85C
ambient temp, and 115C juntion temp
Operating free-air temperature
NOM
MAX
UNIT
1.81
2.06
V
1.70
2.06
V
1.81
2.06
V
1.70
2.06
V
3
3.3
3.6
V
3
3.3
3.6
V
3
3.3
3.6
V
0
V
− 0.1
0.1
V
A version
− 40
85
°C
T version
− 40
105
°C
Q version
− 40
125
°C
− 40
150
°C
Operating junction temperature
‡ All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
electrical characteristics over recommended operating free-air temperature range, A version
(unless otherwise noted)†
PARAMETER
TEST CONDITIONS
Vhys
Input hysteresis
VIL
Low-level input voltage
All inputs‡
VIH
High-level input voltage
All inputs
VOL
Low-level output voltage§
VOH
High-level output voltage§
IIC
Input clamp current (I/O pins)¶
IOL
IOH
Input current (I/O pins)
Low-level output
current
High-level output
current
TYP
MAX
− 0.3
2
0.8
V
VCCIO + 0.3
V
0.2 VCCIO
IOL = 50 μA
IOH = IOH MIN
IOH = 50 μA
0.2
0.8 VCCIO
VI < VSSIO − 0.3 or VI > VCCIO + 0.3
−2
2
−1
1
VI = VCCIO
IIL Pullup (20 μA)
VI = VSS
IIH Pulldown (100 μA) VI = VCCIO
5
40
–40
–5
25
100
IIL Pullup (100 μA)
VI = VSS
–200
–100
IIH Pullup
VI = VCCIO
−1
1
All other pins
No pullup or pulldown
−1
1
CLKOUT, TDO
VOL = VOL MAX
8
RST, SPInCLK,
SPInSOMI,
SPInSIMO,
VOL = VOL MAX
MIBSPICLK,
MIBSPISIMO,
MIBSPISOMI, TMS2
4
All other output pins
VOL = VOL MAX
2
CLKOUT, TDO
VOH = VOH MIN
−8
SPInCLK,
SPInSOMI,
SPInSIMO,
VOH = VOH MIN
MIBSPICLK,
MIBSPISIMO,
MIBSPISOMI, TMS2
−4
VOH = VOH MIN
−2
All other output pins
V
V
VCCIO - 0.2
VI = VSS
IIH Pulldown (20 μA)
UNIT
V
IOL = IOL MAX
IIL Pulldown
II
MIN
0.15
mA
μA
mA
mA
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 31.
§ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
¶ Parameter does not apply to input-only or output-only pins.
# For flash banks/pumps in sleep mode.
||
I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
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SPNS094C – JUNE 2004 – REVISED AUGUST 2006
electrical characteristics over recommended operating free-air temperature range, A version (unless otherwise noted)† (continued)
PARAMETER
MAX
UNIT
SYSCLK = 60 MHz,
ICLK = 30 MHz, VCC = 2.06 V
TEST CONDITIONS
90
mA
SYSCLK = 48 MHz,
ICLK = 24 MHz, VCC = 2.06 V
75
mA
VCC digital supply current (standby mode)#
OSCIN = 6 MHz, VCC = 2.06 V
3.0
mA
VCC digital supply current (halt mode)#
VCC = 2.06 V
1.0
mA
VCCIO digital supply current (operating mode)
No DC load, VCCIO = 3.6 V||
10
mA
VCCIO digital supply current (standby mode)
No DC load, VCCIO = 3.6 V||
300
μA
VCCIO digital supply current (halt mode)
No DC load, VCCIO = 3.6 V||
300
μA
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
15
mA
VCC digital supply current (operating mode)
ICC
ICCIO
ICCAD
ICCP
MIN
TYP
VCCAD supply current (standby mode)
All frequencies, VCCAD = 3.6 V
20
μA
VCCAD supply current (halt mode)
VCCAD = 3.6 V
20
μA
VCCP = 3.6 V read operation
SYSCLK = 60 MHz
55
mA
VCCP = 3.6 V read operation
SYSCLK = 48 MHz
45
mA
VCCP = 3.6 V program and erase
70
mA
20
μA
20
μA
VCCP pump supply current
VCCP = 3.6 V standby mode
operation#
VCCP = 3.6 V halt mode operation#
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 31.
§ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
¶ Parameter does not apply to input-only or output-only pins.
# For flash banks/pumps in sleep mode.
||
I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
Code Composer Studio, XDS510, XDS510WS, XDS510PP, and XDS560 are trademarks of Texas Instruments.
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin (see Note A)
= IOH MIN for the respective pin (see Note A)
IOH
VLOAD = 1.5 V
= 150-pF typical load-circuit capacitance (see Note B)
CL
NOTES: A. For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
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SPNS094C – JUNE 2004 – REVISED AUGUST 2006
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
H
High
X
L
V
Low
Valid
Z
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8 V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 4b.
OSCIN
C1
(see Note A)
OSCOUT
Crystal
OSCIN
C2
(see Note A)
External
Clock Signal
(toggling 0–1.8 V)
(a)
(b)
NOTE A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 4. Crystal/Clock Connection
Code Composer Studio is a trademark of Texas Instruments.
28
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SPNS094C – JUNE 2004 – REVISED AUGUST 2006
ZPLL and clock specifications
timing requirements for ZPLL circuits enabled or disabled
MIN
TYP
MAX
UNIT
20
MHz
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL
4
frequency†
53
kHz
† Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks‡§
PARAMETER
f(SYS)
System clock frequency#
f(CONFIG)
System clock frequency - flash config mode
f(ICLK)
f(ECLK)
Interface clock frequency
External clock output frequency for ECP Module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - flash config mode
tc(ICLK)
tc(ECLK)
Cycle time, interface clock
Cycle time, ECP module external clock output
TEST CONDITIONS¶
MAX
UNIT
Pipeline mode enabled
MIN
64
MHz
Pipeline mode disabled
24
MHz
24
MHz
Pipeline mode enabled
32
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
32
MHz
24
MHz
Pipeline mode disabled
Pipeline mode enabled
15.6
ns
Pipeline mode disabled
41.6
ns
41.6
ns
Pipeline mode enabled
31.25
ns
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
31.25
ns
Pipeline mode disabled
41.6
ns
‡ f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register
(GLBCTRL.3).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
§ f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
¶ Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
# Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
ZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 5 and Figure 6)†‡§
NO.
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK
1
tw(COL)
Pulse duration, CLKOUT low
MIN
¶
ICLK, X is even or 1#
ICLK, X is odd and not
0.5tc(ICLK) – tf
1#
tw(COH)
Pulse duration, CLKOUT high ICLK, X is even or
0.5tc(ICLK) – tr
ICLK, X is odd and not 1
3
4
tw(EOH)
Pulse duration, ECLK low
Pulse duration, ECLK high
ns
0.5tc(SYS) – tr
1#
#
tw(EOL)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK¶
2
MAX
0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tf
N is odd and X is even
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
0.5tc(ECLK) – tr
N is odd and X is even
N is odd and X is odd and not 1
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
ns
ns
0.5tc(ECLK) – 0.5tc(SYS) – tr
† X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
‡ N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
¶ Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 5. CLKOUT Timing Diagram
4
ECLK
3
Figure 6. ECLK Timing Diagram
30
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
RST and PORRST timings
timing requirements for PORRST (see Figure 7)
MIN
NO.
MAX
UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and
become active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and
become active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
3
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
0.6
1.5
V
V
1.1
2.75
V
V
0.2 VCCIO
V
0.5
V
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
μs
8
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
VCCP/VCCIO
VCCIOPORH
VCCIOPORH
VCCIO
8
VCC
VCC
VCCPORH
6
VCCIOPORL
VCC
VCCP/VCCIO
PORRST
11
VCCPORH
7
6
10
7
VCCPORL
VCCPORL
VCCIOPORL
5
3
VIL(PORRST)
9
VIL
VIL
VIL
VIL(PORRST)
VIL
Figure 7. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST†
PARAMETER
MIN
UNIT
4112tc(OSC)
Valid time, RST active after PORRST inactive
tv(RST)
ns
8tc(SYS)
Valid time, RST active (all others)
tfsu
MAX
Flash start up time, from RST inactive to fetch of first instruction from flash
(flash pump stabilization time)
836tc(OSC)
ns
† Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.
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31
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
UNIT
1
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
TCK
1
1
TMS
TDI
2
3
TDO
4
5
32
MAX
tc(JTAG)
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ns
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 8)
MIN
PARAMETER
tr
tf
tr
tf
tr
tf
Rise time, CLKOUT, TDO
Fall time, CLKOUT, TDO
Rise time, SPI2CLK, SPI2SOMI, MIBSPICLK, MIBSPISIMO,
MIBSPISOMI, TMS2
Fall time, RST, SPI2CLK, SPI2SOMI, MIBSPICLK,
MIBSPISIMO, MIBSPISOMI, TMS2
Rise time, all other output pins
Fall time, all other output pins
0.5
2.5
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL= 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
ns
ns
ns
ns
ns
ns
tf
80%
Output
MAX UNIT
CL = 15 pF
20%
VCC
80%
20%
0
Figure 8. CMOS-Level Outputs
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33
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
input timings
timing requirements for input timings† (see Figure 9)
MIN
tpw
tc(ICLK) + 10
Input minimum pulse width
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
20%
VCC
80%
20%
Figure 9. CMOS-Level Inputs
34
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0
MAX
UNIT
ns
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
flash timings
timing requirements for program flash†
tprog(16-bit)
Half word (16-bit) programming time
MIN
TYP
MAX
UNIT
4
16
200
μs
2
8
s
time‡
tprog(Total)
256K-byte programming
terase(sector)
Sector erase time
twec
Write/erase cycles at TA = 125°C
tfp(RST)
2
1000
15
10000
s
cycles
Flash pump settling time from RST to SLEEP
167tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
167tc(SYS)
ns
tfp(STDBY)
Initial flash pump settling time from STANDBY to ACTIVE
84tc(SYS)
ns
† For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
‡ The 256K-byte programming time include overhead of state machine.
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35
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 10)
NO.
1
2#
3#
4
MAX
100
256tc(ICLK)
Cycle time, SPInCLK
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
6#
7#
MIN
tc(SPC)M
#
5#
¶
UNIT
ns
tc(SPC)M – 5 – tr/f
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
36
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 10. SPIn Master Mode External Timing (CLOCK PHASE = 0)
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37
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 11)
NO.
1
2#
3#
4#
5#
6#
7#
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
¶
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)
4
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
38
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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39
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 12)
NO
1
2||
3||
#
MIN
MAX
100
256tc(ICLK)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid (clock
polarity = 0)
12 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid (clock
polarity = 1)
12 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
4||
5||
6||
7||
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
40
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 12. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
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41
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 13)
NO
1
2||
3||
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid (clock
polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 1)
6
4||
5||
6||
7
#
||
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
42
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
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43
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MibSPI master mode timing parameters
MibSPI master mode external timing parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)†‡§ (see Figure 14)
MIN
NO.
1
2¶
3¶
tc(SPC)M
MAX
UNIT
2tc(ICLK)
256tc(ICLK)
ns
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – tr
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO valid
(clock polarity = 0)
6
td(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO valid
(clock polarity = 1)
6
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
0.5tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high (clock
polarity = 1)
0.5tc(SPC)M – 5 – tr
td(SOMI-SPCL)M
Delay time, SPISOMI after SPICLK low
(clock polarity = 0)
0.5ticlk – 10 – tf(max)
td(SOMI-SPCH)M
Delay time, SPISOMI after SPICLK high
(clock polarity = 1)
0.5ticlk – 10 – tr(max)
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after SPICLK low (clock
polarity = 0)
ticlk – tf(min)
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after SPICLK high (clock
polarity = 1)
ticlk – tr(min)
4¶
5
Cycle time, SPICLK ¶
¶
6¶
7¶
POST OFFICE BOX 1443
ns
ns
ns
ns
ns
† The MASTER bit (SPICTRL2.3) is set and the CLOCK PHASE bit (SPICTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICTRK2.1).
44
ns
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MibSPI master mode timing parameters (continued)
1
SPICLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPISOMI
Master In Data Must Be Valid
Figure 14. MibSPI Master Mode External Timing (CLOCK PHASE = 0)
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45
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MibSPI master mode timing parameters (continued)
MibSPI master mode external timing parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO =
output, and SPISOMI = input)†‡§ (see Figure 15)
MIN
MAX
UNIT
2tc(ICLK)
256tc(ICLK)
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
NO.
1
2¶
3¶
4
tc(SPC)M
Cycle time, SPICLK
tw(SPCH)M
¶
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPICLK high after SPISIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 6
tv(SIMO-SPCL)M
Valid time, SPICLK low after SPISIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 6
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
td(SOMI-SPCH)M
Delay time, SPISOMI after SPICLK high
(clock polarity = 0)
0.5ticlk – 10 – tr(max)
td(SOMI-SPCL)M
Delay time, SPISOMI after SPICLK low
(clock polarity = 1)
0.5ticlk – 10 – tf(max)
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
ticlk – tr(min)
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
ticlk – tf(min)
¶
5¶
6¶
7¶
POST OFFICE BOX 1443
ns
ns
ns
ns
ns
† The MASTER bit (SPICTRL2.3) is set and the CLOCK PHASE bit (SPICTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICTRL2.1).
46
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• HOUSTON, TEXAS 77251-1443
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MibSPI master mode timing parameters (continued)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
Data Valid
6
7
SPISOMI
Master In Data Must Be Valid
Figure 15. MibSPI Master Mode External Timing (CLOCK PHASE = 1)
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47
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode†‡§ (see Figure 16)
(BAUD + 1)
IS EVEN OR BAUD = 0
NO.
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 –1) tc(ICLK)
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) +0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
ns
3
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) –0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK
high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data
after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data
- tc(ICLK) + tf + 20
after SCInCLK low
10
10
ns
tc(SCC) – 10
tc(SCC) – 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
ns
† BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
1
3
2
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
48
ns
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode†‡ (see Figure 17)
MIN
NO.
§
MAX
UNIT
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
3
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
8tc(ICLK)
5
tv(TX)
Valid time, SCInTX data after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
ns
2tc(SCC)–10
0
ns
ns
2tc(ICLK) + 10
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
‡ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
§ When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK)
1
2
3
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
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49
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
standard CAN controller (SCC) mode timings
dynamic characteristics for the CANSTX and CANSRX pins
PARAMETER
MIN
td(CANSTX)
Delay time, transmit shift register to CANSTX pin†
td(CANSRX)
Delay time, CANSRX pin to receive shift register
† These values do not include rise/fall times of the output buffer.
50
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MAX
UNIT
15
ns
5
ns
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one High Resolution Clock Period (HRP). The HRP is defined by the 6-bit High Resolution
Prescale Factor (hr) which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the Low Resolution Clock Period (LRP), i.e., the HET loop
(the HET program must fit within the LRP). The LRP is defined by the 3-bit Loop-Resolution Prescale Factor
(lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
Note: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
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51
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . .00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions†
ADREFHI
A-to-D high -voltage reference source
ADREFLO
A-to-D low-voltage reference source
VAI
Analog input voltage
MAX
UNIT
VCCAD
V
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
−2
2
mA
‡
Analog input clamp current
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
IAIC
MIN
VSSAD
† For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
‡ Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions§¶
PARAMETER
TYP
MAX
UNIT
250
500
Ω
Conversion
10
pF
Sampling
30
pF
1
μA
5
mA
DESCRIPTION/CONDITIONS
Ri
Analog input resistance
See Figure 18
Ci
Analog input capacitance
See Figure 18
IAIL
Analog input leakage current
See Figure 18
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value. (See Figure 19)
EINL
ETOT
–1
3
3.6
V
±1.5
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error.
(See Figure 20)
±2
LSB
Total error/Absolute accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 21)
±2
LSB
§ VCCAD = ADREFHI
¶ 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
52
MIN
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC) (continued)
External
Rs
MibADC
Input Pin
Ri
Sample Switch
Parasitic
Capacitance
Vsrc
Sample
Capacitor
Rleak
Ci
Figure 18. MibADC Input Equivalent Circuit
multi-buffer ADC timing requirements
MIN
NOM
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
1
μs
td(C)
Delay time, conversion time
0.55
μs
td(SHC)†
Delay time, total sample/hold and conversion time
1.55
μs
0.05
† This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more
details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
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53
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ...
0.
.. 100
0 ...
0.
.. 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ...
0.
.. 010
0 ...
0.
.. 001
Differential Linearity
Error (–1/2 LSB)
1 LSB
0 ...
0.
.. 000
0
1
2
3
4
Analog Input Value (LSB)
5
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 19. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 20. Integral Nonlinearity (INL) Error
54
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 21. Absolute Accuracy (Total) Error
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
43
RΘJC
5
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55
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°-7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
56
PARAMETER
°C/W
RΘJA
48
RΘJC
5
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TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
List of Figures
TMS470R1VF4B8 100-Pin PZ Package (TOP VIEW)
Functional Block Diagram
Figure 1. TMS470R1VF4B8 Memory Map
Figure 2. TMS470R1x Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. Crystal/Clock Connection
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
Figure 7. PORRST Timing Diagram
Figure 8. CMOS-Level Outputs
Figure 9. CMOS-Level Inputs
Figure 10. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 12. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 14. MibSPI Master Mode External Timing (CLOCK PHASE = 0)
Figure 15. MibSPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 18. MibADC Input Equivalent Circuit
Figure 19. Differential Nonlinearity (DNL)
Figure 20. Integral Nonlinearity (INL) Error
Figure 21. Absolute Accuracy (Total) Error
Mechanical Data
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57
TMS470R1VF4B8
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS094C – JUNE 2004 – REVISED AUGUST 2006
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
58
Device Characteristics
TMS470R1VF4B8 Memory Selection Assignment
VF4B8 Peripherals, System Module, and Flash Base Addresses
Interrupt Priority (CIM)
MibADC Event Hookup Configuration
MibSPI Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Number
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16/32-BIT RISC FLASH MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
C
DATE
NOTES
8/06
Updates:
Throughout, maximum core supply voltage changed from 2.05V to 2.06V
Page 1, core supply voltage conditions under 56MHz and 85C ambient, 115C junction temperature added
Page 5, core supply voltage conditions under 56MHz and 85C ambient, 115C junction temperature added
Page 23, minimum supply voltage and input voltage ranges changed from -0.3V to -0.5V
Page 23, operating junction temperature range broken out into A, T, and Q versions
Page 23, core supply voltage conditions under 56MHz and 85C ambient, 115C junction temperature added
Page 24, RST removed from IOH listing
Page 36, timing #5 updated
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63
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