TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com • • • • • High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™) – 24-MHz System Clock (48-MHz Pipeline Mode) – Independent 16/32-Bit Instruction Set – Open Architecture With Third-Party Support – Built-In Debug Module – Big-Endian Format Utilized Integrated Memory – 64K-Byte Program Flash • One Bank With Five Contiguous Sectors • Internal State Machine for Programming and Erase – 4K-Byte Static RAM (SRAM) Operating Features – Core Supply Voltage (VCC): 1.71 V–2.05 V – I/O Supply Voltage (VCCIO): 3.0 V–3.6 V – Low-Power Modes: STANDBY and HALT – Industrial Temperature Ranges 470+ System Module – 32-Bit Address Space Decoding – Bus Supervision for Memory and Peripherals – Analog Watchdog (AWD) Timer – Real-Time Interrupt (RTI) – System Integrity and Failure Detection Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler – Multiply-by-4 or -8 Internal ZPLL Option – ZPLL Bypass Mode Six Communication Interfaces: – Two Serial Peripheral Interfaces (SPIs) • 255 Programmable Baud Rates – Two Serial Communication Interfaces (SCIs) • 224 Selectable Baud Rates • • • • • • • • (1) • Asynchronous/Isosynchronous Modes – Standard CAN Controller (SCC) – 16-Mailbox Capacity • Fully Compliant With CAN Protocol, Version 2.0B – Class II Serial Interface (C2SIa) • Two Selectable Data Rates • Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps High-End Timer (HET) – 13 Programmable I/O Channels: • 12 High-Resolution Pins • 1 Standard-Resolution Pin – High-Resolution Share Feature (XOR) – HET RAM (64-Instruction Capacity) 10-Bit Multi-Buffered ADC (MibADC) 8-Channel – 64-Word FIFO Buffer – Single- or Continuous-Conversion Modes – 1.55 µs Minimum Sample and Conversion Time – Calibration Mode and Self-Test Features Six External Interrupts Flexible Interrupt Handling 5 Dedicated General-Purpose I/O (GIO) Pins, 1 Input-Only GIO Pin, and 34 Additional Peripheral I/Os External Clock Prescale (ECP) Module – Programmable Low-Frequency External Clock (CLK) On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (1) (JTAG) Test-Access Port 80-Pin Plastic Low-Profile Quad Flatpack (PN Suffix) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2004, Texas Instruments Incorporated ADVANCE INFORMATION • • SPNS099 – NOVEMBER 2004 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 TDO PLLDIS 41 TCK 44 TDI VSSIO HET[8] 46 42 VCCIO 47 43 CLKOUT 48 45 CANSTX CANSRX SCI1CLK 49 SCI1TX 51 50 52 53 VCC VSS SCI1RX 56 54 ADEVT 57 55 ADIN[4] ADIN[6] 58 ADIN[0] ADIN[2] 59 C2SIaTX VSS 73 28 C2SIaLPN VCC 74 27 HET[24] FLTP2 75 26 SCI2TX VCCP 76 25 SCI2RX HET[2] 77 24 HET[4] 78 23 GIOA[1]/ECLK/INT1 GIOA[0]/INT0(A) HET[6] 79 22 TEST HET[7] 80 21 TRST VSSIO 5 20 29 GIOA[4]/INT4 72 19 C2SIaRX HET[0] 18 30 17 71 GIOA[6]/INT6 GIOA[5]/INT5 VSS VSS GIOA[7]/INT7 31 16 70 PORRST TMS2 15 69 HET[12] SPI2CLK TMS 33 32 14 68 13 SPI2SIMO VSSAD HET[14] 34 12 67 VCCIO HET[16] SPI2SOMI VCCAD 10 11 35 RST 66 9 SPI2ENA ADREFLO 8 36 VCC 65 OSCIN HET[22] ADREFHI 7 37 OSCOUT 64 6 HET[20] ADIN[8] SPI1SOMI SPI1CLK VSS 38 4 63 3 HET[18] ADIN[12] SPI1SIMO AWD 39 2 40 62 1 61 ADIN[10] SPI1ENA ADIN[14] SPI1SCS ADVANCE INFORMATION A. 60 TMS470R1A64 80-PIN PN PACKAGE (TOP VIEW) VCC GIOA[0]/INT0 (pin 23) is an input-only GIO pin. DESCRIPTION The TMS470R1A64 (1) device is a member of the Texas Instruments TMS470R1x family of general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The A64 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining high code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from 0. The TMS470R1A64 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A64 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption. The A64 device contains the following: • ARM7TDMI 16/32-Bit RISC CPU • TMS470R1x system module (SYS) with 470+ enhancements • 64K-byte Flash • 4K-byte SRAM (1) 2 Throughout the remainder of this document, the TMS470R1A64 device will be referred to as either the full device name, TMS470R1A64, or asA64. www.ti.com SPNS099 – NOVEMBER 2004 Zero-pin phase-locked loop (ZPLL) clock module Analog watchdog (AWD) timer Real-time interrupt ( RTI) module Two serial peripheral interface (SPI) modules Two serial communication interface (SCI) modules Standard CAN controller (SCC) Class II serial interface (C2SIa) 10-bit multi-buffered analog-to-digital converter (MibADC), 8-input channels High-end timer (HET) controlling 13 I/Os External Clock Prescale (ECP) Up to 39 I/O pins and 1 input-only pin The functions performed by the 470+ system module (SYS) include: • Address decoding • Memory protection • Memory and peripherals bus supervision • Reset and abort exception management • Prioritization for all internal interrupt sources • Device clock control • Parallel signature analysis (PSA) This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189). The A64 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The Flash memory on the A64 device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to 24 MHz. In pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz. For more detailed information on the Flash, see the F05 Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). The A64 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIa allows the A64 to transmit and receive messages on a class II network following an SAE J1850 (2) standard. For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific TMS470R1x Peripheral Reference Guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed functional information on the C2SIa peripheral, see the TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218). The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). (2) SAE Standard J1850 Class B Data Communication Network Interface. 3 ADVANCE INFORMATION • • • • • • • • • • • TMS470R1A64 16/32-Bit RISC Flash Microcontroller TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 The A64 device has a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which are triggerable by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides the system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A64 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212). NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference. ADVANCE INFORMATION The A64 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202). 4 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Device Characteristics The TMS470R1A64 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all the characteristics of the TMS470R1A64 device except the SYSTEM and CPU, which are generic. Table 1. Device Characteristics CHARACTERISTICS DEVICE DESCRIPTION COMMENTS MEMORY For the number of memory selects on this device, see the "Memory Selection Assignment" table (Table 3). Flash is pipeline-capable. INTERNAL MEMORY 64K-Byte Flash 4K-Byte SRAM The A64 RAM is implemented in one 4K array selected by two memory-select signals (see the "Memory Selection Assignment" table, Table 3). PERIPHERALS For the device-specific interrupt priority configurations, see the "Interrupt Priority" table (Table 6). For the 1K peripheral address ranges and their peripheral selects, see the "A64 Peripherals, System Module, and Flash Base Addresses" table (Table 5). ZPLL GENERAL-PURPOSE I/Os 5 I/O 1 Input only ECP YES C2SIa 1 SCI 1 (3-pin) 1 (2-pin) CAN (HECC and/or SCC) 1 SCC SPI (5-pin, 4-pin or 3-pin) 1 (5-pin) 1 (4-pin) Zero-pin PLL has no external loop filter pins. Port A has 6 external pins - GIOA[2]/INT2 and GIOA[3]/INT3 are not available. SCI2 has no external clock pin, only transmit/receive pins (SCI2TX and SCI2RX) Standard CAN controller SPI2 has no chip select pin. The A64 device has both the logic and registers for a full 32-I/O HET implemented, even though not all 32 pins are available externally. HET with XOR Share 13 I/O HET RAM 64-Instruction Capacity MibADC 10-bit, 8-channel 64-word FIFO CORE VOLTAGE 1.71 - 2.05 V I/O VOLTAGE 3.0–3.6 V PINS 80 PACKAGE PN The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). 8-channel MibADC. Both the logic and registers for a full 16-channel MibADC are present. 5 ADVANCE INFORMATION CLOCK TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Functional Block Diagram External Pins FLTP2 OSCIN FLASH 64K Bytes (5 Sectors) RAM (4K Bytes) ZPLL PLLDIS ADIN[14, 12, 10, 8, 6, 4, 2, 0] CPU Address/Data Bus MibADC with 64-Word FIFO TRST TMS470R1x CPU TCK OSCOUT TDI ADVANCE INFORMATION TMS TMS470R1x 470+ SYSTEM MODULE TMS2 RST AWD TEST PORRST Expansion Address/Data Bus TDO CLKOUT HET with XOR Share (64-Word) SCC ADEVT ADREFHI ADREFLO VCCAD VSSAD HET[22, 24, 20, 18, 16, 14, 12, 8, 7, 6, 4, 2, 0] CANSTX CANSRX SCI1CLK SCI1 SCI1TX SCI1RX SCI2 SCI2TX SCI2RX C2SIaTX C2SIa C2SIaRX A. 6 GIOA[0]/INT[0] is an input-only GIO pin. SPI2 SPI1 SPI1SCS SPI1ENA SPI1SIMO SPI1SOMI SPI1CLK GIOA[7:4]/ INT[7:4] GIO GIOA[0]/ INT[0](A) ECP SPI2ENA SPI2SIMO SPI2SOMI SPI2CLK C2SIaLPN GIOA[1]/INT[1]/ ECLK Crystal VCCP External Pins TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Table 2. Terminal Functions TERMINAL NAME PIN NUMBER TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) DESCRIPTION HIGH-END TIMER (HET) HET[0] 72 HET[2] 77 HET[4] 78 HET[6] 79 HET[7] 80 HET[8] 45 HET[12] 15 HET[14] 14 HET[16] 13 HET[18] 39 HET[20] 38 HET[22] 37 HET[24] 27 CANSRX 49 3.3-V I/O CANSTX 50 3.3-V I/O IPU C2SIaLPN 28 3.3-V I/O IPD C2SIaRX 30 3.3-V I/O C2SIaTX 29 3.3-V I/O GIOA[0]/INT 0 23 3.3-V I GIOA[1]/INT 1/ECLK 24 GIOA[4]/ INT4 20 GIOA[5]/ INT5 19 GIOA[6]/ INT6 18 GIOA[7]/ INT7 17 The A64 device has both the logic and registers for a full 32-I/O HET implemented, even though not all 32 pins are available externally Timer input capture or output compare. The HET[31:0] applicable pins can be programmed as general-purpose input/output (GIO) pins. 3.3-V I/O IPD HET pins [22, 20, 18, 16, 14, 12, 8, 7, 6, 4, 2, and 0] are high-resolution pins for A64. HET[24] is a standard-resolution pin. STANDARD CAN CONTROLLER (SCC) SCC receive pin or GIO pin SCC transmit pin or GIO pin CLASS II SERIAL INTERFACE (C2SIA) C2SIa module loopback enable pin or GIO pin C2SIa module receive data input pin or GIO pin IPD C2SIa module transmit data output pin or GIO pin GENERAL-PURPOSE I/O (GIO) General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin. GIOA[7:0]/INT[7:0] are interrupt-capable pins. IPD 3.3-V I/O The GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out function of the external clock prescale (ECP) module. GIOA[2]/INT[2] and GIOA[3]/INT[3]] pins are not applicable on the A64 device. MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) ADEVT 56 ADIN[0] 60 MibADC analog input pins ADIN[2] 59 ADIN[4] 58 The A64 device has only 8 input channels but all S/W registers are capable. ADIN[15,13, 11, 9, 7, 5, 3, and 1] pins are not applicable to the A64 device. ADIN[6] 57 ADIN[8] 64 ADIN[10] 62 ADIN[12] 63 ADIN[14] 61 (1) (2) (3) 3.3-V I/O 3.3-V I MibADC event input. ADEVT can be programmed as a GIO pin. IPD I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.) 7 ADVANCE INFORMATION The high-resolution (HR) SHARE feature allows even-numbered HR pins to share the next higher odd-numbered HR pin structures. This HR sharing is independent of whether or not the odd-numbered pin is available externally. If an odd-numbered pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer Reference Guide (literature number SPNU199). TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Table 2. Terminal Functions (continued) TERMINAL NAME PIN NUMBER TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) DESCRIPTION ADREFHI 65 3.3-V REF I MibADC module high-voltage reference input ADREFLO 66 GND REF I MibADC module low-voltage reference input VCCAD 67 3.3-V PWR MibADC analog supply voltage VSSAD 68 GND MibADC analog ground reference SPI1CLK 5 SPI1 clock. SPI1CLK can be programmed as a GIO pin. SPI1ENA 1 SPI1 chip enable. SPI1ENA can be programmed as a GIO pin. SPI1SCS 2 SPI1SIMO 3 SPI1SOMI 4 SPI2CLK 33 SPI2ENA 36 SPI2SIMO 34 SPI2SOMI 35 OSCIN 8 1.8-V I Crystal connection pin or external clock input OSCOUT 7 1.8-V O External crystal connection pin PLLDIS 41 SERIAL PERIPHERAL INTERFACE 1 (SPI1) SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin. 3.3-V I/O IPD SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a GIO pin. ADVANCE INFORMATION SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a GIO pin. SERIAL PERIPHERAL INTERFACE 2 (SPI2) SPI2 clock. SPI2CLK can be programmed as a GIO pin. SPI2 chip enable. SPI2ENA can be programmed as a GIO pin. 3.3-V I/O IPD SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a GIO pin. SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a GIO pin. ZERO-PIN PHASE-LOCKED LOOP (ZPLL) 3.3-V I IPD Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the system clock. If not in bypass mode, TI recommends that PLLDIS be connected to ground or pulled down to ground by an external resistor. SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) SCI1CLK 51 3.3-V I/O IPD SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1RX 53 3.3-V I/O IPU SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1TX 52 3.3-V I/O IPU SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SERIAL COMMUNICATIONS INTERFACE 2 (SCI2) SCI2RX 25 3.3-V I/O IPU SCI2TX 26 3.3-V I/O IPU SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2 data transmit. SCI2TX can be programmed as a GIO pin. SYSTEM MODULE (SYS) CLKOUT PORRST 48 3.3-V I/O IPD Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of SYSCLK, ICLK, or MCLK. 16 3.3-V I IPD Input master chip power-up reset. External VCC monitor circuitry must assert a power-on reset. RST Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. 10 8 3.3-V I/O IPU On RST, the output buffer is implemented as an open drain (drives low only. To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to RST. TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Table 2. Terminal Functions (continued) TERMINAL NAME PIN NUMBER TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) DESCRIPTION WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. If the user is not using AWD, TI recommends that AWD be connected to ground or pulled down to ground by an external resistor. AWD 40 3.3-V I/O IPD For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide(literature number SPNU189) and the application note Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints (literature number SPNA005). 44 3.3-V I IPD Test clock. TCK controls the test hardware (JTAG) 42 3.3-V I IPU Test data in. TDI inputs serial data to the test instruction register, test data register, and programmable test address (JTAG). 43 3.3-V O IPD Test data out. TDO outputs serial data from the test instruction register, test data register, identification register, and programmable test address (JTAG). TEST 22 3.3-V I IPD Test enable. Reserved for internal use only. TI recommends that TEST be connected to ground or pulled down to ground by an external resistor. TMS 69 3.3-V I IPU Serial input for controlling the state of the CPU test access port (TAP) controller (JTAG) TMS2 70 3.3-V I IPU Serial input for controlling the second TAP. TI recommends that TMS2 be connected to VCCIO or pulled up to VCCIO by an external resistor. 3.3-V I IPD Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic. TI recommends that TRST be pulled down to ground by an external resistor. TDI TDO 21 TRST ADVANCE INFORMATION TEST/DEBUG (T/D) TCK FLASH FLTP2 VCCP 75 NC 76 3.3-V PWR Flash test pad 2. For proper operation,FLTP2 must not be connected (no connect [NC]). Flash external pump voltage (3.3 V) SUPPLY VOLTAGE CORE (1.8 V) 9 VCC 32 55 1.8-V PWR Core logic supply voltage 74 SUPPLY VOLTAGE DIGITAL I/O (3.3 V) VCCIO 12 47 3.3-V PWR Digital I/O supply voltage SUPPLY GROUND CORE 6 31 VSS 54 GND Core supply ground reference 71 73 SUPPLY GROUND DIGITAL I/O VSSIO 11 46 GND Digital I/O supply ground reference 9 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 A64 DEVICE-SPECIFIC INFORMATION memory Figure 1 shows the memory map of the A64 device. 0xFFFF_FFFF Memory (4G Bytes) SYSTEM 0xFFFF_FFFF 0xFFFF_FD00 System Module Control Registers (512K Bytes) Reserved 0xFFF8_0000 0xFFF7_FFFF HET Peripheral Control Registers (512K Bytes) 0xFFF0_0000 0xFFEF_FFFF 0xFFE8_C000 0xFFE8_BFFF 0xFFE8_8000 0xFFE8_7FFF ADVANCE INFORMATION 0xFFE8_4024 0xFFE8_4023 0xFFE8_4000 0xFFE8_3FFF SPI1 SCI2 Reserved SCI1 Flash Control Registers MibADC Reserved GIO/ECP MPU Control Registers Reserved SCC Reserved SCC RAM 0xFFE0_0000 Reserved SPI2 RAM (4K Bytes) Reserved C2SIa Reserved Program and Data Area FLASH (64K Bytes) 0xFFF8_0000 0xFFF7_FC00 0xFFF7_F800 0xFFF7_F500 0xFFF7_F400 0xFFF7_F000 0xFFF7_EC00 0xFFF7_E400 0xFFF7_E000 0xFFF7_DC00 0xFFF7_D800 0xFFF7_D400 0xFFF7_CC00 0xFFF7_C800 0xFFF0_0000 5 Sectors 0x0000_ 001F FIQ IRQ Reserved Data Abort Prefetch Abort 0x0000_0020 0x0000_001F 0x0000_0000 Software Interrupt Undefined Instruction Exception, Interrupt, and Reset Vectors Reset 0x0000_ 0018 0x0000_ 0014 0x0000_ 0010 0x0000_ 000C 0x0000_ 0008 0x0000_ 0004 0x0000_ 0000 A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000. B. The CPU registers are not part of the memory map. Figure 1. Memory Map 10 0x0000_ 001C TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 memory selects Memory selects allow the user to address memory arrays (i.e., Flash, RAM, and HET RAM) at user-defined addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx and MFBALRx) that, together, define the array's starting (base) address, block size, and protection. The base address of each memory select is configurable to any memory address boundary that is a multiple of the decoded block size. For more information on how to control and configure these memory select registers, see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number SPNU189). For the memory selection assignments and the memory selected, see Table 3. Table 3. Memory Selection Assignment MEMORY SELECTED (ALL INTERNAL) 0 (fine) FLASH 1 (fine) FLASH 2 (fine) RAM 3 (fine) RAM 4 (fine) HET RAM MEMORY SIZE 64K 4K (1) 1K MPU MEMORY BASE ADDRESS REGISTER NO MFBAHR0 and MFBALR0 NO MFBAHR1 and MFBALR1 YES MFBAHR2 and MFBALR2 YES MFBAHR3 and MFBALR3 MFBAHR4 and MFBALR4 STATIC MEM CTL REGISTER SMCR1 The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the memory-base address register. RAM The A64 device contains 4K bytes of internal static RAM configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. This A64 RAM is implemented in one 4K array selected by two memory-select signals. This A64 configuration imposes an additional constraint on the memory map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the size of the physical RAM (i.e., 4K for the A64 device). The A64 RAM is addressed through memory selects 2 and 3. The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an operating system while allowing access to the current task. For more detailed information on the MPU portion of the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference Guide (literature number SPNU189). F05 Flash The F05 Flash memory is a nonvolatile electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The F05 Flash has an external state machine for programming and erase functions. See the Flash read and Flash program and erase sections below. Flash protection keys The A64 devices provide Flash protection keys. These four 32-bit protection keys prevent program/erase/compaction operations from occurring until after the four protection keys have been matched by the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A64 are located in the last 4 words of the first 8K sector. For more detailed information on the Flash protection keys and the FMPKEY control register, see the protection keys portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). 11 ADVANCE INFORMATION (1) MEMORY SELECT TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Flash read The A64 Flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The Flash is addressed through memory selects 0 and 1. NOTE: The Flash external pump voltage (VCCP) is required for all operations (program, erase, and read). Flash pipeline mode When in pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz (versus a system clock in normal mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the Flash can be read with no wait states when memory addresses are contiguous (after the initial 1-or 2-wait-state reads). NOTE: ADVANCE INFORMATION After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other words, the A64 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the Flash configuration mode bit (GLBCTRL.4) will override pipeline mode. Flash program and erase The A64 device Flash has one 64K-byte bank that consists of five sectors. These five sectors are shown in Table 4. Table 4. Flash Sectors SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS 0 8K Bytes 0x0000_0000 0x0000_1FFF 1 8K Bytes 0x0000_2000 0x0000_3FFF 2 16K Bytes 0x0000_4000 0x0000_7FFF 3 16K Bytes 0x0000_8000 0x0000_BFFF 4 16K Bytes 0x0000_C000 0x0000_FFFF The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit word. NOTE: The Flash external pump voltage (VCCP) is required for all operations (program, erase, and read). For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). HET RAM The A64 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET RAM is addressed through memory select 4. XOR share The A64 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). 12 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 peripheral selects and base addresses The A64 device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the SYS module. Control registers for the peripherals, SYS module, and Flash begin at the base addresses shown in Table 5. Table 5. A64 Peripherals, System Module, and Flash Base Addresses ADDRESS RANGE BASE ADDRESS ENDING ADDRESS PERIPHERAL SELECTS N/A SYSTEM 0xFFFF_FD00 0xFFFF_FFFF RESERVED 0xFFF8_0000 0xFFFF_FCFF N/A HET 0xFFF7_FC00 0xFFF7_FFFF PS[0] PS[1] SPI1 0xFFF7_F800 0xFFF7_FBFF SCI2 0XFFF7_F500 0XFFF7_F7FF SCI1 0xFFF7_F400 0xFFF7_F4FF PS[2] ADC 0xFFF7_F000 0xFFF7_F3FF GIO/ECP 0xFFF7_EC00 0xFFF7_EFFF PS[3] PS[4] RESERVED 0xFFF7_E400 0xFFF7_EBFF PS[5] - PS[6] SCC 0xFFF7_E000 0xFFF7_E3FF PS[7] PS[8] SCC RAM 0xFFF7_DC00 0xFFF7_DFFF RESERVED 0XFFF7_D800 0XFFF7_DBFF PS[9] SPI2 0XFFF7_D400 0XFFF7_D7FF PS[10] RESERVED 0xFFF7_CC00 0xFFF7_D3FF PS[11] - PS[12] C2SIa 0xFFF7_C800 0xFFF7_CBFF PS[13] RESERVED 0xFFF7_C000 0xFFF7_C7FF PS[14] - PS[15] RESERVED 0xFFF0_0000 0xFFF7_BFFF N/A FLASH CONTROL REGISTERS 0xFFE8_8000 0xFFE8_BFFF N/A MPU CONTROL REGISTERS 0xFFE8_4000 0xFFE8_4023 N/A ADVANCE INFORMATION CONNECTING MODULE 13 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 interrupt priority The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.). Although the CIM can accept up to 32 interrupt request signals, the A64 device only uses 21 of those interrupt request signals. The request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can be programmed in the CIM to be of either type: • Fast interrupt request (FIQ) • Normal interrupt request (IRQ) The precedences of request channels decrease with ascending channel order in the CIM (0, highest, and 31, lowest, priority). For these channel priorities and the associated modules, see Table 6. Table 6. Interrupt Priority MODULES INTERRUPT SOURCES SPI1 end-transfer/overrun 0 RTI COMP2 interrupt 1 RTI COMP1 interrupt 2 ADVANCE INFORMATION RTI TAP interrupt 3 SPI2 SPI2 end-transfer/overrun 4 GIO Interrupt A 5 Reserved HET 6 Interrupt A Reserved SCI1/SCI2 7 8 SCI1/SCI2 error interrupt 9 SCI1 SCI1 receive interrupt 10 C2SIa C2SIa interrupt 11 Reserved 12 Reserved SCC 13 Interrupt A Reserved 14 15 MibADC End event conversion 16 SCI2 SCI2 receive interrupt 17 Reserved 18 Reserved SCI1 System 19 SCI1 transmit interrupt 20 SW interrupt (SSI) 21 Reserved HET 22 Interrupt B Reserved 23 24 SCC Interrupt B 25 SCI2 SCI2 transmit interrupt 26 End Group 1 conversion 27 MibADC Reserved GIO MibADC Reserved 14 INTERRUPT LEVEL/CHANNEL SPI1 28 Interrupt B 29 End Group 2 conversion 30 31 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 MibADC The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a 10-bit digital value. The A64 MibADC module can function in two modes: compatibility mode, where its programmer's model is compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion group (event, group1 [G1], and group2 [G2]). In buffered mode, the MibADC buffers can be serviced by interrupts. MibADC event trigger enhancements The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC. • Both group1 and the event group can be configured for event-triggered operation, providing up to two event-triggered groups. • The trigger source and polarity can be selected individually for both group1 and the event group from the three options identified in Table 7. EVENT # SOURCE SELECT BITS FOR G1 OR EVENT (G1SRC[1:0] or EVSRC[1:0]) SIGNAL PIN NAME EVENT1 00 ADEVT EVENT2 01 HET18 EVENT3 10 HET19 EVENT4 11 Reserved For group 1, these event-triggered selections are configured via the group1 source select bits (G1SRC[1:0]) in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are configured via the event group source select bits (EVSRC[1:0]) in the AD event source register (ADEVTSRC.[1:0]). For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). 15 ADVANCE INFORMATION Table 7. MibADC Event Hookup Configuration TMS470R1A64 16/32-Bit RISC Flash Microcontroller SPNS099 – NOVEMBER 2004 www.ti.com documentation support ADVANCE INFORMATION Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of documentation available include: data sheets with design specifications; complete user's guides; and errata sheets. Useful reference documentation includes: • Bulletin – TMS470 Microcontroller Family Product Bulletin (literature number SPNB086) • Data Sheets – TMS470R1A128 16/32Bit RISC Microcontroller (literature number SPNS098) – TMS470R1A64 16/32Bit RISC Microcontroller (literature number SPNS099) – TMS470R1A256 16/32Bit RISC Microcontroller (literature number SPNS100) • User's Guides – TMS470R1x System Module Reference Guide (literature number SPNU189) – TMS470R1x GeneralPurpose Input/Output (GIO) Reference Guide (literature number SPNU192) – TMS470R1x Serial Peripheral Interface (SPI) Reference Guide SPNU195 – TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196) – TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197) – TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199) – TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202) – TMS470R1x MultiBuffered AnalogtoDigital (MibADC) Reference Guide (literature number SPNU206) – TMS470R1x ZeroPin PhaseLocked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212) – TMS470R1x F05 Flash Reference Guide (literature number SPNU213) – TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214) – TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218) – TMS470 Peripherals Overview Reference Guide (literature number SPNU248) • Errata Sheet: – TMS470R1A64 TMS470 Microcontrollers Silicon Errata (literature number SPNZ134) 16 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 device numbering conventions Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family. TMS 470 R1 A 64 PN OPTIONS Blank = No options PREFIX TMS = Fully Qualified Device FAMILY 470 = TMS470 RISC − Embedded Microcontroller Family PACKAGE TYPE PN = 80-Pin Plastic Low−Profile Quad Flatpack (LQFP) REVISION CHANGE Blank = Original DEVICE TYPE A With 64K−Bytes Flash memory: 1.8V Core, 3.3V I/O Flash Program Memory Temperature Range: −40° to +85°Celsius ZPLL Clock 4K−Byte Static RAM 1K−Byte HET RAM (64 Instructions) Analog Watchdog (AWD) Real−Time Interrupt (RTI) 10−bit, 8−input MibADC Two SPI Modules Two SCI Modules C2SIa CAN [SCC] HET, 13 Channels ECP FLASH MEMORY 64 = 64K-Bytes Flash Memory ADVANCE INFORMATION ARCHITECTURE R1 = ARM7TDM1 CPU Figure 2. TMS470R1x Family Nomenclature 17 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 device identification code register The device identification code register identifies the silicon version, the technology family (TF), a ROM or Flash device, and an assigned device-specific part number (see Figure 3). The A64 device identification code register value is 0x083F. 31 16 Reserved 15 12 11 10 9 3 2 1 0 VERSION TF R/F PART NUMBER 1 1 1 R-K R-K R-K R-K R-1 R-1 R-1 LEGEND: R = Read only; -K = value constant after RESET; -1 = value after RESET Figure 3. TMS470 Device ID Bit Allocation Register Table 8. TMS470 Device ID Bit Allocation Register Description BIT NAME Value DESCRIPTION ADVANCE INFORMATION 31–16 Reserved Reads are undefined and writes have no effect. 15-12 VERSION Silicon version (revision) These bits identify the silicon version of the device. TF Technology Family This bit distinguishes the technology family core power supply: 11 10 18 0 3.3 V for F10/C10 devices 1 1.8 V for F05/C05 devices R/F ROM/Flash This bit distinguishes between ROM and Flash devices: 0 Flash device 1 ROM device 9–3 PART NUMBER Device-specific part number These bits identify the assigned device-specific part number. The assigned device-specific part number for the A64 device is 0000111. 2–0 1 Mandatory High Bits 2,1, and 0 are tied high by default. TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (1) VCC (2) -0.5 V to 2.5 V (2) Supply voltage ranges: VCCIO , VCCAD , VCCP (Flash pump) -0.5 V to 4.1 V Input voltage range: All input pins Input clamp current: I IK (V I < 0 or V I > VCCIO ) All pins except ADIN[0:11], PORRST, TRST , TEST and TCK ± 20 mA I IK (V I < 0 or V I > VCCAD ) ADIN[0:11] ±10 mA -0.5 V to 4.1 V Operating free-air temperature ranges, T A : -40°C to 85°C Operating junction temperature range, T J -40°C to 150°C Storage temperature range, Tstg -65°C to 150°C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds. DEVICE RECOMMENDED OPERATING CONDITIONS (1) MIN NOM UNIT VCC Digital logic and Flash supply voltage (Core) 2.05 V VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V VCCAD ADC supply voltage 3 3.3 3.6 V VCCP Flash pump supply voltage 3 3.3 3.6 V V SS Digital logic supply ground V SSAD ADC supply ground -0.1 0.1 V TA Operating free-air temperature -40 85 °C TJ Operating junction temperature -40 150 °C (1) 1.71 MAX 0 V All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD. 19 ADVANCE INFORMATION Supply voltage ranges: TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (1) PARAMETER TEST CONDITIONS Vhys Input hysteresis VIL Low-level input voltage All inputs (2) VIH High-level input voltage All inputs Vth Input threshold voltage AWD only RDSON Drain to source on resistance AWD only (3) V OL Low-level output voltage (4) VOH High-level output voltage(4) I IC Input clamp current (I/O pins) (5) ADVANCE INFORMATION II IOL IOH Input current (I/O pins) Low-level output current High-level output current CI Input capacitance CO Output capacitance VCC Digital supply current (operating mode) ICC (7) 20 MAX 0.8 2 VCCIO + 0. 3 1.35 V V 45 Ω 0.2 VCCIO I OL = 50 µ A 0.2 0.8 VCCIO I OH = 50 µ A VCCIO -0 .2 V 1.8 VOL = 0.35V @ IOL = 8mA IOH = I OH MIN UNIT V -0 .3 I OL = I OL MAX V V V I < VSSIO -0. 3 or V I > VCCIO + 0. 3 -2 I IL Pulldown V I = V SS -1 1 I IH Pulldown V I = VCCIO 5 40 I IL Pullup V I = V SS -40 -5 I IH Pullup V I = VCCIO -1 1 All other pins No pullup or pulldown -1 1 CLKOUT, AWD, TDO V OL = V OL MAX 8 RST, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK, SPI2SOMI, SPI2SIMO V OL = V OL MAX 4 All other output pins (6) V OL = V OL MAX 2 CLKOUT, TDO V OH = V OH MIN -8 SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK, SPI2SOMI, SPI2SIMO VOH = V OH MIN -4 All other output pins except RST(6) V OH = V OH MIN 2 mA µA mA mA -2 2 pF 3 pF pipeline SYSCLK = 48 MHz, ICLK = 24 MHz, VCC = 2.05 V 75 mA non-pipeline SYSCLK = 24 MHz, ICLK = 12 MHz, VCC = 2.05 V 50 mA OSCIN = 6 MHz, VCC = 2.05 V 3.0 mA All frequencies, VCC = 2.05 V 1.0 mA VCC Digital supply current (halt mode)(7) (4) (5) (6) TY P 0.15 VCC Digital supply current (standby mode) (1) (2) (3) MIN (7) Source currents (out of the device) are negative while sink currents (into the device) are positive. This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section. These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide (literature number SPNU189). VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied. Parameter does not apply to input-only or output-only pins. The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value will always be low. For Flash banks/pumps in sleep mode. TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (continued) PARAMETER ICCIO ICCAD (8) MIN TY P MAX UNIT VCCIO Digital supply current (operating mode) No DC load, VCCIO = 3.6 V (8) 10 mA VCCIO Digital supply current (standby mode) No DC load, VCCIO = 3.6 V(8) 300 µA V(8) VCCIO Digital supply current (halt mode) No DC load, VCCIO = 3.6 300 µA VCCAD supply current (operating mode) All frequencies, VCCAD = 3.6 V 15 mA VCCAD supply current (standby mode) All frequencies, VCCAD = 3.6 V 20 µA VCCAD supply current (halt mode) All frequencies, VCCAD = 3.6 V 20 µA VCCP = 3.6 V read operation 45 mA VCCP = 3.6 V program and erase 70 mA VCCP = 3.6 V standby mode operation(7) 20 µA VCCP = 3.6 V halt mode operation(7) 20 µA VCCP pump supply current I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs≥ VCCIO -0.2 V. ADVANCE INFORMATION ICCP TEST CONDITIONS 21 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 Parameter Measurement Information IOL Tester Pin Electronics 50 Ω VLOAD Output Under Test CL IOH Where: IOL IOH VLOAD CL = = = = IOL MAX for the respective pin(A) IOH MIN for the respective pin(A) 1.5 V 150-pF typical load-circuit capacitance(B) ADVANCE INFORMATION A. For these values, see the electrical characteristics over recommended operating free-air temperature range table. B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted. Figure 4. Test Load Circuit 22 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 timing parameter symbology CM Compaction, CMPCT RD Read CO CLKOUT RST Reset, RST ER Erase RX SCInRX ICLK Interface clock S Slave mode M Master mode SCC SCInCLK OSC, OSCI OSCIN SIMO SPInSIMO OSCO OSCOUT SOMI SPInSOMI P Program, PROG SPC SPInCLK R Ready SYS System clock R0 Read margin 0, RDMRGN0 TX SCInTX R1 Read margin 1, RDMRGN1 ADVANCE INFORMATION Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings are: a access time r rise time c cycle time (period) su setup time d delay time t transition time f fall time v valid time h hold time w pulse duration (width) The following additional letters are used with these meanings: H High X Unknown, changing, or don’t care level L Low Z High impedance V Valid 23 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 external reference resonator/crystal oscillator clock option The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 5b. OSCIN C1(A) OSCOUT Crystal C2(A) OSCIN External Clock Signal (toggling 0– 1.8 V) ADVANCE INFORMATION (a) A. (b) The values of C1 and C2 should be provided by the resonator/crystal vendor. Figure 5. Crystal/Clock Connection 24 OSCOUT TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 ZPLL and clock specifications TIMING REQUIREMENTS FOR ZPLL CIRCUITS ENABLED OR DISABLED MIN MAX UNIT 4 20 MHz f(OSC) Input clock frequency tc(OSC) Cycle time, OSCIN 50 ns tw(OSCIL) Pulse duration, OSCIN low 15 ns tw(OSCIH) Pulse duration, OSCIN high 15 f(OSCRST) OSC FAIL frequency (1) (1) ns 53 kHz Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number SPNU189). PARAMETER f(SYS) System clock frequency (4) f(CONFIG) System clock frequency - Flash config mode f(ICLK) Interface clock frequency f(ECLK) External clock output frequency for ECP Module tc(SYS) Cycle time, system clock tc(CONFIG) Cycle time, system clock - Flash config mode tc(ICLK) Cycle time, interface clock tc(ECLK) Cycle time, ECP module external clock output (1) (2) (3) (4) TEST CONDITIONS (3) MAX UNIT Pipeline mode enabled MIN 48 MHz Pipeline mode disabled 24 24 MHz Pipeline mode enabled 25 MHz Pipeline mode disabled 24 Pipeline mode enabled 25 Pipeline mode disabled 24 Pipeline mode enabled 20.8 Pipeline mode disabled 41.6 MHz ns 41.6 ns Pipeline mode enabled 40 ns Pipeline mode disabled 41.6 Pipeline mode enabled 40 Pipeline mode disabled 41.6 ns f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE [2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register (GLBCTRL.3). f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1. f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module. f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module. Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0). Flash Vread must be set to 5V to achieve maximum System Clock Frequency. 25 ADVANCE INFORMATION SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR CLOCKS (1) (2) TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR EXTERNAL CLOCKS (1) (2) (3) (See Figure 6 and Figure 7) NO. PARAMETER TEST CONDITION SYSCLK or MCLK` (4) 1 tw(COL) Pulse duration, CLKOUT low ICLK, X is even or 1 (5) 0.5tc(ICLK)– tf ICLK, X is odd and not 1 (5) SYSCLK or MCLK (4) 2 tw(COH) Pulse duration, CLKOUT high 3 4 tw(EOL) Pulse duration, ECLK low tw(EOH) Pulse duration, ECLK high 1 (5) ns ns 0.5tc(ICLK)– 0.5tc(SYS)– tr N is even and X is even or odd 0.5tc(ECLK)– tf N is odd and X is even 0.5tc(ECLK)– tf N is odd and X is odd and not 1 0.5tc(ECLK) + 0.5tc(SYS)– tf N is even and X is even or odd 0.5tc(ECLK)– tr N is odd and X is even 0.5tc(ECLK)– tr ns ns 0.5tc(ECLK)– 0.5tc(SYS)– tr ADVANCE INFORMATION X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module. N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module. CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active. Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary). Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary). 2 CLKOUT 1 Figure 6. CLKOUT Timing Diagram 4 ECLK 3 Figure 7. ECLK Timing Diagram 26 UNIT 0.5tc(ICLK) + 0.5tc(SYS)– tf 0.5tc(ICLK) – tr N is odd and X is odd and not 1 (1) (2) (3) (4) (5) MAX 0.5tc(SYS)– tr ICLK, X is even or 1 (5) ICLK, X is odd and not MIN 0.5tc(SYS)– tf TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 RST and PORRST timings TIMING REQUIREMENTS FOR PORRST (see Figure 8) MIN MAX UNIT VCCPORL VCC low supply level when PORRST must be active during power up VCCPORH VCC high supply level when PORRST must remain active during power up and become active during power down VCCIOPORL VCCIO low supply level when PORRST must be active during power up VCCIOPORH VCCIO high supply level when PORRST must remain active during power up and become active during power down VIL Low-level input voltage after VCCIO > VCCIOPORH VIL(PORRST) Low-level input voltage of PORRST before VCCIO > VCCIOPORL 3 tsu(PORRST)r Setup time, PORRST active before VCCIO > VCCIOPORL during power up 0 ms 5 tsu(VCCIO)r Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL 0 ms 6 th(PORRST)r Hold time, PORRST active after VCC > VCCPORH 1 ms 7 tsu(PORRST)f Setup time, PORRST active before VCC≤ VCCPORH during power down 8 ms 8 th(PORRST)rio Hold time, PORRST active after VCC > VCCIOPORH 1 ms 9 th(PORRST)d Hold time, PORRST active after VCC < VCCPORL 0 ms 10 tsu(PORRST)fio Setup time, PORRST active before VCC≤ VCCIOPORH during power down 0 ms 11 tsu(VCCIO)f Setup time, VCC < VCCPORE before VCCIO < VCCIOPORL 0 ms VCCP/VCCIO VCCIOPORH 0.6 1.5 V 1.1 V 2.75 V 0.2 VCCIO V 0.5 V VCCIOPORH VCCIO 8 VCC 11 VCC VCCPORH 6 VCCIOPORL 5 PORRST VIL(PORRST) VCCPORH 7 6 10 7 VCCPORL VCCPORL VCC VCCP/VCCIO V ADVANCE INFORMATION NO. 3 VCCIOPORL 9 VIL VIL VIL VIL VIL(PORRST) Figure 8. PORRST Timing Diagram 27 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SWITCHING CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS FOR RST (1) PARAMETER tv(RST) (1) MIN Valid time, RST active after PORRST inactive MAX 4112tc(OSC) Valid time, RST active (all others) UNIT ns 8tc(SYS) Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. JTAG SCAN INTERFACE TIMING (JTAG clock specification 10-MHz and 50-pF load on TDO output) NO. MIN UNIT ADVANCE INFORMATION tc(JTAG) Cycle time, JTAG low and high period 50 ns 2 tsu(TDI/TMS - TCKr) Setup time, TDI, TMS before TCK rise (TCKr) 15 ns 3 th(TCKr -TDI/TMS) Hold time, TDI, TMS after TCKr 15 ns 4 th(TCKf -TDO) Hold time, TDO after TCKf 10 5 td(TCKf -TDO) Delay time, TDO valid after TCK fall (TCKf) ns 45 TCK 1 1 TMS TDI 2 3 TDO 4 5 Figure 9. JTAG Scan Timing 28 MAX 1 ns TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 OUTPUT TIMINGS SWITCHING CHARACTERISTICS FOR OUTPUT TIMINGS VERSUS LOAD CAPACITANCE (CL) (See Figure 10) tr tf tr tf tr tf Rise time, CLKOUT, AWD, TDO Fall time, CLKOUT, AWD, TDO Rise time, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK, SPI2SOMI, SPI2SIMO Fall time, RST, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK, SPI2SOMI, SPI2SIMO Rise time, all other output pins Fall time, all other output pins MIN MAX CL = 15 pF 0.5 2.50 CL = 50 pF 1.5 5 CL = 100 pF 3 9 CL = 150 pF 4.5 12.5 CL = 15 pF 0.5 2.5 CL = 50 pF 1.5 5 CL = 100 pF 3 9 CL = 150 pF 4.5 12.5 CL = 15 pF 2.5 8 CL = 50 pF 5 14 CL = 100 pF 9 23 CL = 150 pF 13 32 CL = 15 pF 2.5 8 CL = 50 pF 5 14 CL = 100 pF 9 23 CL = 150 pF 13 32 CL = 15 pF 2.5 10 CL = 50 pF 6.0 25 CL = 100 pF 12 45 CL = 150 pF 18 65 CL = 15 pF 3 10 CL = 50 pF 8.5 25 CL = 100 pF 16 45 CL = 150 pF 23 65 ns ns ns ns ns ns tf tr 80% Output UNIT ADVANCE INFORMATION PARAMETER VCC 80% 20% 20% 0 Figure 10. CMOS-Level Outputs 29 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 INPUT TIMINGS TIMING REQUIREMENTS FOR INPUT TIMINGS (1) (See Figure 11) MIN tpw (1) Input minimum pulse width MAX UNIT tc(ICLK) + 10 ns tc(ICLK) = interface clock cycle time = 1 / f(ICLK) tpw Input 80% VCC 80% 20% 20% 0 Figure 11. CMOS-Level Inputs FLASH TIMINGS ADVANCE INFORMATION TIMING REQUIREMENTS FOR PROGRAM FLASH (1) tprog(16-bit) Half word (16-bit) programming time 64K-byte programming terase(sector) Sector erase time twec Write/erase cycles at TA = 125°C 30 TYP MAX UNIT 4 16 200 µs 1 4 s 2 15 s time (2) tprog(Total) (1) (2) MIN For more detailed information on the Flash core sectors, see the Flash program and erase section of this data sheet. The 64K-byte programming times include overhead of state machine. 100 cycles TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SPIn MASTER MODE TIMING PARAMETERS SPIn MASTER MODE EXTERNAL TIMING PARAMETERS (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 12) 1 2 (5) 3 (5) 4 (5) UNIT 256tc(ICLK) ns Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0) 0 10 Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1) 0 10 tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M td(SPCH-SIMO)M td(SPCL-SIMO)M tv(SPCL-SIMO)M Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0) tc(SPC)M - 5 - tf tv(SPCH-SIMO)M Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1) tc(SPC)M - 5 - tr tsu(SOMI-SPCL)M Setup time, SPInSOMI before SPInCLK low (clock polarity = 0) 6 tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 1) 6 tv(SPCL-SOMI)M Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0) 4 tv(SPCH-SOMI)M Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1) 4 6 (5) 7 (5) (5) MAX 100 Cycle time, SPInCLK (4) 5 (5) (1) (2) (3) (4) MIN tc(SPC)M ns ns ns ns ns ns The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared. tc(ICLK) = interface clock cycle time = 1/f(ICLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When the SPI is in master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of 0: tc(SPC)M = 2tc(ICLK)≥ 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSIMO Master Out Data Is Valid 6 7 SPInSOMI Master In Data Must Be Valid Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0) 31 ADVANCE INFORMATION NO. TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SPIn MASTER MODE EXTERNAL TIMING PARAMETERS (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 13) NO. 1 2 (5) 3 (5) MIN UNIT ns Cycle time, 100 256tc(ICLK) tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCH)M Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 tv(SIMO-SPCH)M Valid time, SPInCLK high after SPInSIMO data valid (clock polarity = 0) 0.5tc(SPC)M 10 tv(SIMO-SPCL)M Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1) 0.5tc(SPC)M 10 tv(SPCH-SIMO)M Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0) tc(SPC)M - 5 - tf tv(SPCL-SIMO)M Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1) tc(SPC)M - 5 - tr tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0) 6 tsu(SOMI-SPCL)M Setup time, SPInSOMI before SPInCLK low (clock polarity = 1) 6 tv(SPCH-SOMI)M Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) 4 tv(SPCL-SOMI)M Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) 4 5 (5) ADVANCE INFORMATION 6(5) 7(5) (5) MAX tc(SPC)M 4 (5) (1) (2) (3) (4) SPInCLK (4) ns ns ns ns ns The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set. tc(ICLK) = interface clock cycle time = 1 / f(ICLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When the SPI is in master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of 0: tc(SPC)M = 2tc(ICLK)≥ 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSIMO Master Out Data Is Valid Data Valid 6 7 SPInSOMI Master In Data Must Be Valid Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1) 32 ns TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SPIn SLAVE MODE TIMING PARAMETERS SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 14) 1 MIN MAX UNIT 100 256tc(ICLK) ns Pulse duration, SPInCLK high (clock polarity = 0) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) td(SPCH- Delay time, SPInCLK high to SPInSOMI valid (clock polarity = 0) 6 + tr Delay time, SPInCLK low to SPInSOMI valid (clock polarity = 1) 6 + tf tc(SPC)S Cycle time, SPInCLK (5) tw(SPCH)S 2 (6) 3 (6) 4 (6) SOMI)S td(SPCLSOMI)S tv(SPCH5 (6) SOMI)S tv(SPCLSOMI)S tsu(SIMO6 (6) SPCL)S tsu(SIMOSPCH)S tv(SPCL7 (6) SIMO)S tv(SPCHSIMO)S (1) (2) (3) (4) (5) (6) ns ns ns Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) tc(SPC)S - 6 - tr Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) tc(SPC)S - 6 - tf ns Setup time, SPInSIMO before SPInCLK low (clock polarity = 0) 6 Setup time, SPInSIMO before SPInCLK high (clock polarity = 1) 6 Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0) 6 Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1) 6 ns ns The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared. If the SPI is in slave mode, the following must be true: tc(SPC)S≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5]. For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. tc(ICLK) = interface clock cycle time = 1 /f(ICLK) When the SPIn is in slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of 0: tc(SPC)S = 2tc(ICLK)≥ 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 33 ADVANCE INFORMATION NO. TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSOMI SPISOMI Data Is Valid 6 7 ADVANCE INFORMATION SPInSIMO SPISIMO Data Must Be Valid Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0) 34 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 15) 1 MIN tc(SPC)S Cycle time, SPInCLK (5) tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 1) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 0) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 1) 0.5tc(SPC)S 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) tv(SOMI- Valid time, SPInCLK high after SPInSOMI data valid (clock polarity = 0) 0.5tc(SPC)S - 6 - tr Valid time, SPInCLK low after SPInSOMI data valid (clock polarity = 1) 0.5tc(SPC)S - 6 - tf Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) 0.5tc(SPC)S - 6 - tr Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) 0.5tc(SPC)S - 6 - tf SPCH)S tv(SOMItv(SPCHSOMI)S tv(SPCLSOMI)S tsu(SIMOSPCH)S tsu(SIMOSPCL)S tv(SPCH7 (6) SIMO)S tv(SPCLSIMO)S (1) (2) (3) (4) (5) (6) 256tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) Pulse duration, SPInCLK high (clock polarity = 0) SPCL)S 6 (6) ns 100 tw(SPCH)S 3 (6) 5 (6) UNI T 0.5tc(SPC)S 0.25tc(ICLK) 2 (6) 4 (6) MAX ns ns ns ns Setup time, SPInSIMO before SPInCLK high (clock polarity = 0) 6 Setup time, SPInSIMO before SPInCLK low (clock polarity = 1) 6 Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0) 6 Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1) 6 ns ns The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set. If the SPI is in slave mode, the following must be true: tc(SPC)S≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5]. For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. tc(ICLK) = interface clock cycle time = 1 /f(ICLK) When the SPIn is in slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S≥ (PS +1)tc(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits. For PS values of 0: tc(SPC)S = 2tc(ICLK)≥ 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 35 ADVANCE INFORMATION NO. TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSOMI SPISOMI Data Is Valid Data Valid 6 7 ADVANCE INFORMATION SPInSIMO SPISIMO Data Must Be Valid Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1) 36 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SCIn isosynchronous mode timings — internal clock TIMING REQUIREMENTS FOR INTERNAL CLOCK SCIn ISOSYNCHRONOUS MODE (1) (2) (3) (see Figure 16) 1 UNIT MIN MAX MIN MAX 2tc(ICLK) 224tc(ICLK) 3tc(ICLK) (224 -1) tc(ICLK) ns tc(SCC) Cycle time, SCInCLK 2 tw(SCCL) Pulse duration, SCInCLK low 0.5tc(SCC) - tf 0.5tc(SCC) + 5 0.5tc(SCC) + 0.5tc(ICLK)- tf 0.5tc(SCC) + 0.5tc(ICLK) ns 3 tw(SCCH) Pulse duration, SCInCLK high 0.5tc(SCC) - tr 0.5tc(SCC) + 5 0.5tc(SCC) - 0.5tc(ICLK)- tr 0.5tc(SCC) - 0.5tc(ICLK) ns 4 td(SCCH- Delay time, SCInCLK high to SCInTX valid 10 ns TXV) (1) (2) (3) (BAUD + 1) IS ODD AND BAUD ≠ 0 10 5 tv(TX) Valid time, SCInTX data after SCInCLK low tc(SCC) - 10 tc(SCC) - 10 ns 6 tsu(RX-SCCL) Setup time, SCInRX before SCInCLK low tc(ICLK) + tf + 20 tc(ICLK) + tf + 20 ns 7 tv(SCCL-RX) Valid time, SCInRX data after SCInCLK low - tc(ICLK) + tf + 20 - tc(ICLK) + tf + 20 ns ADVANCE INFORMATION (BAUD + 1) IS EVEN OR BAUD = 0 NO. BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers. tc(ICLK) = interface clock cycle time = 1 / f(ICLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table 1 3 2 SCICLK 5 4 SCITX Data Valid 6 7 SCIRX A. Data Valid Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge. Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock 37 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 SCIn isosynchronous mode timings — external clock TIMING REQUIREMENTS FOR EXTERNAL CLOCK SCIn ISOSYNCHRONOUS MODE (1) (2) (see Figure 17) NO. (1) (2) (3) MIN MAX tc(SCC) Cycle time, SCInCLK (3) 2 tw(SCCH) Pulse duration, SCInCLK high 0.5tc(SCC) - 0.25tc(ICLK) 0.5tc(SCC) + 0.25tc(ICLK) ns 3 tw(SCCL) Pulse duration, SCInCLK low 0.5tc(SCC) - 0.25tc(ICLK) 0.5tc(SCC) + 0.25tc(ICLK) ns 4 td(SCCH-TXV) Delay time, SCInCLK high to SCInTX valid 2tc(ICLK) + 12 + tr ns 5 tv(TX) Valid time, SCInTX data after SCInCLK low 6 tsu(RX-SCCL) Setup time, SCInRX before SCInCLK low 7 tv(SCCL-RX) Valid time, SCInRX data after SCInCLK low 8tc(ICLK) ns 2tc(SCC) - 10 ns 0 ns 2tc(ICLK) + 10 ns tc(ICLK) = interface clock cycle time = 1 / f(ICLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When driving an external SCInCLK, the following must be true: tc(SCC)≥ 8tc(ICLK) 1 ADVANCE INFORMATION 2 3 SCICLK 5 4 Data Valid SCITX 6 7 SCIRX A. Data Valid Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge. Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock 38 UNIT 1 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 high-end timer (HET) timings Minimum PWM output pulse width: This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes. Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns Minimum input pulses we can capture: The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32. Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns ADVANCE INFORMATION NOTE: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is, the captured value gives the number of HRP clocks inside the pulse.) Abbreviations: hr = HET high resolution divide rate = 1, 2, 3,...63, 64 lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32 High resolution clock period = HRP = hr/SYSCLK Loop resolution clock period = LRP = hr*lr/SYSCLK standard CAN controller (SCC) mode timings dynamic characteristics for the CANSTX and CANSRX pins PARAMETER MIN pin (1) td(CANSTX) Delay time, transmit shift register to CANSTX td(CANSRX) Delay time, CANSRX pin to receive shift register (1) MAX UNIT 15 ns 5 ns These values do not include rise/fall times of the output buffer. 39 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 MULTI-BUFFERED A-TO-D CONVERTER (MibADC) The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry. This power bus enhances the A-to-D performance by preventing digital switching noise on the logic circuitry that could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted. Resolution 10 bits (1024 values) Monotonic Assured 00h to 3FFh [00 for VAI≤ ADREFLO; 3FF for VAI≥ ADREFHI] Output conversion code MibADC recommended operating conditions (1) MIN MAX UNIT ADREFHI A-to-D high-voltage reference source VSSAD VCCAD V ADREFLO A-to-D low-voltage reference source VSSAD VCCAD V VAI Analog input voltage VSSAD - 0.3 VCCAD + 0.3 V -2 2 mA current (2) Analog input clamp (VAI < VSSAD - 0.3 or VAI > VCCAD + 0.3) IAIC ADVANCE INFORMATION (1) (2) For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table. Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. operating characteristics over full ranges of recommended operating conditions (1) (2) PARAMETER Ri Analog input resistance DESCRIPTION/CONDITIONS Ci Analog input capacitance See Figure 18. IAIL Analog input leakage current See Figure 18. IADREFHI ADREFHI input current ADREFHI = 3.6 V, ADREFLO = VSSAD CR Conversion range over which specified accuracy is maintained ADREFHI - ADREFLO EDNL Differential nonlinearity error EINL ETOT (1) (2) 40 MIN See Figure 18. TYP MAX UNIT 250 Conversion Sampling -1 Ω 10 pF 30 pF 1 µA 5 mA 3.6 V Difference between the actual step width and the ideal value after offset correction. See Figure 19. ±2 LSB Integral nonlinearity error Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error after offset correction. See Figure 20. ±2 LSB Total error/Absolute accuracy Maximum value of the difference between an analog value and the ideal midstep value. See Figure 21. ±2 LSB VCCAD = ADREFHI 1 LSB = (ADREFHI - ADREFLO)/ 210 for the MibADC 3 500 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 External Rs MibADC Input Pin Ri Sample Switch Parasitic Capacitance Vsrc Sample Capacitor Rleak Ci Figure 18. MibADC Input Equivalent Circuit MIN tc(ADCLK) Cycle time, MibADC clock td(SH) Delay time, sample and hold time td(C) td(SHC) (1) (1) MAX UNIT 0.05 µs 1 µs Delay time, conversion time 0.55 µs Delay time, total sample/hold and conversion time 1.55 µs This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). 41 ADVANCE INFORMATION multi-buffer ADC timing requirements TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (1/2 LSB) 1 LSB 0 ... 010 0 ... 001 Differential Linearity Error (– 1/2 LSB) 1 LSB 0 ... 000 A. 1 2 3 4 Analog Input Value (LSB) 5 1 LSB = (ADREFHI - ADREFLO)/210 Figure 19. Differential Nonlinearity (DNL) The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 0 ... 110 Digital Output Code ADVANCE INFORMATION 0 Ideal Transition 0 ... 101 Actual Transition 0 ... 100 At Transition 011/100 (– 1/2 LSB) 0 ... 011 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (– 1/4 LSB) 0 ... 000 0 1 2 3 4 5 6 Analog Input Value (LSB) A. 1 LSB = (ADREFHI - ADREFLO)/210 Figure 20. Integral Nonlinearity (INL) Error 42 7 TMS470R1A64 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS099 – NOVEMBER 2004 The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (– 1 1/4 LSB) 0 ... 011 0 ... 010 Total Error At Step 0 ... 001 ( 1/2 LSB) 0 ... 001 ADVANCE INFORMATION Digital Output Code 0 ... 110 0 ... 000 0 A. 1 2 3 4 5 Analog Input Value (LSB) 6 7 1 LSB = (ADREFHI - ADREFLO)/210 Figure 21. Absolute Accuracy (Total) Error Thermal Characteristics PARAMETER °C/W RΘJA 48 RΘJC 5 43 PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TMX470R1A64PN PREVIEW LQFP PN Pins Package Eco Plan (2) Qty 80 1 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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