MOTOROLA MTP60N06

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SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
60 AMPERES
60 VOLTS
RDS(on) = 0.014 OHM
This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
D
G
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 30
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
60
42.3
180
Adc
Total Power Dissipation
Derate above 25°C
PD
150
1.0
Watts
W/°C
TJ, Tstg
– 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω)
EAS
540
mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
RθJC
RθJA
1.0
62.5
°C/W
TL
260
°C
Rating
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
TMOS
Motorola
Motorola, Inc.
1995 Power MOSFET Transistor Device Data
1
MTP60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
60
—
—
71
—
—
—
—
—
—
10
100
—
—
100
2.0
—
3.0
7.0
4.0
—
—
0.011
0.014
—
—
—
—
1.0
0.9
15
20
—
Unit
OFF CHARACTERISTICS
(Cpk ≥ 2.0) (3)
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current
(VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 3.0) (3)
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 30 Adc)
(Cpk ≥ 3.0) (3)
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 60 Adc)
(ID = 30 Adc, TJ = 125°C)
VGS(th)
Vdc
RDS(on)
Ohm
VDS(on)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 30 Adc)
mV/°C
Vdc
gFS
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
Ciss
—
1950
2800
Coss
—
660
924
Crss
—
147
300
td(on)
—
14
26
pF
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 30 Vdc, ID = 60 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 60 Adc,
VGS = 10 Vdc)
tr
—
197
394
td(off)
—
50
102
tf
—
124
246
QT
—
51
71
Q1
—
12
—
Q2
—
24
—
Q3
—
21
—
—
—
0.99
0.89
1.2
—
trr
—
60
—
ta
—
36
—
tb
—
24
—
QRR
—
0.143
—
—
—
3.5
4.5
—
—
—
7.5
—
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Reverse Recovery Time
(See Figure 15)
(IS = 60 Adc, VGS = 0 Vdc)
(IS = 60 Adc, VGS = 0 Vdc, TJ = 125°C)
(IS = 60 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
nH
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk =
3 x SIGMA
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
120
120
I D , DRAIN CURRENT (AMPS)
9V
80
TJ = 25°C
60
6V
40
5V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
100°C
25°C
TJ = – 55°C
2.8
3.6
4.4
5.2
6.0
6.8
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
TJ = 100°C
0.016
0.014
25°C
0.012
0.010
– 55°C
0.008
20
30
40
50
60
70
80
90
100 110 120
7.6
0.0132
TJ = 25°C
0.0128
0.0124
0.0120
VGS = 10 V
0.0116
0.0112
0.0108
15 V
0.0104
0.0100
0
10
20
30
40
50
60
70
80
90
100 110 120
ID, DRAIN CURRENT (Amps)
ID, DRAIN CURRENT (Amps)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
1.8
1.6
VGS = 0 V
VGS = 10 V
ID = 30 A
TJ = 125°C
I DSS, LEAKAGE (nA)
R DS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
40
VGS, GATE–TO–SOURCE VOLTAGE (Volts)
0.018
10
60
0
2.0
5.0
VGS = 10 V
0
80
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)
0.020
0.006
100
20
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
100
20
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
VDS ≥ 10 V
7V
8V
VGS = 10 V
1.4
1.2
1.0
100
100°C
25°C
10
0.8
0.6
– 50
1
– 25
0
25
50
75
100
125
150
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
60
3
MTP60N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
5000
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
4000
3000
Crss
Ciss
2000
Coss
1000
Crss
0
10
0
5
VGS
5
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
60
QT
10
50
VGS
8
40
Q1
Q2
6
30
4
20
ID = 60 A
TJ = 25°C
10
2
Q3
0
0
8
VDS
16
24
32
40
48
0
56
1000
VDD = 30 V
ID = 60 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
12
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTP60N06HD
tr
tf
100
td(off)
td(on)
10
1
10
QT, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (Ohms)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short t rr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
I S , SOURCE CURRENT (AMPS)
60
50
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.5
0.6
0.7
0.8
0.9
1.0
VSD, SOURCE–TO–DRAIN VOLTAGE (Volts)
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
MTP60N06HD
di/dt = 300 A/µs
I S , SOURCE CURRENT
Standard Cell Density
trr
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 µs
100
100 µs
10
1
0.1
6
1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0
10 ms
dc
10
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
600
ID = 60 A
500
400
300
200
100
0
100
25
50
75
100
125
150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
Motorola TMOS Power MOSFET Transistor Device Data
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
MTP60N06HD
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7
MTP60N06HD
PACKAGE DIMENSIONS
–T–
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
F
T
S
4
A
Q
1 2 3
U
STYLE 5:
PIN 1.
2.
3.
4.
H
K
Z
L
GATE
DRAIN
SOURCE
DRAIN
R
V
J
G
D
N
CASE 221A–06
ISSUE Y
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
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8
◊
*MTP60N06HD/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP60N06HD/D