CYPRESS CYUSB3014

PRELIMINARY
CYUSB3014
EZ-USB® FX3 SuperSpeed USB Controller
Features
■
Fully accessible 32-bit CPU
❐ ARM926EJ Core with 200MHz operation
❐ 512 kB Embedded SRAM
Additional connectivity to following peripherals
2
❐ I C master controller at 1 MHz
2
❐ I S master (transmitter only) at sampling frequencies 32 kHz,
44.1 kHz, 48 kHz
❐ UART support up to 4 Mbps
❐ SPI master at 33 MHz
Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2 MHz crystal input support
TDI
Logic Block Diagram
TCK
■
■
Independent power domains for core and I/O
❐ Core operation at 1.2 V
2
❐ I S, UART and SPI operation at 1.8 to 3.3V
2
❐ I C operation at 1.2 V
■
10 × 10 mm, 0.8 mm pitch Pb-free ball grid array (BGA) package
■
EZ USB® software and DVK for easy code development
■
Digital video camcorders
■
Digital still cameras
■
Printers
■
Scanners
■
Video capture cards
■
Test and measurement equipment
■
Surveillance cameras
■
Personal navigation devices
■
Medical imaging devices
■
Video IP phones
■
Portable media players
■
Industrial cameras
TDO
■
Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT ON and 20 µA with VBATT off
Applications
General programmable interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II interface enables
connectivity to wide range of external devices
❐ 8-/16-/32-bit data bus
❐ Up to 16 configurable control signals
TMS
■
Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripheral compliant with USB3.0
specification 1.0
❐ 5-Gbps USB3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral
compliant with On-The-Go Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
TRST#
■
■
FSLC[0]
FSLC[1]
FSLC[2]
JTAG
CLKIN
CLKIN_32
Embedded
SRAm
(512kB)
XTALIN
ARM926EJ -S
XTALOUT
HS/FS/LS
OTG Host
OTG_ID
SSRX -
DATA[31:0 ]
PMODE[2:0]
32
EPs
GPIF™ II
HS/FS
Peripheral
INT#
RESET #
SSTX SSTX +
D+
D-
EZ-Dtect™
198 Champion Court
I2S_MSCLK
I2S_SD
I2S_WS
MOSI
I2S
I2S_CLK
SCK
MISO
SSN
SPI
RTS
RX
TX
I2C_SDA
I2C_SCL
•
CTS
UART
I2C
Cypress Semiconductor Corporation
Document Number 001-52136 Rev. *H
SSRX +
USB INTERFACE
SS
Peripheral
CTL[12:0]
•
San Jose, CA 95134-1709
• 408-943-2600
Revised May 17, 2011
[+] Feedback
PRELIMINARY
CYUSB3014
Contents
Functional Overview .......................................................... 3
Application Examples .................................................... 3
USB Interface ...................................................................... 4
OTG............................................................................... 4
ReNumeration ............................................................... 5
EZ-Dtect ........................................................................ 5
VBUS Overvoltage Protection ....................................... 5
Carkit UART Mode ........................................................ 5
GPIF II .................................................................................. 6
CPU ...................................................................................... 6
JTAG Interface .................................................................... 7
Other Interfaces .................................................................. 7
UART Interface.............................................................. 7
I2C Interface.................................................................. 7
I2S Interface .................................................................. 7
SPI Interface.................................................................. 7
Boot Options....................................................................... 7
Reset.................................................................................... 8
Hard Reset .................................................................... 8
Soft Reset...................................................................... 8
Clocking .............................................................................. 8
32-kHz Watchdog Timer Clock Input............................. 8
Power................................................................................... 9
Power Modes ................................................................ 9
Configuration Options ..................................................... 13
Document Number 001-52136 Rev. *H
Digital I/Os.........................................................................
GPIOs.................................................................................
System Level ESD ............................................................
Absolute Maximum Ratings ............................................
Operating Conditions.......................................................
AC Timing Parameters .....................................................
GPIF II Timing .............................................................
Slave FIFO Interface ...................................................
Serial Peripherals Timing ............................................
Reset Sequence................................................................
Pin Description .................................................................
Package Diagram..............................................................
Ordering Information .......................................................
Ordering Code Definition.............................................
Acronyms ..........................................................................
Document Conventions ...................................................
Units of Measure .........................................................
Document History Page ...................................................
Sales, Solutions, and Legal Information ........................
Worldwide Sales and Design Support.........................
Products ......................................................................
PSoC Solutions ...........................................................
13
13
13
14
14
16
16
19
26
30
32
35
35
35
36
36
36
37
38
38
38
38
Page 2 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Functional Overview
EZ-USB FX3 contains 512 kB of on-chip SRAM for code and
data. EZ-USB FX3 also provides interfaces to connect to serial
peripherals such as UART, SPI, I2C, and I2S.
Cypress EZ-USB FX3 is the next generation USB3.0 peripheral
controller providing highly integrated and flexible features that
enable developers to add USB3.0 functionality to any system.
EZ-USB FX3 comes with the easy to use EZ-USB tools providing
a complete solution for fast application development. The
software development kit comes with application examples for
accelerating time to market.
EZ-USB FX3 has a fully configurable, parallel, General
Programmable Interface called GPIF II, which can connect to
any processor, ASIC, or FPGA. The General Programmable
Interface GPIF II is an enhanced version of the GPIF in FX2LP,
Cypress’s flagship USB2.0 product. It provides easy and
glueless connectivity to popular interfaces such as
asynchronous SRAM, asynchronous and synchronous Address
Data Multiplexed interface, parallel ATA, and so on.
EZ-USB FX3 is fully compliant to USB3.0 v1.0 specification and
is also backward compatible with USB2.0. It is also complaint
with the Battery Charging Specification v1.1 and USB2.0 OTG
Specification v2.0.
Application Examples
EZ-USB FX3 has integrated USB3.0 and USB2.0 physical layer
(PHYs) along with a 32-bit ARM926EJ-S microprocessor for
powerful data processing and for building custom applications. It
implements an ingenious architecture which enables data
transfers of 320 MBps[1] from GPIF II to USB interface.
Figure 1 and Figure 2 show typical application diagrams for
EZ-USB FX3. Figure 1 shows a typical application diagram in
which EZ-USB FX3 functions as a co-processor and connects to
an external processor responsible for various system level
functions. Figure 2 shows a typical application diagram when
EZ-USB FX3 functions as the main processor in the system.
An integrated USB2.0 OTG controller enables applications that
need dual role usage scenarios, for example EZ-USB FX3 may
function as OTG Host to MSC and HID class devices.
Figure 1. EZ-USB FX3 as a Co-processor
POWER
SUBSYSTEM
XTALOUT
XTALIN
CRYSTAL*
External Processor
text
(example: MCU/CPU/ASIC/
FPGA)
GPIF II
EZ-USB FX3
(ARM9 Core)
USB
Port
USB Host
Serial Interfaces
(example: I2C)
* A clock input may be provided on the
CLKIN pin instead of a crystal input
External Serial Peripheral
(example: EEPROM)
Note
1. Assuming that GPIF II is configured for 32 bit data bus synchronous interface operating at 100 MHz. This number also includes protocol overheads.
Document Number 001-52136 Rev. *H
Page 3 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Figure 2. EZ-USB FX3 as Main Processor
EXTERNAL SLAVE
DEVICE
(Eg: IMAGE SENSOR)
GPIF II
XTALIN
XTALOUT
CRYSTAL*
EZ-USB FX3
(ARM9 Core)
USB
Port
USB Host
I2C
* A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
Figure 3. USB Interface Signals
EZ-USB FX3
EZ-USB FX3 supports USB peripheral functionality compliant
with USB 3.0 Specification Revision 1.0 and is also backward
compatible with the USB 2.0 Specification.
VBATT
VBUS
OTG_ID
SSRXSSRX+
SSTXSSTX+
DD+
EZ-USB FX3 is compliant with On-The-Go Supplement Revision
2.0. It supports Hi-Speed, Full-Speed, and Low Speed OTG dual
role device capability. It is SuperSpeed, High-Speed, and
Full-Speed capable as a peripheral and High-Speed, Full-Speed,
and Low-Speed capable as a host.
EZ-USB FX3 supports Carkit Pass-Through UART functionality
on USB D+/D- lines based on the CEA-936A specification.
EZ-USB FX3 supports up to 16 IN and 16 OUT endpoints.
EZ-USB FX3 fully supports the USB3.0 Streams feature. It also
supports USB Attached SCSI (UAS) device class to optimize
mass storage access performance.
As a USB peripheral, EZ-USB FX3 supports UAS, USB Video
Class (UVC), Mass Storage Class (MSC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral, all
other device classes are supported only in pass through mode
when handled entirely by a host processor external to the device.
As an OTG host, EZ-USB FX3 supports MSC and HID device
classes.
When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Document Number 001-52136 Rev. *H
USB Interface
USB Interface
OTG
EZ-USB FX3 is compliant with the On-The-Go (OTG) Specification Revision 2.0 .
In OTG mode, EZ-USB FX3 supports both A and B device mode
and supports Control, Interrupt, Bulk, and Isochronous data
transfers.
EZ-USB FX3 requires an external charge pump (either stand
alone or integrated into a PMIC) to power VBUS in OTG A-device
mode.
The Target Peripheral List for OTG host implementation consists
of MSC and HID class devices.
Attach Detection Protocol (ADP) is not supported by EZ-USB
FX3.
Page 4 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
OTG Connectivity
VBUS Overvoltage Protection
In OTG mode, EZ-USB FX3 can be configured to be A, B, or dual
role device. It is able to connect to:
■
ACA device
■
Targeted USB peripheral
■
SRP capable USB peripheral
The maximum input voltage on EZ-USB FX3's VBUS pin is 6V.
A charger can supply up to 9V on VBUS, in this case, it is
necessary to have an external Over voltage Protection (OVP)
device to protect EZ-USB FX3 from damage on VBUS. Figure 4
shows the system application diagram with an OVP device
connected on VBUS. Please refer to Table 7DC Specifications
for the operating range of VBUS and VBATT.
■
HNP capable USB peripheral
Figure 4. System Diagram with OVP Device For VBUS
■
OTG host
■
HNP capable host
■
OTG device
EZ-Dtect
EZ-USB FX3 supports USB Charger and accessory detection
(EZ-Dtect). The charger detection mechanism is in compliance
with the Battery Charging Specification Revision 1.1. In addition
to supporting this version of the specification EZ-USB FX3 also
provides hardware support to detect the resistance values on the
ID pin.
The following are the resistance ranges that EZ-USB FX3 can
detect:
■
Less than 10 Ω
■
Less than 1 kΩ
■
65 kΩ to 72 kΩ
■
35 kΩ to 39 kΩ
■
99.96 kΩ to 104.4 kΩ (102 kΩ ± 2%)
■
119 kΩ to 132 kΩ
■
Higher than 220 kΩ
■
431.2 kΩ to 448.8 kΩ (440 kΩ ± 2%)
VIO5
AVDD
VDD
VIO4
CVDDQ
VIO3
EZ-USB FX3
OVP device
2
SSRXSSRX+
SSTXSSTX+
DD+
3
4
5
6
7
8
9
VBUS
OTG_ID
USB-Port
1
USB Connector
When first plugged into USB, EZ-USB FX3 enumerates
automatically with the Cypress Vendor ID (0x04B4) and
downloads firmware and USB descriptors over the USB
interface. The downloaded firmware executes a electrical
disconnect and connect. EZ-USB FX3 enumerates again, this
time as a device defined by the downloaded information. This
patented two step process called ReNumeration happens
instantly when the device is plugged in.
VIO2
Because EZ-USB FX3's configuration is soft, one chip can take
on the identities of multiple distinct USB devices.
VIO1
ReNumeration
U3TXVDDQ
U3RXVDDQ
POWER SUBSYSTEM
GND
Carkit UART Mode
The USB interface supports Carkit UART mode (UART over
D+/D-) for non-USB serial data transfer. This is based on the
CEA-936A specification.
In Carkit UART mode, the output signaling voltage is 3.3V. When
configured for Carkit UART mode, TXD of UART (output) is
mapped to D- line, and RXD of UART (input) is mapped to D+
line.
In Carkit mode, EZ-USB FX3 disables the USB transceiver and
D+ and D- pins serve as pass through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49] as
shown in Figure 5 on page 6.
A rate of up to 9600 bps is supported by EZ-USB FX3 in this
mode.
EZ-USB FX3's charger detection feature detects a dedicated
wall charger, Host/Hub charger, and Host/Hub.
Document Number 001-52136 Rev. *H
Page 5 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Figure 5. Carkit UART Pass Through Block Diagram
UART_TXD
TXD
UART_RXD
RXD
RXD (DP)
USB-Port
Carkit UART pass through
interface on GPIF(TM)II
interface.
Ctrl
Carkit UART Pass Through
Carkit UART pass through
interface on GPIOs
USB PHY DM
MUX
DP
GPIO[48]
(UART_TX)
TXD (DM)
GPIO[49]
(UART_RX)
GPIF II
EZ-USB FX3 offers a high performance General Programmable
Interface, GPIF II. This interface enables functionality similar to
but more advanced than FX2LP's GPIF and Slave FIFO
interfaces.
Note: Access to all 32 buffer is also supported over Slave FIFO
interface. For details, please contact Cypress Applications
Support.
Figure 6. Slave FIFO Interface
SLCS#
PKTEND
FLAGB
FLAGA
The GPIF II is a programmable state machine that enables a
flexible interface that may function either as a master or slave in
industry standard or proprietary interfaces. Both parallel and
serial interfaces may be implemented with GPIF II.
External
Processor
The features of the GPIF II are summarized as follows:
A[1:0]
D[31:0]
EZ-USB FX3
SLWR#
■
Functions as master or slave
SLRD#
■
Provides 256 firmware programmable states
SLOE#
■
Supports 8 bit, 16 bit and 32 bit parallel data bus
■
Enables interface frequencies up to 100 MHz.
■
Supports 14 configurable control pins when 32 bit data bus is
used. All control pins can be either input/output or bidirectional.
CPU
■
Supports 16 configurable control pins when 16/8 data bus is
used. All control pins can be either input/output or bidirectional.
EZ-USB FX3 has an on chip 32-bit, 200 MHz ARM926EJ-S core
CPU. The core has direct access to 16kB of Instruction Tightly
Coupled Memory (TCM) and 8kB of Data TCM. The
ARM926EJ-S core provides a JTAG interface for firmware
debugging.
GPIFII state transitions occur based on control input signals. The
control output signals are driven as a result of GPIFII state transitions. The behavior of the GPIFII state machine is defined by a
GPIFII descriptor. The GPIFII descriptor is designed such that
the required interface specifications are met. 8kB of memory
(separate from the 512kB of embedded SRAM) is dedicated as
GPIF II Waveform memory where the GPIF II descriptor is stored
in a specific format.
Cypress’ GPIFII Designer Tool enables fast development of
GPIFII descriptors and includes examples for common interfaces.
Example implementations of GPIF II are the Asynchronous
Slave FIFO and Synchronous Slave FIFO interfaces.
Slave FIFO interface
The Slave FIFO interface signals are shown in Figure 6. This
interface allows an external processor to directly access upto 4
buffers internal to EZ-USB FX3. Further details of the Slave FIFO
interface are described on page 19
Document Number 001-52136 Rev. *H
Note: Multiple Flags may be configured.
EZ-USB FX3 also integrates 512 kB of embedded SRAM for
code and data, and 8kB of Instruction cache and Data cache.
EZ-USB FX3 implements highly efficient and flexible DMA
connectivity between the various peripherals (i.e. USB, GPIF II,
I2S, SPI,UART), requiring firmware to only configure data
accesses between peripherals which are then managed by the
DMA fabric.
EZ-USB FX3 allows for easy application development on
industry standard development tools for ARM926EJ-S.
Examples of EZ-USB FX3 firmware are available with the
Cypress EZ-USB FX3 Development Kit.
Software APIs that can be ported to an external processor are
available with the Cypress EZ-USB FX3 Software Development
Kit.
Page 6 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
JTAG Interface
EZ-USB FX3’s JTAG interface provides a standard five-pin
interface for connecting to a JTAG debugger to debug firmware
through the CPU-core's on-chip-debug circuitry.
Industry standard debugging tools for the ARM926EJ-S core can
be used for EZ-USB FX3 application development.
Other Interfaces
EZ-USB FX3 supports the following serial peripherals:
Both SCL and SDA signals of the I2C interface require external
pull-up resistors. The pull-up resistors must be connected to
VIO5.
I2S Interface
EZ-USB FX3 has an I2S port to support external audio codec
devices. EZ-USB FX3 functions as I2S Master as transmitter
only. The I2S interface consists of four signals: clock line
(I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS),
and master system clock (I2S_MCLK). EZ-USB FX3 can
generate the system clock as an output on I2S_MCLK or accept
an external system clock input on I2S_MCLK.
■
UART
■
I2C
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
■
I2S
SPI Interface
■
SPI
The SPI, UART and I2S interfaces are multiplexed on the Serial
Peripheral port.
EZ-USB FX3 supports an SPI Master interface on the Serial
Peripherals port.The maximum frequency of operation is
33 MHz.
UART Interface
The SPI controller supports four modes of SPI communication
with Start-Stop clock. The SPI controller is a single master
controller with a single automated SSN control. It supports
transaction sizes from 4-bit to 32 bits long.
The UART interface of EZ-USB FX3 supports full duplex
communication. It includes the signals noted in Table 1.
Boot Options
Table 1. UART Interface Signals
EZ-USB FX3 can load boot images from various sources,
selected by the configuration of the PMODE pins. The boot
options for EZ-USB FX3 are listed as follows:
The Pin List on page 32 shows details of how these interfaces
are multiplexed.
Signal
Description
TX
Output signal
RX
Input signal
CTS
Flow control
RTS
Flow control
The UART is capable of generating a range of baud rates from
300 bps to 4608 Kbps selectable by the firmware.
2
I C Interface
I2C
I 2C
EZ-USB FX3 has an
interface compatible with the
Bus
Specification Revision 3. EZ-USB FX3’s I2C interface is capable
of operating as I2C Master only, hence may be used to
communicate with other I2C slave devices. For example,
EZ-USB FX3 may boot from an EEPROM connected to the I2C
interface, as a selectable boot option.
I2C
EZ-USB FX3’s
Master Controller also supports Multi-master
mode functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This is
to allow the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
■
Boot from USB
■
Boot from I2C
■
Boot from SPI (SPI devices supported are M25P16 (16 Mbit),
M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents
■
Boot from GPIF II ASync ADMUX mode
■
Boot from GPIF II Sync ADMUX mode
■
Boot from GPIF II ASync SRAM mode
Table 2. Booting Options for EZ-USB FX3
PMODE[2:0][2]
Boot From
F00
Sync ADMUX (16-bit)
F01
Async ADMUX (16-bit)
F11
USB boot
F0F
Async SRAM (16-bit)
F1F
I2C, On Failure, USB Boot is Enabled
1FF
I2C only
0F1
SPI, On Failure, USB Boot is Enabled
The bus frequencies supported by the I2C controller are 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz.
Note
2. F indicates Floating.
Document Number 001-52136 Rev. *H
Page 7 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Reset
Clocking
Hard Reset
EZ-USB FX3 allows either a crystal to be connected between the
XTALIN and XTALOUT pins or an external clock to be connected
at the CLKIN pin.
A hard reset is initiated by asserting the Reset# pin on EZ-USB
FX3. The specific reset sequence and timing requirements are
detailed in Figure 17 and Table 15.
Soft Reset
Soft Reset involves the processor setting the appropriate bits in
the PP_INIT control register. There are two types of Soft Reset:
■
CPU Reset - The CPU Program Counter is reset. Firmware
does not need to be reloaded following a CPU Reset.
■
Whole Device Reset - This reset is identical to Hard Reset. The
firmware must be reloaded following a Whole Device Reset.
Crystal frequency supported is 19.2 MHz, while the external
clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.
EZ-USB FX3 has an on-chip oscillator circuit that uses an
external 19.2 MHz (±100 ppm) crystal (when the crystal option is
used). The FSLC[2:0] pins must be configured appropriately to
select the crystal option/clock frequency option. The configuration options are shown in Table 3.
Clock inputs to EZ-USB FX3 must meet the phase noise and
jitter requirements specified in Table 4.
The input clock frequency is independent of the clock/data rate
of EZ-USB FX3 core or any of the device interfaces (including
P-Port and S-Port). The internal PLL applies the appropriate
clock multiply option depending on the input frequency.
Table 3. Crystal/Clock Frequency Selection
FSLC[2]
FSLC[1]
FSLC[0]
Crystal/ Clock Frequency
0
0
0
19.2 MHz crystal
1
0
0
19.2 MHz input CLK
1
0
1
26 MHz input CLK
1
1
0
38.4 MHz input CLK
1
1
1
52 MHz input CLK
Table 4. Input Clock Specifications for EZ-USB FX3
Parameter
Phase noise
Specification
Description
100 Hz Offset
Units
Min
Max
–
–75
dB
1 kHz Offset
–
–104
dB
10 kHz Offset
–
–120
dB
100 kHz Offset
–
–128
dB
1 MHz Offset
–
–130
dB
Maximum frequency deviation
–
150
ppm
Duty cycle
30
70
%
Overshoot
–
3
%
Undershoot
–
–3
%
Rise time/fall time
–
3
ns
32-kHz Watchdog Timer Clock Input
EZ-USB FX3 includes a watchdog timer. The watchdog timer can
be used to interrupt the ARM926EJ-S core, auto wakeup
EZ-USB FX3 in Standby mode and reset the ARM926EJ-S core.
The watch dog timer runs off a 32 kHz clock. This 32 kHz clock
may optionally be supplied from an external source on a
dedicated pin of EZ-USB FX3.
The watchdog timer can be disabled by firmware.
Document Number 001-52136 Rev. *H
Requirements for the optional 32 kHZ clock input are listed in
Table 5.
Table 5. 32 kHz Clock Input Requirements
Parameter
Min
Max
Units
40
60
%
Frequency deviation
–
±200
ppm
Rise time/fall time
–
3
ns
Duty cycle
Page 8 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Power
EZ-USB FX3 has the following power supply domains.
IO_VDDQ: This refers to a group of independent supply domains
for digital I/Os. The voltage level on these supplies is 1.8V to
3.3V. EZ-USB FX3 provides six independent supply domains for
digital I/Os listed as follows. Refer to Table 16 for details on the
signals assigned to each power domain.
■
VIO1 - GPIF II I/O power supply domain
■
VIO2 - IO2 power supply domain
■
VIO3 - IO3 power supply domain
■
VIO4 - UART/SPI/I2S power supply domain
I2C
VBATT/VBUS: This is the 3.2V to 6V battery power supply for
the USB I/O, and analog circuits. This supply powers the USB
transceiver through EZ-USB FX3's internal voltage regulator.
VBATT is internally regulated to 3.3V.
Power Modes
EZ-USB FX3 supports different power modes as follows:
■
Normal mode: This is the full functional operating mode. In this
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (please refer to Table 7
for current consumption specifications).
The I/O power supplies (VIO1,VIO2,VIO3,VIO4, VIO5) may be
turned off when the corresponding interface is not in use.
■
VIO5 and JTAG power supply domain (1.2V to 3.3V is
supported)
■
CVDDQ - Clock power supply domain
■
Suspend mode with USB 3.0 PHY enabled (L1)
■
VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
❐ AVDD: This is the 1.2 V supply for the PLL, crystal oscillator
and other core analog circuits
❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply voltages for the USB 3.0 interface.
■
Suspend mode with USB 3.0 PHY disabled (L2)
■
Standby mode (L3)
■
Core power down mode (L4)
Document Number 001-52136 Rev. *H
EZ-USB FX3 supports four low power modes:
Page 9 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
The different low power modes are described in Table 6..
Table 6. Entry and Exit Methods for Low Power Modes
Low Power Mode
Suspend Mode with
USB 3.0 PHY
Enabled (L1)
Characteristics
■
The power consumption in this
mode does not exceed ISB1
■
USB 3.0 PHY is enabled and
is in U3 mode (one of the
suspend modes defined by
the USB3.0 specification).
This one block alone is operational with its internal clock
while all other clocks are shut
down
■
All I/Os maintain their previous
state
■
Power supply for the wakeup
source and core power must
be retained. All other power
domains can be turned on/off
individually
■
The states of the configuration
registers, buffer memory and
all internal RAM are
maintained
■
All transactions must be
completed before EZ-USB
FX3 enters Suspend mode
(state of outstanding transactions are not preserved)
■
The firmware resumes
operation from where it was
suspended (except when
woken up by RESET#
assertion) because the
program counter does not
reset
Document Number 001-52136 Rev. *H
Methods of Entry
■
■
Firmware executing on
ARM926EJ-S core can put EZ-USB
FX3 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put EZ-USB FX3 into suspend
mode
External Processor, through the
use of mailbox registers can put
EZ-USB FX3 into suspend mode
Methods of Exit
■
D+ transitioning to low or high
■
D- transitioning to low or high
■
Impedance change on OTG_ID pin
■
Resume condition on SSRX +/-
■
Detection of VBUS
■
Level detect on UART_CTS
(programmable polarity)
■
GPIF II interface assertion of
CTL[0]
■
Assertion of RESET#
Page 10 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 6. Entry and Exit Methods for Low Power Modes (continued)
Low Power Mode
Suspend Mode with
USB 3.0 PHY
Disabled (L2)
Characteristics
■
The power consumption in this
mode does not exceed ISB2
■
USB 3.0 PHY is disabled and
the USB interface is in
suspend mode
■
The clocks are shut off. The
PLLs are disabled
■
All I/Os maintain their previous
state
■
USB interface maintains the
previous state
■
Power supply for the wakeup
source and core power must
be retained. All other power
domains can be turned on/off
individually
■
The states of the configuration
registers, buffer memory and
all internal RAM are
maintained
■
All transactions must be
completed before EZ-USB
FX3 enters Suspend mode
(state of outstanding transactions are not preserved)
■
The firmware resumes
operation from where it was
suspended (except when
woken up by RESET#
assertion) because the
program counter does not
reset
Document Number 001-52136 Rev. *H
Methods of Entry
■
■
Firmware executing on
ARM926EJ-S core can put EZ-USB
FX3 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put EZ-USB FX3 into suspend
mode
External Processor, through the
use of mailbox registers can put
EZ-USB FX3 into suspend mode
Methods of Exit
■
D+ transitioning to low or high
■
D- transitioning to low or high
■
Impedance change on OTG_ID pin
■
Resume condition on SSRX +/-
■
Detection of VBUS
■
Level detect on UART_CTS
(programmable polarity)
■
GPIF II interface assertion of
CTL[0]
■
Assertion of RESET#
Page 11 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 6. Entry and Exit Methods for Low Power Modes (continued)
Low Power Mode
Standby Mode (L3)
Core Power Down
Mode (L4)
Characteristics
■
The power consumption in this
mode does not exceed ISB3
■
All configuration register
settings and program/data
RAM contents are preserved.
However, data in the buffers or
other parts of the data path, if
any, is not guaranteed.
Therefore, the external
processor should take care
that needed data is read
before putting EZ-USB FX3
into this Standby Mode
■
The program counter is reset
on waking up from Standby
mode
■
GPIO pins maintain their
configuration
■
Crystal oscillator is turned off
■
Internal PLL is turned off
■
USB transceiver is turned off
■
ARM926EJ-S core is powered
down. Upon wakeup, the core
re-starts and runs the program
stored in the program/data
RAM
■
Power supply for the wakeup
source and core power must
be retained. All other power
domains can be turned on/off
individually
■
The power consumption in this
mode does not exceed ISB4
■
Core power is turned off
■
All buffer memory, configuration registers and the
program RAM do not maintain
state. It is necessary to reload
the firmware on exiting from
this mode
■
In this mode, all other power
domains can be turned on/off
individually
Document Number 001-52136 Rev. *H
Methods of Entry
■
■
Firmware executing on
ARM926EJ-S core or external
processor configures the appropriate register
Turn off VDD
Methods of Exit
■
Detection of VBUS
■
Level detect on UART_CTS
(Programmable Polarity)
■
GPIF II interface assertion of
CTL[0]
■
Assertion of RESET#
■
Reapply VDD
■
Assertion of RESET#
Page 12 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Configuration Options
EMI
Configuration options are available for specific usage models.
Contact Cypress Applications/Marketing for details.
EZ-USB FX3 meets EMI requirements outlined by FCC 15B
(USA) and EN55022 (Europe) for consumer electronics.
EZ-USB FX3 can tolerate reasonable EMI conducted by
aggressor outlined by these specifications and continue to
function as expected.
Digital I/Os
EZ-USB FX3 provides firmware controlled pull up or pull down
resistors internally on all digital I/O pins. The pins can be pulled
high through an internal 50 kΩ resistor or can be pulled low
through an internal 10 kΩ resistor to prevent the pins from
floating. The I/O pins may have the following states:
■
Tristated (High-Z)
■
Weak Pull up (via internal 50 kΩ)
■
Pull down (via internal 10 kΩ)
■
Hold (I/O hold its value) when in low power modes
■
The JTAG signals TDI, TMC, TRST# signals have fixed 50 kΩ
internal pull-ups & the TCK signal has a fixed 10 kΩ pull down
resistor.
GPIOs
EZ-USB allows for a flexible pin configuration both on the GPIF
II and the serial peripheral interfaces. Any unused control pins
on the GPIF II interface may be used as GPIOs. Similarly, any
unused pins on the serial peripheral interfaces may be
configured as GPIOs. Please refer to the Pin List for pin configuration options.
System Level ESD
EZ-USB FX3 has built-in ESD protection on the D+, D-, GND
pins on the USB interface. The ESD protection levels provided
on these ports are:
■
± 2.2 KV Human Body Model (HBM) based on JESD22-A114
Specification
■
± 6 KV Contact Discharge and ± 8 KV Air Gap Discharge based
on IEC61000-4-2 level 3A
■
± 8 KV Contact Discharge and ± 15 KV Air Gap Discharge
based on IEC61000-4-2 level 4C.
This protection ensures the device will continue to function after
ESD events up to the levels stated.
The SSRX+, SSRX-, SSTX+, SSTX- pins only have up to +/2.2KV Human Body Model (HBM) internal ESD protection.
All GPIF II and GPIO pins support an external load of up to 16pF
per pin.
Document Number 001-52136 Rev. *H
Page 13 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Absolute Maximum Ratings
Contact discharge, ± 8 KV air gap discharge based on
IEC61000-4-2 level 3A and ± 8 KV contact discharge, ± 15 KV
air gap discharge based on IEC61000-4-2 level 4C
Exceeding maximum ratings may shorten the useful life of the
device.
Latch up current...........................................................> 200 mA
Storage temperature............................... ...... –65 °C to +150 °C
Maximum output short circuit current
Ambient temperature with
power supplied (Industrial).................... ... ...... –40 °C to +85 °C
for all I/O configurations. (Vout = 0V)[1].................... .. –100 mA
Supply voltage to ground potential
VDD, AVDDQ ....................................................................... TBD
Operating Conditions
TA (ambient temperature under bias)
VIO1,VIO2, VIO3, VIO4, VIO5.......................................... ...TBD
Industrial....................................................... .. –40 °C to +85 °C
U3TXVDDQ, U3RXVDDQ......................................... ..... .....TBD
DC input voltage to any input pin........................................ .TBD
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
DC voltage applied to
outputs in high Z state.................... ..................................... TBD
VBATT supply voltage.......................... ....................3.2 V to 6 V
Supply voltage................................................ ...1.15 V to 1.25 V
VIO1, VIO2, VIO3, VIO4, CVDDQ
Static discharge voltage
ESD protection levels............................................................
Supply voltage.................................................... ...1.7 V to 3.6 V
± 2.2 KV human body model (HBM) based on JESD22-A114
VIO5 supply voltage...................... .................... 1.15 V to 3.6 V
Additional ESD protection levels on D+, D-,
GND pins and serial Peripherals pins................. ........... ± 6 KV
Table 7. DC Specifications
Parameter
Description
Min
Max
Units
Notes
VDD
Core voltage supply
1.15
1.25
V
1.2 V typical
AVDD
Analog voltage supply
1.15
1.25
V
1.2 V typical
VIO1
GPIF II I/O power supply domain
1.7
3.6
V
1.8, 2.5 and 3.3 V typical
VIO2
IO2 power supply domain
1.7
3.6
V
1.8, 2.5 and 3.3 V typical
VIO3
IO3 power supply domain
1.7
3.6
V
1.8, 2.5 and 3.3 V typical
VIO4
UART/SPI/I2S power supply domain
1.7
3.6
V
1.8, 2.5 and 3.3 V typical
VBATT
USB voltage supply
3.2
6
V
3.7 V typical
VBUS
USB voltage supply
4.1
6
V
5 V typical
U3TXVDDQ
USB3.0 1.2-V supply
1.15
1.25
V
1.2 V typical
U3RXVDDQ
USB3.0 1.2-V supply
1.15
1.25
V
1.2 V typical
CVDDQ
Clock voltage supply
1.7
3.6
V
1.8,3.3 V typical
VIO5
I2C and JTAG voltage supply
1.15
3.6
V
1.2,1.8, 2.5 and 3.3 V typical
VIH1
Input HIGH voltage 1
0.625 × VCC
VCC + 0.3
V
For 2.0V ≤ VCC ≤ 3.6 V
(except USB port)
VIH2
Input HIGH voltage 2
VCC – 0.4
VCC + 0.3
V
For 1.7 V ≤ VCC ≤ 2.0 V
(except USB port)
VIL
Input LOW voltage
VOH
Output HIGH voltage
VOL
IIX
IOZ
–0.3
0.25 × VCC
V
0.9 × VCC
–
V
IOH (max)= –100 µA
Output LOW voltage
–
0.1 × VCC
V
IOL(min) = +100 µA
Input leakage current
–1
1
µA
All I/O signals held at VDDQ
(For I/Os that have a
pull-up/down resistor
connected, the leakage
current increases by
VDDQ/Rpu or VDDQ/RPD
Output High-Z leakage current
–1
1
µA
All I/O signals held at VDDQ
Document Number 001-52136 Rev. *H
Page 14 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 7. DC Specifications (continued)
Min
Max
Units
ICC Core
Parameter
Core and analog voltage operating
current
Description
–
200
mA
ICC USB
USB voltage supply operating current
–
60
mA
ISB1
Total suspend current during suspend
mode with USB 3.0 PHY enabled (L1)
–
–
mA
Core Current: 1.5 mA
IO Current: 20 uA
USB Current: 2 mA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
ISB2
Total suspend current during suspend
mode with USB 3.0 PHY disabled (L2)
–
–
mA
Core Current: 250 uA
IO Current: 20 uA
USB Current: 1.2 mA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
ISB3
Total standby current during standby
mode (L3)
–
–
µA
Core Current: 60 uA
IO Current: 20 uA
USB Current: 40 uA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
ISB4
Total standby current during core
power-down mode (L4)
–
–
µA
Core Current: 0 uA
IO Current: 20 uA
USB Current: 40 uA
for Typical PVT (Typical
silicon, all power supplies at
their respective nominal levels
at 25°C.)
VRAMP
Voltage ramp rate on core and I/O
supplies
0.2
50
V/ms
VN
Noise level permitted on VDD and I/O
supplies
–
100
mV
Max p-p noise level permitted
on all supplies except AVDD
VN_AVDD
Noise level permitted on AVDD supply
–
20
mV
Max p-p noise level permitted
on AVDD
Document Number 001-52136 Rev. *H
Notes
Total current through AVDD,
VDD
Voltage ramp must be
monotonic
Page 15 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
AC Timing Parameters
GPIF II Timing
Figure 7. GPIF II Timing in Synchronous Mode
tC LK H tC LKL
C LK
tC LK
tLZ
- [31:0]
DQ
tD S
tH Z
tD O H
tLZ
tD O H
D ata 2
( O U T)
D ata 1
( O U T)
D ata ( IN)
tS
tC O
tC O E
tD H
tH
C TL(IN)
tC TLO
tC O H
C TL ( O U T)
Table 8. GPIF II Timing Parameters in Synchronous Mode[3]
Parameter
Description
Min
Max
Unit
Frequency
Interface clock frequency
–
100
MHz
tCLK
Interface clock period
10
–
ns
tCLKH
Clock high time
4
–
ns
tCLKL
Clock low time
4
–
ns
tS
CTL input to clock setup time
(Sync speed =1)
2
–
ns
tH
CTL input to clock hold time
(Sync speed =1)
0.5
–
ns
tDS
Data in to clock setup time
(Sync speed =1)
2
–
ns
tDH
Data in to clock hold time
(Sync speed =1)
0.5
–
ns
tCO
Clock to data out propagation delay when DQ bus is already in
output direction(Sync speed =1)
–
8
ns
tCOE
Clock to data out propagation delay when DQ lines change to
output from tristate and valid data is available on the DQ bus
(Sync speed =1)
-
9
tCTLO
Clock to CTL out propagation delay (Sync speed =1)
–
8
tDOH
Clock to data out hold
2
–
ns
tCOH
Clock to CTL out hold
0
–
ns
ns
tHZ
Clock to High-Z
–
8
ns
tLZ
Clock to Low-Z (Sync speed =1)
0
–
ns
tS_ss0
CTL input/data input to clock setup time (Sync speed = 0)
5
–
ns
tH_ss0
CTL input/data input to clock hold time (Sync speed = 0)
2.5
–
ns
tCO_ss0
Clock to data out / CTL out
propagation delay (sync speed = 0)
–
15
ns
tLZ_ss0
Clock to low-Z (sync speed = 0)
2
–
ns
Note
3. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 16 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Figure 8. GPIF II Timing in Asynchronous Mode
tDS/ tAS
tDH/tAH
DATA IN
DATA/ ADDR
tCHZ
tCTLassert_DQlatch
CTL#
(I/P , ALE/ DLE)
tCTLdeassert_DQlatch
tAA/tDO
tCHZ/tOEHZ
tCLZ/ tOELZ
DATA OUT
DATA OUT
CTL#
(I/P, non ALE/ DLE
tCTLdeassert
tCTLassert
tCTLalpha
ALPHA
O/P
tCTLbeta
BETA
O/P
tCTLassert + n * tGRANULARITY
1
tCTLdeassert + n * tGRANULARITY
1
tCTL#
(O/P)
1. n is an integer >= 0
tDST
tDHT
DATA/
ADDR
tCTLdeassert_DQassert
tCTLassert_DQassert
CTL#
I/P (non DLE/ALE)
Figure 9. GPIF II Timing in Asynchronous DDR Mode
tDS
CTL#
(I/P)
tCTLdeassert_DqlatchDDR
tCTLassert_DQlatchDDR
tDS
tDH
tDH
DATA IN
Document Number 001-52136 Rev. *H
Page 17 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 9. GPIF II Timing in Asynchronous Mode[4]
Note The following parameters assume one state transition
Parameter
Description
Min
Max
Units
tDS
Data In to DLE setup time. Valid in DDR async
also.
2.3
–
ns
tDH
Data In to DLE hold time. Valid in DDR async
mode.
2
–
ns
tAS
Address In to ALE setup time
2.3
–
ns
tAH
Address In to ALE hold time
2
–
ns
tCTLassert
CTL I/O asserted width for CTRL inputs without
DQ input association and for outputs.
7
–
ns
tCTLdeassert
CTL I/O deasserted width for CTRL inputs
without DQ input association and for outputs.
7
–
ns
tCTLassert_DQassert
CTL asserted pulse width for CTL inputs that
signify DQ inputs valid at the asserting edge but
do not employ in-built latches (ALE/DLE) for
those DQ inputs.
20
–
ns
tCTLdeassert_DQassert
CTL deasserted pulse width for CTL inputs that
signify DQ input valid at the asserting edge but
do not employ in-built latches (ALE/DLE) for
those DQ inputs.
7
–
ns
tCTLassert_DQdeassert
CTL asserted pulse width for CTL inputs that
signify DQ inputs valid at the de-asserting edge
but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
7
–
ns
tCTLdeassert_DQdeassert
CTL deasserted pulse width for CTL inputs that
signify DQ inputs valid at the deasserting edge
but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
20
–
ns
tCTLassert_DQlatch
CTL asserted pulse width for CTL inputs that
employ in-built latches (ALE/DLE) to latch the
DQ inputs. In this non_DDR case, in-built
latches always close at the de-asserting edge.
7
–
ns
tCTLdeassert_DQlatch
CTL deasserted pulse width for CTL inputs that
employ in-built latches (ALE/DLE) to latch the
DQ inputs. In this non-DDR case, in-built
latches always close at the de-asserting edge.
10
–
ns
tCTLassert_DQlatchDDR
CTL asserted pulse width for CTL inputs that
employ in-built latches (DLE) to latch the DQ
inputs in DDR mode.
10
–
ns
tCTLdeassert_DQlatchDDR
CTL deasserted pulse width for CTL inputs that
employ in-built latches (DLE) to latch the DQ
inputs in DDR mode.
10
–
ns
tGRANULARITY
Granularity of tCTLassert/tCTLdeassert for all
outputs
5
–
ns
tAA
DQ/CTL input to DQ output time when DQ
change or CTL change needs to be detected
and affects internal updates of input and output
DQ lines.
–
30
ns
tDO
CTL to data out when the CTL change merely
enables the output flop update whose data was
already established.
–
25
ns
Notes
At 200 MHz internal
clock
Note
4. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 18 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 9. GPIF II Timing in Asynchronous Mode[4] (continued)
Note The following parameters assume one state transition
Parameter
Description
Min
Max
Units
tOELZ
CTL designated as OE to low-Z. Time when
external devices should stop driving data.
0
–
ns
tOEHZ
CTL designated as OE to High-Z
8
8
ns
tCLZ
CTL (non OE) to Low-Z. Time when external
devices should stop driving data.
0
–
ns
tCHZ
CTL (non OE) to High-Z
30
30
ns
tCTLalpha
CTL to alpha change at output
–
25
ns
tCTLbeta
CTL to Beta change at output
–
30
ns
tDST
Addr/data setup when DLE/ALE not used
2
–
ns
tDHT
Addr/data hold when DLE/ALE not used
20
–
ns
Notes
Slave FIFO Interface
Synchronous Slave FIFO Timing
Figure 10. Synchronous Slave FIFO Read Mode
Synchronous Read Cycle Timing
tCYC
PCLK
tCH
tCL
3 cycle latency
from addr to data
SLCS
tAS tAH
FIFO ADDR
An
Am
tRDS tRDH
SLRD
SLOE
FLAGA
(Dedicated thread Flag for An)
(1 = Not Empty 0= Empty)
FLAGB
(Dedicated thread Flag for Am)
(1 = Not Empty 0= Empty)
tOELZ
Data Out
High-Z
tOEZ
Data
driven:DN(An)
tOELZ
tCDH
DN+1(An)
tOEZ
tCO
DN(Am)
DN+1(Am) DN+2(Am)
SLWR (HIGH)
Document Number 001-52136 Rev. *H
Page 19 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Synchronous Slave FIFO sequence description:
The same sequence of events is shown for a burst read.
1. FIFO address is stable and SLCS is asserted
2. SLOE is asserted. SLOE is an output enable only, whose sole
function is to drive the data bus.
3. SLRD is asserted
4. The FIFO pointer is updated on the rising edge of the PCLK,
while the SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tco (measured from the rising edge of
PCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
must also be asserted.
Note For burst mode, the SLRD# and SLOE# are left asserted
during the entire duration of the read. When SLOE# is asserted,
the data bus is driven (with data from the previously addressed
FIFO). For each subsequent rising edge of PCLK, while the
SLRD# is asserted, the FIFO pointer is incremented and the next
data value is placed on the data bus.
Document Number 001-52136 Rev. *H
Page 20 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Figure 11. Synchronous Slave FIFO Write Mode
Synchronous Write Cycle Timing
tCYC
PCLK
tCH
tCL
SLCS
tAS tAH
Am
An
FIFO ADDR
tWRS
tWRH
SLWR
tCFLG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
tCFLG
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
Data IN
tDS tDH
High-Z
tDS tDH
tDH
DN+1(Am) DN+2(Am)
DN(Am)
DN(An)
tPES tPEH
PKTEND
SLOE
(HIGH)
Synchronous ZLP Write Cycle Timing
tCYC
PCLK
tCH
tCL
SLCS
tAS tAH
An
FIFO ADDR
SLWR
(HIGH)
tPES tPEH
PKTEND
tCFLG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
Data IN
High-Z
SLOE
(HIGH)
Document Number 001-52136 Rev. *H
Page 21 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Synchronous Slave FIFO Write Sequence Description
■
FIFO address is stable and the signal SLCS# is asserted
■
External master/peripheral outputs the data onto the data bus
■
SLWR# is asserted
■
While the SLWR# is asserted, data is written to the FIFO and
on the rising edge of gthe PCLK, the FIFO pointer is incremented
■
The FIFO flog is updated after a delay of t WFLG from the rising
edge of the clock
The same sequence of events is also shown for burst write
Note: Forthe burst mode, SLWR# and SLCS# are left asserted
for the entire duration of writing all the required data values. In
this burst write mode, after the SLWR# is asserted, the data on
the FIFO data bus is written to the FIFO on every rising edge of
PCLK. The FIFO pointer is updated on each rising edge of PCLK.
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device/processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines have to be held constant during the PKTEND#
assertion.
Zero Length Packet: The external device/processor can signal a
Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in the above timing diagram.
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are outputs from
EZ-USB FX3 that may be configured to show empty/full/partial
status for a dedicated thread or the current thread being
addressed.
Table 10. Synchronous Slave FIFO Parameters[5]
Parameter
Description
Min
Max
Units
FREQ
Interface clock frequency
–
100
MHz
tCYC
Clock period
10
–
ns
tCH
Clock high time
4
–
ns
tCL
Clock low time
4
–
ns
tRDS
SLRD# to CLK setup time
2
–
ns
tRDH
SLRD# to CLK hold time
0.5
–
ns
tWRS
SLWR# to CLK setup time
2
–
ns
tWRH
SLWR# to CLK hold time
0.5
–
ns
tCO
Clock to valid data
–
8
ns
tDS
Data input setup time
2
–
ns
tDH
CLK to data input hold
0.5
–
ns
tAS
Address to CLK setup time
2
–
ns
tAH
CLK to address hold time
tOELZ
SLOE# to data low-Z
tCFLG
CLK to flag output propagation delay
–
8
ns
tOEZ
SLOE# deassert to Data Hi Z
–
8
ns
ns
0.5
–
ns
0
–
ns
tPES
PKTEND# to CLK setup
2
–
tPEH
CLK to PKTEND# hold
0.5
–
tCDH
CLK to data output hold
2
–
ns
Note Three-cycle latency from ADDR to DATA/FLAGS
.
Note
5. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 22 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Asynchronous Slave FIFO Timing
Figure 12. Asynchronous Slave FIFO Read Mode
SLCS
tAS
tAH
An
FIFO ADDR
tRDl
Am
tRDh
SLRD
SLOE
tFLG
tRFLG
FLAGA
dedicated thread Flag for An
(1=Not empty 0 = Empty)
FLAGB
dedicated thread Flag for Am
(1=Not empty 0 = Empty)
tOE
tRDO
tOH
tOE
tRDO
tRDO
tOH
tLZ
Data Out
High-Z
DN(An)
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
SLWR
(HIGH)
Asynchronous Slave FIFO Read Sequence
Description
■
FIFO address is stable and the SLCS# signal is asserted.
In the above diagram , data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read cycle
SLOE# must be in an asserted state. SLRD# and SLOE# can
also be tied together.
■
SLOE# is asserted. This results in the data bus being driven.
The same sequence of events is also shown for a burst read.
■
SLRD # is asserted.
■
Data from the FIFO is driven on assertion of SLRD#. This data
is valid after a propagation delay of tRDO from the falling edge
of SLRD#.
Note: In burst read mode, during SLOE# assertion, the data bus
is in a driven state (data driven is from previously addressed
FIFO). On assertion of SLRD# data from the FIFO is driven on
the data bus (SLOE# must also be asserted) and the FIFO
pointer is incremented on de-assertion of SLRD#.
■
FIFO pointer is incremented on de-assertion of SLRD#
Document Number 001-52136 Rev. *H
Page 23 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Figure 13. Asynchronous Slave FIFO Write Mode
SLCS
tAS
tAH
An
FIFO ADDR
tWRl
Am
tWRh
SLWR
tFLG
tWFLG
FLAGA
dedicated thread Flag for An
(1=Not Full 0 = Full)
tWFLG
FLAGB
dedicated thread Flag for Am
(1=Not Full 0 = Full)
tWR
S
High-Z
DATA In
tWRH
tWR
S
tWRH
DN(Am)
DN(An)
DN+1(Am)
DN+2(Am)
tWRPEt
PEh
PKTEND
SLOE
(HIGH)
Change tWRPE definition to SLWR# de-assert to PKTEND de-assert = 0ns min (This means that PKTEND should not be be deasserted before SLWR#)
Note: PKTEND must be asserted at the same time as SLWR#.
Asynchronous ZLP Write Cycle Timing
SLCS
tAS
tAH
An
FIFO ADDR
SLWR
(HIGH)
tPEl tPEh
PKTEND
tWFLG
FLAGA
dedicated thread Flag for An
(1=Not Full 0 = Full)
FLAGB
dedicated thread Flag for Am
(1=Not Full 0 = Full)
DATA In
High-Z
SLOE
(HIGH)
Document Number 001-52136 Rev. *H
Page 24 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Asynchronous Slave FIFO Write Sequence
Description
■
FIFO address is driven and SLCS# is asserted
■
SLWR# is asserted. SLCS# must be asserted with SLWR# or
before SLWR# is asserted
■
Data must be present on the bus tWRS before the deasserting
edge of SLWR#
■
De-assertion of SLWR# causes the data to be written from the
data bus to the FIFO and then FIFO pointer is incremented
■
The FIFO flag is updated after the tWFLG from the de-asserting
edge of SLWR.
The same sequence of events is shown for a burst write.
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device/processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines have to be held constant during the PKTEND#
assertion.
Zero Length Packet: The external device/processor can signal a
Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in the above timing diagram.
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are outputs from
EZ-USB FX3 that may be configured to show empty/full/partial
status for a dedicated address or the current address.
Note that in the burst write mode, on SLWR# de-assertion, the
data is written to the FIFO and then the FIFO pointer is incremented.
Table 11. Asynchronous Slave FIFO Parameters[6]
Parameter
Description
Min
Max
Units
tRDI
SLRD# low
20
–
ns
tRDh
SLRD# high
10
–
ns
tAS
Address to SLRD#/SLWR# setup time
7
–
ns
tAH
SLRD#/SLWR#/PKTEND to address hold time
2
–
ns
tRFLG
SLRD# to FLAGS output propagation delay
–
35
ns
tFLG
ADDR to FLAGS output propagation delay
tRDO
SLRD# to data valid
–
25
ns
tOE
OE# low to data valid
–
25
ns
tLZ
OE# low to data low-Z
0
–
ns
tOH
SLOE# deassert data output hhold
–
22.5
ns
tWRI
SLWR# low
20
–
ns
tWRh
SLWR# high
10
–
ns
tWRS
Data to SLWR# setup time
7
–
ns
tWRH
SLWR# to Data Hold time
2
–
ns
tWFLG
SLWR#/PKTEND to Flags output propagation delay
–
35
ns
tPEI
PKTEND low
7.5
–
ns
tPEh
PKTEND high
7.5
–
ns
tWRPE
SLWR# deassert to PKTEND deassert
0
–
22.5
Note
6. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 25 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Serial Peripherals Timing
I2C Timing
Figure 14. I2C Timing Definition
Document Number 001-52136 Rev. *H
Page 26 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 12. I2C Timing Parameters[7]
Parameter
Description
I2C Standard Mode Parameters
fSCL
SCL clock frequency
tHD:STA
Hold time START condition
tLOW
LOW period of the SCL
tHIGH
HIGH period of the SCL
tSU:STA
Setup time for a repeated START condition
tHD:DAT
Data hold time
tSU:DAT
Data setup time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU:STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
tVD:DAT
Data valid time
tVD:ACK
Data valid ACK
tSP
Pulse width of spikes that must be suppressed by input filter
I2C Fast Mode Parameters
fSCL
SCL clock frequency
tHD:STA
Hold time START condition
tLOW
LOW period of the SCL
tHIGH
HIGH period of the SCL
tSU:STA
Setup time for a repeated START condition
tHD:DAT
Data hold time
tSU:DAT
Data setup time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU:STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
tVD:DAT
Data valid time
tVD:ACK
Data valid ACK
tSP
Pulse width of spikes that must be suppressed by input filter
I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2V)
fSCL
SCL clock frequency
tHD:STA
Hold time START condition
tLOW
LOW period of the SCL
tHIGH
HIGH period of the SCL
tSU:STA
Setup time for a repeated START condition
tHD:DAT
Data hold time
tSU:DAT
Data setup time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU:STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
tVD:DAT
Data valid time
tVD:ACK
Data valid ACK
tSP
Pulse width of spikes that must be suppressed by input filter
Min
Max
Units
0
4
4.7
4
4.7
0
250
–
–
4
4.7
–
–
n/a
100
–
–
–
–
–
–
1000
300
–
–
3.45
3.45
n/a
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
0
0.6
1.3
0.6
0.6
0
100
–
–
0.6
1.3
–
–
0
400
–
–
–
–
–
–
300
300
–
–
0.9
0.9
50
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
0
0.26
0.5
0.26
0.26
0
50
–
–
0.26
0.5
–
–
0
1000
–
–
–
–
–
–
120
120
–
–
0.45
0.45
50
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
Notes
Note
7. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 27 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
I2S Timing Diagram
Figure 15. I2S Transmit Cycle
Table 13. I2S Timing Parameters[8]
Parameter
Description
Min
Max
Units
Ttr
–
ns
tT
I2S transmitter clock cycle
tTL
I 2S
transmitter cycle LOW period
0.35 Ttr
–
ns
tTH
I2S transmitter cycle HIGH period
0.35 Ttr
–
ns
tTR
I2S transmitter rise time
–
0.15 Ttr
ns
tTF
I2S transmitter fall time
–
0.15 Ttr
ns
tThd
I 2S
0
–
ns
tTd
I2S transmitter delay time
–
0.3tT
ns
transmitter data hold time
Note tT is selectable through clock gears. Max Ttr is designed for 96 kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
8. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *H
Page 28 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
SPI Timing Specification
Figure 16. SPI Timing
SSN
(output)
tlead
SCK
(CPOL=0,
Output)
tsdi
MISO
(input)
twsck
tdis
thoi
MSB
LSB
td
tsdd
tdi
v
MOSI
(output)
tlag
trf
twsck
SCK
(CPOL=1,
Output)
tssnh
tsck
LSB
MSB
SPI Master Timing for CPHA = 0
SSN
(output)
SCK
(CPOL=0,
Output)
tssnh
tsck
tlead
twsck
trf
tlag
twsck
SCK
(CPOL=1,
Output)
tsdi
MISO
(input)
LSB
MSB
tdi
tdv
MOSI
(output)
tdis
thoi
LSB
MSB
SPI Master Timing for CPHA = 1
Document Number 001-52136 Rev. *H
Page 29 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 14. SPI Timing Parameters[9]
Parameter
Description
Min
Max
Units
fop
Operating frequency
0
33
MHz
tsck
Cycle time
30
–
ns
twsck
Clock high/low time
13.5
–
ns
tlead
SSN-SCK lead time
1/2 tsck[10]-5
1.5tsck[10]+ 5
ns
tlag
Enable lag time
0.5
1.5 tsck[10]+5
ns
trf
Rise/fall time
–
8
ns
tsdd
Output SSN to valid data delay time
–
5
ns
tdv
Output data valid time
–
5
ns
tdi
Output data invalid
0
–
ns
tssnh
Minimum SSN high time
10
–
ns
tsdi
Data setup time input
8
–
ns
thoi
Data hold time input
0
–
ns
tdis
Disable data output on SSN high
0
–
ns
Conditions
Min (ms)
Max (ms)
Clock Input
1
–
Reset Sequence
The hard reset sequence requirements for EZ-USB FX3 are specified here.
Table 15. Reset and Standby Timing Parameters
Parameter
Definition
tRPW
Minimum RESET# pulse width
Crystal Input
5
–
tRH
Minimum high on RESET#
–
5
–
tRR
Reset recovery time (after which Boot loader begins
firmware download)
–
1
–
tSBY
Time to enter standby/suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
–
–
1
tWU
Time to wakeup from standby
tWH
Minimum time before Standby/Suspend source may
be reasserted
Clock Input
1
–
Crystal Input
5
–
–
5
–
Notes
9. All parameters guaranteed by design and validated through characterization.
10. Depends on LAG and LEAD setting in SPI_CONFIG register.
Document Number 001-52136 Rev. *H
Page 30 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Figure 17. Reset Sequence
VDD
( core )
xVDDQ
XTALIN/
CLKIN
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
Mandatory
Reset Pulse
tRh
tRR
Hard Reset
RESET #
tWH
tRPW
tWU
tSBY
Standby/
Suspend
Source
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Standby/Suspend
source Is deasserted
Ball Map
Figure 18. Ball Map for EZ-USB FX3 (Top View)
A
1
2
3
4
5
6
7
8
9
10
11
U3VSSQ
U3RXVDDQ
SSRXM
SSRXP
SSTXP
SSTXM
AV DD
VSS
DP
DM
NC
TRST#
B
VIO4
FSLC[0]
R_USB3
FSLC[1]
U3TXVDDQ
CVDDQ
AV SS
V SS
VSS
V DD
C
GPIO[54]
GPIO[55]
VDD
GPIO[57]
RESET#
XTALIN
XTALOUT
R_USB2
OTG_ID
TDO
D
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
GPIO[56]
CLKIN_32
CLKIN
VSS
I2C_GPIO[58] I2C_GPIO[59]
VIO5
O[60]
E
GPIO[47]
VSS
VIO3
GPIO[49]
GPIO[48]
FSLC[2]
TDI
TMS
VDD
V BATT
V BUS
F
VIO2
GPIO[45]
GPIO[44]
GPIO[41]
GPIO[46]
TCK
GPIO[2]
GPIO[5]
GPIO[1]
GPIO[0]
VDD
G
VSS
GPIO[42]
GPIO[43]
GPIO[30]
GPIO[25]
GPIO[22]
GPIO[21]
GPIO[15]
GPIO[4]
GPIO[3]
VSS
H
VDD
GPIO[39]
GPIO[40]
GPIO[31]
GPIO[29]
GPIO[26]
GPIO[20]
GPIO[24]
GPIO[7]
GPIO[6]
VIO1
J
GPIO[38]
GPIO[36]
GPIO[37]
GPIO[34]
GPIO[28]
GPIO[16]
GPIO[19]
GPIO[14]
GPIO[9]
GPIO[8]
VDD
K
GPIO[35]
GPIO[33]
VSS
VSS
GPIO[27]
GPIO[23]
GPIO[18]
GPIO[17]
GPIO[13]
GPIO[12]
GPIO[10]
L
VSS
VSS
VSS
GPIO[32]
VDD
VSS
VDD
INT#
VIO1
GPIO[11]
VSS
Document Number 001-52136 Rev. *H
Page 31 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Pin Description
Table 16. Pin List
Pin
I/O
Name
Description
GPIFII (VIO1 Power Domain)
GPIF™II Interface
Slave FIFO Interface
F10
VIO1
I/O
GPIO[0]
DQ[0]
DQ[0]
F9
VIO1
I/O
GPIO[1]
DQ[1]
DQ[1]
F7
VIO1
I/O
GPIO[2]
DQ[2]
DQ[2]
DQ[3]
G10
VIO1
I/O
GPIO[3]
DQ[3]
G9
VIO1
I/O
GPIO[4]
DQ[4]
DQ[4]
F8
VIO1
I/O
GPIO[5]
DQ[5]
DQ[5]
H10
VIO1
I/O
GPIO[6]
DQ[6]
DQ[6]
H9
VIO1
I/O
GPIO[7]
DQ[7]
DQ[7]
J10
VIO1
I/O
GPIO[8]
DQ[8]
DQ[8]
J9
VIO1
I/O
GPIO[9]
DQ[9]
DQ[9]
K11
VIO1
I/O
GPIO[10]
DQ[10]
DQ[10]
L10
VIO1
I/O
GPIO[11]
DQ[11]
DQ[11]
K10
VIO1
I/O
GPIO[12]
DQ[12]
DQ[12]
K9
VIO1
I/O
GPIO[13]
DQ[13]
DQ[13]
J8
VIO1
I/O
GPIO[14]
DQ[14]
DQ[14]
DQ[15]
G8
VIO1
I/O
GPIO[15]
DQ[15]
J6
VIO1
I/O
GPIO[16]
PCLK
CLK
K8
VIO1
I/O
GPIO[17]
CTL[0]
SLCS#
K7
VIO1
I/O
GPIO[18]
CTL[1]
SLWR#
SLOE#
J7
VIO1
I/O
GPIO[19]
CTL[2]
H7
VIO1
I/O
GPIO[20]
CTL[3]
SLRD#
G7
VIO1
I/O
GPIO[21]
CTL[4]
FLAGA
G6
VIO1
I/O
GPIO[22]
CTL[5]
FLAGB
K6
VIO1
I/O
GPIO[23]
CTL[6]
GPIO
H8
VIO1
I/O
GPIO[24]
CTL[7]
PKTEND#
G5
VIO1
I/O
GPIO[25]
CTL[8]
GPIO
H6
VIO1
I/O
GPIO[26]
CTL[9]
GPIO
K5
VIO1
I/O
GPIO[27]
CTL[10]
GPIO
J5
VIO1
I/O
GPIO[28]
CTL[11]
A1
H5
VIO1
I/O
GPIO[29]
CTL[12]
A0
G4
VIO1
I/O
GPIO[30]
PMODE[0]
PMODE[0]
H4
VIO1
I/O
GPIO[31]
PMODE[1]
PMODE[1]
L4
VIO1
I/O
GPIO[32]
PMODE[2]
PMODE[2]
L8
VIO1
I/O
INT#
INT#/CTL[15]
CTL[15]
C5
CVDDQ
I
RESET#
RESET#
RESET#
IO2 (VIO2 Power Domain)
GPIF II (32-bit data mode)
K2
VIO2
I/O
GPIO[33]
DQ[16]
GPIO
GPIO
J4
VIO2
I/O
GPIO[34]
DQ[17]
K1
VIO2
I/O
GPIO[35]
DQ[18]
GPIO
J2
VIO2
I/O
GPIO[36]
DQ[19]
GPIO
J3
VIO2
I/O
GPIO[37]
DQ[20]
GPIO
Document Number 001-52136 Rev. *H
Page 32 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 16. Pin List (continued)
I/O
Name
J1
Pin
VIO2
I/O
GPIO[38]
DQ[21]
GPIO
H2
VIO2
I/O
GPIO[39]
DQ[22]
GPIO
H3
VIO2
I/O
GPIO[40]
DQ[23]
GPIO
F4
VIO2
I/O
GPIO[41]
DQ[24]
GPIO
G2
VIO2
I/O
GPIO[42]
DQ[25]
GPIO
G3
VIO2
I/O
GPIO[43]
DQ[26]
GPIO
DQ[27]
F3
VIO2
I/O
GPIO[44]
F2
VIO2
I/O
GPIO[45]
Description
GPIO
GPIO
IO3 (VIO3 Power Domain)
F5
VIO3
I/O
GPIO[46]
GPIO
GPIO
GPIF II - 32
(FX3)+UART+I2S
GPIO+I2S
UART+SPI+
I2S
DQ[28]
GPIO
UART_RTS
UART_CTS
GPIO
E1
VIO3
I/O
GPIO[47]
GPIO
GPIO
GPIO
DQ[29]
GPIO
E5
VIO3
I/O
GPIO[48]
GPIO
GPIO
GPIO
DQ[30]
GPIO
UART_TX
E4
VIO3
I/O
GPIO[49]
GPIO
GPIO
GPIO
DQ[31]
GPIO
UART_RX
D1
VIO3
I/O
GPIO[50]
GPIO
GPIO
GPIO
I2S_CLK
GPIO
I2S_CLK
D2
VIO3
I/O
GPIO[51]
GPIO
GPIO
GPIO
I2S_SD
GPIO
I2S_SD
D3
VIO3
I/O
GPIO[52]
GPIO
GPIO
GPIO
I2S_WS
GPIO
I2S_WS
D4
VIO4
I/O
GPIO[53]
SPI_SCK
UART_RTS
GPIO
UART_RTS
GPIO
SPI_SCK
C1
VIO4
I/O
GPIO[54]
SPI_SSN
UART_CTS
GPIO
UART_CTS
I2S_CLK
SPI_SSN
C2
VIO4
I/O
GPIO[55]
SPI_MISO
UART_TX
GPIO
UART_TX
I2S_SD
SPI_MISO
IO4 (VIO4) Power Domain
D5
VIO4
I/O
GPIO[56]
SPI_MOSI
UART_RX
GPIO
UART_RX
I2S_WS
SPI_MOSI
C4
VIO4
I/O
GPIO[57]
GPIO
GPIO
GPIO
I2S_MCLK
I2S_MCLK
I2S_MCLK
C9
VBUS/
VBATT
I
OTG_ID
A3
U3RXVDDQ
I
SSRXM
SSRX-
A4
U3RXVDDQ
I
SSRXP
SSRX+
A6
U3TXVDDQ
O
SSTXM
SSTX-
A5
U3TXVDDQ
O
SSTXP
SSTX+
A9
VBUS/VBATT
I/O
DP
A10
VBUS/VBATT
I/O
DM
D-
NC
No connect
USB Port (VBATT/VBUS Power Domain)
OTG_ID
USB Port (U3TXVDDQ/U3RXVDDQ Power Domain)
USB Port (VBATT/VBUS Power Domain)
A11
D+
Crystal/Clocks (CVDDQ Power Domain)
B2
CVDDQ
I
FSLC[0]
FSLC[0]
C6
AVDD
I/O
XTALIN
XTALIN
C7
AVDD
I/O
XTALOUT
XTALOUT
B4
CVDDQ
I
FSLC[1]
FSLC[1]
E6
CVDDQ
I
FSLC[2]
FSLC[2]
D7
CVDDQ
I
CLKIN
CLKIN
D6
CVDDQ
I
CLKIN_32
CLKIN_32
D9
VIO5
I/O
I2C_GPIO[58]
I2C_SCL
D10
VIO5
I/O
I2C_GPIO[59]
I2C_SDA
I2C and JTAG (VIO5 Power Domain)
Document Number 001-52136 Rev. *H
Page 33 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Table 16. Pin List (continued)
I/O
Name
E7
Pin
VIO5
I
TDI
Description
TDI
C10
VIO5
O
TDO
TDO
B11
VIO5
I
TRST#
TRST#
E8
VIO5
I
TMS
TMS
F6
VIO5
I
TCK
TCK
D11
VIO5
I/O
O[60]
Charger detect output
E10
PWR
VBATT
B10
PWR
VDD
A1
PWR
U3VSSQ
E11
PWR
VBUS
D8
PWR
VSS
H11
PWR
VIO1
E2
PWR
VSS
VIO1
Power
L9
PWR
G1
PWR
VSS
F1
PWR
VIO2
G11
PWR
VSS
E3
PWR
VIO3
L1
PWR
VSS
B1
PWR
VIO4
L6
PWR
VSS
B6
PWR
CVDDQ
B5
PWR
U3TXVDDQ
A2
PWR
U3RXVDDQ
C11
PWR
VIO5
L11
PWR
VSS
A7
PWR
AVDD
B7
PWR
AVSS
C3
PWR
VDD
B8
PWR
VSS
E9
PWR
VDD
B9
PWR
VSS
F11
PWR
VDD
H1
PWR
VDD
L7
PWR
VDD
J11
PWR
VDD
L5
PWR
VDD
K4
PWR
VSS
L3
PWR
VSS
K3
PWR
VSS
L2
PWR
VSS
A8
PWR
VSS
Precision Resistors
C8
VBUS/VBATT
I/O
R_usb2
Precision resistor for USB2.0 (Connect a 6.04 kΩ+/-1% resistor between this pin and GND)
B3
U3TXVDDQ
I/O
R_usb3
Precision resistor for USB3.0 (Connect a 200 Ω+/-1% resistor between this pin and GND)
Document Number 001-52136 Rev. *H
Page 34 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Package Diagram
Figure 19. 121-Ball FBGA 10x10x1.2 Diagram
001-54471 *B
Ordering Information
Table 17. Ordering Information
Ordering Code
Package Type
CYUSB3014-BZXI
121-ball BGA
Ordering Code Definition
CY USB 3 XXX BZX I
Temperature range : Industrial
Package type: BGA
Marketing Part Number
Base part number for USB 3.0
Marketing Code: USB = USB Controller
Company ID: CY = Cypress
Document Number 001-52136 Rev. *H
Page 35 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Acronyms
Document Conventions
Acronym
Description
Units of Measure
DMA
direct memory access
HNP
host negotiation protocol
°C
degree Celsius
MMC
multimedia card
µA
microamperes
MTP
media transfer protocol
µs
microseconds
PLL
phase locked loop
mA
milliamperes
SD
secure digital
Mbps
Megabytes per second
SD
secure digital
MHz
mega hertz
SDIO
secure digital input / output
ms
milliseconds
SLC
single-level cell
ns
nanoseconds
SPI
serial peripheral interface
Ω
ohms
SRP
session request protocol
pF
pico Farad
USB
universal serial bus
V
volts
WLCSP
wafer level chip scale package
Document Number 001-52136 Rev. *H
Symbol
Unit of Measure
Page 36 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Document History Page
Document Title: CYUSB3014 EZ-USB® FX3 SuperSpeed USB Controller
Document Number: 001-52136
Orig. of
Submission
Revision
ECN
Change
Date
Description of Change
**
2669761
VSO/PYRS
03/06/09
New Datasheet
*A
2758370
VSO
09/01/09
Updated the part# from CYX01XXBB to CYUSB3011-BZXI
Changed the title from “ADVANCE” to “ADVANCE INFORMATION”
In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz”
to first sub bullet.
In page 1, changed the second bullet “Flexible Host Interface” to General
Programmable Interface”.
In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave
Support” and "MMC Slave support with Pass through Boot" sub bullets.
In page 1, third bullet, changed "50 μA with Core Power" to "60 μA with
Core Power"
In page 1, fifth bullet, added "at 1 MHz"
In page 1, seventh bullet, added "up to 4MHz" to UART
In page 1, Applications Section, move “Digital Still Cameras” to second line.
In page 1, Applications Section, added “Machine Vision” and Industrial
Cameras”
Added ™ to GPIF and FX3.
In page 1, updated Logic Block Diagram.
In page 2, section of “Functional Overview”, updated the whole section.
In page 2, removed the section of “Product Interface”
In page 2, removed the section of “Processor Interface (P-Port)”
In page 2, removed the section of “USB Interface (U-Port)”
In page 2, removed the section of “Other Interfaces”
In page 2, added a section of "GPIF II"
In page 2, added a section of "CPU"
In page 2, added a section of "JTAG Interface"
In page 2, added a section of "Boot Options"
In page 2, added a section of "ReNumeration"
In page 2, added a section of "Power"
In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by
FX3.
In the section of “Package”, added 0.8 mm pitch in front of BGA.
Added Pin List (Table 1)
*B
2779196
VSO/PYRS
09/29/09
Features:
Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of
embedded SRAM”
Added the thrid line “EZ USB™ Software and DVK for easy code development”
Table 1: Pin 74, corrected to NC - No Connect.
Changed title to EZ-USB™ FX3: SuperSpeed USB Controller
*C
2823531
OSG
12/08/09
Added data sheet to the USB3.0 EROS spec 001-51884. No technical
updates.
*D
3080927
OSG
11/08/2010 Changed status from Advance to Preliminary
Changed part number from CYUSB3011 to CYUSB3014
Added the following sections: Power, Configuration Options, Digital I/Os,
System Level ESD, Absolute Maximum Ratings, AC Timing Parameters,
Reset Sequence, Package Diagram
Added DC Specifications table
Updated feature list
Updated Pin List
Added support for selectable clock input frequencies.
Updated block diagram
Updated part number
Updated package diagram
Document Number 001-52136 Rev. *H
Page 37 of 38
[+] Feedback
PRELIMINARY
CYUSB3014
Document Title: CYUSB3014 EZ-USB® FX3 SuperSpeed USB Controller
Document Number: 001-52136
Orig. of
Submission
Revision
ECN
Change
Date
Description of Change
*E
3204393
OSG
03/24/2011 Updated Slave FIFO protocol and added ZLP signaling protocol
Changed GPIFII asynchronous tDO parameter
Changed Async Slave FIFO tOE parameter
Changed Async Slave FIFO tRDO parameter
Added tCOE parameter to GPIFII Sync mode timing parameters
Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0
Modified description of GPIFII Sync tCO (previously tDO) parameter
Changed tAH(address hold time) parameter in Async Slave FIFO modes
to be with respect to rising edge of SLWR#/SLRD# instead of falling edge.
Correspondingly, changed the tAH number.
Removed 24 bit data bus support for GPIFII.
*F
3218493
OSG
04/07/2011 Minor ECN - Release to web. No content changes.
*G
3235250
GSZ
04/20/2011 Minor updates in Features.
*H
3217917
OSG
04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option.
Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST#
pull-up/pull-down configuration. Minor updates to block diagrams.
Corrected Synchronous Slave FIFO tDH parameter.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number 001-52136 Rev. *H
Revised May 17, 2011
Page 38 of 38
®
EZ-USB™ is a trademark and West Bridge is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their
respective holders.
[+] Feedback