CYWB0320ABX-FDXI, CYWB0321ABX-FDXI West Bridge®:Arroyo USB and Mass Storage Peripheral Controller Datasheet.pdf

CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
West Bridge®: Arroyo USB and
Mass Storage Peripheral Controller
West Bridge®: Arroyo USB and Mass Storage Peripheral Controller
Features
■
■
■
■
Multimedia device support
❐ Support next-gen SD, SDHC, SDIO, and MMC+
®
Simultaneous link to independent multimedia (SLIM )
architecture, enabling simultaneous and independent data
paths between the processor and USB, and between the USB
and mass storage.
High speed USB at 480 Mbps
❐ USB 2.0 compliant
❐ Integrated USB 2.0 transceiver, smart Serial Interface Engine
❐ 16 programmable endpoints
Flexible processor interface, which supports:
❐ SPI (slave mode) interface
❐ Multiplexing and nonmultiplexing address and data interface
❐ SRAM interface
❐ Pseudo CRAM interface
❐ Pseudo NAND Flash interface
❐ DMA slave support
■
Ultra low power, 1.8 V core operation
■
Low power modes
■
Small footprint, 3.9 × 3.9 mm, 0.4 mm pitch, WLCSP
■
Supports USB Boot, I2C Boot and Processor Boot
■
Clock input frequency
❐ 19.2 MHz
❐ 26 MHz
Applications
■
Cellular phones
■
Portable media players
■
Personal digital assistants
■
Portable navigation devices
■
Digital cameras
■
POS terminals
■
Portable video recorders
Logic Block Diagram
Control Registers
µC
Processor
Interface
P
Hi-Speed
USB 2.0 XCVR
Access Control
U
SLIM™
Mass Storage Interface
SD/MMC
S
Errata: For information on silicon errata, see “Errata” on page 50 and “Errata” on page 51. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-57458 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2014
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Contents
Functional Overview ........................................................ 3
The SLIM Architecture ................................................. 3
8051 Microprocessor ................................................... 3
Configuration and Status Registers ............................. 3
Processor Interface (P-Port) ........................................ 3
USB Interface (U-Port) ................................................ 3
Clocking ....................................................................... 3
Power Domains ........................................................... 4
Power Modes .............................................................. 5
Pin Assignments .............................................................. 6
Absolute Maximum Ratings .......................................... 13
Operating Conditions ..................................................... 13
DC Characteristics ......................................................... 14
AC Timing Parameters ................................................... 16
P Port Interface ......................................................... 16
S Port Interface AC Timing Parameters .................... 43
Reset and Standby Timing Parameters .................... 45
Ordering Information ...................................................... 47
Ordering Code Definitions ......................................... 47
Document Number: 001-57458 Rev. *H
Package Diagram ............................................................ 48
Acronyms ........................................................................ 49
Document Conventions ................................................. 49
Units of Measure ....................................................... 49
Errata ............................................................................... 50
Part Numbers Affected .............................................. 50
Arroyo Qualification Status ........................................ 50
Arroyo Errata Summary ............................................. 50
Errata ............................................................................... 51
Part Numbers Affected .............................................. 51
Arroyo Qualification Status ........................................ 51
Arroyo Errata Summary ............................................. 51
Document History Page ................................................. 52
Sales, Solutions, and Legal Information ...................... 54
Worldwide Sales and Design Support ....................... 54
Products .................................................................... 54
PSoC® Solutions ...................................................... 54
Cypress Developer Community ................................. 54
Technical Support ..................................................... 54
Page 2 of 54
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Functional Overview
The SLIM Architecture
The SLIM architecture enables three different interfaces (P-port,
S-port, and U-port) to connect to each other independently.
With this architecture, a device using Arroyo is connected to a
PC through a USB, without disturbing any of the device
functions. The device can still access mass storage when the PC
is synchronizing with the main processor.
The SLIM architecture enables new usage models, in which a
PC accesses a mass storage device independent of the main
processor, or enumerates access to both the mass storage and
the main processor at the same time.
You can do the following in a handset using SLIM architecture:
■
Use the phone as a thumb drive.
■
Download media files to the phone with all the functionalities
still available on the phone.
■
Use the same phone as a modem to connect the PC to the
internet.
8051 Microprocessor
The 8051 microprocessor embedded in Arroyo does basic
transaction management for all transactions between the P-Port,
S-Port, and the U-Port. The 8051 does not reside in the data
path; it manages the path. The data path is optimized for
performance. The 8051 executes firmware that supports SD,
SDHC, SDIO, and MMC+ devices at the S-Port.
Configuration and Status Registers
Access to these buffers is controlled by using a DMA protocol or
using an interrupt to the main processor. These two modes are
configured by the external processor.
As a DMA slave, Arroyo generates a DMA request signal to notify
the main processor that a specific buffer is ready to be read from
or written to. The external processor monitors this signal and
polls Arroyo for the specific buffers ready for a read or write
operation. It then performs the appropriate read or write
operations on the buffer through the processor interface. As a
result, the external processor only deals with the buffers to
access a storage device connected to Arroyo.
In the Interrupt mode, Arroyo communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Arroyo for the specific
buffers ready for read or write, and it performs the appropriate
read or write operations through the processor interface.
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Arroyo can
operate in both full speed and high speed USB modes. The USB
interface consists of the USB transceiver. The USB interface can
access and be accessed by both the P-Port and the S-Port.
The Arroyo USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Mass Storage Support (S-Port)
The S-Port may be configured to support the following:
■
Next-gen SD/SDIO/eMMC+ port
When Arroyo is configured through firmware to support
SD/SDIO/MMC+, this interface supports the following:
The West Bridge® Arroyo device includes configuration and
status registers that are accessible as memory-mapped
registers through the processor interface. The configuration
registers enable the system to specify some behaviors of Arroyo.
For example, it can mask certain status registers from raising an
interrupt. The status registers convey the status of Arroyo, such
as the addresses of buffers for read operations.
■
SD Memory Card Specification - Part 1, Physical Layer
Specification, SD Group, Version 2.0, May 9, 2006.
■
SD Memory Card Specification - Part 1, Physical Layer
Specification, SD Group, Version 1.10, October 15, 2004.
■
SD Specifications - Part E1 SDIO specification, Version 1.10,
August 18, 2004.
Processor Interface (P-Port)
■
The Multimedia Card System Specification, MMCA Technical
Committee, Version 4.1.
Communication with the external processor is realized through a
dedicated processor interface. This interface is configured to
support different interface standards. This interface supports
multiplexing and nonmultiplexing address or data bus in both
synchronous and asynchronous pseudo CRAM-mapped, and
nonmultiplexing address or data asynchronous SRAM-mapped
memory accesses. The interface also can be configured to a
pseudo NAND interface to support the processor’s NAND
interface. In addition, this interface can be configured to support
SPI slave. Asynchronous accesses can reach a bandwidth of up
to 66.7 MBps. Synchronous accesses can be performed at
33 MHz across 16 bits for up to 66.7 MBps bandwidth.
The memory address is decoded to access any of the multiple
endpoint buffers inside Arroyo. These endpoints serve as buffers
for data between each pair of ports; for example, between the
processor port and the USB port. The processor writes and reads
to these buffers through the memory interface.
Document Number: 001-57458 Rev. *H
West Bridge Arroyo supports 1-bit and 4-bit SD and SDIO cards;
1-bit, 4-bit, and 8-bit MMC; MMC+ cards. For the SD, SDIO, and
MMC/MMC Plus, this block supports one card for one physical
bus interface. Arroyo supports SD commands including the
multisector program command that is handled by API
Clocking
Arroyo enables connection of an external clock at the XTALIN
pin. The power supply level at the crystal supply XVDDQ
determines whether a crystal or a clock is provided. If XVDDQ is
detected to be 1.8 V, Arroyo assumes that a clock input is
provided. For a crystal to be connected, XVDDQ must be 3.3 V.
Note Clock inputs at 3.3 V level are not supported.
The 81-pin WLCSP supports 19.2 MHz and 26 MHz external
clock input. The crystal or clock frequency selection is shown in
Table 1 on page 4.
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CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 1. Crystal Configuration
The XTALIN frequency is independent of the clock and data rate
of the 8051 microprocessor or any of the device interfaces
(including P-Port and S-Port). The internal PLL applies the
proper clock multiply option depending on the input frequency.
Arroyo
Astoria
XTALIN
For applications that use an external clock source to drive
XTALIN, the XTALOUT, pin must be left floating. The external
clock source must also stop high or low and not toggle, to
achieve the lowest possible current consumption. The
requirements for an external clock source are shown in Table 3.
XTAL
PLL
XTALOUT
12pf
12pf
Arroyo has an on-chip oscillator circuit that uses an external
26 MHz (±150 ppm) crystal with the following characteristics:
* 12 pF capacitor values assumes a trace capacitance of 3 pF per
side on a four layer FR4 PCA
■
Parallel resonant
■
Fundamental mode
■
1 mW drive level
■
12 pF (5% tolerance) load capacitors 150 ppm
Note CYWB0321ABX-FDXI does not support crystal.
Table 1. CYWB0320ABX-FDXI Clock Selection
XTALSLC
Freq
Crystal/Clock
NA
26 MHz
Clock or Crystal
Table 2. CYWB0321ABX-FDXI Clock Selection
XTALSLC
Freq
Crystal/Clock
0
19.2 MHz
Clock
1
26 MHz
Clock
Table 3. External Clock Requirements
Parameter
Specification
Description
Min
Max
–
20
Unit
Vn (AVDDQ)
Supply Voltage Noise at Frequencies < 50 MHz
PN_100
Input Phase Noise at 100 Hz
–
–75
dBc/Hz
PN_1k
Input Phase Noise at 1 kHz Offset
–
–104
dBc/Hz
PN_10k
Input Phase Noise at 10 kHz Offset
–
–120
dBc/Hz
PN_100k
Input Phase Noise at 100 kHz Offset
–
–128
dBc/Hz
PN_1M
mV p-p
Input Phase Noise at 1 MHz Offset
–
–130
dBc/Hz
Duty Cycle
30
70
%
Maximum Frequency Deviation
–
150
ppm
Overshoot
–
3
%
Undershoot
–
–3
%
Power Domains
Arroyo has multiple power domains that serve different purposes
within the chip.
VDDQ: This refers to a group of five independent supply
domains for the digital I/Os. The nominal voltage level on these
Document Number: 001-57458 Rev. *H
supplies are 1.8 V, 2.5 V, or 3.3 V. Specifically, the four separate
I/O power domains are:
■
PVDDQ – P-Port Processor interface I/O
■
SSVDDQ – S-Port SD interface I/O
■
GVDDQ – Other miscellaneous I/O
Page 4 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
UVDDQ: This is the 3.3 V nominal supply for the USB I/O and
some analog circuits. It also supplies power to the USB
transceiver.
VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.8 V. This supplies the core logic circuits.
The same supply must also be used for AVDDQ.
AVDDQ: This is the 1.8 V supply for PLL and USB serializer
analog components. The same supply must also be used for
VDD. Maximum permitted noise on AVDDQ is 20 mV p-p.
XVDDQ: This is the clock I/O supply; 3.3 V for XTAL or 1.8 V for
an external clock.
Noise guideline for all supplies except AVDDQ is maximum
100 mV p-p. All I/O supplies of Arroyo must be ON when a
system is active even if Arroyo is not in use. The core VDD can
also be deactivated at any time to preserve power, provided
there is a minimum impedance of 1 k between the VDD pin and
ground. All I/Os tristate when the core is disabled.
Figure 2. Arroyo Power Supply Domains
VDD
*VDDQ
UVDDQ
D+
I/O
D-CORE
USB-IO
D-
■
The states of the configuration registers, endpoint buffers, and
the program RAM are maintained. All transactions must be
complete before Arroyo enters suspend mode (state of
outstanding transactions are not preserved).
■
The firmware resumes its operation from where it was
suspended, since the program counter is not reset.
■
Only inputs that are sensed are RESET#, GPIO[0]/SD_CD,
GPIO[1], SD_D3, D+, and CE#. The last three are wake up
sources (each can be individually enabled or disabled).
■
Hard Reset can be performed by asserting the RESET# input,
and Arroyo is initialized.
Standby Mode
Standby mode is a low power state. This is the lowest power
mode of Arroyo while still maintaining external supply levels. This
mode is entered through deassertion of the WAKEUP input pin
or through internal register settings. To leave this mode, assert
WAKEUP, CE#, and RESET#; and change the state of
GPIO[0]/SD_CD, GPIO[1], or SD_D3.
In this mode all configuration register settings and program RAM
contents are preserved. However, data in the buffers or other
parts of the data path, if any, is not guaranteed in values.
Therefore, the external processor must ensure that the required
data is read before putting Arroyo into the standby mode.
In the standby mode:
■
The program counter is reset on waking up from standby mode.
■
All outputs are tristated and I/O is placed in input only
configuration. Values of I/Os in standby mode are listed in the
pin assignments table.
■
Core power supply must be retained.
■
Hard Reset can be performed by asserting the RESET# input,
and Arroyo is initialized.
■
PLL is disabled.
Power Supply Sequence
The power supplies are independently sequenced without
damaging the part. All power supplies must be up and stable
before the device operates. If the supplies are not stable, the
remaining domains are in low power (standby) state.
Power Modes
In addition to the normal operating mode, Arroyo contains
several low power states when normal operation is not required.
Normal Mode
Normal mode is the mode in which Arroyo is fully functional. In
this mode data transfer functions described in this document are
performed.
Suspend Mode
This mode is entered internally by 8051 (external processor only
initiates entry into this mode through Mailbox commands). This
mode is exited by the D+ bus going low, GPIO[0] going to a
pre-determined state or by asserting CE# LOW.
In Arroyo’s suspend mode:
Core Power Down Mode
The core power supply VDD is powered down in this state.
AVDDQ is tied to the same supply as VDD and is hence, also
powered down. Neither the endpoint buffers, configuration
registers nor program RAM maintain state. It is required that all
VDDQ power supplies (except AVDDQ) are on and not power
downer down in this mode. When UVDDQ is powered down,
D+/D– can’t be driven by external device.
The core power down mode has two power down options:
■
Core only power down – VDD power down.
■
Core and USB power down – VDD and UVDDQ are both
powered down.
■
The clocks are shut off.
■
All I/Os maintain their previous state.
■
Core power supply must be retained.
In these power down options, the endpoint buffers, configuration
registers, or the program RAM do not maintain state. It is
necessary to reload the firmware on exiting from this mode. It is
required that all VDDQ power supplies are on and not powered
down in this mode.
Document Number: 001-57458 Rev. *H
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CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Pin Assignments
Table 4. CYWB0320ABX-FDXI WLCSP Package Pin Assignments
Pin Name
J3
E2
Pseudo CRAM
Interface
CE#
A7
H1
F2
G2
J1
H2
J2
H3
F3
J4
H4
G4
J5
H5
J6
G6
H6
J7
F6
J8
H7
G7
H8
H9
G8
F8
G9
A7
D6
C6
D9
E9
D7
E7
A6
A5
A4
A3
A2
A1
A0
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
ADV#
OE#
WE#
INT#
DRQ
DACK
D+
D–
NC
NC
U-Port
Int
P-Port
Ball #
I/O
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
I
SRAM Interface
CE#
A7
A6
A5
A4
A3
A2
A1
A0
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
OE#
[1]
I/O
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
I
ADM (Address/Data
Multiplexing)
CE#
External Pull Up
SDA
SCL
External Pull Up
External Pull Low
External Pull Up
External Pull Up
External Pull Up
AD[15]
AD[14]
AD[13]
AD[12]
AD[11]
AD[10]
AD[9]
AD[8
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0]
ADV#
OE#
WE#
INT#
DRQ
DACK
Pin Description
I/O
I
I
I/O
I/O
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
I
PNAND
CE#
A7 => 1:SBD
A7 => 0: LBD
SDA
SCL
WP#
External Pull Low
External Pull Low
R/B#
CLE
I/O[15]
I/O[14]
I/O[13]
I/O[12]
I/O[11]
I/O[10]
I/O[9]
I/O[8]
I/O[7]
I/O[6]
I/O[5]
I/O[4]
I/O[3]
I/O[2]
I/O[1]
I/O[0]
ALE
RE#
WE#
INT#
DRQ
DACK
Power
Domain
I/O
I
I
I/O
I/O
I
I
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
CE#
A7
PVDDQ
VGND
A6 or SDA
A5 or SCL
A4 or WP#
A3
A2
A1 or R/B#
A0 or CLE
D15, AD15, or IO15
D14, AD14, or IO14
D13, AD13, or IO13
D12, AD12, or IO12
D11, AD11, or IO11
D10, AD10, or IO10
D9, AD9, or IO9
D8, AD8, or IO8
D7, AD7, or IO7
D6, AD6, or IO6
D5, AD5, or IO5
D4, AD4, or IO4
D3, AD3, or IO3
D2, AD2, or IO2
D1, AD1, or IO1
D0I, AD0, or IO0
Address Valid
Output Enable
WE#
INT Request
GVDDQ
VGND
DMA Request
DMA ACK
USB D+
UVDDQ
UVSSQ
USB D–
Left floating
Left floating
Note
1. Errata: When Arroyo is configured to use SRAM for P-port interface, OE should be asserted simultaneously with CE. If this is not possible, OE should be asserted
prior to CE. Otherwise, data can be dropped when external processor reads the Arroyo through SRAM interface. For more information, see the “Errata” on page 50
and “Errata” on page 51.
Document Number: 001-57458 Rev. *H
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CYWB0321ABX-FDXI
Table 4. CYWB0320ABX-FDXI WLCSP Package Pin Assignments (continued)
SSVDDQ
VGND
S-Port
Power
Domain
C4
A2
B3
C5
B4
A4
B5
A5
A3
A1
E1
D1
D2
C1
C2
D3
B1
B2
G1
F1
SD_D[7]
SD_D[6]
SD_D[5]
SD_D[4]
SD_D[3]
SD_D[2]
SD_D[1]
SD_D[0]
SD_CLK
SD_CMD
PB[7] (GPIO)
PB[6] (GPIO)
PB[5] (GPIO)
PB[4] (GPIO)
PB[3] (GPIO)
PB[2] (GPIO)
PB[1] (GPIO)
PB[0] (GPIO)
TESTTREE
SCAN (Ext Pull-Low)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
CLK Conf Other
S-Port Interface
Pin Description
A6
B7
E5
C7
E6
A8
B9
A9
SD_CD
RESET#
WAKEUP
TEST[2]
TEST[1]
TEST[0]
XTALIN
XTALOUT
I
I
I
I
I
I
I
O
SD Data or GPIO
SD Data or GPIO
SD Data or GPIO
SD Data or GPIO
SD Data or GPIO
SD Data or GPIO
SD Data or GPIO
SD Data or GPIO
SD Clock or GPIO
SD CMD or GPIO
GPIOI
GPIOI
GPIOI
GPIOI
GPIOI
GPIOI
GPIOI
GPIOI
Test Mode
Test Mode (Ext
Pull-Low)
SD CD
RESET
Wake Up Signal
Test Cfg 2
Test Cfg 1
Test Cfg 0
Clock IN
Clock OUT
Power
Pin Name
F4, J9
E8
D5
B6
C8
D8
E4,
G5,
F7, F9
C9
B8
C3,
D4,
E3,
F5, G3
PVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
VDD
Power
Power
Power
Power
Power
Power
Power
Processor I/F VDD
USBVDD
SDIO VDD
Misc I/O VDD
Analog VDD
Crystal VDD
Core VDD
UVSSQ
AVSSQ
VGND
Power USB GND
Power Analog GND
Power Core GND
Document Number: 001-57458 Rev. *H
GVDDQ
VGND
GVDDQ
VGND
XVDDQ
VGND
Page 7 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 5. CYWB0321ABX-FDXI WLCSP Package Pin Assignments
Pin Name
U-Port
Int
P-Port
Ball #
PNAND
I/O
Pin Description
SPI
[2]
Power
Domain
I/O
J2
Ext pull low
I
SCK
I
Clock
J4
CE#
I
SS#
I
CE# or SPI Slave
Select
G5
SDA
I/O
SDA
I/O
I2C data
H2
SCL
I/O
SCL
I/O
I2C clock
J1
WP#
I
Ext pull up
I
H3
A[3] (Ext pull low)
I
A[3] (Ext pull up)
I
A[3]
F5
A[2] (Ext pull low)
I
A[2] (Ext pull low)
I
A[2]
J3
RB#
O
Ext pull up
I
PNAND R/B#
H4
CLE
I
Ext pull up
I
PNAND CLE
PVDDQ
VGND
PNAND WP
J6
I/O[7]
I/O
Ext pull up
I
IO7
H6
I/O[6]
I/O
Ext pull up
I
IO6
J7
I/O[5]
I/O
Ext pull up
I
IO5
J8
I/O[4]
I/O
Ext pull up
I
IO4
H7
I/O[3]
I/O
Ext pull up
I
IO3
G7
I/O[2]
I/O
Ext pull up
I
IO2
H8
I/O[1]
I/O
SDO
O
IO1 or SPI SDO
H9
I/O[0]
I/O
SDI
I
IO0 or SPI SDI
G8
ALE
I
Ext pull up
I
Address Valid
F8
RE#
I
Ext pull up
I
Output Enable
G9
WE#
I
Ext pull up
I
WE#
A7
INT#
O
SINT#
O
INT Request
D9
D+
I/O/Z USB D+
E9
D–
I/O/Z USB D–
D7
NC
I/O/Z Left floating
E7
NC
I/O/Z Left floating
GVDDQ
VGND
UVDDQ
UVSSQ
Note
2. Errata: When Arroyo is configured to use SPI for Processor-Port (P-Port) interface, transfers from U-Port to P-Port may intermittently fail after wakeup from STANDBY
mode. Workaround for this problem is added in SDK version 1.0 or later. For more information, see the “Errata” on page 50 and “Errata” on page 51.
Document Number: 001-57458 Rev. *H
Page 8 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 5. CYWB0321ABX-FDXI WLCSP Package Pin Assignments (continued)
Pin Name
CLK
Conf
Other
S-Port
Ball #
SDIO
I/O
Pin Description
GPIO only Configuration
I/O
B2
SD_D[7]
I/O
PD[7] (GPIO)
I/O
SD Data or GPIO
A2
SD_D[6]
I/O
PD[6] (GPIO)
I/O
SD Data or GPIO
C3
SD_D[5]
I/O
PD[5] (GPIO)
I/O
SD Data or GPIO
B3
SD_D[4]
I/O
PD[4] (GPIO)
I/O
SD Data or GPIO
B4
SD_D[3]
I/O
PD[3] (GPIO)
I/O
SD Data or GPIO
C4
SD_D[2]
I/O
PD[2] (GPIO)
I/O
SD Data or GPIO
C5
SD_D[1]
I/O
PD[1] (GPIO)
I/O
SD Data or GPIO
B5
SD_D[0]
I/O
PD[0] (GPIO)
I/O
SD Data or GPIO
A3
SD_CLK
O
PC-7 (GPIO)
I/O
SD Clock
D4
SD_CMD
I/O
PC-3 (GPIO)
I/O
SD CMD
A1
SD_POW
O
PC-6 (GPIO)
I/O
SD POW
A5
SD_WP
I
Unused
E2
SD_RSV
I/O
PB[7] (GPIO)
I/O
D1
SD_RSV
I/O
PB[6] (GPIO)
I/O
I
E3
SD_RSV
I/O
PB[5] (GPIO)
I/O
D2
SD_RSV
I/O
PB[4] (GPIO)
I/O
C1
SD_RSV
I/O
PB[3] (GPIO)
I/O
D3
SD_RSV
I/O
PB[2] (GPIO)
I/O
C2
SD_RSV
I/O
PB[1] (GPIO)
I/O
B1
SD_RSV
I/O
PB[0] (GPIO)
I/O
G2
SD_RSV
I
Unused
F2
NC
O
PA-7 (GPIO)
I/O
G3
NC
O
PC-0 (GPIO)
I/O
O
Connect to
SSVDDQ with 10K
pull up resister
Left floating
NC
O
N/C
NC
O
N/C
O
F3
NC
O
PA-5 (GPIO)
I/O
G4
NC
O
PA-6 (GPIO)
I/O
G1
NC
O
PC-2 (GPIO)
I/O
B7
RESETOUT
O
RESETOUT
O
RESETOUT
B6
PC-5 (GPIO[1])
I/O
O
PC-5 (GPIO[1])
I/O
GPIO, SD2 CD4
A6
PC-4 (GPIO[0]) or SD_CD
I/O
I
O
PC-4 (GPIO[0])
I/O
GPIO, SD1 CD
C7
RESET#
I
D6
WAKEUP
I
A9
XTALSLC
A8
TEST[2]
TEST[1]
TEST[0]
B9
XTALIN
Document Number: 001-57458 Rev. *H
SSVDDQ
VGND
I
E1
D8
SSVDDQ
VGND
SD WP, GPIO
H1
F7
Power
Domain
RESET
Wake Up Signal
Clock Select
I
GVDDQ
VGND
Test Cfg 2
GVDDQ
VGND
Test Cfg 1
Test Cfg 0
I
Clock IN
VGND
Page 9 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 5. CYWB0321ABX-FDXI WLCSP Package Pin Assignments (continued)
Power
Pin Name
Pin Description
H5, J9 PVDDQ
Power Processor I/F VDD
F1
SSVDDQ
Power SDIO VDD
E8
UVDDQ
Power USB VDD
A4
SSVDDQ
Power SDIO VDD
C6
GVDDQ
Power Misc I/O VDD
C8
AVDDQ
Power Analog VDD
E5,
VDD
F4,
F6, F9
Power Core VDD
C9
UVSSQ
Power USB GND
B8
AVSSQ
Power Analog GND
D5,
VGND
E4,
E6,
G6, J5
Document Number: 001-57458 Rev. *H
Power
Domain
Power Core GND
Page 10 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 3. CYWB0320ABX-FDXI WLCSP Ball Map - Top View
A
1
2
3
4
5
6
7
8
9
SD_CMD
SD_D[6]
SD_CLK
SD_D[2]
SD_D[0]
GPIO[0]
INT#
TEST[0]
XTALOUT
A
B
NAND_IO[1] NAND_IO[0]
SD_D[5]
SD_D[3]
SD_D[1]
GVDDQ
RESET#
AVSSQ
XTALIN
B
C
NAND_IO[4] NAND_IO[3]
VGND
SD_D[7]
SD_D[4]
DACK#
TEST[2]
AVDDQ
UVSSQ
C
D
NAND_IO[6] NAND_IO[5] NAND_IO[2]
VGND
SSVDDQ
DRQ#
NC
XVDDQ
D+
D
E
NAND_IO[7]
A[7]
VGND
VDD
WAKEUP
TEST[1]
NC
UVDDQ
D-
E
F
SCAN
A[5]
DQ[15]
PVDDQ
VGND
DQ[5]
VDD
OE#
VDD
F
G
TESTTREE
A[4]
VGND
DQ[12]
VDD
DQ[8]
DQ[2]
ADV#
WE#
G
H
A[6]
A[2]
A[0]
DQ[13]
DQ[10]
DQ[7]
DQ[3]
DQ[1]
DQ[0]
H
J
A[3]
A[1]
CE#
DQ[14]
DQ[11]
DQ[9]
DQ[6]
DQ[4]
PVDDQ
J
1
2
3
4
5
6
7
8
9
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDD/AVDDQ
VGND/AVSSQ
PVDDQ
XVDDQ
Document Number: 001-57458 Rev. *H
Page 11 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 4. CYWB0321ABX-FDXI WLCSP Ball Map – Top View
1
2
3
4
5
6
7
8
9
A
SD_POW
SD_D[6]
SD_CLK
SSVDDQ
SD_WP
GPIO[0]
INT#
TEST[2]
XTALSLC
A
B
SD_RSV
SD_D[7]
SD_D[4]
SD_D[3]
SD_D[0]
GPIO[1]
RESETOUT
AVSSQ
XTALIN
B
C
SD_RSV
SD_RSV
SD_D[5]
SD_D[2]
SD_D[1]
GVDDQ
RESET#
AVDDQ
UVSSQ
C
D
SD_RSV
SD_RSV
SD_RSV
SD_CMD
VGND
WAKEUP
NC
TEST[0]
D+
D
E
NC
SD_RSV
SD_RSV
VGND
VDD
VGND
NC
UVDDQ
D-
E
F
SSVDDQ
NC
NC
VDD
A[2]
VDD
TEST[1]
RE#
VDD
F
G
NC
SD_RSV
NC
NC
SDA
VGND
IO[2]
ALE
WE#
G
H
NC
SCL
A[3]
CLE
PVDDQ
IO[6]
IO[3]
IO[1]
IO[0]
H
J
WP#
Pull-Low
R/B#
CE#
VGND
IO[7]
IO[5]
IO[4]
PVDDQ
J
1
2
3
4
5
6
7
8
9
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDD/AVDDQ
VGND/AVSSQ
PVDDQ
Document Number: 001-57458 Rev. *H
Page 12 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Absolute Maximum Ratings
Operating Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
TA (Ambient Temperature Under Bias)
Industrial .................................................... –40 °C to +85 °C
Storage Temperature ............................... –65 °C to +150 °C
VDD, AVDDQ Supply Voltage .........................1.7 V to 1.9 V
Ambient Temperature with
Power Supplied (Industrial) ....................... –40 °C to +85 °C
UVDDQ Supply Voltage ...................................3.0 V to 3.6 V
Supply Voltage to Ground Potential
VDD, AVDDQ ..............................................–0.5 V to +2.0 V
GVDDQ, PVDDQ, SSVDDQ,
UVDDQ, and XVDDQ ..................................–0.5 V to +4.0 V
PVDDQ, GVDDQ, SSVDDQ
Supply Voltage .................................................1.7 V to 3.6 V
XVDDQ (Crystal I/O) Supply Voltage ..............3.0 V to 3.6 V
XVDDQ (Ext. Clock I/O) Supply Voltage .........1.7 V to 1.9 V
DC Input Voltage to Any Input Pin .................1.89 V to 3.6 V
(Depends on I/O supply voltage. Inputs are not overvoltage
tolerant.)
DC Voltage applied to
Outputs in High Z State .................. –0.5 V to VDDQ + 0.5 V
Static Discharge Voltage
(ESD) from JESD22-A114 ...................................... > 2000 V
Latch up current ..................................................... > 200 mA
Maximum Output Short Circuit Current
for all I/O Configurations. (Vout = 0 V) .................... –100 mA
Document Number: 001-57458 Rev. *H
Page 13 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
DC Characteristics
Table 6. DC Specifications for All Voltage Supplies
Parameter
Description
Conditions
Min
Typ
Max
Unit
VDD
Core Voltage Supply
1.7
1.8
1.9
V
AVDDQ
Analog Voltage Supply
1.7
1.8
1.9
V
XVDDQ
Crystal Voltage Supply
3.0
3.3
3.6
V
XVDDQ
Clock Voltage Supply
1.7
1.8
1.9
V
PVDDQ
[3]
GVDDQ [3]
Processor Interface I/O
1.7
1.8, 2.5, 3.3
3.6
V
Miscellaneous I/O Voltage
Supply
1.7
1.8, 2.5, 3.3
3.6
V
1.7
1.8, 2.5, 3.3
3.6
V
SSVDDQ [3, 4] S-Port SD I/O Voltage Supply
UVDDQ
[5]
3.0
3.3
3.6
V
VIH1[6]
USB Voltage Supply
Input HIGH Voltage 1
All ports except USB,
2.0 V < VCC < 3.6 V
0.625 ×
VCC
–
VCC + 0.3
V
VIH2[6]
Input HIGH Voltage 2
All ports except USB,
1.7 V < VCC < 2.0 V
VCC – 0.4
–
VCC + 0.3
VIL
Input LOW Voltage
–0.3
–
0.25 × VCC
V
0.9 × VCC
–
–
V
–
0.1 × VCC
V
VOH
Output HIGH Voltage
IOH(MAX) = –0.1 mA
VOL
Output LOW Voltage
IOL(MIN) = 0.1 mA
IIX
Input Leakage Current
All I/O signals held at VDDQ
–1
–
1
A
IOZ
Output Leakage Current
All I/O signals held at VDDQ
–1
–
1
A
ICC Core
WLCSP package, outputs tristated
Operating Current of Core
Voltage Supply (VDD) and
Analog Voltage Supply (AVDDQ)
–
–
115
mA
ICC Crystal
Operating Current of Crystal
Voltage Supply (XVDDQ) [7]
WLCSP package
–
–
N/A
ICC USB
Operating Current of USB
Voltage Supply (UVDDQ) [7]
Operating and terminated for high
speed mode
–
–
25
ISB1
Total Standby Current of Arroyo 1. *VDDQ = 3.3 V nominal 25 °C
when Device is in Suspend Mode
(3.0–3.6 V)
85 °C
2. Outputs and Bidirs high
or floating[7]
3. XTALOUT floating
4. D+ floating, D– grounded
5. Device in suspend mode
TBD
TBD
TBD
TBD
TBD
TBD
mA
Notes
3. Interfaces with a voltage range are adjustable with respect to the I/O voltage and supports multiple I/O voltages.
4. The SSVDDQ I/O voltage can be dynamically changed (for example, from high range to low range) as long as the supply voltage undershoot does not surpass the
lower minimum voltage limit. SSVDDQ and SNVDDQ levels for SD modes: 2.0 V3.6 V, MMC modes: 1.7 V3.6 V.
5. When U-Port is in a disabled state, UVDDQ can go down to 2.4 V, provided UVDDQ is still the highest supply voltage level.
6. VCC = pertinent VDDQ value.
7. The Outputs and Bidirs that are forced low in standby mode can increase I/O supply standby current beyond specified value.
Active Current Conditions:
-UVDDQ: USB transmitting 50% of the time, receiving 50% of the time.
-PVDDQ/SNVDDQ/SSVDDQ/GVDDQ: Active current depends on I/O activity, bus load and supply level.
Document Number: 001-57458 Rev. *H
Page 14 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 6. DC Specifications for All Voltage Supplies (continued)
Parameter
ISB2
Description
Conditions
Total Standby Current of Arroyo 1. *VDDQ = 3.3 V Nominal 25 °C
when Device is in Standby Mode
(3.0–3.6 V)
85 °C
2. Outputs and Bidirs High
or Floating [7]
Min
Typ
Max
Unit
–
–
52
A
–
–
450
A
–
–
28
A
–
–
139
A
Typ
Max
Unit
–
9
pF
3. XTALOUT Floating
4. D+ Floating,
D– Grounded
ISB3
Total Standby Current of Arroyo
when Device is in Core Power
Down Mode
1. Outputs and Bidirs High 25 °C
or Floating [7]
85 °C
2. XTALOUT Floating
3. D+ Floating,
D– Grounded
4. Core Powered Down
Table 7. Capacitance
Parameter
CIN
COUT
Description
Input Pin Capacitance, Except
D+/D–
Conditions
TA = 25 °C, f = 1 MHz, VCC = VCCIO
Input Pin Capacitance, D+/D–
–
15
Output Pin Capacitance
–
10
Document Number: 001-57458 Rev. *H
pF
Page 15 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
AC Timing Parameters
P Port Interface
PCRAM Non Multiplexing Asynchronous Mode
Table 8. Asynchronous Mode Timing Parameters
Parameter
Description
Min
Max
Unit
Read Timing Parameters
Interface Bandwidth (MBPS)
–
66.7
MBps
tAA
Address to Data Valid
–
30
ns
tOH
Data Output Hold from Address Change
3
–
ns
tEA
Chip Enable to Data Valid
–
30
ns
tAADV
ADV# to Data Valid Access Time
–
30
ns
tAVS
Address Valid to ADV# HIGH
5
–
ns
tAVH
ADV# HIGH to Address Hold
2 [8]
–
ns
tCVS
CE# Low Setup Time to ADV# HIGH
5
–
ns
tVPH
ADV# HIGH Time
15 [9]
–
ns
tVP
ADV# Pulse Width LOW
7.5
–
ns
tOE
OE# LOW to Data Valid
–
22.5
ns
tOLZ
OE# LOW to Low Z
3
–
ns
tOHZ
OE# HIGH to High Z
0
22.5
ns
tLZ
CE# LOW to Low Z
3
–
ns
tHZ
CE# HIGH to High Z
–
22.5
ns
Write Timing Parameters
tCW
CE# LOW to Write End
30
–
ns
tAW
Address Valid to Write End
30
–
ns
tAS
Address Setup to Write Start
0
–
ns
tADVS
ADV# Setup to Write Start
0
–
ns
tWP
WE# Pulse Width
22
–
ns
tWPH
WE# HIGH Time
10
–
ns
tCPH
CE# HIGH Time
10
–
ns
tAVS
Address Valid to ADV# HIGH
5
–
ns
tAVH
ADV# HIGH to Address Hold
2 [8]
–
ns
tCVS
CE# LOW Setup Time to ADV# HIGH
5
–
ns
tVPH
ADV# HIGH Time
15 [9]
–
ns
tVP
ADV# Pulse Width LOW
7.5
–
ns
tVS
ADV# LOW to End of Write
30
–
ns
tDW
Data Setup to Write End
18
–
ns
tDH
Data Hold from Write End
0
–
ns
tWHZ
Write to DQ High Z Output
–
22.5
ns
tOW
End of Write to Low Z Output
3
–
ns
Notes
8. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum tAVH spec. can be relaxed to 0 ns.
9. In applications where access cycle time is at least 60 ns, tVPH can be relaxed to 12 ns.
Document Number: 001-57458 Rev. *H
Page 16 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 5. Non Multiplexing Asynchronous Pseudo CRAM mode Single Read Timing Parameters
A
Valid Address
tAA
tVPH
tAVH
tAVS
tOH
ADV#
tVP
tHZ
tAADV
tCVS
CE#
tEA
tOE
OE#
tOHZ
R/W#
tOLZ
tLZ
DQ
High-Z
Valid Output
Figure 6. Non Multiplexing Asynchronous Pseudo CRAM Mode Back to Back Read Timing Parameters
A
Valid Address
Valid Address
tAA
tVPH
tAVS
tAVH
ADV#
tHZ
tVP
CE#
tAADV
tEA
OE#
tOHZ
WE#
DQ
High-Z
Valid Output
Valid Output
tLZ
Document Number: 001-57458 Rev. *H
Page 17 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 7. Non Multiplexing Asynchronous Pseudo CRAM mode Back to Back Write Timing Parameters
A
Valid Address
tAVS
tVPH
ADV#
Valid Address
tAVH
tVP
tCPH
tVS
CE#
tCW
OE#
tAW
tWPH
tWP
WE#
tAS
DQ_IN
tOW
tDH
tDW
tADVS
High-Z
tLZ
Valid Input
tWHZ
Valid Input
DQ_OUT
Figure 8. Non Multiplexing Asynchronous Pseudo CRAM Mode Read to Write Timing Parameters
Valid Address
A
Valid Address
tAA
tVPH
tAVS
tAVS
tVPH
tAVH
Valid Address
tAVH
tVP
ADV#
tVP
CE#
tVS
tAADV
tEA
tOE
OE#
tOHZ
tAW
tWP
WE#
tAS
DQ_IN
DQ_OUT
High-Z
tOLZ
High-Z
tLZ
Document Number: 001-57458 Rev. *H
tWHZ
tDW
tDH
Valid Input
tOW
Valid Input
Valid Output
Page 18 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 9. Non Multiplexing Asynchronous Pseudo CRAM Mode Write to Read Timing Parameters
A
Valid Address
tAVS
Valid Address
tAA
tAVH
tAVS
tVP
tAVH
ADV#
tVP
tVS
CE#
tAADV
tOE
OE#
tAW
tWP
WE#
tAS
DQ_IN
tWHZ
DQ_OUT
Document Number: 001-57458 Rev. *H
tDW
tDH
Valid Input
tOLZ
Valid Output
Page 19 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Address Data Multiplexing Asynchronous Mode
Table 9. Address Data Multiplexing Asynchronous Mode Timing Parameters
Parameter
Description
Min
Max
Unit
Interface Bandwidth
–
50
MBps
Read Timing Parameters
tAA
Address to Data Valid
–
30
ns
tEA
Chip Enable Access Time
–
30
ns
tAADV
ADV# to Data Valid Access Time
–
30
ns
tAVS
Address Valid to ADV# HIGH
5
–
ns
tAVH
ADV# HIGH to Address Hold
2
–
ns
tCVS
CE# LOW Setup Time to ADV# HIGH
5
–
ns
tVPH
ADV# HIGH Time
15
–
ns
tVP
ADV# Pulse Width LOW
7.5
–
ns
tAVDOE
ADV# HIGH to OE# LOW
0
–
ns
tOE
OE# LOW to Data Valid
–
22.5
ns
tOLZ
OE# LOW to Low Z
3
–
ns
tOHZ
OE# HIGH to High Z
–
22.5
ns
tLZ
CE# LOW to Low Z
3
–
ns
tHZ
CE# HIGH to High Z
–
22.5
ns
Write Timing Parameters
tCW
CE# LOW to Write End
30
–
ns
tAW
Address Valid to Write End
30
–
ns
tAVDWE
ADV# HIGH to Write Start
0
–
ns
tWP
WE# Pulse Width
22
–
ns
tAVS
Address Valid to ADV# HIGH
5
–
ns
tAVH
ADV# HIGH to Address Hold
2
–
ns
tCVS
CE# LOW Setup Time to ADV# HIGH
5
–
ns
tVPH
ADV# HIGH Time
15
–
ns
tVP
ADV# Pulse Width LOW
7.5
–
ns
tVS
ADV# LOW to End of Write
30
–
ns
tDS
Data Setup to Write End
18
–
ns
tDH
Data Hold from Write End
0
–
ns
Document Number: 001-57458 Rev. *H
Page 20 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 10. Address Data Multiplexing Asynchronous Single Read Timing Parameters
tAA
tAVH
tAVS
A<7:0>/
DQ<15:0>
High-Z
Valid Address
tVPH
tAADV
tVP
ADV#
tHZ
tCVS
tLZ
tEA
CE#
tOHZ
tAVDOE tOLZ
OE#
WE#
High-Z
Valid Data
tOE
Logic High
Figure 11. Address Data Multiplexing Asynchronous Single Write Timing Parameters
tAW
tAVS
A<7:0>/
DQ<15:0>
tAVH
tDS
Valid Address
tVPH
Valid Input
tDH
High-Z
tVS
tVP
ADV#
tCVS
CE#
tCW
tAVDWE
WE#
Document Number: 001-57458 Rev. *H
tWP
Page 21 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Asynchronous SRAM Mode Timing Parameters
Table 10. Asynchronous SRAM Mode Timing Parameters
Parameter
Description
Interface Bandwidth (MBps)
Min
Max
Unit
–
66.7
MBps
Read Timing Parameters
tRC
Read Cycle Time
30
–
ns
tAA
Address to Data Valid
–
30
ns
tOH
Data Output Hold from Address Change
3
–
ns
tEA
Chip Enable to Data Valid
–
30
ns
tOE
OE# LOW to Data Valid
–
22.5
ns
tOLZ
OE# LOW to Low Z
3
–
ns
tOHZ
OE# HIGH to High Z
0
22.5
ns
tLZ
CE# LOW to Low Z
3
–
ns
tHZ
CE# HIGH to High Z
–
22.5
ns
Write Timing Parameters
tWC
Write Cycle Time
30
–
ns
tCW
CE# LOW to Write End
30
–
ns
tAW
Address Valid to WE# End
30
–
ns
tAS
Address Setup to WE# or CE# Start
0
–
ns
tAH
Address Hold Time from WE# or CE# End for PCRAM to SRAM Changes (Astoria
is default in PCRAM mode after RESET. This timing is the requirement for the first
time to access the P-Port Interface Configuration Register to change the Astoria to
PSRAM mode)
2
–
ns
Address Hold Time from WE# or CE# End for PSRAM Mode
0
–
tWP
WE# Pulse Width
22
–
ns
tWPH
WE# HIGH Time
10
–
ns
tCPH
CE# HIGH Time
10
–
ns
tDS
Data Setup to Write End
18
–
ns
tDH
Data Hold from Write End
0
–
ns
tWHZ
Write to DQ High Z Output
–
22.5
ns
tOW
End of Write to Low Z Output
tDPW
DRQ# Pulse Width
Document Number: 001-57458 Rev. *H
3
–
ns
110
–
ns
Page 22 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 12. Non Multiplexing Asynchronous SRAM Read Timing Parameters [10]
Endpoint Read – Address Transition Controlled Timing (OE# is asserted )
tRC
ADDRESS
tAA
tOH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
OE# Controlled Timing
ADDRESS
tRC
CE#
tEA
tHZ
OE#
tOHZ
tOE
tOLZ
DATA OUT
HIGH IMPEDANCE
tLZ
DATA VALID
HIGH
IMPEDANCE
Note
10. Errata: When Arroyo is configured to use SRAM for P-port interface, OE should be asserted simultaneously with CE. If this is not possible, OE should be asserted
prior to CE. Otherwise, data can be dropped when external processor reads the Arroyo through SRAM interface. For more information, see the “Errata” on page 50
and “Errata” on page 51.
Document Number: 001-57458 Rev. *H
Page 23 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 13. Non Multiplexing Asynchronous SRAM Write Timing (WE# and CE# Controlled)
Write Cycle 1 WE# Controlled, OE# High During Write
tWC
ADDRESS
tCW
CE#
tAW
WE#
tAH
tWP
tAS
tWPH
OE#
tDS
DATA I/O
tDH
VALID DATA
VALID DATA
tWHZ
Write Cycle 2 CE# Controlled , OE# High During W rite
tWC
ADDRESS
tAS
tCW
tCPH
CE#
tAW
tAH
tWP
WE#
OE#
tDS
DATA I/O
VALID DATA
tDH
VALID DATA
tWHZ
Document Number: 001-57458 Rev. *H
Page 24 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 14. Non Multiplexing Asynchronous SRAM Write Timing (WE# Controlled, OE# LOW)
Write Cycle 3 WE# Controlled. OE# Low
tWC
tCW
CE#
tAW
tAH
tAS
tWP
WE#
tDS
DATA I/O
tDH
VALID DATA
tOW
tWHZ
Pseudo NAND (PNAND) Mode
Table 11. PNAND Mode Parameters
Parameter
Description
Min
Max
Unit
Non LNA Mode Register Write
100
–
ns
Non LNA Mode EP Write
100
–
ns
LNA Mode
tADL
Address to Data Loading Time
450
–
ns
tALH
ALE Hold Time
5
–
ns
tALS
ALE Setup Time
15
–
ns
tAR
ALE to RE# Delay
10
–
ns
tBERS
Block Erase Time
tCEA
CE# Access Time
–
35
ns
tCH
CE# Hold Time
5
–
ns
tCHZ
CE# HIGH to O/P HI-Z
–
40
ns
tCLH
CLE Hold Time
5
–
ns
tCLR
CLE to RE# Time
10
–
ns
tCLS
CLE Setup Time
15
–
ns
tCS
CE# Setup Time
20
–
ns
tDH
Data Hold Time
5
–
ns
tDS
Data Setup Time
15
–
ns
tOH
Data Output Hold Time
15
–
ns
Document Number: 001-57458 Rev. *H
MCU/S-Port NAND
dependent
Page 25 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 11. PNAND Mode Parameters (continued)
Parameter
Description
Program Time for LNA Mode
tPROG
tR
Min
Max
Depends on
MCU/S-Port/NAND
Unit
ns
Program Time for Register Write in Non LNA Mode
130
–
ns
Program Time for EP Write in Non LNA Mode
130
–
ns
Busy Duration during Non LNA Register Read using Page Read
130
–
ns
Busy Duration during Non LNA EP Read using Page Read
130
–
ns
Busy Duration during LNA Page Read (SBD/SLD)
Depends on
MCU/S-Port/NAND
ns
Read Cycle Time (VFBGA Package)
30
–
Read Cycle Time (WLCSP Package)
33
–
RE# for Register Access Time
–
30
ns
RE# for EP Access Time
–
30
ns
tREH
RE# HIGH Hold Time
10
–
ns
tRHW
RE# HIGH to WE LOW
40
–
ns
tRHZ
RE# HIGH to Output HI-Z
–
40
ns
tRP
RE# Pulse Width
15
–
ns
tRR
Ready to RE LOW
20
–
ns
tRC
tREA
Depends on
MCU/S-Port/NAND
ns
tRST
Device Reset Time
tWB
WE# HIGH to Busy
–
100
Write Cycle Time (VFBGA Package)
30
–
Write Cycle Time (WLCSP Package)
33
–
WE# HIGH Hold Time
10
–
ns
WE# HIGH to RE LOW in Non LNA Mode
30
–
ns
WE# HIGH to RE LOW in LNA Mode
450
–
ns
WE# Pulse Width
15
–
ns
tWC
tWH
tWHR
tWP
Document Number: 001-57458 Rev. *H
ns
ns
ns
Page 26 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 15. PNAND Mode Command Latch Cycle
CLE
CE#
tCLS
tCLH
tCS
tCH
tWP
WE#
tALH
tALS
ALE
tDS
tDH
Command
I/Ox
Figure 16. PNAND Mode Address Latch Cycle
CLE
tCLS
tCS
CE#
tWC
tWC
tWP
WE#
tWC
tWP
tWH
tALS
tWC
tWP
tWH
tALS
tWP
tWH
tWH
tALS
tALS
tALS
tALH
ALE
tALH
tDS
I/Ox
Document Number: 001-57458 Rev. *H
tDH
Col.Add1
tALH
tDS
tDH
Col.Add2
tALH
tALH
tDS tDH
tDS
tDH
Row.Add1
Row.Add2
tDS
tDH
Row.Add3
Page 27 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 17. PNAND Mode Input Data Latch Cycle
tCLH
CLE
tCH
CE#
tWC
ALE
tALS
tWP
WE#
tWP
tWP
tWH
tDS
I/Ox
tDH
tDS
DIN 0
tDH
DIN 1
tDS
tDH
DIN final
Figure 18. PNAND Mode Serial Access Cycle After Read
tCEA
tCHZ
CE#
tOH
tREH
tREA
tREA
tREA
RE#
tRHZ
tRHZ
tOH
Dout
I/Ox
tRR
Dout
Dout
tRC
R/B#
Document Number: 001-57458 Rev. *H
Page 28 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 19. PNAND Mode Status Read Cycle
tCLR
CLE
tCLH
tCLS
tCS
CE#
tWP
WE#
tCHZ
tCEA
tOH
tWHR
RE#
tRHZ
tDS
I/Ox
tDH
tIR
tREA
70h
tOH
Status Output
Figure 20. PNAND LBD Read Operation
tCLR
CLE
CE#
tWC
WE#
tWB
tAR
ALE
tR
tRR
tRP
tRC
tRHZ
RE#
Column Address
I/Ox
00h
Col Add1 Col Add2
R/B#
Document Number: 001-57458 Rev. *H
Row Address
Row
Add1
Row
Add2
Row
Add3
Dout N
30h
Dout
N+1
Dout M
Busy
Page 29 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 21. PNAND SBD Read Operation
CLE
CE#
tWC
WE#
tWB
tAR
ALE
tR
tRR
tRP
tRC
tRHZ
RE#
Column
Address
00h, 01h, Col Add1
or *50h
I/Ox
Row Address
Row
Add2
Row
Add1
Row
Add3
R/B#
Dout N
Dout
N+1
Dout M
Busy
* For the Command 50h, A[3:0] in Col Add1 are
valid address and A [7:4] are Don’t care
Document Number: 001-57458 Rev. *H
Page 30 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 22. PNAND Mode LBD Random Data Operation (CASDO)
CLE
tCLR
CE#
WE#
tRHW
tWB
tWHR
tAR
ALE
tR
tRP
tRC
tREA
RE#
tRR
I/Ox
00h
Col Add1 Col Add2
Row
Add1
Column Address
Row
Row
Add2
Add3
Row Address
30h
Dout
N+1
Dout N
05h Col Add1 Col Add2 E0h
Dout M
Dout
M+1
Column Address
Busy
R/B#
Figure 23. PNAND Mode Register Read Using CASDO in 8-Bit Mode
CLE
tCLR
CE#
tCH
WE#
tWHR
ALE
tREA
RE#
05h
I/Ox
R/B#
Col
Col
Add1
Add2
Column Address
E0h
DOUT1 *DOUT2
* This timing diagram shows the 8-bit register read. For 16-bit
register read, DOUT2 is not available
Document Number: 001-57458 Rev. *H
Page 31 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 24. PNAND Mode LBD Read Operation (With CE# Don’t Care)
CLE
CE#
WE#
tWB
ALE
tR
RE#
I/Ox
00h
Col
Add1
Col
Add2
Column Address
Row
Add1
R ow
Add2
Row
Add3
Dout N Dout
N+1
30h
Dout
M
Row Address
Busy
R/B#
CE#
tCEA
tREA
RE#
I/Ox
Document Number: 001-57458 Rev. *H
Dout
Page 32 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 25. PNAND Mode SBD Read Operation (With CE# Don’t Care)
CLE
CE#
WE#
tWB
ALE
tR
RE#
I/Ox
00h
Col
Add1
Column
Address
Row
Add1
Row
Add2
Row
Add3
D out N Dout
N+1
Dout
M
Row Address
Busy
R/B#
CE#
tCEA
tREA
RE#
I/Ox
Document Number: 001-57458 Rev. *H
Dout
Page 33 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 26. PNAND Mode LBD Page Program Operation
CLE
CE#
tWC
WE#
tADL
tWB
tWHR
tPROG
ALE
RE#
Col Col Row Row Row
Din
Din 10
Add1 Add2 Add1 Add2 Add3
N
h
M
1 up to m Byte Program
Serial Data Input Column
Row Address
Address
Serial Input Command
Command
I/Ox
80h
R/B#
M = 2112byte in 8-bit interface
M = 1056 in 16-bit interface
70h
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
Note: tADL is the time from WE rising edge of final address cycle to the WE rising edge of first data cycle
Document Number: 001-57458 Rev. *H
Page 34 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 27. PNAND Mode SBD Page Program Operation
CLE
CE#
tWC
WE#
tADL
tWB
tPROG
ALE
RE#
Column
Address
Col Row Row Row
I/Ox
80h
Add1 Add1 Add2 Add3
Row Address
Serial Data
Input
Command
R/B#
Document Number: 001-57458 Rev. *H
Din
N
1 up to m Byte
Serial Input
Din
M
10h
Program
Command
M = 528 byte in 8-bit interface
M = 264 byte in 16-bit interface
70h
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
Page 35 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 28. PNAND Mode LBD Page Program Operation with Random Data Input (CASDI)
CLE
CE#
tWC
WE#
tADL
tWB tPROG
tWHR
ALE
RE#
Col Col Row Row Row
Add1 Add2 Add1 Add2 Add3
Serial Data Input Column
Row Address
Address
Command
I/Ox
80h
Din
M
Din
N
85h
Col
Col
Add1 Add2
Serial
Input
R/B#
Din
J
Column
Address
Din
K
Serial
Input
10h
70h
Program
Command
Read Status
Command
I/O0
Random Data
Input Command
*Random Programming (CASDI) to endpoint is only supported during logical NAND emulation (LNA mode) of LBD device.
Partial page programming is not supported
Figure 29. PNAND Mode Register Write Using CASDI in 8-Bit Mode
CLE
CE#
tWC
WE#
tADL
ALE
RE#
I/Ox
Col Col
Add1 Add2 DIN1 *DIN2
Serial
Input
Random Data
Input Command
85h
R/B#
* This timing diagram shows the 8-bit register write. For 16-bit
register write, DIN2 should not be available
Document Number: 001-57458 Rev. *H
Page 36 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 30. PNAND Mode LBD Page Program Operation (With CE# Don’t Care)
CLE
CE#
tWC
WE#
tADL
tWB tPROG
tWHR
ALE
RE#
1 up to M Byte
Serial Input
Col Col Row Row Row
Add1 Add2 Add1 Add2 Add3
Serial Data Input Column
Row Address
Address
Command
I/Ox
80h
Din
N
Din
M
10h
70h
Program
Command
M = 2112 byte in 8-bit interface
M = 1056 byte in 16-bit interface
Note: tADL is the time from WE rising edge of final
address cycle to the WE rising edge of first data cycle
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
R/B#
CE#
I/O0
tCS
tCH
tWP
WE#
Document Number: 001-57458 Rev. *H
Page 37 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 31. PNAND Mode SBD Page Program Operation (With CE# Don’t Care)
CLE
CE#
tWC
WE#
tADL
tWB
tPROG
ALE
RE#
Column
Address
Col Row Row Row
I/Ox
80h
Add1 Add1 Add2 Add3
Row Address
Serial Data
Input
Command
R/B#
Din
N
1 up to m Byte
Serial Input
Din
M
10h
70h
Program
Command
M = 528 byte in 8-bit interface
M = 264 byte in 16-bit interface
CE#
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tCS
tCH
tWP
WE#
Document Number: 001-57458 Rev. *H
Page 38 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 32. PNAND Mode Block Erase Operation
CLE
CE#
tWC
WE#
tWB
ALE
tBERS
RE#
I/Ox
R/B#
60h
Row
Row
Row
Add1
Add2
Add3
Row Address
D0h
70h
Busy
Erase Command
Auto Block Erase
Setup Command
I/O 0
Read Status I/O0=0 Successful Erase
Command
I/O0=1 Error in Erase
Figure 33. PNAND Mode Multi-Blocks (up to 4) Erase
CLE
CE#
tWC
WE#
tWB
tBERS
ALE
RE#
2nd and 3 rd
Block Erase
st
I/Ox
60h
1 Block Erase
Row
Row
Row
Add1
Add2
Add3
D0h
60h
4 th Block Erase
Row
Row
Row
Add1
Add2
Add3
R/B#
Auto Block Erase
Setup Command
D0h
70h
I/O 0
Row Address
Row Address
Erase Command Auto Block Erase
Setup Command
Erase Command
Busy
Read Status
Command
I/O 0= 0 Successful Erase
I/O0=1 Error in Erase
Note: The multi-block erase can support up to 4 blocks erase
Document Number: 001-57458 Rev. *H
Page 39 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 34. PNAND Mode Read ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tREA
I/Ox
90h
Read ID Command
00h
Byte 0
Byte 1
Address 1cycle
Byte 2
Byte 3
Byte 4
Byte 5
Can up to six bytes
Byte 0 – Byte 5 are the values of registers of PNAD_RD_ID0 to PNAND_RD_ID5.
Figure 35. PNAND Mode Read ID2 Operation
CLE
CE#
WE#
tAR
ALE
RE#
tREA
I/Ox
91h
Read ID Command
Document Number: 001-57458 Rev. *H
00h
Ext_ID
Address 1cycle
Page 40 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 36. PNAND Mode Reset Operation
CLE
CE#
tWB
WE#
tRST
R/B#
FFh
I/Ox
Table 12. SPI Mode Parameters
Parameter
Description
fOP
Operating frequency
tCYC
Cycle time
Min
Max
Units
0
26
MHz
38.5
–
ns
tLead
Enable lead time
19.23
–
ns
tLag
Enable lag time
19.23
–
ns
tSCKH
Clock high time
17.33
–
ns
tSCKL
Clock low time
17.33
–
ns
tSU
Data setup time (inputs)
–
7
ns
tH
Data hold time (inputs)
–
7
ns
tV
Data valid time, after enable edge
–
18
ns
tHO
Data hold time, after enable edge
0
–
ns
Document Number: 001-57458 Rev. *H
Page 41 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 37. SPI Timing Diagram
SS#
tCYC
tLag
tSCKL
SCK
tSCKH
tLead
MISO
(MSB) BIT-7 OUT
tSU
tH
tV
(MSB)
BIT-7 IN
MOSI
(LSB) BIT-7 OUT
BIT-6 OUT
tHO
BIT-6 IN
Note
tHO
(LSB)
BIT-0 IN
Note: Not defined but normal MSB of character just received
Table 13. PI2C Interface Standard Mode Parameters
Parameter
Description
Min
Max
Units
0
82
kHz
Bus Free Time (between stop and start conditions)
4.7
–
µs
tHD:STA
Hold Time After (Repeated) Start Condition. After this period the first clock is
generated
4.0
–
µs
F
Operating Frequency
tBUF
tSU:STA
Repeated Start Condition Setup Time
4.7
–
µs
tSU:STO
Stop Condition Setup Time
4.0
–
µs
tHD:DAT
Data Hold Time
0
–
ns
tSU:DAT
Data Setup Time
250
tTIMEOUT
Detect Clock Low Timeout
tLOW
Clock Low Period
4.7
–
µs
tHIGH
Clock High Period
4.0
–
µs
tLOW:SEXT
Cumulative Clock Low Extend Time (slave device)
tr
Rise Time
–
1000
ns
tf
Fall Time
–
300
ns
Document Number: 001-57458 Rev. *H
–
NA
ns
ms
NA
ms
Page 42 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 14. PI2C Interface Fast Mode Parameters
Parameter
Description
Min
Max
Units
F
Operating Frequency
0
312
kHz
tBUF
Bus Free Time (between stop and start condition)
1.3
–
µs
tHD:STA
Hold Time after (Repeated) Start Condition. After this period the first clock is
generated
0.6
–
µs
tSU:STA
Repeated Start Condition Setup Time
0.6
–
µs
tSU:STO
Stop Condition Setup Time
0.6
–
µs
tHD:DAT
Data Hold Time
0
0.9
ns
tSU:DAT
Data Setup Time
100
–
ns
tTIMEOUT
Detect Clock Low Timeout
tLOW
Clock Low Period
1.3
tHIGH
Clock High Period
0.6
tLOW:SEXT
Cumulative Clock Low Extend Time (slave device)
tr
Rise Time
–
300
ns
tf
Fall Time
–
300
ns
NA
ms
–
–
NA
µs
µs
ms
Figure 38. PI2C Timing Diagram
tf
70%
SDA
50%
30%
tr
SCL
tBUF
tHIGH
70%
tSU;DAT
50%
tLOW
tHD;STA
50%
30%
tHD;DAT
tSU;STA
S
Other P-Port Timings
DRQ# Min Pulse Width (tDPW): The minimum duration that
DRQ# is deasserted following a DRQ acknowledgement (clear
of DMAVAL) is 110 ns in Async mode or five P-Port clock (CLK)
cycles in Sync mode.
Same Register Write-to-Read Holdoff (tWRHO): A read of a
particular register must wait for a holdoff period following a write
operation to that same register address to ensure that valid
updated data is read. In Async mode, this holdoff time is 150 ns.
In Sync mode, this holdoff time is seven P-Port clock (CLK)
cycles.
tHD;STA
tSU;STO
Sr
P
S
before the update is reflected in a subsequent read operation.
This holdoff time is identical to the tWRHO.
S Port Interface AC Timing Parameters
SD/MMC/MMC+ Timing Parameters
For all conditions, SD/MMC data is driven and sampled on the
rising edge of SD_CLK. Note that CE-ATA electrical and timing
parameters are equivalent to MMC.
Register Update-to-Read Holdoff (tURHO): Same status
registers are updated as side effect from accesses to other
registers. For example, clearing the DMAVAL field automatically
clears the associated endpoint buffer bit within the DRQ status
register. A holdoff time must elapse from the first register access
Document Number: 001-57458 Rev. *H
Page 43 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 39. SD/MMC+ Timing Waveform — All Modes
tSDCLKH
tSDCLK
SD_CLK
tSDCLKL
SD_CMD/
SD_D0-D3
tSDOS
tSDCKLZ
tSDOH
tSDCKHZ
Output
SD_CMD/
SD_D0-D3
Input
tSDIS tSDIH
Table 15. Common Timing Parameters for SD/MMC+ – During Identification Mode
Parameter
Description
Min
Max
Units
0
400
kHz
Clock Period
2.5
–
µs
Clock High Time
1.0
–
µs
Clock Low Time
1.0
–
µs
Min
Max
Units
5
48
MHz
20.8
200
ns
40
60
%
SDFREQ
SD_CLK Interface Clock Frequency
tSDCLK
tSDCLKH
tSDCLKL
Table 16. Common Timing Parameters for SD/MMC+ – During Data Transfer Mode
Parameter
Description
SDFREQ
SD_CLK Interface Clock Frequency
tSDCLK
Clock Period
tSDCLKOD
Clock Duty Cycle
tSCLKR
Clock Rise Time
–
3
ns
tSCLKF
Clock Fall Time
–
3
ns
Min
Max
Units
Table 17. Timing Parameters for SD – All Modes
Parameter
Description
tSDIS
Input Setup Time
4
–
ns
tSDIH
Input Hold Time
2.5
–
ns
tSDOS
Output Setup Time
7
–
ns
tSDOH
Output Hold Time
6
–
ns
tSDCKHZ
Clock to Data High Z
–
18
ns
tSDCKLZ
Clock to Data Low Z
3
–
ns
Document Number: 001-57458 Rev. *H
Page 44 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 18. Timing Parameters for MMC+ – All Modes
Parameter
Description
Min
Max
Units
tSDIS
Input Setup Time
4
–
ns
tSDIH
Input Hold Time
4
–
ns
tSDOS
Output Setup Time
6
–
ns
tSDOH
Output Hold Time
6
–
ns
tSDCKHZ
Clock to Data High Z
–
18
ns
tSDCKLZ
Clock to Data Low Z
3
–
ns
Reset and Standby Timing Parameters
The Arroyo reset mechanism is described in this section. The
standby mode is also described.
Minimum RESET# pulse width (tRPW): 5 ms when a crystal is
used as clock or 1 ms when an external clock is used.
Minimum WAKEUP pulse width (tWPW): 5 ms.
Sleep Time (tSLP): The maximum time from deassertion of
WAKEUP to when Arroyo enters low power state (sleep mode)
is 1 ms.
Minimum HIGH on RESET# and WAKEUP (tRH, tWH): The
WAKEUP and RESET# pins must be held HIGH for a minimum
of 5 ms.
Wakeup Time (tWU): The minimum time from assertion of
WAKEUP pin (or initial power on with WAKEUP HIGH) to when
any register operation is conducted is 1 ms if an external clock
is present, or 5 ms if a crystal is used. The
CY_AN_MEM_PWR_MAGT_STAT.WAKEUP field can only be
polled after wakeup time following reset deassertion or WAKEUP
assertion.
Reset Recovery Time (tRR): A minimum 1 ms reset recovery
time must be allowed before Arroyo registers can be accessed
for read or write.
Figure 40. Reset and Standby Timing Diagram
Core
Power-Down
VDD
(core)
VDDQ
(I/O)
XTALIN up & stable
before WAKEUP
asserted
XTALIN
tWPW
tWH
WAKEUP
Mandatory
Reset Pulse
RESET#
RESETOUT
Standby
Mode
Hard Reset
Firmware Init
Complete
Mandatory
Reset Pulse
tRH
Firmware Init
Complete
Firmware Init
Complete
High-Z
tRPW
tSLP
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘0’
Document Number: 001-57458 Rev. *H
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘1’
CY_AN_MEM_PMU_UPDATE.UVALID
bit is set to ‘0’
Page 45 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Table 19. Reset and Standby Timing Parameters
Parameter
Description
Conditions
Min
Max
Units
tSLP
Sleep Time
tWU
Wakeup Time from Standby
Mode
5
–
ms
tWH
WAKEUP High Time
5
–
ms
tWPW
WAKEUP Pulse Width
5
–
ms
tRH
RESET# High Time
5
–
ms
tRPW
RESET# Pulse Width
Clock on XTALIN
1
–
ms
Crystal on XTALIN-XTALOUT
5
–
ms
1
–
ms
tRP
RESET# Recovery Time
Clock on XTALIN
Crystal on XTALIN-XTALOUT
–
1
ms
1
–
ms
Figure 41. AC Test Loads and Waveforms (Except SD and MMC, SD and MMC are comply with the SD/MMC specification)
Document Number: 001-57458 Rev. *H
Page 46 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Ordering Information
For ordering information, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com
and refer to the product summary page at http://www.cypress.com/products.
Table 20. Device Ordering Information
Ordering Code
Package Type
Clock Input Frequencies (MHz)
Status
CYWB0320ABX-FDXIT
81-pin WLCSP (Pb-free)
26
Production
Release
CYWB0321ABX-FDXIT
81-pin WLCSP (Pb-free)
19.2, 26
Sample
Ordering Code Definitions
CY WB 03 XX ABX -
FD
X
I
T
T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type:
FD = 81-pin WLCSP
Pin Count
Part Number: XX = 20 or 21
Family Code
Technology Code: WB = West Bridge
Company ID: CY = Cypress
Document Number: 001-57458 Rev. *H
Page 47 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Package Diagram
Figure 42. Astoria 81-pin WLCSP (3.91 × 3.91 × 0.55 mm) FN81B Package Outline, 001-45618
BOTTOM VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
9
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
SIDE VIEW
001-45618 *C
Document Number: 001-57458 Rev. *H
Page 48 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CE
Chip Enable
ESD
Electrostatic Discharge
°C
degree Celsius
I/O
Input/Output
mA
milliampere
LSB
Least Significant Bit
MHz
megahertz
MSB
Most Significant Bit
µA
microampere
OE
Output Enable
µF
microfarad
RE
Read Enable
µs
microsecond
SPI
Serial Peripheral Interface
µW
microwatt
USB
Universal Serial Bus
ms
millisecond
WE
Write Enable
mV
millivolt
WLCSP
Wafer Level Chip Scale Package
mW
milliwatt
ns
nanosecond
Document Number: 001-57458 Rev. *H
Symbol
Unit of Measure
ppm
parts per million
pF
picofarad
V
volt
W
watt
Page 49 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Errata
This section describes the errata for West Bridge Arroyo USB and Mass Storage Peripheral Controller, CYWB0320ABX-FDXI. Details
include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Package Type
Operating Range
CYWB0320ABX-FDXI
81-pin WLCSP
Industrial
Arroyo Qualification Status
Product Status: In Production
Arroyo Errata Summary
The following table defines the errata applicability to available Arroyo family devices. An “X” indicates that the erratum pertains to the
selected device.
Items
CYWB0320ABX-FDXI
Revision
Fix Status
1. P-Port SRAM mode fails if OE and CE are
not asserted simultaneously.
[X]
A
–
1. P-Port SRAM mode fails if OE and CE are not asserted simultaneously
■
Problem Definition
When Arroyo is configured to use SRAM for P-port interface, OE should be asserted simultaneously with CE. If this is not possible,
OE should be asserted prior to CE.
■
Parameters Affected
Data can be dropped when external processor reads the Arroyo through SRAM interface.
■
Trigger Condition(S)
When Arroyo P-port is configured in SRAM mode and if OE and CE don’t happen at the same time.
■
Scope of Impact
NIL
■
Workaround
The workaround available at this time include asserting OE and CE at the same time and asserting OE prior to CE.
■
Fix Status
NIL.
Document Number: 001-57458 Rev. *H
Page 50 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Errata
This section describes the errata for West Bridge Arroyo USB and Mass Storage Peripheral Controller, CYWB0321ABX-FDXI. Details
include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Package Type
Operating Range
CYWB0321ABX-FDXI
81-pin WLCSP
Industrial
Arroyo Qualification Status
Product Status: In Production
Arroyo Errata Summary
The following table defines the errata applicability to available Arroyo family devices. An “X” indicates that the erratum pertains to the
selected device.
Items
CYWB0321ABX-FDXI
Revision
Fix Status
[X]
A
Fixed in SDK in version
1.0 or later
1. P-Port PSPI mode fails U-Port to P-Port
transfer after wake up from STANDBY
mode.
1. P-Port PSPI mode fails U-Port to P-Port transfer after wake up from STANDBY mode
■
Problem Definition
When Arroyo is configured to use SPI for Processor-Port (P-Port) interface, transfers from U-Port to P-Port may intermittently fail after
wakeup from STANDBY mode.
■
Parameters Affected
Intermittent failure in U-Port to P-Port transfer after wakeup from STANDBY.
■
Trigger Condition(S)
The condition occurs when Arroyo is configured for PSPI mode and wakes up from STANDBY mode.
■
Scope of Impact
When Arroyo is configured to use SPI for Processor-Port (P-Port) interface, transfers from U-Port to P-Port may intermittently fail after
wakeup from STANDBY mode.
■
Workaround
SDK version 1.0 or later provides the software workaround for this issue. The workaround requires using version 1.0 or later of the
SDK for the system software development.
The workaround fixes the intermittent failure as described in Problem Definition. However, the workaround cause wakeup time (from
STANDBY mode) to increase. This duration increase depends upon the system configuration as listed in the following table:
Arroyo System Configuration
Additional Wakeup Time (from STANDBY mode)
Using external crystal
5 ms
Using external oscillator
1 ms
Firmware image is loaded from EEPROM (through I2C™)
> 250 ms depending on the firmware image size and the I2C
frequency
This errata only affects Arroyo when the P-Port is configured for SPI mode.
■
Fix Status
Fixed in SDK version 1.0 or later.
Document Number: 001-57458 Rev. *H
Page 51 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Document History Page
Document Title: CYWB0320ABX-FDXI/CYWB0321ABX-FDXI, West Bridge®: Arroyo USB and Mass Storage Peripheral
Controller
Document Number: 001-57458
Revision
ECN
Orig. of
Change
Submission
Date
**
2846580
SHIN /
AESA
01/12/2010
New data sheet.
*A
2902575
STVC
03/31/2010
Updated Pin Assignments (Updated Table 4).
Updated AC Timing Parameters (Added PCRAM Non Multiplexing
Asynchronous Mode subsection).
Changed status from Advance to Final.
Updated links in Sales, Solutions, and Legal Information.
*B
3207801
ANOP
03/28/2011
Updated Pin Assignments (In Table 4, changed R/B# from ‘I’ to ‘O’ in the ‘I/O'
column corresponding to ‘PNAND’, changed ‘A7 or SDA’ to ‘A6 or SDA’ in the
‘Pin Description’ column corresponding to Ball H1, changed ‘A6 or SCL’ to ‘A5
or SCL’ in the ‘Pin Description’ column corresponding to Ball F2, changed
SD_CLK from ‘I/O’ to ‘O’ in the ‘I/O' column corresponding to 'S-Port
Interface’.).
*C
3499405
RSKV
01/17/2012
Updated title to read as “CYWB0320ABX-FDXI/CYWB0321ABX-FDXI, West
Bridge®: Arroyo USB and Mass Storage Peripheral Controller”.
Updated Features.
Updated Functional Overview (Updated the subsection Processor Interface
(P-Port) (description), updated the subsection Clocking (description, updated
Table 1 and added Table 2).
Updated Pin Assignments (Updated Table 4 and added Table 5, updated
caption of Figure 3 and added Figure 4).
Updated AC Timing Parameters (Added Table 12 and Figure 37).
Added Ordering Information.
Replaced Arroyo-II with Arroyo across the document.
Updated to new template.
*D
3539329
RSKV
03/01/2012
Removed the tag “Company Confidential” from the header.
Revised package diagram spec.
Moving to external web.
*E
3878676
RSKV
01/21/2013
No technical updates.
Completing Sunset Review.
*F
3978102
RSKV
04/22/2013
Added Acronyms and Units of Measure.
Added Errata.
Added Errata.
*G
4072903
RSKV
07/22/2013
Added Errata footnotes (Note 1, 2, 10).
Description of Change
Updated Pin Assignments:
Added Note 1 and referred the same note in “SRAM Interface” column in
Table 4.
Added Note 2 and referred the same note in “SPI” column in Table 5.
Updated AC Timing Parameters:
Updated P Port Interface:
Updated Asynchronous SRAM Mode Timing Parameters:
Added Note 10 and referred the same note in Figure 12.
Updated to new template.
Document Number: 001-57458 Rev. *H
Page 52 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Document History Page (continued)
Document Title: CYWB0320ABX-FDXI/CYWB0321ABX-FDXI, West Bridge®: Arroyo USB and Mass Storage Peripheral
Controller
Document Number: 001-57458
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*H
4583918
GAYA
12/01/2014
Updated Features:
Replaced “Supports I2C Boot and Processor Boot” with “Supports USB Boot,
I2C Boot and Processor Boot”.
Updated Ordering Information:
Updated part numbers.
Included a column “Status” and added details in that column.
Completing Sunset Review.
Document Number: 001-57458 Rev. *H
Page 53 of 54
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-57458 Rev. *H
Revised December 1, 2014
Page 54 of 54
West Bridge is the registered trademark and Astoria, Antioch, and SLIM are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be
the trademarks of their respective holders.