CY62146E MoBL® 4-Mbit (256K x 16) Static RAM Features ■ Very high speed: 45 ns mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: ■ Wide voltage range: 4.5V–5.5V ■ Deselected (CE HIGH) ■ Ultra low standby power ❐ Typical standby current: 1 μA ❐ Maximum standby current: 7 μA ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) ■ Write operation is active (CE LOW and WE LOW) ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Available in Pb-free 44-pin TSOP II package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See Table 1 for a complete description of read and write modes. Functional Description The CY62146E is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 256K x 16 RAM Array IO0–IO7 IO8–IO15 • BHE WE CE OE BLE A17 A15 A16 A13 A14 A11 Cypress Semiconductor Corporation Document Number: 001-07970 Rev. *D A12 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 01, 2008 [+] Feedback CY62146E MoBL® Pin Configuration Figure 1. 44-Pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12 Product Portfolio Power Dissipation Product CY62146ELL VCC Range (V) Range Ind’l/Auto-A Speed (ns) Min Typ[2] Max 4.5 5.0 5.5 Operating ICC, (mA) f = 1 MHz Typ 45 2 [2] f = fmax Standby, ISB2 (μA) Max Typ [2] Max Typ [2] Max 2.5 15 20 1 7 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document Number: 001-07970 Rev. *D Page 2 of 11 [+] Feedback CY62146E MoBL® DC Input Voltage [3, 4] .......................................–0.5V to 6.0V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage to Ground Potential..................–0.5V to 6.0V Device DC Voltage Applied to Outputs in High-Z State [3, 4] ..........................................–0.5V to 6.0V CY62146ELL Ambient Temperature Range VCC [5] Ind’l/Auto-A –40°C to +85°C 4.5V–5.5V Electrical Characteristics Over the Operating Range 45 ns (Ind’l/Auto-A) Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –1.0 mA VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage 4.5 < VCC < 5.5 VIL Input LOW Voltage 4.5 < VCC < 5.5 GND < VI < VCC Typ [2] Max Unit 2.4 IIX Input Leakage Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current ISB2 [6] Min f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA, CMOS levels f = 1 MHz Automatic CE Power CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, down Current — CMOS f = 0, VCC = VCC(max) Inputs V 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V –1 +1 μA –1 +1 μA 15 20 mA 2 2.5 1 7 μA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF TSOP II Unit 77 °C/W 13 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two layer printed circuit board Notes 3. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization. 6. Only chip enable (CE) and byte enables (BHE and BLE) is tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs are left floating. Document Number: 001-07970 Rev. *D Page 3 of 11 [+] Feedback CY62146E MoBL® Figure 2. AC Test Loads and Waveforms R1 VCC VCC OUTPUT 30 pF 10% GND R2 Rise Time = 1 V/ns INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V TH Parameters 5.0V Unit R1 1800 Ω R2 990 Ω RTH 639 Ω VTH 1.77 V Data Retention Characteristics Over the Operating Range Parameter Conditions VCC for Data Retention VDR ICCDR Description [6] Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8] Operation Recovery Time Min Typ[2] Max 2 VCC = 2V, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Unit V 1 7 μA 0 ns tRC ns Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 2.0V tCDR VCC(min) tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. Document Number: 001-07970 Rev. *D Page 4 of 11 [+] Feedback CY62146E MoBL® Switching Characteristics Over the Operating Range [9, 10] Parameter Description 45 ns (Ind’l/Auto-A) Min Max Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to LOW-Z[11] tHZOE OE HIGH to High-Z[11, 12] ns 45 10 ns ns 45 22 5 ns ns ns 18 ns CE LOW to Low-Z[11] tHZCE CE HIGH to High-Z[11, 12] tPU CE LOW to Power Up tPD CE HIGH to Power Down 45 ns tDBE BLE/BHE LOW to Data Valid 22 ns 18 ns tLZCE Low-Z[11] tLZBE BLE/BHE LOW to tHZBE BLE/BHE HIGH to HIGH-Z[11, 12] 10 ns 18 0 ns ns 5 ns Write Cycle [13] tWC Write Cycle Time 45 ns tSCE CE LOW to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tBW BLE/BHE LOW to Write End 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns High-Z[11, 12] tHZWE WE LOW to tLZWE WE HIGH to Low-Z[11] 18 10 ns ns Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4. 10. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 11. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document Number: 001-07970 Rev. *D Page 5 of 11 [+] Feedback CY62146E MoBL® Switching Waveforms Figure 4. Read Cycle No.1: Address Transition Controlled. [14, 15] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [15, 16] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE HIGH IMPEDANCE HIGHIMPEDANCE DATA VALID DATA OUT tLZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Notes 14. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 15. WE is HIGH for read cycle. 16. Address valid before or similar to CE, BHE, BLE transition LOW. Document Number: 001-07970 Rev. *D Page 6 of 11 [+] Feedback CY62146E MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No 1: WE Controlled [13, 17, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA IO tSD NOTE 19 tHD DATAIN tHZOE Figure 7. Write Cycle 2: CE Controlled [13, 17, 18] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD DATAIN NOTE 19 tHZOE Notes 17. Data IO is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period, the IOs are in output state. Do not apply input signals. Document Number: 001-07970 Rev. *D Page 7 of 11 [+] Feedback CY62146E MoBL® Switching Waveforms (continued) Figure 8. Write Cycle 3: WE controlled, OE LOW [18] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA IO NOTE 19 tHD DATAIN tLZWE tHZWE Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [18] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA IO NOTE 19 tSD tHD DATAIN tLZWE Document Number: 001-07970 Rev. *D Page 8 of 11 [+] Feedback CY62146E MoBL® Table 1. Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby (ISB) L X X H H High-Z Output Disabled Active (ICC) L H L L L Data Out (IO0–IO15) Read Active (ICC) L H L H L Data Out (IO0–IO7); IO8–IO15 in High-Z Read Active (ICC) L H L L H Data Out (IO8–IO15); IO0–IO7 in High-Z Read Active (ICC) L H H L L High-Z Output Disabled Active (ICC) L H H H L High-Z Output Disabled Active (ICC) L H H L H High-Z Output Disabled Active (ICC) L L X L L Data In (IO0–IO15) Write Active (ICC) L L X H L Data In (IO0–IO7); IO8–IO15 in High-Z Write Active (ICC) L L X L H Data In (IO8–IO15); IO0–IO7 in High-Z Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type Operating Range CY62146ELL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free) Industrial CY62146ELL-45ZSXA 51-85087 44-pin Thin Small Outline Package II (Pb-free) Automotive-A Contact your local Cypress sales representative for availability of these parts. Document Number: 001-07970 Rev. *D Page 9 of 11 [+] Feedback CY62146E MoBL® Package Diagrams Figure 10. 44-Pin TSOP II, 51-85087 51-85087-*A Document Number: 001-07970 Rev. *D Page 10 of 11 [+] Feedback CY62146E MoBL® Document History Page Document Title: CY62146E MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 001-07970 REV. ECN NO. Issue Date Orig. of Change ** 463213 See ECN NXR New Data Sheet *A 684343 See ECN VKN Added Preliminary Automotive-A Information Updated Ordering Information Table *B 925501 See ECN VKN Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters VKN Converted Automotive-A specs from preliminary to final *C 1045260 See ECN *D 2073548 See ECN Description of Change VKN/AESA Corrected typo in the Data Retention Waveform and removed its irrelevant footnote © Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Document Number: 001-07970 Rev. *D Revised February 01, 2008 Page 11 of 11 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback