62 CY29962 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer Features • • • • • • • • • • • • • 2.5V or 3.3V operation Output frequency up to 150MHz Supports PowerPC ® and Pentium® processors 21 clock outputs: drive up to 42 clock lines LVPECL or LVCMOS/LVTTL clock input Output-to-output skew < 150 ps Split 2.5V/3.3V outputs Spread-spectrum-compatible Glitch-free output clocks transitioning Output disable control Pin-compatible with MPC9600 Industrial temperature range: –40°C to +85°C 48-pin TQFP package Table 1. Frequency Table[1] SELA QA SELB QB SELC QC FB_SEL FB_OUT 0 VCO/2 0 VCO/2 0 VCO/2 0 VCO/8 1 VCO/4 1 VCO/4 1 VCO/4 1 VCO/12 Block Diagram 1 2 3 SELB 4 5 C 0 1 DQ VDDA QA6 QA5 QA4 VSSA QA3 QA2 VDDA C Y29962 VSSA FB_O U T Q B0 Q B1 VD D B Q B2 Q B3 VSSB Q B4 Q B5 Q B6 VD D B 13 14 15 16 17 18 19 20 21 22 23 24 6 0 1 VSSB 1 36 35 34 33 32 31 30 29 28 27 26 25 QC0 6 0 QC1 DQ QC2 B 0 1 VDDC 5 1 2 3 4 5 6 7 8 9 10 11 12 VSS T C LK PEC L_C LK PEC L_C LK# VD D R EF_SEL F B_SEL AVD D SELA SELB SELC VSSC QC3 4 QC4 FB_IN SELA 48 47 46 45 44 43 42 41 40 39 38 37 VSSC 2 3 QA1 0 QC5 DQ QC6 1 0 1 OE# REF FB /2 /4 /8 /12 VDDC 0 1 0 VSS A PLL QA0 AVDD REF_SEL TCLK PECL_CLK PECL_CLK# FB_IN Pin Configuration 2 3 SELC 4 5 6 OE# FB 0 1 DQ FB_OUT FB_SEL Note: 1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1) or 25 MHz to 50 MHz (FB_SEL = 0). Cypress Semiconductor Corporation Document #: 38-07364 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 26, 2002 CY29962 Pin Description[2] Pin Name PWR I/O Description 3 PECL_CLK I, PD PECL clock input 4 PECL_CLK# I, PU PECL clock input 2 TCLK I, PD External reference/test clock input 38, 39, 40, 42, QA(6:0) 43, 45, 46 VDDA 26, 27, 28, 30, QB(6:0) 31, 33, 34 VDDB 15, 16, 18, 19, QC(6:0) 21, 22, 23 VDDC 35 FB_OUT O O O VDD O Clock Outputs. See Table 1 for frequency selections. Clock Outputs. See Table 1 for frequency selections. Clock Outputs. See Table 1 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. 9 SELA I, PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:6) outputs. See Table 1. 10 SELB I, PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:6) outputs. See Table 1. 11 SELC I, PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:6) outputs. See Table 1. 7 FB_SEL I, PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. 47 FB_IN 6 REF_SEL 14 OE# 37, 44 VDDA Power supply for Bank A clock buffers 25, 32 VDDB Power supply for Bank B clock buffers 13, 20 VDDC Power supply for Bank C clock buffers 5 VDD Power supply for core 8 AVDD Power Supply for PLL. When AVDD is set LOW, PLL is bypassed. 36, 41 VSSA Common ground for Bank A 24, 29 VSSB Common ground for Bank B 12, 17 VSSC Common ground for Bank C 1, 48 VSS Common ground I, PD Feedback Clock Input. Connect to FB_OUT for accessing the PLL. I, PU Reference Select Input. When HIGH, the PECL clock is selected. When LOW, TCLK is the reference clock. Output Enable Input. When asserted LOW, enables all of the outputs. I, PD When pulled HIGH, disables to high impedance all of the outputs except FB_OUT. Table 2. Function Table Control Pin 0 1 REF_SEL TCLK PECL_CLK AVDD PLL Bypass, outputs controlled by OE# PLL power OE# Outputs Enabled Outputs Disabled (except FB_OUT) SELA Output Bank A at VCO/2 Output Bank A at VCO/4 SELB Output Bank B at VCO/2 Output Bank B at VCO/4 SELC Output Bank C at VCO/2 Output Bank C at VCO/4 FB_SEL Feedback Output at VCO/8 Feedback Output at VCO/12 Note: 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07364 Rev. *B Page 2 of 7 CY29962 Description Zero Delay Buffer The CY29962 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of seven outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 400 MHz. This allows a wide range of output frequencies up to 150 MHz. When used as a zero delay buffer, the CY29962 will likely be in a nested clock tree application. For these applications the CY29962 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The CY29962 can then lock onto the LVPECL reference and translate with near zero delay to low-skew outputs. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL select inputs (see Table 1). The VCO frequency is then divided down to provide the required output frequencies. By using one of the outputs as a feedback to the PLL, the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge, thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock, the Tpd of the CY29962 is a function of the configuration used. Document #: 38-07364 Rev. *B Page 3 of 7 CY29962 Maximum Ratings[3] Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection ............................................... 2 kV VSS < (VIN or VOUT) < VDD. Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Current:..................................................±20 mA Table 3. DC Parameters VDD = 2.5V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit 0.7 V VIL[4] VIH[4] Input LOW Voltage Input HIGH Voltage 1.7 VDD V VPP Peak-to-Peak Input Voltage PECL_CLK 500 1000 mV VCMR[5] Common Mode Range PECL_CLK VDD – 1.4 VDD – 0.6 V IIL[6] IIH[6] VOL[7] VOH[7] Input LOW Current (@ VIL = VSS) –120 µA 120 µA 0.6 V VSS Input HIGH Current (@ VIH = VDD) Output LOW Voltage IOL = 15 mA Output HIGH Voltage IOH = –15 mA IDD Quiescent Supply Current VDD and AVDD CIN Input Pin Capacitance 1.8 V 10 13 mA 4 pF Table 4. DC Parameters VDD = 3.3V ±5%, TA = –40°C to +85°C Max. Unit VIL[3] Parameter Input LOW Voltage VSS 0.8 V VIH[3] Input HIGH Voltage 2.0 VDD V Peak-to-Peak Input Voltage PECL_CLK 500 1000 mV VDD – 1.4 VPP [5] Description Conditions Typ. VDD – 0.6 V IIL[6] Input LOW Current (@ VIL = VSS) –120 µA IIH[6] Input HIGH Current (@ VIH = VDD) 120 µA VOL[7] VOH[7] Output LOW Voltage 0.55 V IDD Quiescent Supply Current 20 mA CIN Input Pin Capacitance VCMR Common Mode Range PECL_CLK Min. Output HIGH Voltage IOL = 24mA IOH = –24mA VDD and AVDD 2.4 V 15 4 pF Notes: 3. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. The LVCMOS inputs threshold is at 30% of VDD. 5. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input lies within the VPP specification. 6. Inputs have pull-up/pull-down resistors that affect input current. 7. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07364 Rev. *B Page 4 of 7 CY29962 Table 5. AC Parameters VDD = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C[8] Parameter Fref Description Conditions Reference Input Frequency Min. Typ. Max. Unit MHz FB_SEL = 1 16 33 FB_SEL = 0 25 50 FrefDC Reference Input Duty Cycle 25 75 % Fvco PLL VCO Lock Range 200 400 MHz Tlock Maximum PLL lock Time 10 ms Tr/Tf Output Clocks Rise/Fall Time[9,10] 0.1 1.0 ns 100 150 MHz 0.55V to 2.0V, VDD = 3.3V 0.5V to 1.8V, VDD=2.5V Fout Maximum Output Frequency FoutDC Output Duty Cycle[9,10] Q (÷2) Q (÷4) Output Enable Time (all outputs) tpLZ, tpHZ Output Disable Time[9] (all outputs) TCCJ Cycle-to-Cycle Jitter[9,10] Tskew Any Output to Any Output Skew[9,10] Tskew Bank to Bank Skew Part to Part Skew Tpd Phase Error[9,10] 100 50 55 % 2 10 ns 2 8 ns [9] tpZL, tpZH Tskew(pp) 50 45 ±100 Same Frequency ps Different Frequency 300 Banks at different voltages 400 ps [11] TCLK or PECL_CLK to FB_IN ps 150 450 ps VDD = 3.3V 0 100 200 ps VDD = 2.5V 25 125 225 Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. Outputs loaded with 30 pF each. 10. 50Ω transmission line terminated into VDD/2 11. Part-to-part skew at a given temperature and voltage. Ordering Information Part Number Package Type Production Flow CY29962AI 48-pin TQFP Industrial, –40°C to +85°C CY29962AIT 48-pin TQFP - Tape and Reel Industrial, –40°C to +85°C Document #: 38-07364 Rev. *B Page 5 of 7 CY29962 Package Drawing and 48-Lead Thin Plastic Quad Flat Pack (7x7x1.0 mm) A48A 51-85166-** PowerPC is a registered trademark of International Business Machines. Pentium is a registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07364 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29962 Document Title: CY29962 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer Document Number: 38-07364 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 112490 03/06/02 CTK New Data Sheet *A 116092 09/03/02 HWT Changed the Package Drawing and Dimension to CY standard on page 6. *B 122906 12/26/02 RBI Document #: 38-07364 Rev. *B Add power up requirements to maximum ratings requirements Page 7 of 7