CYPRESS Z9975CA

Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Product Features
•
•
•
•
•
•
•
•
•
Output Frequency up to 150MHz
TM
TM
Processors
Supports Power PC , and Pentium
15 Clock Output: Frequency Configurable
Two Reference Clock Inputs for Dynamic Toggling
Output Tri-State Control
Spread Spectrum Compatible
3.3V Power Supply
Industrial Temp. Range: -40°C to +85°C
52 Pin TQFP Package
Product Description
The Z9975 is a low cost 3.3V zero delay clock driver for
high speed signal buffering and redistribution.
Feedback Ratio Selection Table
Inputs
VCO_Sel1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VCO_Sel0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Qb0
VDDb
NC
VSSc
Qc3
VDDc
QC2
VSSc
QC1
VDDc
QC0
VSSc
VCO_Sel0
This device includes a Master Reset signal that disables
the outputs into Tristate (Hi-Z) mode, and reset all
internal digital circuitry (excluding the PLL).
An Output Enable, OE, input pin is available for shutting
Qa(0:4), Qb(0:4), and Qc(0:3) outputs in a low state. All
outputs are held low with input clock turned off.
QFB
VCO/8
VCO/12
VCO/16
VCO/24
VCO/16
VCO/24
VCO/32
VCO/48
VCO/4
VCO/6
VCO/8
VCO/12
VCO/8
VCO/12
VCO/16
VCO/24
Pin Configuration
The Z9975 has three banks of outputs with independent
divider stages. These dividers allow the banks to have
different frequencies as per table 2.
TCLK0 and TCLK1 one are selectable input reference
clocks and may be toggled dynamically during operation
to provide modulation and phase shifting designs.
fselFB1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 1
It provides the designer with the flexibility of selecting
various Output/Input Frequency ratios selected by fsela,
fselb, fselc, fselFB(0:1), and VCO_sel input settings.
The Z9975 integrates PLL technology for Zero delay
propagation from Input to Output. The PLL feedback is
externally available for propagation delay tuning and
divide ratio alternatives as per table 1.
Outputs
fselFB0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
52 51 50 49 48 47 46 45 44 43 42 41 40
VSSA
MR#
OE
fselb
fselc
PLL_EN
fsela
TClk_Sel
TClk0
TClk1
VCO_Sel1
VDDI
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
Z9975
39
38
37
36
35
34
33
32
31
30
29
28
27
VSSb
QB1
VDDb
Qb2
VSSb
Qb3
VDDb
Qb4
FB_IN
VSSFB
QFB
VDDFB
NC
14 15 16 17 18 19 20 21 22 23 24 25 26
VDDa
Qa0
VSSa
Qa1
VDDa
Qa2
fselFB1
VSSa
Qa3
VDDa
Qa4
VSSI
fselFB0
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 1 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Block Diagram
fsela
0
250K
A
1
AND Y
Gate
5
5
Qa(0:4)
AND
Y
Gate
5
5
Qb(0:4)
AND Y
B Gate
4
4
Qc(0:3)
1
QFB
B
TCLK_sel
5
250K
VDD
0
250K
TCLK0
1
TCLK1
A
1
PLL
0
Ref-in
VCO-out
0
1
B
/1
C
/2
5
C
/2
/4
250K
/4
VDD
Feedback
PLLinit#
250K
FB_In
Reset#
Divide by
1, 2 & 4
/6
0
Reset#
1
A
Divide by
2, 4 & 6
4
VDD
250K
PLL_EN
VCO_sel0
0
250K
1
fselb
0
C
/2
1
Reset#
Div. by 2
250K
fselc
250K
fselFB1
250K
fselFB0
250K
VDD
250K
OE
VDD
250K
MR#
VCO_Sel1
250K
VSS
Fig.1
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 2 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Output Frequency Selection Table (VCO_Sel1 = 0)
Inputs
Output Frequency Selection Table (VCO_Sel1 = 1)
Outputs
VCO_sel0
fsela
fselb
fselc
Qa(0:4)
0
0
0
0
VCO/4
0
0
0
1
VCO/4
0
0
1
0
VCO/4
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
1
1
Qb(0:4)
Inputs
Outputs
Qc(0:3)
VCO_sel0
fsela
fselb
fselc
Qa(0:4)
Qb(0:4)
Qc(0:3)
VCO/4
VCO/8
0
0
0
0
VCO/2
VCO/2
VCO/4
VCO/4
VCO/12
0
0
0
1
VCO/2
VCO/2
VCO/6
VCO/8
VCO/8
0
0
1
0
VCO/2
VCO/4
VCO/4
VCO/4
VCO/8
VCO/12
0
0
1
1
VCO/2
VCO/4
VCO/6
VCO/8
VCO/4
VCO/8
0
1
0
0
VCO/4
VCO/2
VCO/4
1
VCO/8
VCO/4
VCO/12
0
1
0
1
VCO/4
VCO/2
VCO/6
0
VCO/8
VCO/8
VCO/8
0
1
1
0
VCO/4
VCO/4
VCO/4
1
1
VCO/8
VCO/8
VCO/12
0
1
1
1
VCO/4
VCO/4
VCO/6
0
0
0
VCO/8
VCO/8
VCO/16
1
0
0
0
VCO/4
VCO/4
VCO/8
1
0
0
1
VCO/8
VCO/8
VCO/24
1
0
0
1
VCO/4
VCO/4
VCO/12
1
0
1
0
VCO/8
VCO/16
VCO/16
1
0
1
0
VCO/4
VCO/8
VCO/8
1
0
1
1
VCO/8
VCO/16
VCO/24
1
0
1
1
VCO/4
VCO/8
VCO/12
1
1
0
0
VCO/16
VCO/8
VCO/16
1
1
0
0
VCO/8
VCO/4
VCO/8
1
1
0
1
VCO/16
VCO/8
VCO/24
1
1
0
1
VCO/8
VCO/4
VCO/12
1
1
1
0
VCO/16
VCO/16
VCO/16
1
1
1
0
VCO/8
VCO/8
VCO/8
1
1
1
1
VCO/16
VCO/16
VCO/24
1
1
1
1
VCO/8
VCO/8
VCO/12
Table 2
Table 3
Pin Description
PIN No.
Pin Name
I/O
Description
2
MR#
I
3
OE
I
7,4, 5
Fsel(a,b,c)
I
6
PLL_EN
I
8
TCLK_sel
I
9,10
TCLK(0:1)
I
14, 20
FselFB(0:1)
I
25,23,21,
18,16
29
Qa(0:4)
O
QFB
O
31
FB_In
I
Active low Master Reset pin. It has a 250KΩ internal pull-up. When forced low, all outputs
are Tri-stated (high impedance) and internal ratio dividers are reset.
Active high Output Enable pin. It has a 250KΩ internal pull-up. When forced low, Qa(0:4),
Qb(0:4), and Qc(0:3) outputs are stopped in a low state. QFB is not effected by this signal.
Input select pins for setting the output dividers at Qa(0:4), Qb(0:4), and Qc(0:3)
respectively. Each pin has an internal 250KΩ pull-down. See table 2, page 3.
Input pin for bypassing the PLL. It has an internal 250KΩ pull-up. When forced low,
the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL and drives the
dividers, typically for device testing. In this case, the PLL is disabled.
Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel = 0, TCLK0 is
selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a 250KΩ internal pull-down.
Input pins for applying a reference clock to the PLL. The active input is selected by
TCLK_sel, pin# 8. TCLK0 has a 250KΩ internal pull-down. TCLK1 has a 250KΩ internal
pull-up.
Input select pins for setting the Feedback divide ratio at QFB output, pin#29. See table 1,
page1. Each of these pins has a 250KΩ internal pull-down.
High drive, Low Voltage CMOS, Output clock buffers, Bank Qa. Their divide ratio is
programmed by fsela, pin#7.
Low Voltage CMOS output feedback clock to the internal PLL. The divide ratio for this
output is set by fsleFB(0:1). A delay capacitor, or trace may be applied to this pin in order
to control the Input Reference/Output Banks phase relationship.
Feedback input pin. Typically connects to the QFB output for accessing the Feedback to
the PLL. It has a 250KΩ internal pull-up.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 3 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Pin Description (Cont.)
PIN No.
Pin Name
I/O
Description
11
VCO_Sel1
I
40,38,36,
34,32
50,48,46,
44
52
Qb(0:4)
O
Qc(0:3)
O
VCO_Sel0
I
27,42
12
15
13,
17,22,26
19,24
28, 30
33,37,41
35,39
45,49
43,47,51
1
n/c
VDDI
VSSI
VDDA
VDDa
VSSa
VDDFB / VSSFB
VDDb
VSSb
VDDc
VSSc
VSSA
P
P
P
P
P
P
P
P
P
P
P
Output Division Selection contains an internal pulldown resistor. When left floating or pulled
to VSS (Logic 0) output frequencies are described by Output Frequency Table 2, when
driven to VDD (Logic 1), output frequencies are described by Table 3.
High drive, Low Voltage CMOS, Output clock buffers, Bank Qb. Their divide ratio is
programmed by fselb, pin#4.
High drive, Low Voltage CMOS, Output clock buffers, Bank Qc. Their divide ratio is
programmed by fselc, pin#5.
Input select pin for setting the divider of the VCO output. It has a 250KΩ internal pull-down.
If VCO_sel = 0, then the PLL VCO output is divided by 2. If VCO_sel = 1, then the PLL
VCO output is divided by 4. See fig.1, page2; table 1, page1, table 2, page 3.
These pins are not connected internally. They may be attached to a ground plane.
Power for input logic circuitry.
Ground for input logic circuitry.
Power and Ground supply pins for internal Analog circuitry.
3.3V supply for Qa(0:4) output bank, and fselFB1 input.
Common ground for Qa(0:4) output bank, and fselFB1 input.
Power and ground supply pins for QFB output and FB_In input pins and digital circuitry.
3.3V supply for Qb(0:4) output bank.
Common ground for Qb(0:4) output bank.
3.3V supply for Qc(0:3) output bank and VCO_sel pin.
Common ground for Qc(0:3) output bank and VCO_sel pin.
Analog Ground
A bypass capacitor (0.1µ
µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass
capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of
the traces.
Glitch-Free Output Frequency Transitions
Customarily when zero delay buffers have their internal counter’s changed “on the fly’ their output clock periods will:
A. Contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either
the old or new frequency that is being transitioned to.
B. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old
or new frequency that is being transitioned to.
This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly” while it is operating: Fsela, Fselb, Fselc, VCO_Sel, FselFB1,
and FselFB2.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 4 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Maximum Ratings¹
Input Voltage Relative to VSS:
VSS-0.3V
Input Voltage Relative to VDD:
VDD+0.3V
Storage Temperature:
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
-65°C to + 150°C
Operating Temperature:
-40°C to +85°C
Maximum Power Supply:
5.5V
DC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL
VSS
-
0.8
Vdc
Input High Voltage
VIH
2.0
-
VDD
Vdc
Input Low Current
IIL
-100
µA
Input High Current
IIH
100
Applicable to all input signals.
µA
Output Low Voltage
VOL
Output High Voltage
VOH
2.4
0.5
V
IOL = 20 mA
V
IOH = - 20mA
Quiescent Supply Current
Idd
-
-
20
mA
Input Pin Capacitance
Cin
-
-
8
pF
Per input
VDD* =3.3V + 5%, TA = -40°°C to +85°°C
PLL AC Parameters
Characteristic
Symbol
Maximum PLL Lock Time
tLOCK
VCO Lock Range
fVCO
TCLK(0:1) input rise / fall
time
Min
200
Tinr, Tinf
Typ
Max
Units
10
mS
Stable power supply & valid clocks
presented on TCLK(0:1) pins.
500
MHz
FselFB(0:1) = /4 to /12
3
nS
Input Reference frequency
fREF
Note 2
Note 2
MHz
Input Reference duty cycle
fREFpw
25
75
%
Conditions
VDD* = 3.3V + 5%, TA = -40°°C to +85°°C
Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is
NOT required.
Note 2: Input Reference Frequency is limited by the divider selection and the VCO lock range.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 5 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
AC Parameters
Characteristic
Min
Typ
Max
Units
Output Duty Cycle
Symbol
Tpw
Tcycle/2
- 800
Tcycle/2
+ 500
Tcycle/2
+ 800
ps
Measured @ VDD/2
Conditions
Rise Time / Fall Time
Tr, Tf
0.15
-
1.5
ns
Measured between 0.8V and 2.0V
7
10
Ω
Output Impedance
Zo
Output to Output Skew
Ts
-
-
250
ps
All output equally loaded
Propagation Delay,
TCLK(0:1) to FBIN
Tpd
-250
-
100
ps
Measured for 50MHz at VDD/2
Cycle to Cycle Jitter
tj
-
+100
-
ps
Measured for 50 MHz at VDD/2
Output Disable Time
tPLZ,
tPHZ
2
-
10
ns
After MR# goes low
Output Enable Time
tPZL
2
-
10
ns
After MR# goes High
Maximum Output
Frequency
Fout
-
-
150
MHz
-
-
125
Q (÷4)
-
-
83
Q (÷6)
Q (÷2)
VDD* = 3.3V + 5%, TA = -40°°C to +85°°C
Note: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters
specified with loaded outputs. Z9975 outputs can drive series or parallel terminator 50 Ω (or 50 Ω to VDD/2).
Test Circuit Diagram
VDD*
1K Ω
Output under Test
43 Ω
50 Ω Impedance
PROBE
7Ω
1K Ω
NOTE: All buffer outputs are tied to a common 3.3 Volt
VDD (VDD*) for testing purposes
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 6 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Package Drawing and Dimensions (52 TQFP)
52 Pin TQFP Outline Dimensions
INCHES
SYMBOL
D
D1
MIN
A1
A2
MAX
MIN
NOM
MAX
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
-
0.041
0.95
-
1.05
D
-
0.472
-
-
12.00
-
D1
-
0.394
-
-
10.00
-
b
0.009
-
0.015
0.22
-
0.38
e
10°
NOM
MILLIMETERS
L
0.026 BSC
0.018
-
0.65 BSC
0.030
0.45
-
0.75
A
L
e
b
Ordering Information
Part Number
Package Type
Production Flow
Z9975CA
52 TQFP
Industrial, -40°C to +85°C
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example:
Cypress
Z9975CA
Date Code, Lot #
Z9975CA
Package
A = TQFP
Revision
IMI Device Number
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of
its products in the life supporting and medical applications.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 7 of 8
Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Document Title: Z9975 3.3V, 150 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07091
Rev. ECN
No.
**
107127
*A
108069
*B
122776
Issue
Date
06/05/01
07/03/01
12/26/02
Cypress Semiconductor Corporation
http://www.cypress.com
Orig. of
Change
IKA
NDP
RBI
Description of Change
Converted from IMI to Cypress
Changed Commercial to Industrial
Add power up requirements to maximum ratings information.
Document#: 38-07091 Rev. *B
12/26/2002
Page 8 of 8