CYPRESS Z9952

Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Product Features
Frequency Table
•
•
•
•
•
•
•
•
•
•
•
•
VCO_SEL
SEL (A:C)
QA(0:4)
QB(0:3)
QC (0,1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
VCO/4
VCO/4
VCO/4
VCO/4
VCO/6
VCO/6
VCO/6
VCO/6
VCO/8
VCO/8
VCO/8
VCO/8
VCO/12
VCO/12
VCO/12
VCO/12
VCO/4
VCO/4
VCO/2
VCO/2
VCO/4
VCO/4
VCO/2
VCO/2
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/2
VCO/4
VCO/2
VCO/4
VCO/2
VCO/4
VCO/2
VCO/4
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
180MHz Clock Support
150ps Maximum Output to Output Skew
TM
Supports PowerPC , Intel and RISC Processors
11 Clock Outputs: Frequency Configurable
Outputs Drive up to 22 Clock Lines
LVCMOS/LVTTL Compatible Inputs
Output Tri-state Control
Spread Spectrum Compatible
3.3V Power Supply
Pin Compatible with MPC952
Industrial Temp. Range: -40°C to +85°C
32-Pin TQFP Package
Block Diagram
PLL_EN#
Table 1
VSS
QB3
QB2
VDDC
26
25
QB0
27
/4,
/2
VSS
SELA
28
VCO_SEL
Pin Configuration
QC0
QA2
QA3
QA4
LPF
29
QA1
QC1
FB_IN
QA0
30
/2
/4,
/6
VDDC
VCO
200-480M
31
Phase
Detector
32
REFCLK
QB1
Cypress Semiconductor Corporation
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12
13
14
15
16
QA0
VSS
QA1
QA2
VDDC
Z9952
11
Figure 1
QC1
24
23
22
21
20
19
18
17
VDD
SELC
MR/OE#
QC0
1
2
3
4
5
6
7
8
9
/2,
/4
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
VSS
FB_IN
10
QB3
VDDA
QB2
PLL_EN#
SELB
Document#: 38-07085 Rev. *B
VSS
QB1
QB0
VDDC
VDDC
QA4
QA3
VSS
12/22/2002
Page 1 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Pin Description
PIN
6
12, 14, 15,
18, 19
22, 23, 26, 27
30, 31
8
1
NAME
REFCLK
QA(0:4)
5
MR/OE#
I, PD
9
PLL_EN#
I
2, 3, 4
SEL(C:A)
I, PD
16, 20, 21,
25, 32
10
11
7, 13, 17, 24,
28, 29
VDDC
VCO Divider Select Input. When set high, the VCO output is
divided by 2. When set low, the divider is bypassed. See
Table 1
Master Reset/Output Enable Input. When asserted high,
resets all of the internal flip-flops and also disables all of the
outputs. When pulled low, releases the internal flip-flops from
reset and enables all of the outputs.
PLL Enable Input. When asserted low, PLL is enabled. And
when set high, PLL is bypassed.
Frequency Select Inputs. See Frequency Table.
If SEL_ = 0, then QA, QB divider = ÷4, QC divider = ÷2
If SEL_ = 1, then QA divider = ÷6, QB divider = ÷2, QC divider
= ÷4
3.3V Power Supply for Output Clock Buffers.
VDDA
VDD
VSS
3.3V Power Supply for PLL
3.3V Power Supply for Core Logic
Common Ground
QB(0:3)
QC(0,1)
FB_IN
VCO_SEL
PWR
VDDC
VDDC
VDDC
I/O
I
O
Description
External Test Clock Input.
Clock Output. See Frequency Table.
O
O
I
I, PD
Clock Output. See Frequency Table.
Clock Outputs. See Frequency Table.
Feedback Clock Input. Connect to an output for normal operation.
PD = Internal Pull-Down
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Document#: 38-07085 Rev. *B
12/22/2002
Page 2 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Maximum Ratings¹
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
-65°C to + 150°C
-40°C to +85°C
Maximum ESD protection
2KV
Maximum Power Supply:
Maximum Input Current:
VSS<(Vin or Vout)<VDD
5.5V
±20mA
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Symbol
Min
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Output Low Voltage
VIL
VIH
IIL
IIH
VOL
VSS
2.0
Output High Voltage
VOH
2.4
Quiescent Supply Current
Typ
-
Max
0.8
VDD
10
120
0.5
Units
Conditions
V
V
µA
µA
V
Note 2
IOL = 20mA, Note 3
V
IOH = -20mA, Note 3
IDDC
-
15
20
mA
All VDDC, VDDA, and VDD
PLL Supply Current
IDD
-
15
20
mA
VDDA only
Input Capacitance
Cin
-
-
4
pF
VDDA = VDD = VDDC = 3.3V ±5%, TA = -40°°C to +85°°C
Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is
NOT required.
Note 2: Inputs have internal pull-down resistors that affect input current.
Note 3: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Cypress Semiconductor Corporation
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Document#: 38-07085 Rev. *B
12/22/2002
Page 3 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
AC Parameters1
SYMBOL
PARAMETER
MIN
Freq
Reference Input Frequency
Fvco
PLL VCO Lock Range
Tlock
Tr / Tf
Fout
FoutDC
TYP
MAX
UNITS
Note 2
Note 2
MHz
200
480
MHz
10
ms
0.10
1.0
ns
0.8V to 2.0V
-
180
MHz
QB, QC = (÷2)
Maximum PLL lock Time
Output Clocks Rise / Fall Time
4,5
Maximum Output Frequency
Output Duty Cycle
4,5
120
QA, QB, QC = (÷4)
80
QA = (÷6)
TCYCLE/2 –
750
TCYCLE/2 +
750
ps
tpZL, tpZH
Output enable time (all outputs)
2
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
2
8
ns
TCCJ
Cycle to Cycle Jitter (peak to peak)
-200
200
ps
-
150
ps
Tpd
TSKEW0
3,,4,5
REFCLK to FB_IN Delay
4,5
Any Output to Any Output Skew
5
CONDITIONS
+/- 100
ps
250
Same frequencies
Different frequencies
VDDA = VDD = VDDC = 3.3V +/- 5%, TA = -40°°C to +85°°C
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with
loaded outputs.
Note 2: Maximum and minimum input reference is limited by the VCO lock range.
Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2).
Note 5: Outputs loaded with 30pF each
Cypress Semiconductor Corporation
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Document#: 38-07085 Rev. *B
12/22/2002
Page 4 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Description
The Z9952 has an integrated PLL that provides low skew and low jitter clock outputs for high performance
microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480
MHz. This allows a wide range of output frequencies up to 180MHz. The Z9952 features three banks of individually
configurable outputs: Bank A five outputs, Bank B four outputs, and Bank C two outputs. When MR/OE# input is set
high, all the outputs are tri-stated. The Z9952 outputs are LVCMOS compatible and can drive two series terminated 50Ω
transmission lines. With this capability the Z9952 has an effective fanout of 1:22. Low output-to-output skews make the
Z9952 ideal for clock distribution in nested clock trees in the most demanding of synchronous systems.
The phase detector compares the input reference clock to the external feedback input. For normal operation, the
external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input
reference clock set by SEL(A:C) select inputs, see Table 2. The VCO_SEL input allows for the choice of two VCO
ranges to optimize PLL stability and jitter performance, see Table 1. The VCO frequency is then divided down to provide
the required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.
SELA
0
1
QA
÷4
÷6
SELB
0
1
QB
÷4
÷2
SELC
0
1
QC
÷2
÷4
Table 2
Zero Delay Buffer
When used as a zero delay buffer the Z9952 will likely be in a nested clock tree application. Any of the eleven outputs
can be used as the feedback to the PLL. By using one of the outputs as a feedback to the PLL the propagation delay
through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a
near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between
the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9952 is a
function of the configuration used.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002
Page 5 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Package Drawing and Dimensions
32 Pin TQFP Outline Dimensions
INCHES
SYMBOL
MIN
NOM
MILLIMETERS
NOM
MAX
A
-
-
MAX
0.047
MIN
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
-
0.041
0.95
-
1.05
D
-
0.354
-
-
9.00
-
D1
-
0.276
-
-
7.00
-
b
0.012
-
0.018
0.30
-
0.45
D
D1
e
12°
L
A1
0.031 BSC
0.018
-
0.80 BSC
0.030
0.45
-
0.75
A
L
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e
b
Document#: 38-07085 Rev. *B
12/22/2002
Page 6 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Ordering Information
Part Number
Package Type
Production Flow
Z9952AA
32 PIN TQFP
Industrial, -40°C to +85°C
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example:
Cypress
Z9952AA
Date Code, Lot #
Z9952AA
Package
A = TQFP
Revision
IMI Device Number
Cypress Semiconductor Corporation
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Document#: 38-07085 Rev. *B
12/22/2002
Page 7 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing Cypress Semiconductor Corporation for the use of its
products in the life supporting and medical applications.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002
Page 8 of 9
Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Document Title: Z9952 3.3V, 180 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07085
Rev.
**
*A
*B
ECN
No.
107121
108064
122770
Issue
Date
06/05/01
07/03/01
12/22/02
Cypress Semiconductor Corporation
http://www.cypress.com
Orig. of
Change
IKA
NDP
RBI
Description of Change
Convert from IMI to Cypress
Changed Commercial to Industrial
Add power up requirements to maximum ratings
information
Document#: 38-07085 Rev. *B
12/22/2002
Page 9 of 9