TI TMS320TCI6602

TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
Data Manual
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Literature Number: SPRS782A
August 2011
TMS320TCI6602
Data Manual
SPRS782A—August 2011
www.ti.com
Release History
Release
Date
Description/Comments
SPRS782A
August 2011
• Added sections: NMI and LRSET
• Added Pin Map diagrams
• Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers
• Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL
• Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns
• Corrected items in the Memory Map Summary table
• Changed all occurrences of PA_SS to Network Coprocessor
• Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR
SPRS782
November 2010
Initial release
For detailed revision information, see ‘‘Revision History’’ on page A-198.
2
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Contents
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.1 KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1
2.2
2.3
2.4
2.5
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DSP Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.5.3 PLL Boot Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.7.1 Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.7.2 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.9 Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.10 Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.3.2 Device Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.3.11 NMI Even Generation to CorePac (NMIGRx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.3.12 IPC Generation (IPCGRx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4
System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
4.1
4.2
4.3
4.4
5
Internal Buses, Bridges, and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Data Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Configuration Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Copyright 2011 Texas Instruments Incorporated
3
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
5.2
5.3
5.4
5.5
5.6
6
www.ti.com
5.1.4 MSMC SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7
Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1.1 1.8-V Signal Transition Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.1.2 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.2 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.3 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.4 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.4.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.4.2 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.4.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.5 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.5.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.5.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.5.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.5.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.5.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.5.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.5.7 Reset Electrical Data / Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.6 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.6.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.6.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.6.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.6.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.7 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.7.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.7.2 DDR3 PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.7.3 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.8 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.8.1 PASS PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.8.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.9 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.9.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.9.2 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.9.3 EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.9.4 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.10.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.10.2 INTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.10.3 Inter-Processor Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.10.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.10.5 External Interrupts Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.11 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.11.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
7.11.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13.2 I2C Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18 TSIP Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22 Gigabit Ethernet (GbE) Switch Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23 Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.24 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.24.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.24.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.25 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.26 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.26.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.26.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.27 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.28 Emulation Features and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.28.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.28.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.28.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
B.1
B.2
Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Copyright 2011 Texas Instruments Incorporated
5
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
List of Figures
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 2-17
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 4-1
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
TMS320TCI6602 DSP Core Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
No Boot/ EMIF16 Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Ethernet (SGMII) Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Serial Rapid I/O Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PCI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
I2C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
CYP 841-Pin BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Pin Map Quadrants (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Upper Left Quadrant—A (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Upper Right Quadrant—B (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Lower Right Quadrant—C (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Lower Left Quadrant—D (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
C66x DSP Device Nomenclature (including the TMS320TCI6602) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
NMI Generation Register (NMIGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
IPC Acknowledgement Registers (IPCARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Reset Mux Register RSTMUXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
TMS320TCI6602 L1P Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
TMS320TCI6602 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
TMS320TCI6602 L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
CorePac Revision ID Register (MM_REVID) Address - 0181 2000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Rise and Fall Transition Time Voltage Reference Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Soft/Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
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Figure 7-60
Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Main PLL Control Register 0 (MAINPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Main PLL Control Register 1 (MAINPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
PLL Transition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DDR3 PLL Control Register 0 (DDR3PLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DDR3 PLL Control Register 1 (DDR3PLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
PASS PLL Control Register 0 (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
PASS PLL Control Register 1 (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
TMS320TCI6602 Interrupt Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
NMI and Local Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
SPI Additional Timings for 4 Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
UART RTS (Request-to-Send Output) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
CPTS_RFTCLK_SEL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
HS-RTDX Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Copyright 2011 Texas Instruments Incorporated
7
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
List of Tables
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
Table 3-17
Table 3-18
Table 3-19
Table 4-1
Table 4-2
Table 4-3
Table 5-1
Table 5-2
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
8
Characteristics of the TMS320TCI6602 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Memory Map Summary for TMS320TCI6602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
No Boot / EMIF16 Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Ethernet (SGMII) Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Serial Rapid I/O Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PCI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
C66x DSP System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Terminal Functions — Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Terminal Functions — By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
TMS320TCI6602 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IPC Generation Registers (IPCGRH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
CPU/2 Data SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
DSP/3 Data SCR Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Board-Level Timing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Power Supply Rails on TMS320TCI6602. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
Table 7-22
Table 7-23
Table 7-24
Table 7-25
Table 7-26
Table 7-27
Table 7-28
Table 7-29
Table 7-30
Table 7-31
Table 7-32
Table 7-33
Table 7-34
Table 7-35
Table 7-36
Table 7-37
Table 7-38
Table 7-39
Table 7-40
Table 7-41
Table 7-42
Table 7-43
Table 7-44
Table 7-45
Table 7-46
Table 7-47
Table 7-48
Table 7-49
Table 7-50
Table 7-51
Table 7-52
Table 7-53
Table 7-54
Table 7-55
Table 7-56
Table 7-57
Table 7-58
Table 7-59
SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Reset Configuration Register (RSTCFG) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
DDR3 PLL Control Register 0 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DDR3 PLL Control Register 1 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
PASS PLL Control Register 0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
PASS PLL Control Register 1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
PASS PLL Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
EDMA3 Transfer Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
TPCC0 Events for TCI6602. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
TPCC1 Events for TCI6602. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
TPCC2 Events for TCI6602. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
TMS320TCI6602 System Event Mapping — C66x CorePac Primary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
INTC3 Event Inputs (Secondary Events for TPCC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
INTC0/INTC1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
INTC2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
INTC3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
NMI and Local Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Copyright 2011 Texas Instruments Incorporated
9
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-60
Table 7-61
Table 7-62
Table 7-63
Table 7-64
Table 7-65
Table 7-66
Table 7-67
Table 7-68
Table 7-69
Table 7-70
Table 7-71
Table 7-72
Table 7-73
Table 7-74
Table 7-75
Table 7-76
Table 7-77
Table 7-78
Table 7-79
Table 7-80
Table 7-81
Table 7-82
Table 7-83
Table 7-84
Table 7-85
Table B-1
10
www.ti.com
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Programmable Range n End Address Register (PROGn_MPEAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions . . . . . . . . . . . .171
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .173
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
I2C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
I2C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
CPTS_RFTCLK_SEL Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MDIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
HS-RTDX Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Thermal Resistance Characteristics (PBGA Package) [CYP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
• TwoTMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each with
– 1.5 GHz C66x Fixed/Floating-Point CPU Core
› 48 GMAC/Core for Fixed Point @ 1.5 GHz
› 24 GFLOP/Core for Floating Point @ 1.5 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 512K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 4096 KB MSM SRAM Memory Shared by Two DSP
C66x CorePacs
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed Throughput at 1.5M Packets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP, WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Peripherals
– Four Lanes of SRIO 2.1
› 1.24/2.5/3.125/5 GBaud Operation Supported
Per Lane
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other specifications
are subject to change without notice.
–
–
–
–
–
–
–
–
–
–
–
–
–
› Supports Direct I/O, Message Passing
› Supports Four 1×, Two 2×, One 4×, and Two 1x +
One 2x Link Configurations
PCIe Gen2
› Single port supporting 1 or 2 lanes
› Supports Up To 5 GBaud Per Lane
HyperLink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 50 Gbaud
Gigabit Ethernet (GbE) Switch Subsystem
› Two SGMII Ports
› Supports 10/100/1000 Mbps operation
64-Bit DDR3 Interface (DDR3-1600)
› 8G Byte Addressable Memory Space
16-Bit EMIF
› Support For Up To 256MB NAND Flash and
16MB NOR Flash
› Support For Asynchronous SRAM up to 1MB
Two Telecom Serial Ports (TSIP)
› Supports 1024 DS0s Per TSIP
› Supports 2/4/8 Lanes at 32.768/16.384/8.192
Mbps Per Lane
UART Interface
2
I C Interface
16 GPIO Pins
SPI Interface
Semaphore Module
Four 64-Bit Timers
Three On-Chip PLLs
• Commercial Temperature:
– 0°C to 85°C
• Extended Temperature:
– - 40°C to 100°C
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
1 Features
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
1.1 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores
with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
ADVANCE INFORMATION
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.2 Device Description
The TMS320TCI6602 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone
multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of
up to 1.5 GHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and
automation, and other applications requiring high performance, TI's TMS320TCI6602 DSP offers 3 GHz
cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward
compatible with all existing C6000 family of fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory
subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize
intra-device and inter-device communication that allows the various DSP resources to operate efficiently and
seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data
management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and
contention-free internal data movement. The multicore shared memory controller allows access to shared and
external memory directly without drawing from switch fabric capacity.
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition,
the C66x core integrates floating point capability and the per core raw computational performance is an
industry-leading 32 MACS/cycle and 16 flops/cycle. It can execute 8 single precision floating point MAC operations
per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. The C66x core
incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented
processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal
processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's
previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software
development cycles for applications migrating to faster hardware.
The TCI6602 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache,
there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also
integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All
L2 memories incorporate error detection and error correction. For fast access to external memory, this device
includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.
12
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS782A—August 2011
The TCI6602 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source
code execution.
Copyright 2011 Texas Instruments Incorporated
13
ADVANCE INFORMATION
This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and
Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I2C, UART, Telecom Serial Interface Port
(TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication
between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding
to the network awareness of this device is a network co-processor that includes both packet and optional security
acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for
the entire multicore TCI6602 device. It also provides L2 to L4 classification, along with checksum and QoS
capabilities.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the TMS320TCI6602 device.
Figure 1-1
Functional Block Diagram
Memory Subsystem
4MB
MSM
SRAM
64-Bit
DDR3 EMIF
MSMC
ADVANCE INFORMATION
Debug & Trace
Boot ROM
Semaphore
C66x
CorePac
Power
Management
PLL
32KB L1
P-Cache
´3
C66x
CorePac
32KB L1
P-Cache
32KB L1
D-Cache
512KB L2 Cache
EDMA
´3
32KB L1
D-Cache
512KB L2 Cache
2 Cores @ up to 1.5 GHz
TeraNet
HyperLink
Multicore Navigator
14
Switch
Ethernet
Switch
´4
SRIO
SGMII
´2
´2
TSIP
SPI
UART
´2
PCIe
I2C
GPIO
EMIF 16
Queue
Manager
Packet
DMA
Security
Accelerator
Packet
Accelerator
Network Coprocessor
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the TMS320TCI6602 DSP. The table shows significant features of the device,
including the capacity of on-chip RAM, the peripherals, the DSP frequency, and the package and pin count.
Characteristics of the TMS320TCI6602 Processor
HARDWARE FEATURES
Peripherals
1
EDMA3 (16 independent channels) [DSP/2 clock rate]
1
EDMA3 (64 independent channels) [DSP/3 clock rate]
2
High-speed 1×/2x/4× Serial RapidIO Port (4 lanes)
1
PCIe (2 lanes)
1
10/100/1000 Ethernet
2
Management Data Input/Output (MDIO)
1
HyperLink
1
EMIF16
1
TSIP
2
SPI
1
UART
1
2
Accelerators
TMS320TCI6602
DDR3 Memory Controller (64-bit bus width) [1.5 V I/O]
(clock source = DDRREFCLKN|P)
IC
1
64-Bit Timers (configurable) (internal clock source = DSP/6 clock frequency)
Four 64-bit (each configurable as eight 32-bit
timers)
General-Purpose Input/Output Port (GPIO)
16
Packet Accelerator
1
Security Accelerator
(1)
Size (Bytes)
1
5376KB
64KB L1 Program Memory [SRAM/Cache]
On-Chip Memory
64KB L1 Data Memory [SRAM/Cache]
Organization
1024KB L2 Unified Memory/Cache
4096KB MSM SRAM
128KB L3 ROM
C66x CorePac
Revision ID
CorePac Revision ID Register (address location: 0181 2000h)
See Section 5.5 ‘‘C66x CorePac Revision’’ on
page 91.
JTAG BSDL_ID
JTAGID register (address location: 0262 0018h)
See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register
Description’’ on page 70
1500 (1.5 GHz)
Frequency
MHz
1250 (1.25 GHz)
1000 (1.0 GHz)
Cycle Time
Voltage
ns
1 ns
Core (V)
SmartReflex variable supply
I/O (V)
1.0 V, 1.5 V, and 1.8 V
Process Technology
μm
0.040 μm
BGA Package
24 mm × 24 mm
841-Pin Flip-Chip Plastic BGA (CYP)
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
AI
Product Status
(2)
End of Table 2-1
1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
Copyright 2011 Texas Instruments Incorporated
15
ADVANCE INFORMATION
Table 2-1
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2 ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change
without notice.
2.2 DSP Core Description
ADVANCE INFORMATION
The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through
enhancements and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data.
On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions.
C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to
perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also
supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process
multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g
execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP
programmers through the use of TI's optimized C/C++ compiler.
The C66x DSP consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The
two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The
general-purpose registers can be used for data or can be data address pointers. The data types supported include
packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data.
40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and
the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data
values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the
remaining 96 MSBs in the next 3 upper registers.
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.
Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit
multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies
with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field
multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding
capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with
rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions
that multiply a complex number with a complex conjugate of another number with rounding capability.
Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable
of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability.
A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.
Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes
one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a
mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an
operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The
C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing
one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x
.M unit can also perform one the following floating-point operations each clock cycle: one, two, or four
single-precision multiplies or a complex single-precision multiply.
16
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS782A—August 2011
The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall
until the completion of all the DSP-triggered memory transactions, including:
• Cache line fills
• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints
• Victim write backs
• Block or global coherence operations
• Cache mode changes
• Outstanding XMC prefetch requests
This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides
ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that
depend on ordering, and manual coherence operations.
For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following
documents:
• C66x CPU and Instruction Set Reference Guide (literature number SPRUGH7)
• C66x DSP Cache User Guide (literature number SPRUGY8)
• C66x CorePac User Guide (literature number SPRUGW0)
Copyright 2011 Texas Instruments Incorporated
17
ADVANCE INFORMATION
The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic,
logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were
added yielding performance enhancements of the floating point addition and subtraction instructions, including the
ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and
single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger
operands, instructions were also added to double the number of these conversions that can be done. The .L unit also
has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of
complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the
conjugate of a complex number.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Figure 2-1 shows the DSP core functional units and data paths.
Figure 2-1
TMS320TCI6602 DSP Core Data Paths
Note:
Default bus width
is 64 bits
(i.e. a register pair)
src1
.L1
Register
File A
(A0, A1, A2,
...A31)
src2
dst
ST1
src1
.S1
src2
ADVANCE INFORMATION
dst
src1
src1_hi
Data Path A
.M1
src2
src2_hi
dst2
dst1
LD1
32
src1
DA1
32
.D1
dst
32
src2
32
32
2´
1´
src2
DA2
32
.D2
dst
src1
Register
File B
(B0, B1, B2,
...B31)
32
32
32
32
32
LD2
dst1
dst2
src2_hi
.M2
src2
src1_hi
src1
Data Path B
dst
.S2
src2
src1
ST2
dst
.L2
src2
src1
32
Control
Register
32
18
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the TMS320TCI6602 device.
Table 2-2
Memory Map Summary for TMS320TCI6602 (Part 1 of 7)
Start
End
Bytes
Description
00000000
007FFFFF
8M
Reserved
00800000
0087FFFF
512K
Local L2 SRAM
00880000
00DFFFFF
5M+512K
Reserved
00E00000
00E07FFF
32K
Local L1P SRAM
00E08000
00EFFFFF
1M-32K
Reserved
00F00000
00F07FFF
32K
L1D SRAM
00F08000
017FFFFF
9M-32K
Reserved
01800000
01BFFFFF
4M
C66x CorePac Registers
01C00000
01CFFFFF
1M
Reserved
01D00000
01D0007F
128
Tracer 0
01D00080
01D07FFF
32K-128
Reserved
01D08000
01D0807F
128
Tracer 1
01D08080
01D0FFFF
32K-128
Reserved
01D10000
01D1007F
128
Tracer 2
01D10080
01D17FFF
32K-128
Reserved
01D18000
01D1807F
128
Tracer3
01D18080
01D1FFFF
32K-128
Reserved
01D20000
01D2007F
128
Tracer 4
01D20080
01D27FFF
32K-128
Reserved
01D28000
01D2807F
128
Tracer 5
01D28080
01D2FFFF
32K-128
Reserved
01D30000
01D3007F
128
Tracer 6
01D30080
01D37FFF
32K-128
Reserved
01D38000
01D3807F
128
Tracer 7
01D38080
01D3FFFF
32K-128
Reserved
01D40000
01D4007F
128
Tracer 8
01D40080
01D47FFF
32K-128
Reserved
01D48000
01D4807F
128
Tracer 9
01D48080
01D4FFFF
32K-128
Reserved
01D50000
01D5007F
128
Tracer 10
01D50080
01D57FFF
32K-128
Reserved
01D58000
01D5807F
128
Tracer 11
01D58080
01D5FFFF
32K-128
Reserved
01D60000
01D6007F
128
Tracer 12
01D60080
01D67FFF
32K-128
Reserved
01D68000
01D6807F
128
Tracer 13
01D68080
01D6FFFF
32K-128
Reserved
01D70000
01D7007F
128
Tracer 14
01D70080
01D77FFF
32K-128
Reserved
01D78000
01D7807F
128
Tracer 15
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Address
19
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-2
www.ti.com
Memory Map Summary for TMS320TCI6602 (Part 2 of 7)
Address
Start
End
Bytes
Description
01D78080
01D7FFFF
32K-128
Reserved
01D80000
01D8007F
128
Tracer 16
01D80080
01DFFFFF
512K-128
Reserved
01E00000
01E3FFFF
256K
Telecom Serial Interface Port (TSIP) 0
ADVANCE INFORMATION
01E40000
01E7FFFF
256K
Reserved
01E80000
01EBFFFF
256K
Telecom Serial Interface Port (TSIP) 1
01EC0000
01FFFFFF
1M +256K
Reserved
02000000
020FFFFF
1M
Network Coprocessor (Packet Accelerator, Gigabit Ethernet Switch Subsystem and
Security Accelerator)
02100000
021FFFFF
1M
Reserved
02200000
0220007F
128
Timer0
02200080
0220FFFF
64K-128
Reserved
02210000
0221007F
128
Timer1
02210080
0221FFFF
64K-128
Reserved
02220000
0222007F
128
Timer2
02220080
0222FFFF
64K-128
Reserved
02230000
0223007F
128
Timer3
02230080
0223FFFF
64K-128
Reserved
02240000
0224007F
128
Reserved
02240080
0224FFFF
64K-128
Reserved
02250000
0225007F
128
Reserved
02250080
0225FFFF
64K-128
Reserved
02260000
0226007F
128
Reserved
02260080
0226FFFF
64K-128
Reserved
02270000
0227007F
128
Reserved
02270080
0227FFFF
64K-128
Reserved
02280000
0228007F
128
Reserved
02280080
0228FFFF
64K-128
Reserved
02290000
0229007F
128
Reserved
02290080
0229FFFF
64K-128
Reserved
022A0000
022A007F
128
Reserved
022A0080
022AFFFF
64K-128
Reserved
022B0000
022B007F
128
Reserved
022B0080
022BFFFF
64K-128
Reserved
022C0000
022C007F
128
Reserved
022C0080
022CFFFF
64K-128
Reserved
022D0000
022D007F
128
Reserved
022D0080
022DFFFF
64K-128
Reserved
022E0000
022E007F
128
Reserved
022E0080
022EFFFF
64K-128
Reserved
022F0000
022F007F
128
Reserved
022F0080
022FFFFF
64K-128
Reserved
02300000
0230FFFF
64K
Reserved
20
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 2-2
Memory Map Summary for TMS320TCI6602 (Part 3 of 7)
Address
End
Bytes
Description
02310000
023101FF
512
PLL Controller
02310200
0231FFFF
64K-512
Reserved
02320000
023200FF
256
GPIO
02320100
0232FFFF
64K-256
Reserved
02330000
023303FF
1K
SmartRlex
02330400
0234FFFF
127K
Reserved
02350000
02350FFF
4K
Power Sleep Controller (PSC)
02351000
0235FFFF
64K-4K
Reserved
02360000
023603FF
1K
Memory Protection Unit (MPU) 0
02360400
02367FFF
31K
Reserved
02368000
023683FF
1K
Memory Protection Unit (MPU) 1
02368400
0236FFFF
31K
Reserved
02370000
023703FF
1K
Memory Protection Unit (MPU) 2
02370400
02377FFF
31K
Reserved
02378000
023783FF
1K
Memory Protection Unit (MPU) 3
02378400
0237FFFF
31K
Reserved
02380000
0243FFFF
768K
Reserved
02440000
02443FFF
16K
DSP Trace Formatter 0
02444000
0244FFFF
48K
Reserved
02450000
02453FFF
16K
DSP Trace Formatter 1
02454000
0245FFFF
48K
Reserved
02460000
02463FFF
16K
Reserved
02464000
0246FFFF
48K
Reserved
02470000
02473FFF
16K
Reserved
02474000
0247FFFF
48K
Reserved
02480000
02483FFF
16K
Reserved
02484000
0248FFFF
48K
Reserved
02490000
02493FFF
16K
Reserved
02494000
0249FFFF
48K
Reserved
024A0000
024A3FFF
16K
Reserved
024A4000
024AFFFF
48K
Reserved
024B0000
024B3FFF
16K
Reserved
024B4000
024BFFFF
48K
Reserved
024C0000
0252FFFF
448K
Reserved
02530000
0253007F
128
I C Data & Control
02530080
0253FFFF
64K-128
Reserved
02540000
0254003F
64
UART
02540400
0254FFFF
64K-64
Reserved
02550000
025FFFFF
704K
Reserved
02600000
02601FFF
8K
Secondary Interrupt Controller (INTC) 0
02602000
02603FFF
8K
Reserved
02604000
02605FFF
8K
Reserved
02606000
02607FFF
8K
Reserved
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Start
2
21
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-2
www.ti.com
Memory Map Summary for TMS320TCI6602 (Part 4 of 7)
Address
Start
End
Bytes
Description
02608000
02609FFF
8K
Secondary Interrupt Controller (INTC) 2
0260A000
0260BFFF
8K
Reserved
0260C000
0260DFFF
8K
Secondary Interrupt Controller (INTC) 3
0260E000
0261FFFF
72K
Reserved
ADVANCE INFORMATION
02620000
026207FF
2K
Chip-Level Registers
02620800
0263FFFF
126K
Reserved
02640000
026407FF
2K
Semaphore
02640800
0264FFFF
64K-2K
Reserved
02650000
026FFFFF
704K
Reserved
02700000
02707FFF
32K
EDMA Channel Controller (TPCC) 0
02708000
0271FFFF
96K
Reserved
02720000
02727FFF
32K
EDMA Channel Controller (TPCC) 1
02728000
0273FFFF
96K
Reserved
02740000
02747FFF
32K
EDMA Channel Controller (TPCC) 2
02748000
0275FFFF
96K
Reserved
02760000
027603FF
1K
EDMA TPCC0 Transfer Controller (TPTC) 0
02760400
02767FFF
31K
Reserved
02768000
027683FF
1K
EDMA TPCC0 Transfer Controller (TPTC) 1
02768400
0276FFFF
31K
Reserved
02770000
027703FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 0
02770400
02777FFF
31K
Reserved
02778000
027783FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 1
02778400
0277FFFF
31K
Reserved
02780000
027803FF
1K
EDMA TPCC1 Transfer Controller (TPTC) 2
02780400
02787FFF
31K
Reserved
02788000
027883FF
1K
EDMA TPCC1Transfer Controller (TPTC) 3
02788400
0278FFFF
31K
Reserved
02790000
027903FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 0
02790400
02797FFF
31K
Reserved
02798000
027983FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 1
02798400
0279FFFF
31K
Reserved
027A0000
027A03FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 2
027A0400
027A7FFF
31K
Reserved
027A8000
027A83FF
1K
EDMA TPCC2 Transfer Controller (TPTC) 3
027A8400
027AFFFF
31K
Reserved
027B0000
027CFFFF
128K
Reserved
027D0000
027D0FFF
4K
TI Embedded Trace Buffer (TETB) core 0
027D1000
027DFFFF
60K
Reserved
027E0000
027E0FFF
4K
TI Embedded Trace Buffer (TETB) core 1
027E1000
027EFFFF
60K
Reserved
027F0000
027F3FFF
60K
Reserved
027F4000
027FFFFF
4K
Reserved
02800000
02803FFF
60K
Reserved
22
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 2-2
Memory Map Summary for TMS320TCI6602 (Part 5 of 7)
Address
End
Bytes
Description
02801000
0280FFFF
60K
Reserved
02810000
02813FFF
60K
Reserved
02814000
0281FFFF
4K
Reserved
02820000
02823FFF
60K
Reserved
02824000
0282FFFF
4K
Reserved
02830000
02833FFF
60K
Reserved
02834000
0283FFFF
4K
Reserved
02840000
02843FFF
60K
Reserved
02841000
0284FFFF
60K
Reserved
02850000
02857FFF
32K
TI Embedded Trace Buffer (TETB) — system
02858000
0285FFFF
32K
Reserved
02860000
028FFFFF
640K
Reserved
02900000
02920FFF
132K
Serial RapidIO (SRIO) Configuration
02921000
029FFFFF
1M-132K
Reserved
02A00000
02BFFFFF
2M
Queue Manager Subsystem Configuration
02C00000
07FFFFFF
84M
Reserved
08000000
0800FFFF
64K
Extended Memory Controller (XMC) Configuration
08010000
0BBFFFFF
60M-64K
Reserved
0BC00000
0BCFFFFF
1M
Multicore Shared Memory Controller (MSMC) Config
0BD00000
0BFFFFFF
3M
Reserved
0C000000
0C3FFFFF
4M
Multicore Shared Memory
0C400000
107FFFFF
68 M
Reserved
10800000
1087FFFF
512K
Core0 L2 SRAM
10880000
108FFFFF
512K
Reserved
10900000
10DFFFFF
5M
Reserved
10E00000
10E07FFF
32K
Core0 L1P SRAM
10E08000
10EFFFFF
1M-32K
Reserved
10F00000
10F07FFF
32K
Core0 L1D SRAM
10F08000
117FFFFF
9M-32K
Reserved
11800000
1187FFFF
512K
Core1 L2 SRAM
11880000
118FFFFF
512K
Reserved
11900000
11DFFFFF
5M
Reserved
11E00000
11E07FFF
32K
Core1 L1P SRAM
11E08000
11EFFFFF
1M-32K
Reserved
11F00000
11F07FFF
32K
Core1 L1D SRAM
11F08000
127FFFFF
9M-32K
Reserved
12800000
1287FFFF
512K
Reserved
12880000
128FFFFF
512K
Reserved
12900000
12DFFFFF
5M
Reserved
12E00000
12E07FFF
32K
Reserved
12E08000
12EFFFFF
1M-32K
Reserved
12F00000
12F07FFF
32K
Reserved
12F08000
137FFFFF
9M-32K
Reserved
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Start
23
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-2
www.ti.com
Memory Map Summary for TMS320TCI6602 (Part 6 of 7)
Address
Start
End
Bytes
Description
13800000
1387FFFF
512K
Reserved
13880000
138FFFFF
512K
Reserved
13900000
13DFFFFF
5M
Reserved
13E00000
13E07FFF
32K
Reserved
ADVANCE INFORMATION
13E08000
13EFFFFF
1M-32K
Reserved
13F00000
13F07FFF
32K
Reserved
13F08000
147FFFFF
9M-32K
Reserved
14800000
1487FFFF
512K
Reserved
14880000
148FFFFF
512K
Reserved
14900000
14DFFFFF
5M
Reserved
14E00000
14E07FFF
32K
Reserved
14E08000
14EFFFFF
1M-32K
Reserved
14F00000
14F07FFF
32K
Reserved
14F08000
157FFFFF
9M-32K
Reserved
15800000
1587FFFF
512K
Reserved
15880000
158FFFFF
512K
Reserved
15900000
15DFFFFF
5M
Reserved
15E00000
15E07FFF
32K
Reserved
15E08000
15EFFFFF
1M-32K
Reserved
15F00000
15F07FFF
32K
Reserved
15F08000
167FFFFF
9M-32K
Reserved
16800000
1687FFFF
512K
Reserved
16880000
168FFFFF
512K
Reserved
16900000
16DFFFFF
5M
Reserved
16E00000
16E07FFF
32K
Reserved
16E08000
16EFFFFF
1M-32K
Reserved
16F00000
16F07FFF
32K
Reserved
16F08000
177FFFFF
9M-32K
Reserved
17800000
1787FFFF
512K
Reserved
17880000
178FFFFF
512K
Reserved
17900000
17DFFFFF
5M
Reserved
17E00000
17E07FFF
32K
Reserved
17E08000
17EFFFFF
1M-32K
Reserved
17F00000
17F07FFF
32K
Reserved
17F08000
1FFFFFFF
129M-32K
Reserved
20000000
200FFFFF
1M
System Trace Manager (STM) Configuration
20100000
20AFFFFF
10M
Reserved
20B00000
20B1FFFF
128K
Boot ROM
20B20000
20BEFFFF
832K
Reserved
20BF0000
20BF03FF
1K
SPI
20BF0400
20BFFFFF
63K
Reserved
20C00000
20C000FF
256
EMIF-16 Config
20C00100
20FFFFFF
12M - 256
Reserved
24
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 2-2
Memory Map Summary for TMS320TCI6602 (Part 7 of 7)
Address
End
Bytes
Description
21000000
21000123
292
DDR3 EMIF Configuration
21000100
213FFFFF
4M-256
Reserved
21400000
214003FF
1K
HyperLink Config
21400400
217FFFFF
4M-1K
Reserved
21800000
21807FFF
32K
PCIe Config
21808000
33FFFFFF
296M-32K
Reserved
34000000
341FFFFF
2M
Queue Manager Subsystem Data
34200000
3FFFFFFF
190M
Reserved
40000000
4FFFFFFF
256M
HyperLink data
50000000
5FFFFFFF
256M
Reserved
60000000
6FFFFFFF
256M
PCIe Data
70000000
73FFFFFF
64M
EMIF16 CS2 Data NAND Memory
74000000
77FFFFFF
64M
EMIF16 CS3 Data NAND Memory
78000000
7BFFFFFF
64M
EMIF16 CS4 Data NOR Memory
7C000000
7FFFFFFF
64M
EMIF16 CS5 Data SRAM Memory
80000000
8FFFFFFF
256M
DDR3_ Data
90000000
9FFFFFFF
256M
DDR3_ Data
A0000000
AFFFFFFF
256M
DDR3_ Data
B0000000
BFFFFFFF
256M
DDR3_ Data
C0000000
CFFFFFFF
256M
DDR3_ Data
D0000000
DFFFFFFF
256M
DDR3_ Data
E0000000
EFFFFFFF
256M
DDR3_ Data
F0000000
FFFFFFFF
256M
DDR3_ Data
ADVANCE INFORMATION
Start
End of Table 2-2
2.4 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect
the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section
7.5 ‘‘Reset Controller’’ on page 113.
The TCI6602 supports several boot processes that begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software-driven and use
the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be
completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide (literature number
SPRUGY5).
Copyright 2011 Texas Instruments Incorporated
25
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.5 Boot Modes Supported and PLL Settings
ADVANCE INFORMATION
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:
• Public ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base
2
address. After performing the boot process (e.g., from I C ROM, Ethernet, or RapidIO), C66x CorePac0 then
begins execution from the provided boot entry point, other C66x CorePac’s are released from reset and begin
executing an IDLE from the L3 ROM. They are then released from IDLE based on interrupts generated by
C66x CorePac0. See the Bootloader for the C66x DSP User Guide (literature number SPRUGY5) for more
details.
• Secure ROM Boot - On secure devices, the C66x CorePac0 is released from reset and begin executing from
secure ROM. Software in the secure ROM will free up internal RAM pages, after which C66x CorePac 0
initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the
bootloaded image prior to beginning execution.
The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by
the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the
associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].
Figure 2-2
Boot Mode Pin Decoding
Boot Mode Pins
12
11
10
9
8
PLL Mult
2
I C /SPI Ext Dev Cfg
7
6
Device Configuration
5
4
3
2
1
0
Boot Device
2.5.1 Boot Device Field
The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 shows the supported boot
modes.
Table 2-3
Boot Mode Pins: Boot Device Values
Bit
Field
Description
2-0
Boot Device
Device boot mode
0 = EMIF16 / No Boot
1 = Serial Rapid I/O
2 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as CORECLK(P|N); BOOTMODE[12:10] values drive
the PASS PLL configuration during boot.
3 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as SRIOSGMIICLK(P|N); BOOTMODE[9:8] values
drive the PASS PLL configuration during boot.
4 = PCI
5 = I2C
6 = SPI
7 = HyperLink
End of Table 2-3
26
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.5.2 Device Configuration Field
The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit
definitions depend on the boot mode
2.5.2.1 No Boot/ EMIF16 Boot Device Configuration
Figure 2-3
No Boot/ EMIF16 Configuration Fields
9
8
Reserved
6
Wait Enable
Reserved
5
4
3
Sub-Mode
Reserved
No Boot / EMIF16 Configuration Field Descriptions
Bit
Field
Description
9-8
Reserved
Reserved
7
Wait Enable
Extended Wait mode for EMIF16.
0 = Wait enable disabled (EMIF16 sub mode)
1 = Wait enable enabled (EMIF16 sub mode)
6
Reserved
Reserved
5-4
Sub-Mode
Sub mode selection.
0 = No boot
1 = EMIF16 boot
2 -3 = Reserved
3
Reserved
Reserved
ADVANCE INFORMATION
Table 2-4
7
End of Table 2-4
2.5.2.2 Ethernet (SGMII) Boot Device Configuration
Figure 2-4
Ethernet (SGMII) Device Configuration Fields
9
8
7
SerDes Clock Mult
Table 2-5
6
Ext connection
5
Device ID
4
3
Reserved
Ethernet (SGMII) Configuration Field Descriptions
Bit
Field
Description
9-8
SerDes Clock Mult
SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.
0 = ×8 for input clock of 156.25 MHz
1 = ×5 for input clock of 250 MHz
2 = ×4 for input clock of 312.5 MHz
3 = Reserved
7-6
Ext connection
External connection mode
0 = Mac to Mac connection, master with auto negotiation
1 = Mac to Mac connection, slave, and Mac to Phy
2 = Mac to Mac, forced link
3 = Mac to fiber connection
5
Device ID
This value is used in the device ID field of the Ethernet-ready frame and can range from 0 to 7.
4-3
Reserved
Reserved
End of Table 2-5
Copyright 2011 Texas Instruments Incorporated
27
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.5.2.3 Serial Rapid I/O Boot Device Configuration
The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
Figure 2-5
Serial Rapid I/O Device Configuration Fields
9
8
Lane Setup
Table 2-6
7
6
Data Rate
5
4
Ref Clock
3
Reserved
Serial Rapid I/O Configuration Field Descriptions
ADVANCE INFORMATION
Bit
Field
Description
9
Lane Setup
SRIO port and lane configuration
0 = Port Configured as 4 ports each 1 lane wide (4 -1× ports)
1 = Port Configured as 2 ports 2 lanes wide (2 – 2× ports)
8-7
Data Rate
SRIO data rate configuration
0 = 1.25 GBs
1 = 2.5 GBs
2 = 3.125 GBs
3 = 5.0 GBs
6-5
Ref Clock
SRIO reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
4-3
Reserved
Reserved
End of Table 2-6
In SRIO boot mode, the message mode will be enabled by default. If use of the memory reserved for received
messages is required and reception of messages cannot be prevented, the master can disable the message mode by
writing to the boot table and generating a boot restart.
2.5.2.4 PCI Boot Device Configuration
Extra device configuration is provided in the PCI bits in the DEVSTAT register.
Figure 2-6
PCI Device Configuration Fields
9
8
7
Reserved
Table 2-7
6
BAR Config
5
4
3
Reserved
PCI Device Configuration Field Descriptions
Bit
Field
Description
9
Reserved
Reserved
8-5
BAR Config
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 2-8.
4-3
Reserved
Reserved
End of Table 2-7
28
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
BAR Config / PCIe Window Sizes
32-Bit Address Translation
64-Bit Address Translation
BAR cfg
BAR0
BAR1
BAR2
BAR3
BAR4
BAR5
0b0000
PCIe MMRs
32
32
32
32
Clone of BAR4
BAR2/3
BAR4/5
0b0001
16
16
32
64
0b0010
16
32
32
64
0b0011
32
32
32
64
0b0100
16
16
64
64
0b0101
16
32
64
64
0b0110
32
32
64
64
0b0111
32
32
64
128
0b1000
64
64
128
256
0b1001
4
128
128
128
0b1010
4
128
128
256
0b1011
0b1100
4
128
256
256
256
256
0b1101
512
512
0b1110
1024
1024
0b1111
2048
2048
End of Table 2-8
2
2.5.2.5 I C Boot Device Configuration
2.5.2.5.1 I2C Master Mode
2
In master mode, the I C device configuration uses ten bits of device configuration instead of seven as used in other
2
boot modes. In this mode, the device will make the initial read of the I C EEPROM while the PLL is in bypass mode.
The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.
I2C Master Mode Device Configuration Bit Fields
Figure 2-7
12
11
10
9
8
Reserved
Speed
Address
Reserved
Mode
Table 2-9
7
6
5
4
3
Parameter Index
I2C Master Mode Device Configuration Field Descriptions
Bit
Field
Description
12
Reserved
Reserved
11
Speed
I C data rate configuration
2
0 = I C data rate set to approximately 20 kHz
2
1 = I C fast mode. Data rate set to approximately 400 kHz (will not exceed)
10
Address
I2C bus address configuration
2
2
0 = Boot from I C EEPROM at I C bus address 0x50
2
1 = Boot from I C EEPROM at I2C bus address 0x51
9
Reserved
Reserved
8
Mode
I C operation mode
0 = Master mode
2
1 = Passive mode (see section I C Passive Mode)
7-3
Parameter Index
Identifies the index of the configuration table initially read from the I2C EEPROM
2
2
This value can range from 0 to 31.
End of Table 2-9
Copyright 2011 Texas Instruments Incorporated
29
ADVANCE INFORMATION
Table 2-8
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.5.2.5.2 I2C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
I2C Passive Mode Device Configuration Bit Fields
Figure 2-8
9
8
Reserved
Table 2-10
7
5
4
2
Mode
Receive I C Address
3
Reserved
I2C Passive Mode Device Configuration Field Descriptions
ADVANCE INFORMATION
Bit
Field
Description
9
Reserved
Reserved
8
Mode
I2C operation mode
0 = Master Mode (See ‘‘I2C Master Mode’’ on page 29)
1 = Passive Mode
7-5
Receive I C Address
I C bus address configuration
0 - 7 = The I2C Bus address the device will listen to for data
4-3
Reserved
Reserved
2
2
End of Table 2-10
2.5.2.6 SPI Boot Device Configuration
In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.
Figure 2-9
SPI Device Configuration Bit Fields
12
11
Mode
Table 2-11
10
9
4, 5 Pin
Addr Width
8
7
Chip Select
6
5
Parameter Table Index
4
3
Reserved
SPI Device Configuration Field Descriptions
Bit
Field
Description
12-11
Mode
Clk Pol / Phase
0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data
is latched on the rising edge of SPICLK.
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data
is latched on the falling edge of SPICLK.
10
4, 5 Pin
SPI operation mode configuration
0 = 4-pin mode used
1 = 5-pin mode used
9
Addr Width
SPI address width configuration
0 = 16-bit address values are used
1 = 24-bit address values are used
8-7
Chip Select
The chip select field value
6-5
Parameter Table Index
Specifies which parameter table is loaded
4-3
Reserved
Reserved
End of Table 2-11
30
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10
HyperLink Boot Device Configuration Fields
9
8
7
Reserved
Data Rate
5
4
3
Ref Clock
Reserved
HyperLink Boot Device Configuration Field Descriptions
Bit
Field
Description
9
Reserved
Reserved
8-7
Data Rate
HyperLink data rate configuration
0 = 1.25 GBs
1 = 3.125 GBs
2 = 6.25 GBs
3 = 12.5 GBs
6-5
Ref Clocks
HyperLink reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
4-3
Reserved
Reserved
End of Table 2-12
2.5.3 PLL Boot Configuration Settings
The PLL default settings are determined by the BOOTMODE[12:10] bits. Table 2-13 shows settings for various
input clock frequencies. OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the
maximum clock setting for the device (with OUTPUT_DIVIDE=2, by default).
CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1))
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet
boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See
Table 2-3 for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip
divider to reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after
the chip divider (=3), feeds 350 MHz to the NETCP.
See section 7.6 ‘‘Main PLL and PLL Controller’’ on page 118 for further details
Table 2-13
C66x DSP System PLL Configuration
1000 MHz Device
1250 MHz Device
PASS PLL = 350 MHz
BOOTMODE
[12:10]
Input Clock
Freq (MHz)
0b000
50.00
0
39
1000
0
49
1250
0
41
1050
0b001
66.67
0
29
1000.05
1
74
1250.06
1
62
1050.053
0b010
80.00
0
24
1000
3
124
1250
3
104
1050
0b011
100.00
0
19
1000
0
24
1250
0
20
1050
PLLD
PLLM
DSP ƒ
PLLD
PLLM
DSP ƒ
PLLD
PLLM
DSP ƒ
0b100
156.25
4
63
1000
24
399
1250
24
335
1050
0b101
250.00
0
7
1000
4
49
1250
4
41
1050
0b110
312.50
4
31
1000
24
199
1200
24
167
1050
0b111
122.88
28
471
999.989
31
650
1249.92
11
204
1049.6
End of Table 2-13
Copyright 2011 Texas Instruments Incorporated
31
ADVANCE INFORMATION
Table 2-12
6
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.
2.7 Terminals
2.7.1 Package Terminals
Figure 2-11 shows the TMS320TCI6602CYP ball grid area (BGA) package (bottom view).
Figure 2-11
CYP 841-Pin BGA Package (Bottom View)
ADVANCE INFORMATION
AH
AF
AD
AB
Y
AJ
AG
AE
AC
AA
W
V
T
U
R
P
N
M
L
K
J
H
F
D
G
E
C
B
A
3
1
2
5
4
9
7
6
8
11 13 15 17 19 21 23 25 27 29
10 12 14 16 18 20 22 24 26 28
2.7.2 Pin Map
Figure 2-13 through Figure 2-16 show the TMS320TCI6602 pin assignments in four quadrants (A, B, C, and D).
Figure 2-12
32
Pin Map Quadrants (Bottom View)
A
B
D
C
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Upper Left Quadrant—A (Bottom View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AJ
VSS
DVDD18
RSV05
PASSCLKN
PASSCLKP
SRIOSGMII
CLKN
VSS
PCIERXP1
PCIERXN1
VSS
RIORXN0
RIORXP0
VSS
RIORXP3
RIORXN3
AH
DVDD18
RSV04
RSV25
RSV24
PCIECLKN
VSS
PCIERXN0
PCIERXP0
VSS
RIORXN1
RIORXP1
VSS
RIORXP2
RIORXN2
VSS
AG
SPISCS0
SPISCS1
PCIECLKP
SRIOSGMII
CLKP
VSS
PCIETXP1
PCIETXN1
VSS
RIOTXN1
RIOTXP1
VSS
RIOTXP2
RIOTXN2
AF
RSV22
CORESEL0
DVDD18
VSS
PCIETXP0
PCIETXN0
VSS
RIOTXN0
RIOTXP0
VSS
RIOTXP3
RIOTXN3
VSS
AE
SPICLK
BOOT
COMPLETE SYSCLKOUT PACLKSEL
CORESEL3
CORESEL2
VSS
VSS
VSS
VDDR2
VSS
RSV15
VSS
VDDR4
VSS
AD
UARTRXD
SPIDIN
SCL
CORESEL1
AVDDA3
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
AC
UARTTXD
VSS
DVDD18
SDA
VSS
AVDDA2
VSS
VDDT2
RSV16
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
AB
SPIDOUT
UARTRTS
UARTCTS
VSS
DVDD18
VSS
DVDD18
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
AA
MCMTX
FLCLK
MCMTX
PMCLK
MCMTX
FLDAT
MCMTX
PMDAT
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
Y
MCMREF
CLKOUTP
MCMCLKN
MCMRX
PMCLK
MCMRX
PMDAT
RSV12
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
W
MCMREF
CLKOUTN
MCMCLKP
MCMRX
FLCLK
MCMRX
FLDAT
RSV13
RSV14
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
VSS
V
VSS
VSS
VSS
VSS
VDDR1
VSS
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
U
VSS
MCMRXN0
VSS
MCMTXP1
VSS
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
VSS
T
MCMRXN1
MCMRXP0
VSS
MCMTXN1
MCMTXP2
VSS
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
CORECLKP CORECLKN
RSV20
VSS
A
Copyright 2011 Texas Instruments Incorporated
33
ADVANCE INFORMATION
Figure 2-13
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Figure 2-14
www.ti.com
Upper Right Quadrant—B (Bottom View)
ADVANCE INFORMATION
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VSS
SGMII0RXP
SGMII0RXN
VSS
TR15
TR13
FSB1
CLKA1
TX02
TR01
FSA0
EMU16
DVDD18
VSS
AJ
SGMII1RXP
SGMII1RXN
VSS
RSV08
TX16
TR16
TR14
CLKB1
TX04
TR05
TR00
EMU18
RSV01
DVDD18
AH
VSS
SGMII0TXP
SGMII0TXN
VSS
TX14
TR17
DVDD18
FSA1
TX03
CLKB0
FSB0
EMU15
EMU14
EMU12
AG
SGMII1TXP
SGMII1TXN
VSS
RSV09
TX17
TX10
VSS
TX07
TX05
CLKA0
DVDD18
EMU17
EMU11
EMU09
AF
VDDR3
VSS
VDDT2
VSS
TX15
TX13
TR10
TX06
TX00
TR07
VSS
EMU10
EMU08
EMU07
AE
VSS
VDDT2
VSS
RSV17
HOUT
TR11
TX11
TR02
TR03
TX01
EMU13
EMU06
EMU05
EMU04
AD
VDDT2
VSS
VDDT2
VSS
POR
TR12
TX12
TR04
TR06
EMIFD15
EMU03
EMU02
EMU01
EMU00
AC
VSS
VDDT2
VSS
DVDD18
VSS
DVDD18
VSS
EMIFD12
EMIFD13
EMIFD09
EMIFD14
EMIFD05
DVDD18
EMIFD01
AB
CVDD
VSS
CVDD
VSS
RSV0B
RSV0A
CVDD
VSS
EMIFD10
EMIFD07
EMIFD06
EMIFD04
VSS
EMIFD02
AA
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
EMIFD11
EMIFD08
EMIFD03
EMIFD00
EMIFA22
EMIFA21
Y
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
EMIFA20
EMIFA19
EMIFA18
EMIFA17
EMIFA15
EMIFA14
EMIFA16
W
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
EMIFA13
EMIFA12
EMIFA11
EMIFA10
EMIFA08
EMIFA09
V
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
EMIFA23
EMIFA07
EMIFA06
DVDD18
EMIFA04
EMIFA05
EMIFA02
U
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
EMIFA01
EMIFA03
VSS
EMIFA00
EMIFWAIT1 EMIFWAIT0
T
B
34
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Figure 2-15
Lower Right Quadrant—C (Bottom View)
R
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
EMIFBE1
EMIFBE0
EMIFCE3
EMIFOE
EMIFCE1
EMIFCE2
TDO
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
EMIFWE
EMIFCE0
EMIFRW
TDI
TRST
TMS
P
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
RSV03
RSV02
RESETFULL
LRESET
RESETSTAT
DVDD18
TCK
N
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
RSV26
RSV27
NMI
TIMO1
LRESET
NMIEN
VSS
RESET
M
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
VCNTL0
TIMI0
TIMO0
TIMI1
GPIO15
GPIO11
GPIO12
L
VSS
CVDD
VSS
CVDD
VSS
CVDD
RSV10
VCNTL1
GPIO14
GPIO13
GPIO09
GPIO07
GPIO08
GPIO10
K
CVDD
VSS
CVDD
VSS
CVDD
VSS
RSV11
VCNTL2
GPIO06
GPIO04
GPIO03
GPIO05
GPIO01
GPIO02
J
VSS
CVDD
VSS
CVDD
VSS
CVDD
AVDDA1
VCNTL3
DVDD18
GPIO00
MDCLK
DDRSL
RATE1
RSV06
DDRCLKN
H
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
PTV15
DVDD15
VSS
RSV21
MDIO
DDRSL
RATE0
RSV07
DDRCLKP
G
VSS
DVDD15
VSS
DVDD15
DDRD25
DDRD27
DDRD17
DDRD16
DDRD08
DDRD07
DVDD15
VSS
DVDD15
VSS
F
DDRA10
DDRA12
DDRCKE1
DDRCB00
VSS
DDRD26
DDRD23
DDRD19
DDRD09
DDRD10
DDRD06
DDRD02
DDRD00
DDRDQM0
E
DDRA11
DDRA14
VSS
DDRCB02
DVDD15
DDRD24
DDRD28
DVDD15
DDRD18
DDRD11
DDRD12
DDRD04
DDRD03
DDRD01
D
DDRA13
DDRA15
DDRCB05
DDRCB04
DDRCB01
DDRD29
DDRD31
VSS
DDRD22
DVDD15
DDRD13
DDRDQM1
DDRCLK
OUTN1
VSS
DDRCB06
DDRDQS8N
DDRCB03
DDRDQS3N
DDRD30
DDRD21
DDRDQS2N
VSS
DDRD14
DDRDQS1N
DDRD05
DVDD15
B
DDRCLK
OUTP1
DVDD15
DDRCB07
DDRDQS8P
DDRDQM8
DDRDQS3P
DDRDQM3
DDRD20
DDRDQS2P
DDRDQM2
DDRD15
DDRDQS1P
DVDD15
VSS
A
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Copyright 2011 Texas Instruments Incorporated
DDRDQS0P DDRDQS0N
C
35
ADVANCE INFORMATION
C
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Figure 2-16
www.ti.com
Lower Left Quadrant—D (Bottom View)
D
ADVANCE INFORMATION
R
MCMRXP1
VSS
VSS
VSS
MCMTXN2
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
VSS
P
VSS
MCMRXN3
VSS
MCMTXP3
VSS
VSS
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
N
MCMRXP2
MCMRXP3
VSS
MCMTXN3
MCMTXP0
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
M
MCMRXN2
VSS
VSS
VSS
MCMTXN0
VSS
VDDT1
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
K
VSS
VSS
VSS
VSS
VSS
VSS
CVDD1
VSS
CVDD1
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
H
VSS
VSS
VSS
VSS
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
G
VSS
DVDD15
VSS
DVDD15
VSS
VSS
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
F
DDRD63
DDRD60
DDRD61
DDRD56
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DDRA03
DDRA02
DDRA08
E
DDRD62
DDRD58
DVDD15
DDRD53
VSS
DDRD45
DDRD42
DDRD39
DDRD36
DDRD32
DDRRESET
DDRWE
DDRODT1
VREFSSTL
DDRA09
D
DDRDQS7P
DDRD57
VSS
DDRD52
DVDD15
DDRD46
DDRD41
DVDD15
DDRD35
DDRD33
DDRCKE0
DDRCAS
DDRODT0
VSS
DDRA07
C
DDRDQS7N
DDRD59
DDRD55
DDRD54
DDRD48
DDRD47
DDRD43
VSS
DDRD37
DDRRAS
DDRCE0
DDRCE1
DDRBA2
DVDD15
DDRA05
B
DVDD15
DDRD44
DDRD38
DDRDQS4N
DDRD34
VSS
DDRCLK
OUTN0
DDRBA1
DDRA01
DDRA06
A
VSS
DVDD15
DDRDQS6N
DDRD51
DDRD49
DDRDQS5N
DDRD40
DVDD15
DDRCLK
OUTP0
DDRBA0
DDRA00
DDRA04
1
2
3
4
5
6
7
11
12
13
14
15
36
DDRDQM7 DDRDQS6P
DDRD50
DDRDQM6 DDRDQS5P
DDRDQM5 DDRDQS4P DDRDQM4
8
9
10
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
2.8 Terminal Functions
The terminal functions table (Table 2-15) identifies the external signal names, the associated pin (ball) numbers, the
pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin
descriptions. This table is arranged by function. The power terminal functions table (Table 2-16) lists the various
power supply pins and ground pins and gives functional pin descriptions. Table 2-17 shows all pins arranged by
signal name. Table 2-18 shows all pins arranged by ball number.
There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated
with a dagger (†).
ADVANCE INFORMATION
For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and
pullup/pulldown resistors, see section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 81.
Use the symbol definitions in Table 2-14 when reading Table 2-15.
Table 2-14
I/O Functional Symbol Definitions
Functional
Symbol
IPD or IPU
A
Definition
Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can
be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and
situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for
KeyStone Devices (literature number SPRABI2).
Table 2-15
Column Heading
IPD/IPU
Analog signal
Type
Ground
Type
Input terminal
Type
O
Output terminal
Type
S
Supply voltage
Type
Z
Three-state terminal or high impedance
Type
GND
I
End of Table 2-14
Table 2-15
Signal Name
Terminal Functions — Signals and Control by Function (Part 1 of 12)
Ball No. Type
IPD/IPU
Description
Boot Configuration Pins
LENDIAN †
H25
IOZ
UP
BOOTMODE00 †
J28
IOZ
Down
BOOTMODE01†
J29
IOZ
Down
BOOTMODE02 †
J26
IOZ
Down
BOOTMODE03 †
J25
IOZ
Down
BOOTMODE04 †
J27
IOZ
Down
BOOTMODE05 †
J24
IOZ
Down
BOOTMODE06 †
K27
IOZ
Down
BOOTMODE07 †
K28
IOZ
Down
BOOTMODE08 †
K26
IOZ
Down
BOOTMODE09 †
K29
IOZ
Down
BOOTMODE10 †
L28
IOZ
Down
BOOTMODE11 †
L29
IOZ
Down
BOOTMODE12 †
K25
IOZ
Down
Copyright 2011 Texas Instruments Incorporated
Endian configuration pin (Pin shared with GPIO[0])
See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 26 for more details
(Pins shared with GPIO[1:13])
37
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 2 of 12)
Signal Name
Ball No. Type
IPD/IPU
PCIESSMODE0 †
K24
IOZ
Down
Description
PCIESSMODE1 †
L27
IOZ
Down
PCIESSEN †
L24
I
Down
CORECLKP
AG3
I
CORECLKN
AG4
I
SRIOSGMIICLKP
AG6
I
SRIOSGMIICLKN
AJ6
I
DDRCLKP
G29
I
DDRCLKN
H29
I
PCIECLKP
AG5
I
PCIECLKN
AH5
I
MCMCLKP
W2
I
MCMCLKN
Y2
I
PASSCLKP
AJ5
I
PASSCLKN
AJ4
I
AVDDA1
H22
P
AVDDA2
AC6
P
DDR_CLK PLL Power Supply Pin
AVDDA3
AD5
P
PASS_CLK PLL Power Supply Pin
PCIe Mode selection pins (Pins shared with GPIO[14:15])
PCIe module enable (Pin shared with TIMI0)
Clock / Reset
Core Clock Input to main PLL.
RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes
ADVANCE INFORMATION
DDR Reference Clock Input to DDR PLL (
PCIe Clock Input to drive PCIe SerDes
HyperLink Reference Clock to drive the HyperLink SerDes
Network Coprocessor (PASS PLL) Reference Clock
SYS_CLK PLL Power Supply Pin
SYSCLKOUT
AE3
OZ
Down
System Clock Output to be used as a general purpose output clock for debug purposes
PACLKSEL
AE4
I
Down
PA clock select to choose between core clock and PASSCLK pins
HOUT
AD20
OZ
UP
Interrupt output pulse created by IPCGRH
NMI
M25
I
UP
Non-maskable Interrupt
LRESET
N26
I
UP
Warm Reset
LRESETNMIEN
M27
I
UP
Enable for core selects
CORESEL0
AF2
I
Down
CORESEL1
AD4
I
Down
CORESEL2
AE6
I
Down
CORESEL3
AE5
I
Down
RESETFULL
N25
I
UP
Full Reset
RESET
M29
I
UP
Warm Reset of non isolated portion on the IC
POR
AC20
I
RESETSTAT
N27
O
UP
Reset Status Output
BOOTCOMPLETE
AE2
OZ
Down
Boot progress indication output
PTV15
G22
A
38
Select for the target core for LRESET and NMI. For more details see Table 7-48‘‘NMI and
Local Reset Timing Requirements’’ on page 160
Power-on Reset
PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15
pin and ground is used to closely tune the output impedance of the DDR interface drivers
to 50ohms. Presently the recommended value for this 1% resistor is 45.3 ohms.
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 2-15
Signal Name
Terminal Functions — Signals and Control by Function (Part 3 of 12)
Ball No. Type
IPD/IPU
Description
DDR
E29
OZ
DDRDQM1
C27
OZ
DDRDQM2
A25
OZ
DDRDQM3
A22
OZ
DDRDQM4
A10
OZ
DDRDQM5
A8
OZ
DDRDQM6
B5
OZ
DDRDQM7
B2
OZ
DDRDQM8
A20
OZ
DDRDQS0P
C28
IOZ
DDRDQS0N
C29
IOZ
DDRDQS1P
A27
IOZ
DDRDQS1N
B27
IOZ
DDRDQS2P
A24
IOZ
DDRDQS2N
B24
IOZ
DDRDQS3P
A21
IOZ
DDRDQS3N
B21
IOZ
DDRDQS4P
A9
IOZ
DDRDQS4N
B9
IOZ
DDRDQS5P
B6
IOZ
DDRDQS5N
A6
IOZ
DDRDQS6P
B3
IOZ
DDRDQS6N
A3
IOZ
DDRDQS7P
D1
IOZ
DDRDQS7N
C1
IOZ
DDRDQS8P
A19
IOZ
DDRDQS8N
B19
IOZ
DDRCB00
E19
IOZ
DDRCB01
C20
IOZ
DDRCB02
D19
IOZ
DDRCB03
B20
IOZ
DDRCB04
C19
IOZ
DDRCB05
C18
IOZ
DDRCB06
B18
IOZ
DDRCB07
A18
IOZ
Copyright 2011 Texas Instruments Incorporated
DDR EMIF Data Masks
ADVANCE INFORMATION
DDRDQM0
DDR EMIF Data Strobe
DDR EMIF Check Bits
39
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 4 of 12)
Signal Name
Ball No. Type
DDRD00
E28
DDRD01
D29
IOZ
DDRD02
E27
IOZ
DDRD03
D28
IOZ
DDRD04
D27
IOZ
ADVANCE INFORMATION
DDRD05
B28
IOZ
DDRD06
E26
IOZ
DDRD07
F25
IOZ
DDRD08
F24
IOZ
DDRD09
E24
IOZ
DDRD10
E25
IOZ
DDRD11
D25
IOZ
DDRD12
D26
IOZ
DDRD13
C26
IOZ
DDRD14
B26
IOZ
DDRD15
A26
IOZ
DDRD16
F23
IOZ
DDRD17
F22
IOZ
DDRD18
D24
IOZ
DDRD19
E23
IOZ
DDRD20
A23
IOZ
DDRD21
B23
IOZ
DDRD22
C24
IOZ
DDRD23
E22
IOZ
DDRD24
D21
IOZ
DDRD25
F20
IOZ
DDRD26
E21
IOZ
DDRD27
F21
IOZ
DDRD28
D22
IOZ
DDRD29
C21
IOZ
DDRD30
B22
IOZ
DDRD31
C22
IOZ
DDRD32
E10
IOZ
DDRD33
D10
IOZ
DDRD34
B10
IOZ
DDRD35
D9
IOZ
DDRD36
E9
IOZ
DDRD37
C9
IOZ
DDRD38
B8
IOZ
DDRD39
E8
IOZ
DDRD40
A7
IOZ
DDRD41
D7
IOZ
40
IPD/IPU
Description
IOZ
DDR EMIF Data Bus
DDR EMIF Data Bus
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Terminal Functions — Signals and Control by Function (Part 5 of 12)
Signal Name
Ball No. Type
DDRD42
E7
IOZ
DDRD43
C7
IOZ
DDRD44
B7
IOZ
DDRD45
E6
IOZ
DDRD46
D6
IOZ
DDRD47
C6
IOZ
DDRD48
C5
IOZ
DDRD49
A5
IOZ
DDRD50
B4
IOZ
DDRD51
A4
IOZ
DDRD52
D4
IOZ
DDRD53
E4
IOZ
DDRD54
C4
IOZ
DDRD55
C3
IOZ
DDRD56
F4
IOZ
DDRD57
D2
IOZ
DDRD58
E2
IOZ
DDRD59
C2
IOZ
DDRD60
F2
IOZ
DDRD61
F3
IOZ
DDRD62
E1
IOZ
DDRD63
F1
IOZ
DDRCE0
C11
OZ
DDRCE1
C12
OZ
DDRBA0
A13
OZ
DDRBA1
B13
OZ
DDRBA2
C13
OZ
DDRA00
A14
OZ
DDRA01
B14
OZ
DDRA02
F14
OZ
DDRA03
F13
OZ
DDRA04
A15
OZ
DDRA05
C15
OZ
DDRA06
B15
OZ
DDRA07
D15
OZ
DDRA08
F15
OZ
DDRA09
E15
OZ
DDRA10
E16
OZ
DDRA11
D16
OZ
DDRA12
E17
OZ
DDRA13
C16
OZ
DDRA14
D17
OZ
DDRA15
C17
OZ
DDRCAS
D12
OZ
IPD/IPU
Copyright 2011 Texas Instruments Incorporated
Description
ADVANCE INFORMATION
Table 2-15
DDR EMIF Data Bus
DDR EMIF Chip Enables
DDR EMIF Bank Address
DDR EMIF Address Bus
DDR EMIF Column Address Strobe
41
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 6 of 12)
Signal Name
Ball No. Type
DDRRAS
C10
OZ
DDR EMIF Row Address Strobe
DDRWE
E12
OZ
DDR EMIF Write Enable
DDRCKE0
D11
OZ
DDR EMIF Clock Enable
DDR EMIF Clock Enable
ADVANCE INFORMATION
DDRCKE1
E18
OZ
DDRCLKOUTP0
A12
OZ
DDRCLKOUTN0
B12
OZ
DDRCLKOUTP1
A16
OZ
DDRCLKOUTN1
B16
OZ
DDRODT0
D13
OZ
IPD/IPU
Description
DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDRODT1
E13
OZ
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDRRESET
E11
OZ
DDR Reset signal
DDRSLRATE0
G27
I
Down
DDRSLRATE1
H27
I
Down
VREFSSTL
E14
P
DDR Slew rate control
Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)
EMIF16
EMIFRW
P26
O
UP
EMIFCE0
P25
O
UP
EMIFCE1
R27
O
UP
EMIFCE2
R28
O
UP
EMIFCE3
R25
O
UP
EMIFOE
R26
O
UP
EMIFWE
P24
O
UP
EMIFBE0
R24
O
UP
EMIFBE1
R23
O
UP
EMIFWAIT0
T29
I
Down
EMIFWAIT1
T28
I
Down
42
EMIF16 Control Signals
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Terminal Functions — Signals and Control by Function (Part 7 of 12)
Signal Name
Ball No. Type
IPD/IPU
EMIFA00
T27
Down
EMIFA01
T24
O
Down
EMIFA02
U29
O
Down
EMIFA03
T25
O
Down
EMIFA04
U27
O
Down
EMIFA05
U28
O
Down
EMIFA06
U25
O
Down
EMIFA07
U24
O
Down
EMIFA08
V28
O
Down
EMIFA09
V29
O
Down
EMIFA10
V27
O
Down
EMIFA11
V26
O
Down
EMIFA12
V25
O
Down
O
EMIFA13
V24
O
Down
EMIFA14
W28
O
Down
EMIFA15
W27
O
Down
EMIFA16
W29
O
Down
EMIFA17
W26
O
Down
EMIFA18
W25
O
Down
EMIFA19
W24
O
Down
EMIFA20
W23
O
Down
EMIFA21
Y29
O
Down
EMIFA22
Y28
O
Down
EMIFA23
U23
O
Down
EMIFD00
Y27
IOZ
Down
EMIFD01
AB29
IOZ
Down
EMIFD02
AA29
IOZ
Down
EMIFD03
Y26
IOZ
Down
EMIFD04
AA27
IOZ
Down
EMIFD05
AB27
IOZ
Down
EMIFD06
AA26
IOZ
Down
EMIFD07
AA25
IOZ
Down
EMIFD08
Y25
IOZ
Down
EMIFD09
AB25
IOZ
Down
EMIFD10
AA24
IOZ
Down
EMIFD11
Y24
IOZ
Down
EMIFD12
AB23
IOZ
Down
EMIFD13
AB24
IOZ
Down
EMIFD14
AB26
IOZ
Down
EMIFD15
AC25
IOZ
Down
Copyright 2011 Texas Instruments Incorporated
Description
ADVANCE INFORMATION
Table 2-15
EMIF16 Address
EMIF16 Data
43
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-15
Signal Name
www.ti.com
Terminal Functions — Signals and Control by Function (Part 8 of 12)
Ball No. Type
IPD/IPU
Description
EMU
ADVANCE INFORMATION
EMU00
AC29
IOZ
UP
EMU01
AC28
IOZ
UP
EMU02
AC27
IOZ
UP
EMU03
AC26
IOZ
UP
EMU04
AD29
IOZ
UP
EMU05
AD28
IOZ
UP
EMU06
AD27
IOZ
UP
EMU07
AE29
IOZ
UP
EMU08
AE28
IOZ
UP
EMU09
AF29
IOZ
UP
EMU10
AE27
IOZ
UP
EMU11
AF28
IOZ
UP
EMU12
AG29
IOZ
UP
EMU13
AD26
IOZ
UP
EMU14
AG28
IOZ
UP
EMU15
AG27
IOZ
UP
EMU16
AJ27
IOZ
UP
EMU17
AF27
IOZ
UP
EMU18
AH27
IOZ
UP
Emulation and Trace Port
General Purpose Input/Output (GPIO)
GPIO00
H25
IOZ
UP
GPIO01
J28
IOZ
Down
GPIO02
J29
IOZ
Down
GPIO03
J26
IOZ
Down
GPIO04
J25
IOZ
Down
GPIO05
J27
IOZ
Down
GPIO06
J24
IOZ
Down
GPIO07
K27
IOZ
Down
GPIO08
K28
IOZ
Down
GPIO09
K26
IOZ
Down
GPIO10
K29
IOZ
Down
GPIO11
L28
IOZ
Down
GPIO12
L29
IOZ
Down
GPIO13
K25
IOZ
Down
GPIO14
K24
IOZ
Down
GPIO15
L27
IOZ
Down
44
General Purpose Input/Output
These GPIO pins have secondary functions assigned to them as mentioned in the ‘‘Boot
Configuration Pins’’ on page 37.
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 2-15
Terminal Functions — Signals and Control by Function (Part 9 of 12)
Signal Name
Ball No. Type
IPD/IPU
Description
HyperLink
U2
I
MCMRXP0
T2
I
MCMRXN1
T1
I
MCMRXP1
R1
I
MCMRXN2
M1
I
MCMRXP2
N1
I
MCMRXN3
P2
I
MCMRXP3
N2
I
MCMTXN0
M5
O
MCMTXP0
N5
O
MCMTXN1
T4
O
MCMTXP1
U4
O
MCMTXN2
R5
O
MCMTXP2
T5
O
MCMTXN3
N4
O
MCMTXP3
P4
O
Serial HyperLink Receive Data
ADVANCE INFORMATION
MCMRXN0
Serial HyperLink Transmit Data
MCMRXFLCLK
W3
O
Down
MCMRXFLDAT
W4
O
Down
MCMTXFLCLK
AA1
I
Down
MCMTXFLDAT
AA3
I
Down
MCMRXPMCLK
Y3
I
Down
MCMRXPMDAT
Y4
I
Down
MCMTXPMCLK
AA2
O
Down
MCMTXPMDAT
AA4
O
Down
MCMREFCLKOUTP
Y1
O
MCMREFCLKOUTN
W1
O
Serial HyperLink Sideband Signals
HyperLink Reference clock output for daisy chain connection
2
I C
2
SCL
AD3
IOZ
I C Clock
SDA
AC4
IOZ
I2C Data
JTAG
TCK
N29
I
UP
JTAG Clock Input
TDI
P27
I
UP
JTAG Data Input
TDO
R29
OZ
UP
JTAG Data Output
TMS
P29
I
UP
JTAG Test Mode Input
TRST
P28
I
Down
JTAG Reset
MDIO
MDIO
G26
IOZ
UP
MDIO Data
MDCLK
H26
O
Down
MDIO Clock
PCIERXN0
AH7
I
PCIERXP0
AH8
I
PCIERXN1
AJ9
I
PCIERXP1
AJ8
I
PCIe
Copyright 2011 Texas Instruments Incorporated
PCIexpress Receive Data (2 links)
45
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 10 of 12)
Signal Name
Ball No. Type
PCIETXN0
AF8
O
PCIETXP0
AF7
O
PCIETXN1
AG9
O
PCIETXP1
AG8
O
IPD/IPU
Description
PCIexpress Transmit Data (2 links)
Serial RapidIO
ADVANCE INFORMATION
RIORXN0
AJ11
I
RIORXP0
AJ12
I
RIORXN1
AH10
I
RIORXP1
AH11
I
RIORXN2
AH14
I
RIORXP2
AH13
I
RIORXN3
AJ15
I
RIORXP3
AJ14
I
RIOTXN0
AF10
O
RIOTXP0
AF11
O
RIOTXN1
AG11
O
RIOTXP1
AG12
O
RIOTXN2
AG15
O
RIOTXP2
AG14
O
RIOTXN3
AF14
O
RIOTXP3
AF13
O
SGMII0RXN
AJ18
I
SGMII0RXP
AJ17
I
SGMII0TXN
AG18
O
SGMII0TXP
AG17
O
SGMII1RXN
AH17
I
SGMII1RXP
AH16
I
SGMII1TXN
AF17
O
SGMII1TXP
AF16
O
Serial RapidIO Receive Data (2 links)
Serial RapidIO Receive Data (2 links)
Serial RapidIO Transmit Data (2 links)
Serial RapidIO Transmit Data (2 links)
SGMII
Ethernet MAC SGMII Receive Data
Ethernet MAC SGMII Transmit Data
Ethernet MAC SGMII Receive Data
Ethernet MAC SGMII Transmit Data
SmartReflex
VCNTL0
L23
OZ
VCNTL1
K23
OZ
VCNTL2
J23
OZ
VCNTL3
H23
OZ
SPISCS0
AG1
OZ
UP
SPI Interface Enable 0
SPISCS1
AG2
OZ
UP
SPI Interface Enable 1
SPICLK
AE1
OZ
Down
SPI Clock
SPIDIN
AD2
I
Down
SPI Data In
SPIDOUT
AB1
OZ
Down
SPI Data Out
TIMI0
L24
I
Down
TIMI1
L26
I
Down
Voltage Control Outputs to variable core power supply
SPI
Timer
46
Timer Inputs
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 2-15
Terminal Functions — Signals and Control by Function (Part 11 of 12)
Signal Name
Ball No. Type
IPD/IPU
TIMO0
L25
OZ
Down
TIMO1
M26
OZ
Down
Description
Timer Outputs
CLKA0
AF25
I
Down
TSIP0 external clock A
CLKB0
AG25
I
Down
TSIP0 external clock B
FSA0
AJ26
I
Down
TSIP0 frame sync A
FSB0
AG26
I
Down
TSIP0 frame sync B
TR00
AH26
I
Down
TR01
AJ25
I
Down
TR02
AD23
I
Down
TR03
AD24
I
Down
TR04
AC23
I
Down
TR05
AH25
I
Down
TR06
AC24
I
Down
TR07
AE25
I
Down
TX00
AE24
OZ
Down
TX01
AD25
OZ
Down
TX02
AJ24
OZ
Down
TX03
AG24
OZ
Down
TX04
AH24
OZ
Down
TX05
AF24
OZ
Down
TX06
AE23
OZ
Down
TX07
AF23
OZ
Down
CLKA1
AJ23
I
Down
TSIP1 external clock A
CLKB1
AH23
I
Down
TSIP1 external clock B
FSA1
AG23
I
Down
TSIP1 frame sync A
FSB1
AJ22
I
Down
TSIP1 frame sync B
TR10
AE22
I
Down
TR11
AD21
I
Down
TR12
AC21
I
Down
TR13
AJ21
I
Down
TR14
AH22
I
Down
TR15
AJ20
I
Down
TR16
AH21
I
Down
TR17
AG21
I
Down
TX10
AF21
OZ
Down
TX11
AD22
OZ
Down
TX12
AC22
OZ
Down
TX13
AE21
OZ
Down
TX14
AG20
OZ
Down
TX15
AE20
OZ
Down
TX16
AH20
OZ
Down
TX17
AF20
OZ
Down
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
TSIP
TSIP0 receive data
TSIP0 transmit data
TSIP1 receive data
TSIP1 transmit data
47
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-15
www.ti.com
Terminal Functions — Signals and Control by Function (Part 12 of 12)
Signal Name
Ball No. Type
IPD/IPU
Description
UART
UARTRXD
AD1
I
Down
UART Serial Data In
UARTTXD
AC1
OZ
Down
UART Serial Data Out
UARTCTS
AB3
I
Down
UART Clear To Send
UARTRTS
AB2
OZ
Down
UART Request To Send
RSV01
AH28
IOZ
Down
Reserved - Pullup to DVDD18
RSV02
N24
OZ
Down
Reserved - leave unconnected
RSV03
N23
OZ
Down
Reserved - leave unconnected
RSV04
AH2
O
Reserved - leave unconnected
RSV05
AJ3
O
Reserved - leave unconnected
RSV06
H28
O
Reserved - leave unconnected
RSV07
G28
O
Reserved - leave unconnected
RSV08
AH19
A
Reserved - Connect to GND
RSV09
AF19
A
Reserved - leave unconnected
RSV10
K22
A
Reserved - leave unconnected
RSV11
J22
A
Reserved - leave unconnected
RSV12
Y5
A
Reserved - leave unconnected
RSV13
W5
A
Reserved - leave unconnected
RSV14
W6
A
Reserved - leave unconnected
RSV15
AE12
A
Reserved - leave unconnected
RSV16
AC9
A
Reserved - leave unconnected
RSV17
AD19
A
Reserved - leave unconnected
RSV20
AF3
OZ
Down
Reserved - leave unconnected
RSV21
G25
OZ
Down
Reserved - leave unconnected
Down
Reserved
ADVANCE INFORMATION
RSV22
AF1
OZ
RSV24
AH4
O
Reserved - leave unconnected
RSV25
AH3
O
Reserved - leave unconnected
RSV26
M23
IOZ
Reserved - leave unconnected
RSV27
M24
IOZ
Reserved - leave unconnected
RSV0A
AA21
A
Reserved - leave unconnected
RSV0B
AA20
A
Reserved - leave unconnected
Reserved - leave unconnected
End of Table 2-15
48
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Terminal Functions — Power and Ground
Supply
Ball No.
Volts Description
AVDDA1
H22
1.8
PLL Supply - CORE_PLL
AVDDA2
AC6
1.8
PLL Supply - DDR3_PLL
AVDDA3
AD5
1.8
PLL Supply - PASS_PLL
CVDD
H7, H9, H11, H13, H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16, 0.9
to
L18, M11, M13, M15, M17, M19, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19,
P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11, 1.1
V17, V19, V21, W8, W10, W18, W20, W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12,
AA14, AA16, AA18, AA22
SmartReflex core supply voltage
CVDD1
J8, J14, K7, K9, K13, K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16,
V13, V15, W12, W14, W16
Fixed core supply voltage
DVDD15
A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28, 1.5
G2, G4, G8, G10, G12, G14, G16, G18, G20, G23
DDR IO supply
DVDD18
H24, N28, P23, T23, U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26,
AG22, AH1, AH29, AJ2, AJ28
1.8
IO supply
VDDR1
V5
1.5
HyperLink SerDes regulator supply
VDDR2
AE10
1.5
PCIe SerDes regulator supply
VDDR3
AE16
1.5
SGMII SerDes regulator supply
1.0
VDDR4
AE14
1.5
SRIO SerDes regulator supply
VDDT1
M7, N6, P7, R6, T7, U6, V7
1.0
HyperLink SerDes termination
supply
VDDT2
AB9, AB11, AB13, AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13,
AD15, AD17, AE18
1.0
SGMII/SRIO/PCIe SerDes
termination supply
VREFSSTL
E14
0.75
VSS
A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1, GND
G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24, H1, H2, H3, H4, H5, H6, H8, H10, H12,
H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6,
K8, K10, K12, K14, K16, K18, K20, L1, L2, L3, L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2,
M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9, N11, N13, N15, N17,
N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13,
R15, R17, R19, R21, T3, T6, T8, T10, T12, T14, T16, T18, T20, T22, T26, U1, U3, U5, U7, U9, U11,
U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9,
W11, W13, W15, W17, W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9,
AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8, AB10, AB12, AB14, AB16, AB18,
AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14,
AD16, AD18, AE7, AE8, AE9, AE11, AE13, AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15,
AF18, AF22, AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18, AJ1, AJ7, AJ10,
AJ13, AJ16, AJ19, AJ29
DDR3 reference voltage
Ground
End of Table 2-16
Copyright 2011 Texas Instruments Incorporated
49
ADVANCE INFORMATION
Table 2-16
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-17
Terminal Functions
— By Signal Name
(Part 1 of 12)
www.ti.com
Table 2-17
Terminal Functions
— By Signal Name
(Part 2 of 12)
Table 2-17
Terminal Functions
— By Signal Name
(Part 3 of 12)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
AVDDA1
H22
CVDD1
DDRCLKP
G29
AVDDA2
AC6
J8, J14, K7, K9, K13,
K15, L8, L14, L20,
L22, M9, M21, N20,
N22, R12, R14, R16,
U12, U14, U16, V13,
V15, W12, W14,
W16
DDRA00
Signal Name
AVDDA3
AD5
BOOTCOMPLETE
AE2
BOOTMODE00 †
J28
BOOTMODE01†
J29
ADVANCE INFORMATION
BOOTMODE02 †
BOOTMODE03 †
BOOTMODE04 †
BOOTMODE05 †
J26
J25
J27
J24
BOOTMODE06 †
K27
BOOTMODE07 †
K28
BOOTMODE08 †
K26
BOOTMODE09 †
K29
BOOTMODE10 †
BOOTMODE11 †
L28
L29
BOOTMODE12 †
K25
CLKA0
AF25
CLKA1
CLKB0
CLKB1
CORECLKN
CORECLKP
CORESEL0
AJ23
AG25
AH23
AG4
AG3
AF2
CORESEL1
AD4
CORESEL2
AE6
CORESEL3
CVDD
CVDD
CVDD
50
AE5
H7, H9, H11, H13,
H15, H17, H19, H21,
J10, J12, J16, J18,
J20, K11, K17, K19,
K21, L10, L12, L16,
L18, M11, M13,
M15, M17, M19, N8,
N10, N12, N14,
N16, N18, P9, P11,
P13, P15, P17, P19,
P21, R8, R10, R18,
R20, R22, T9, T11,
T13, T15, T17, T19,
T21, U8, U10, U18,
U20, U22, V9, V11,
V17, V19, V21, W8,
W10, W18, W20,
W22, Y9, Y11, Y13,
Y15, Y17, Y19, Y21,
AA8, AA10, AA12,
AA14, AA16, AA18,
AA22
DDRD00
E28
DDRD01
D29
DDRD02
E27
DDRD03
D28
A14
DDRD04
D27
DDRA01
B14
DDRD05
B28
DDRA02
F14
DDRD06
E26
DDRA03
F13
DDRD07
F25
DDRA04
A15
DDRD08
F24
DDRA05
C15
DDRD09
E24
DDRA06
B15
DDRD10
E25
DDRA07
D15
DDRD11
D25
DDRA08
F15
DDRD12
D26
DDRA09
E15
DDRD13
C26
DDRA10
E16
DDRD14
B26
DDRA11
D16
DDRD15
A26
DDRA12
E17
DDRD16
F23
DDRA13
C16
DDRD17
F22
DDRA14
D17
DDRD18
D24
DDRA15
C17
DDRD19
E23
DDRBA0
A13
DDRD20
A23
DDRBA1
B13
DDRD21
B23
DDRBA2
C13
DDRD22
C24
DDRCAS
D12
DDRD23
E22
DDRCB00
E19
DDRD24
D21
DDRCB01
C20
DDRD25
F20
DDRCB02
D19
DDRD26
E21
DDRCB03
B20
DDRD27
F21
DDRCB04
C19
DDRD28
D22
DDRCB05
C18
DDRD29
C21
DDRCB06
B18
DDRD30
B22
DDRCB07
A18
DDRD31
C22
DDRCE0
C11
DDRD32
E10
DDRCE1
C12
DDRD33
D10
DDRCKE0
D11
DDRD34
B10
DDRCKE1
E18
DDRD35
D9
DDRCLKN
H29
DDRD36
E9
DDRCLKOUTN0
B12
DDRD37
C9
DDRCLKOUTN1
B16
DDRD38
B8
DDRCLKOUTP0
A12
DDRD39
E8
DDRCLKOUTP1
A16
DDRD40
A7
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-17
Terminal Functions
— By Signal Name
(Part 4 of 12)
Table 2-17
Terminal Functions
— By Signal Name
(Part 5 of 12)
Table 2-17
Terminal Functions
— By Signal Name
(Part 6 of 12)
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
DDRD41
D7
DDRDQS5N
A6
EMIFA17
W26
DDRD42
E7
DDRDQS5P
B6
EMIFA18
W25
DDRD43
C7
DDRDQS6N
A3
EMIFA19
W24
DDRD44
B7
DDRDQS6P
B3
EMIFA20
W23
DDRD45
E6
DDRDQS7N
C1
EMIFA21
Y29
DDRD46
D6
DDRDQS7P
D1
EMIFA22
Y28
DDRD47
C6
DDRDQS8N
B19
EMIFA23
U23
DDRD48
C5
DDRDQS8P
A19
EMIFBE0
R24
DDRD49
A5
DDRODT0
D13
EMIFBE1
R23
DDRD50
B4
DDRODT1
E13
EMIFCE0
P25
DDRD51
A4
DDRRAS
C10
EMIFCE1
R27
DDRD52
D4
DDRRESET
E11
EMIFCE2
R28
DDRD53
E4
DDRSLRATE0
G27
EMIFCE3
R25
DDRD54
C4
DDRSLRATE1
H27
EMIFD00
Y27
DDRD55
C3
DDRWE
E12
EMIFD01
AB29
DDRD56
F4
DVDD15
EMIFD02
AA29
DDRD57
D2
EMIFD03
Y26
DDRD58
E2
EMIFD04
AA27
DDRD59
C2
EMIFD05
AB27
DDRD60
F2
EMIFD06
AA26
DDRD61
F3
A2, A11, A17, A28,
B1, B29, C14, C25,
D5, D8, D20, D23,
E3, F5, F7, F9, F11,
F17, F19, F26, F28,
G2, G4, G8, G10,
G12, G14, G16, G18,
G20, G23
DDRD62
E1
DDRD63
F1
DDRDQM0
E29
DDRDQM1
C27
DDRDQM2
A25
DDRDQM3
A22
DDRDQM4
A10
DDRDQM5
A8
DDRDQM6
B5
DDRDQM7
B2
DDRDQM8
A20
DDRDQS0N
C29
DDRDQS0P
C28
DDRDQS1N
B27
DDRDQS1P
A27
DDRDQS2N
B24
DDRDQS2P
A24
DDRDQS3N
B21
DDRDQS3P
A21
DDRDQS4N
B9
DDRDQS4P
A9
Copyright 2011 Texas Instruments Incorporated
DVDD18
H24, N28, P23, T23,
U26, V23, Y7, Y23,
AA6, AB5, AB7,
AB19, AB21, AB28,
AC3, AF5, AF26,
AG22, AH1, AH29,
AJ2, AJ28
EMIFA00
T27
EMIFA01
T24
EMIFA02
U29
EMIFA03
T25
EMIFA04
U27
EMIFA05
U28
EMIFA06
U25
EMIFA07
U24
EMIFA08
V28
EMIFA09
V29
EMIFA10
V27
EMIFA11
V26
EMIFA12
V25
EMIFA13
V24
EMIFA14
W28
EMIFA15
W27
EMIFA16
W29
EMIFD07
AA25
EMIFD08
Y25
EMIFD09
AB25
EMIFD10
AA24
EMIFD11
Y24
EMIFD12
AB23
EMIFD13
AB24
EMIFD14
AB26
EMIFD15
AC25
EMIFOE
R26
EMIFRW
P26
EMIFWAIT0
T29
EMIFWAIT1
T28
EMIFWE
P24
EMU00
AC29
EMU01
AC28
EMU02
AC27
EMU03
AC26
EMU04
AD29
EMU05
AD28
EMU06
AD27
EMU07
AE29
ADVANCE INFORMATION
www.ti.com
51
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-17
Terminal Functions
— By Signal Name
(Part 7 of 12)
Signal Name
www.ti.com
Table 2-17
Terminal Functions
— By Signal Name
(Part 8 of 12)
Table 2-17
Terminal Functions
— By Signal Name
(Part 9 of 12)
ADVANCE INFORMATION
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
EMU08
AE28
MCMRXN1
T1
RESETFULL
N25
EMU09
AF29
MCMRXN2
M1
RESETSTAT
N27
EMU10
AE27
MCMRXN3
P2
RESET
M29
EMU11
AF28
MCMRXP0
T2
RIORXN0
AJ11
EMU12
AG29
MCMRXP1
R1
RIORXN1
AH10
EMU13
AD26
MCMRXP2
N1
RIORXN2
AH14
EMU14
AG28
MCMRXP3
N2
RIORXN3
AJ15
EMU15
AG27
MCMRXPMCLK
Y3
RIORXP0
AJ12
EMU16
AJ27
MCMRXPMDAT
Y4
RIORXP1
AH11
EMU17
AF27
MCMTXFLCLK
AA1
RIORXP2
AH13
EMU18
AH27
MCMTXFLDAT
AA3
RIORXP3
AJ14
FSA0
AJ26
MCMTXN0
M5
RIOTXN0
AF10
FSA1
AG23
MCMTXN1
T4
RIOTXN1
AG11
FSB0
AG26
MCMTXN2
R5
RIOTXN2
AG15
FSB1
AJ22
MCMTXN3
N4
RIOTXN3
AF14
GPIO00
H25
MCMTXP0
N5
RIOTXP0
AF11
GPIO01
J28
MCMTXP1
U4
RIOTXP1
AG12
GPIO02
J29
MCMTXP2
T5
RIOTXP2
AG14
GPIO03
J26
MCMTXP3
P4
RIOTXP3
AF13
GPIO04
J25
MCMTXPMCLK
AA2
RSV01
AH28
GPIO05
J27
MCMTXPMDAT
AA4
RSV02
N24
GPIO06
J24
MDCLK
H26
RSV03
N23
GPIO07
K27
MDIO
G26
RSV04
AH2
GPIO08
K28
NMI
M25
RSV05
AJ3
GPIO09
K26
PACLKSEL
AE4
RSV06
H28
GPIO10
K29
PASSCLKN
AJ4
RSV07
G28
GPIO11
L28
PASSCLKP
AJ5
RSV08
AH19
GPIO12
L29
PCIECLKN
AH5
RSV09
AF19
GPIO13
K25
PCIECLKP
AG5
RSV0A
AA21
GPIO14
K24
PCIERXN0
AH7
RSV0B
AA20
GPIO15
L27
PCIERXN1
AJ9
RSV10
K22
HOUT
AD20
PCIERXP0
AH8
RSV11
J22
LENDIAN †
H25
PCIERXP1
AJ8
RSV12
Y5
LRESETNMIEN
M27
PCIESSMODE0 †
K24
RSV13
W5
LRESET
N26
PCIESSMODE1 †
L27
RSV14
W6
MCMCLKN
Y2
PCIESSEN †
L24
RSV15
AE12
MCMCLKP
W2
PCIETXN0
AF8
RSV16
AC9
MCMREFCLKOUTN
W1
PCIETXN1
AG9
RSV17
AD19
MCMREFCLKOUTP
Y1
PCIETXP0
AF7
RSV20
AF3
MCMRXFLCLK
W3
PCIETXP1
AG8
RSV21
G25
MCMRXFLDAT
W4
POR
AC20
RSV22
AF1
MCMRXN0
U2
PTV15
G22
RSV24
AH4
52
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Terminal Functions
— By Signal Name
(Part 10 of 12)
Table 2-17
Terminal Functions
— By Signal Name
(Part 11 of 12)
Table 2-17
Terminal Functions
— By Signal Name
(Part 12 of 12)
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
RSV25
AH3
TR17
AG21
VSS
SCL
AD3
TRST
P28
SDA
AC4
TX00
AE24
SGMII0RXN
AJ18
TX01
AD25
SGMII0RXP
AJ17
TX02
AJ24
SGMII0TXN
AG18
TX03
AG24
H1, H2, H3, H4, H5,
H6, H8, H10, H12,
H14, H16, H18, H20,
J1, J2, J3, J4, J5, J6,
J7, J9, J11, J13, J15,
J17, J19, J21, K1, K2,
K3, K4, K5, K6, K8,
K10, K12, K14, K16,
SGMII0TXP
AG17
TX04
AH24
VSS
SGMII1RXN
AH17
TX05
AF24
SGMII1RXP
AH16
TX06
AE23
SGMII1TXN
AF17
TX07
AF23
SGMII1TXP
AF16
TX10
AF21
K18, K20, L1, L2, L3,
L4, L5, L6, L7, L9,
L11, L13, L15, L17,
L19, L21, M2, M3,
M4, M6, M8, M10,
M12, M14, M16,
M18, M20, M22,
M28, N3, N7, N9,
SPICLK
AE1
TX11
AD22
VSS
SPIDIN
AD2
TX12
AC22
SPIDOUT
AB1
TX13
AE21
SPISCS0
AG1
TX14
AG20
SPISCS1
AG2
TX15
AE20
SRIOSGMIICLKN
AJ6
TX16
AH20
N11, N13, N15, N17,
N19, N21, P1, P3,
P5, P6, P8, P10, P12,
P14, P16, P18, P20,
P22, R2, R3, R4, R7,
R9, R11, R13, R15,
R17, R19, R21, T3,
T6, T8, T10, T12,
SRIOSGMIICLKP
AG6
TX17
AF20
VSS
SYSCLKOUT
AE3
UARTCTS
AB3
TCK
N29
UARTRTS
AB2
TDI
P27
UARTRXD
AD1
TDO
R29
UARTTXD
AC1
T14, T16, T18, T20,
T22, T26, U1, U3,
U5, U7, U9, U11,
U13, U15, U17, U19,
U21, V1, V2, V3, V4,
V6, V8, V10, V12,
V14, V16, V18, V20,
V22, W7, W9, W11,
TIMI0
L24
VCNTL0
L23
VSS
TIMI1
L26
VCNTL1
K23
TIMO0
L25
VCNTL2
J23
TIMO1
M26
VCNTL3
H23
TMS
P29
VDDR1
V5
TR00
AH26
VDDR2
AE10
W13, W15, W17,
W19, W21, Y6, Y8,
Y10, Y12, Y14, Y16,
Y18, Y20, Y22, AA5,
AA7, AA9, AA11,
AA13, AA15, AA17,
AA19, AA23, AA28,
AB4, AB6, AB8,
TR01
AJ25
VDDR3
AE16
VSS
TR02
AD23
VDDR4
AE14
TR03
AD24
VDDT1
TR04
AC23
M7, N6, P7, R6, T7,
U6, V7
TR05
AH25
VDDT2
TR06
AC24
VSS
TR07
AE25
TR10
AE22
AB9, AB11, AB13,
AB15, AB17, AC8,
AC10, AC12, AC14,
AC16, AC18, AD7,
AD9, AD11, AD13,
AD15, AD17, AE18
AB10, AB12, AB14,
AB16, AB18, AB20,
AB22, AC2, AC5,
AC7, AC11, AC13,
AC15, AC17, AC19,
AD6, AD8, AD10,
AD12, AD14, AD16,
AD18, AE7, AE8,
TR11
AD21
VREFSSTL
E14
TR12
AC21
VSS
A1, A29, B11, B17,
B25, C8, C23, D3,
D14, D18, E5, E20,
F6, F8, F10, F12,
F16, F18, F27, F29,
G1, G3, G5, G6, G7,
G9, G11, G13, G15,
G17, G19, G21, G24,
AE9, AE11, AE13,
AE15, AE17, AE19,
AE26, AF4, AF6,
AF9, AF12, AF15,
AF18, AF22AG7,
AG10, AG13, AG16,
AG19, AH6, AH9,
AH12, AH15, AH18,
VSS
AJ1, AJ7, AJ10,
AJ13, AJ16, AJ19,
AJ29
TR13
AJ21
TR14
AH22
TR15
AJ20
TR16
AH21
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 2-17
End of Table 2-17
53
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Terminal Functions
— By Ball Number
(Part 1 of 21)
www.ti.com
Table 2-18
Terminal Functions
— By Ball Number
(Part 2 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 3 of 21)
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
A1
VSS
B14
DDRA01
C27
DDRDQM1
A2
DVDD15
B15
DDRA06
C28
DDRDQS0P
A3
DDRDQS6N
B16
DDRCLKOUTN1
C29
DDRDQS0N
A4
DDRD51
B17
VSS
D1
DDRDQS7P
A5
DDRD49
B18
DDRCB06
D2
DDRD57
A6
DDRDQS5N
B19
DDRDQS8N
D3
VSS
A7
DDRD40
B20
DDRCB03
D4
DDRD52
A8
DDRDQM5
B21
DDRDQS3N
D5
DVDD15
A9
DDRDQS4P
B22
DDRD30
D6
DDRD46
A10
DDRDQM4
B23
DDRD21
D7
DDRD41
A11
DVDD15
B24
DDRDQS2N
D8
DVDD15
A12
DDRCLKOUTP0
B25
VSS
D9
DDRD35
A13
DDRBA0
B26
DDRD14
D10
DDRD33
A14
DDRA00
B27
DDRDQS1N
D11
DDRCKE0
A15
DDRA04
B28
DDRD05
D12
DDRCAS
A16
DDRCLKOUTP1
B29
DVDD15
D13
DDRODT0
A17
DVDD15
C1
DDRDQS7N
D14
VSS
A18
DDRCB07
C2
DDRD59
D15
DDRA07
A19
DDRDQS8P
C3
DDRD55
D16
DDRA11
A20
DDRDQM8
C4
DDRD54
D17
DDRA14
A21
DDRDQS3P
C5
DDRD48
D18
VSS
A22
DDRDQM3
C6
DDRD47
D19
DDRCB02
A23
DDRD20
C7
DDRD43
D20
DVDD15
A24
DDRDQS2P
C8
VSS
D21
DDRD24
A25
DDRDQM2
C9
DDRD37
D22
DDRD28
A26
DDRD15
C10
DDRRAS
D23
DVDD15
A27
DDRDQS1P
C11
DDRCE0
D24
DDRD18
A28
DVDD15
C12
DDRCE1
D25
DDRD11
A29
VSS
C13
DDRBA2
D26
DDRD12
B1
DVDD15
C14
DVDD15
D27
DDRD04
B2
DDRDQM7
C15
DDRA05
D28
DDRD03
B3
DDRDQS6P
C16
DDRA13
D29
DDRD01
B4
DDRD50
C17
DDRA15
E1
DDRD62
B5
DDRDQM6
C18
DDRCB05
E2
DDRD58
B6
DDRDQS5P
C19
DDRCB04
E3
DVDD15
B7
DDRD44
C20
DDRCB01
E4
DDRD53
B8
DDRD38
C21
DDRD29
E5
VSS
B9
DDRDQS4N
C22
DDRD31
E6
DDRD45
B10
DDRD34
C23
VSS
E7
DDRD42
B11
VSS
C24
DDRD22
E8
DDRD39
B12
DDRCLKOUTN0
C25
DVDD15
E9
DDRD36
B13
DDRBA1
C26
DDRD13
E10
DDRD32
Ball Number
ADVANCE INFORMATION
54
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Terminal Functions
— By Ball Number
(Part 4 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 5 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 6 of 21)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
E11
DDRRESET
F24
DDRD08
H8
VSS
E12
DDRWE
F25
DDRD07
H9
CVDD
E13
DDRODT1
F26
DVDD15
H10
VSS
E14
VREFSSTL
F27
VSS
H11
CVDD
E15
DDRA09
F28
DVDD15
H12
VSS
E16
DDRA10
F29
VSS
H13
CVDD
E17
DDRA12
G1
VSS
H14
VSS
E18
DDRCKE1
G2
DVDD15
H15
CVDD
E19
DDRCB00
G3
VSS
H16
VSS
E20
VSS
G4
DVDD15
H17
CVDD
E21
DDRD26
G5
VSS
H18
VSS
E22
DDRD23
G6
VSS
H19
CVDD
E23
DDRD19
G7
VSS
H20
VSS
E24
DDRD09
G8
DVDD15
H21
CVDD
E25
DDRD10
G9
VSS
H22
AVDDA1
E26
DDRD06
G10
DVDD15
H23
VCNTL3
E27
DDRD02
G11
VSS
H24
DVDD18
E28
DDRD00
G12
DVDD15
H25
GPIO00
E29
DDRDQM0
G13
VSS
H25
LENDIAN †
F1
DDRD63
G14
DVDD15
H26
MDCLK
F2
DDRD60
G15
VSS
H27
DDRSLRATE1
F3
DDRD61
G16
DVDD15
H28
RSV06
F4
DDRD56
G17
VSS
H29
DDRCLKN
F5
DVDD15
G18
DVDD15
J1
VSS
F6
VSS
G19
VSS
J2
VSS
F7
DVDD15
G20
DVDD15
J3
VSS
F8
VSS
G21
VSS
J4
VSS
F9
DVDD15
G22
PTV15
J5
VSS
F10
VSS
G23
DVDD15
J6
VSS
F11
DVDD15
G24
VSS
J7
VSS
F12
VSS
G25
RSV21
J8
CVDD1
F13
DDRA03
G26
MDIO
J9
VSS
F14
DDRA02
G27
DDRSLRATE0
J10
CVDD
F15
DDRA08
G28
RSV07
J11
VSS
F16
VSS
G29
DDRCLKP
J12
CVDD
F17
DVDD15
H1
VSS
J13
VSS
F18
VSS
H2
VSS
J14
CVDD1
F19
DVDD15
H3
VSS
J15
VSS
F20
DDRD25
H4
VSS
J16
CVDD
F21
DDRD27
H5
VSS
J17
VSS
F22
DDRD17
H6
VSS
J18
CVDD
F23
DDRD16
H7
CVDD
J19
VSS
Copyright 2011 Texas Instruments Incorporated
Signal Name
ADVANCE INFORMATION
www.ti.com
55
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Ball Number
Terminal Functions
— By Ball Number
(Part 7 of 21)
www.ti.com
Table 2-18
ADVANCE INFORMATION
Signal Name
Ball Number
J20
CVDD
J21
VSS
J22
RSV11
J23
VCNTL2
J24
GPIO06
J24
BOOTMODE05 †
J25
GPIO04
J25
BOOTMODE03 †
J26
GPIO03
J26
BOOTMODE02 †
J27
J27
Terminal Functions
— By Ball Number
(Part 8 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 9 of 21)
Signal Name
Ball Number
Signal Name
K25
BOOTMODE12 †
M1
MCMRXN2
K26
GPIO09
M2
VSS
K26
BOOTMODE08 †
M3
VSS
K27
GPIO07
M4
VSS
K27
BOOTMODE06 †
M5
MCMTXN0
K28
GPIO08
M6
VSS
K28
BOOTMODE07 †
M7
VDDT1
K29
GPIO10
M8
VSS
K29
BOOTMODE09 †
M9
CVDD1
L1
VSS
M10
VSS
GPIO05
L2
VSS
M11
CVDD
BOOTMODE04 †
L3
VSS
M12
VSS
J28
GPIO01
L4
VSS
M13
CVDD
J28
BOOTMODE00 †
L5
VSS
M14
VSS
J29
GPIO02
L6
VSS
M15
CVDD
J29
BOOTMODE01†
L7
VSS
M16
VSS
K1
VSS
L8
CVDD1
M17
CVDD
K2
VSS
L9
VSS
M18
VSS
K3
VSS
L10
CVDD
M19
CVDD
K4
VSS
L11
VSS
M20
VSS
K5
VSS
L12
CVDD
M21
CVDD1
K6
VSS
L13
VSS
M22
VSS
K7
CVDD1
L14
CVDD1
M25
NMI
K8
VSS
L15
VSS
M26
TIMO1
K9
CVDD1
L16
CVDD
M27
LRESETNMIEN
K10
VSS
L17
VSS
M28
VSS
K11
CVDD
L18
CVDD
M29
RESET
K12
VSS
L19
VSS
N1
MCMRXP2
K13
CVDD1
L20
CVDD1
N2
MCMRXP3
K14
VSS
L21
VSS
N3
VSS
K15
CVDD1
L22
CVDD1
N4
MCMTXN3
K16
VSS
L23
VCNTL0
N5
MCMTXP0
K17
CVDD
L24
TIMI0
N6
VDDT1
K18
VSS
L24
PCIESSEN †
N7
VSS
K19
CVDD
L25
TIMO0
N8
CVDD
K20
VSS
L26
TIMI1
N9
VSS
K21
CVDD
L27
GPIO15
N10
CVDD
K22
RSV10
L27
PCIESSMODE1 †
N11
VSS
K23
VCNTL1
L28
GPIO11
N12
CVDD
K24
GPIO14
L28
BOOTMODE10 †
N13
VSS
K24
PCIESSMODE0 †
L29
GPIO12
N14
CVDD
K25
GPIO13
L29
BOOTMODE11 †
N15
VSS
56
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Ball Number
Terminal Functions
— By Ball Number
(Part 10 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 11 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 12 of 21)
Signal Name
Ball Number
Signal Name
Ball Number
N16
CVDD
P29
TMS
T13
CVDD
N17
VSS
R1
MCMRXP1
T14
VSS
N18
CVDD
R2
VSS
T15
CVDD
N19
VSS
R3
VSS
T16
VSS
N20
CVDD1
R4
VSS
T17
CVDD
N21
VSS
R5
MCMTXN2
T18
VSS
N22
CVDD1
R6
VDDT1
T19
CVDD
N23
RSV03
R7
VSS
T20
VSS
N24
RSV02
R8
CVDD
T21
CVDD
N25
RESETFULL
R9
VSS
T22
VSS
N26
LRESET
R10
CVDD
T23
DVDD18
N27
RESETSTAT
R11
VSS
T24
EMIFA01
N28
DVDD18
R12
CVDD1
T25
EMIFA03
N29
TCK
R13
VSS
T26
VSS
P1
VSS
R14
CVDD1
T27
EMIFA00
P2
MCMRXN3
R15
VSS
T28
EMIFWAIT1
P3
VSS
R16
CVDD1
T29
EMIFWAIT0
P4
MCMTXP3
R17
VSS
U1
VSS
P5
VSS
R18
CVDD
U2
MCMRXN0
P6
VSS
R19
VSS
U3
VSS
P7
VDDT1
R20
CVDD
U4
MCMTXP1
P8
VSS
R21
VSS
U5
VSS
P9
CVDD
R22
CVDD
U6
VDDT1
P10
VSS
R23
EMIFBE1
U7
VSS
P11
CVDD
R24
EMIFBE0
U8
CVDD
P12
VSS
R25
EMIFCE3
U9
VSS
P13
CVDD
R26
EMIFOE
U10
CVDD
P14
VSS
R27
EMIFCE1
U11
VSS
P15
CVDD
R28
EMIFCE2
U12
CVDD1
P16
VSS
R29
TDO
U13
VSS
P17
CVDD
T1
MCMRXN1
U14
CVDD1
P18
VSS
T2
MCMRXP0
U15
VSS
P19
CVDD
T3
VSS
U16
CVDD1
P20
VSS
T4
MCMTXN1
U17
VSS
P21
CVDD
T5
MCMTXP2
U18
CVDD
P22
VSS
T6
VSS
U19
VSS
P23
DVDD18
T7
VDDT1
U20
CVDD
P24
EMIFWE
T8
VSS
U21
VSS
P25
EMIFCE0
T9
CVDD
U22
CVDD
P26
EMIFRW
T10
VSS
U23
EMIFA23
P27
TDI
T11
CVDD
U24
EMIFA07
P28
TRST
T12
VSS
U25
EMIFA06
Copyright 2011 Texas Instruments Incorporated
Signal Name
ADVANCE INFORMATION
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57
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Terminal Functions
— By Ball Number
(Part 13 of 21)
www.ti.com
Table 2-18
Ball Number
Signal Name
Ball Number
U26
DVDD18
U27
EMIFA04
U28
U29
Terminal Functions
— By Ball Number
(Part 14 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 15 of 21)
ADVANCE INFORMATION
Signal Name
Ball Number
Signal Name
W10
CVDD
Y23
DVDD18
W11
VSS
Y24
EMIFD11
EMIFA05
W12
CVDD1
Y25
EMIFD08
EMIFA02
W13
VSS
Y26
EMIFD03
V1
VSS
W14
CVDD1
Y27
EMIFD00
V2
VSS
W15
VSS
Y28
EMIFA22
V3
VSS
W16
CVDD1
Y29
EMIFA21
V4
VSS
W17
VSS
AA1
MCMTXFLCLK
V5
VDDR1
W18
CVDD
AA2
MCMTXPMCLK
V6
VSS
W19
VSS
AA3
MCMTXFLDAT
V7
VDDT1
W20
CVDD
AA4
MCMTXPMDAT
V8
VSS
W21
VSS
AA5
VSS
V9
CVDD
W22
CVDD
AA6
DVDD18
V10
VSS
W23
EMIFA20
AA7
VSS
V11
CVDD
W24
EMIFA19
AA8
CVDD
V12
VSS
W25
EMIFA18
AA9
VSS
V13
CVDD1
W26
EMIFA17
AA10
CVDD
V14
VSS
W27
EMIFA15
AA11
VSS
V15
CVDD1
W28
EMIFA14
AA12
CVDD
V16
VSS
W29
EMIFA16
AA13
VSS
V17
CVDD
Y1
MCMREFCLKOUTP
AA14
CVDD
V18
VSS
Y2
MCMCLKN
AA15
VSS
V19
CVDD
Y3
MCMRXPMCLK
AA16
CVDD
V20
VSS
Y4
MCMRXPMDAT
AA17
VSS
V21
CVDD
Y5
RSV12
AA18
CVDD
V22
VSS
Y6
VSS
AA19
VSS
V23
DVDD18
Y7
DVDD18
AA20
RSV0B
V24
EMIFA13
Y8
VSS
AA21
RSV0A
V25
EMIFA12
Y9
CVDD
AA22
CVDD
V26
EMIFA11
Y10
VSS
AA23
VSS
V27
EMIFA10
Y11
CVDD
AA24
EMIFD10
V28
EMIFA08
Y12
VSS
AA25
EMIFD07
V29
EMIFA09
Y13
CVDD
AA26
EMIFD06
W1
MCMREFCLKOUTN
Y14
VSS
AA27
EMIFD04
W2
MCMCLKP
Y15
CVDD
AA28
VSS
W3
MCMRXFLCLK
Y16
VSS
AA29
EMIFD02
W4
MCMRXFLDAT
Y17
CVDD
AB1
SPIDOUT
W5
RSV13
Y18
VSS
AB2
UARTRTS
W6
RSV14
Y19
CVDD
AB3
UARTCTS
W7
VSS
Y20
VSS
AB4
VSS
W8
CVDD
Y21
CVDD
AB5
DVDD18
W9
VSS
Y22
VSS
AB6
VSS
58
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Terminal Functions
— By Ball Number
(Part 16 of 21)
Table 2-18
Ball Number
Signal Name
Ball Number
AB7
DVDD18
AB8
VSS
AB9
AB10
Terminal Functions
— By Ball Number
(Part 17 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 18 of 21)
Signal Name
Ball Number
AC20
POR
AE4
PACLKSEL
AC21
TR12
AE5
CORESEL3
VDDT2
AC22
TX12
AE6
CORESEL2
VSS
AC23
TR04
AE7
VSS
AB11
VDDT2
AC24
TR06
AE8
VSS
AB12
VSS
AC25
EMIFD15
AE9
VSS
AB13
VDDT2
AC26
EMU03
AE10
VDDR2
AB14
VSS
AC27
EMU02
AE11
VSS
AB15
VDDT2
AC28
EMU01
AE12
RSV15
AB16
VSS
AC29
EMU00
AE13
VSS
AB17
VDDT2
AD1
UARTRXD
AE14
VDDR4
AB18
VSS
AD2
SPIDIN
AE15
VSS
AB19
DVDD18
AD3
SCL
AE16
VDDR3
AB20
VSS
AD4
CORESEL1
AE17
VSS
AB21
DVDD18
AD5
AVDDA3
AE18
VDDT2
AB22
VSS
AD6
VSS
AE19
VSS
AB23
EMIFD12
AD7
VDDT2
AE20
TX15
AB24
EMIFD13
AD8
VSS
AE21
TX13
AB25
EMIFD09
AD9
VDDT2
AE22
TR10
AB26
EMIFD14
AD10
VSS
AE23
TX06
AB27
EMIFD05
AD11
VDDT2
AE24
TX00
AB28
DVDD18
AD12
VSS
AE25
TR07
AB29
EMIFD01
AD13
VDDT2
AE26
VSS
AC1
UARTTXD
AD14
VSS
AE27
EMU10
AC2
VSS
AD15
VDDT2
AE28
EMU08
AC3
DVDD18
AD16
VSS
AE29
EMU07
AC4
SDA
AD17
VDDT2
AF1
RSV22
AC5
VSS
AD18
VSS
AF2
CORESEL0
AC6
AVDDA2
AD19
RSV17
AF3
RSV20
AC7
VSS
AD20
HOUT
AF4
VSS
AC8
VDDT2
AD21
TR11
AF5
DVDD18
AC9
RSV16
AD22
TX11
AF6
VSS
AC10
VDDT2
AD23
TR02
AF7
PCIETXP0
AC11
VSS
AD24
TR03
AF8
PCIETXN0
AC12
VDDT2
AD25
TX01
AF9
VSS
AC13
VSS
AD26
EMU13
AF10
RIOTXN0
AC14
VDDT2
AD27
EMU06
AF11
RIOTXP0
AC15
VSS
AD28
EMU05
AF12
VSS
AC16
VDDT2
AD29
EMU04
AF13
RIOTXP3
AC17
VSS
AE1
SPICLK
AF14
RIOTXN3
AC18
VDDT2
AE2
BOOTCOMPLETE
AF15
VSS
AC19
VSS
AE3
SYSCLKOUT
AF16
SGMII1TXP
Copyright 2011 Texas Instruments Incorporated
Signal Name
ADVANCE INFORMATION
www.ti.com
59
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 2-18
Terminal Functions
— By Ball Number
(Part 19 of 21)
www.ti.com
Table 2-18
Terminal Functions
— By Ball Number
(Part 20 of 21)
Table 2-18
Terminal Functions
— By Ball Number
(Part 21 of 21)
ADVANCE INFORMATION
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
AF17
SGMII1TXN
AH1
DVDD18
AJ14
RIORXP3
AF18
VSS
AH2
RSV04
AJ15
RIORXN3
AF19
RSV09
AH3
RSV25
AJ16
VSS
AF20
TX17
AH4
RSV24
AJ17
SGMII0RXP
AF21
TX10
AH5
PCIECLKN
AJ18
SGMII0RXN
AF22
VSS
AH6
VSS
AJ19
VSS
AF23
TX07
AH7
PCIERXN0
AJ20
TR15
AF24
TX05
AH8
PCIERXP0
AJ21
TR13
AF25
CLKA0
AH9
VSS
AJ22
FSB1
AF26
DVDD18
AH10
RIORXN1
AJ23
CLKA1
AF27
EMU17
AH11
RIORXP1
AJ24
TX02
AF28
EMU11
AH12
VSS
AJ25
TR01
AF29
EMU09
AH13
RIORXP2
AJ26
FSA0
AG1
SPISCS0
AH14
RIORXN2
AJ27
EMU16
AG2
SPISCS1
AH15
VSS
AJ28
DVDD18
AG3
CORECLKP
AH16
SGMII1RXP
AJ29
VSS
AG4
CORECLKN
AH17
SGMII1RXN
AG5
PCIECLKP
AH18
VSS
AG6
SRIOSGMIICLKP
AH19
RSV08
AG7
VSS
AH20
TX16
AG8
PCIETXP1
AH21
TR16
AG9
PCIETXN1
AH22
TR14
AG10
VSS
AH23
CLKB1
AG11
RIOTXN1
AH24
TX04
AG12
RIOTXP1
AH25
TR05
AG13
VSS
AH26
TR00
AG14
RIOTXP2
AH27
EMU18
AG15
RIOTXN2
AH28
RSV01
AG16
VSS
AH29
DVDD18
AG17
SGMII0TXP
AJ1
VSS
AG18
SGMII0TXN
AJ2
DVDD18
AG19
VSS
AJ3
RSV05
AG20
TX14
AJ4
PASSCLKN
AG21
TR17
AJ5
PASSCLKP
AG22
DVDD18
AJ6
SRIOSGMIICLKN
AG23
FSA1
AJ7
VSS
AG24
TX03
AJ8
PCIERXP1
AG25
CLKB0
AJ9
PCIERXN1
AG26
FSB0
AJ10
VSS
AG27
EMU15
AJ11
RIORXN0
AG28
EMU14
AJ12
RIORXP0
AG29
EMU12
AJ13
VSS
60
Signal Name
End of Table 2-18
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS782A—August 2011
2.9 Development and Support
2.9.1 Development Support
The following products support development of C6000™ DSP-based applications:
• Software Development Tools:
– Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly
Code Generation, and Debug plus additional development tools.
– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
• Hardware Development Tools:
– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
– EVM (Evaluation Module)
2.9.2 Device Support
2.9.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices
and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,
TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
• TMX: Experimental device that is not necessarily representative of the final device's electrical specifications
• TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
• TMS: Fully qualified production device
Support tool development evolutionary flow:
• TMDX: Development-support product that has not yet completed Texas Instruments internal qualification
testing.
• TMDS: Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Copyright 2011 Texas Instruments Incorporated
61
ADVANCE INFORMATION
In case the customer would like to develop their own features and software on the TCI6602 device, TI offers an
extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for
example, CYP), the temperature range (for example, blank is the default case temperature range), and the device
speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).
For device part numbers and further ordering information for TMS320TCI6602 in the CYP package type, see the TI
website www.ti.com or contact your TI sales representative.
Figure 2-17 provides a legend for reading the complete device name for any C66x KeyStone device.
Figure 2-17
C66x DSP Device Nomenclature (including the TMS320TCI6602)
ADVANCE INFORMATION
TMX
320 TCI6602
(
) (
) CYP
(
)
(
)
PREFIX
TMX = Experimental device
TMS = Qualified device
DEVICE SPEED RANGE
Blank = 1 GHz
25 = 1.25 GHz
5 = 1.5 GHz
DEVICE FAMILY
320 = TMS320 DSP family
TEMPERATURE RANGE
Blank = 0°C to +100°C (default case temperature)
A = Extended temperature range
(-40°C to +100°C)
DEVICE
C66x DSP: TCI6602
SILICON REVISION
Blank = Initial Silicon 1.0
PACKAGE TYPE
CYP = 841-pin plastic ball grid array,
with Pb-free solder balls
ENCRYPTION
Blank = Encryption NOT enabled
X = Encryption enabled
62
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS782A—August 2011
2.10 Related Documentation from Texas Instruments
64-bit Timer (Timer 64) for KeyStone Devices User Guide
SPRUGV5
Antenna Interface 2 (AIF2) for KeyStone Devices User Guide
SPRUGV7
Bootloader for the C66x DSP User Guide
SPRUGY5
C66x CorePac User Guide
SPRUGW0
C66x CPU and Instruction Set Reference Guide
SPRUGH7
C66x DSP Cache User Guide
SPRUGY8
DDR3 Design Guide for KeyStone Devices
SPRABI1
Emulation and Trace Headers Technical Reference
SPRU655
Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide
SPRUGS5
Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide
SPRUGV9
External Memory Interface (EMIF16) for KeyStone Devices User Guide
SPRUGZ3
Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide
SPRUGS2
General Purpose Input/Output (GPIO) for KeyStone Devices User Guide
SPRUGV1
Hardware Design Guide for KeyStone Devices
SPRABI2
HyperLink for KeyStone Devices User Guide
SPRUGW8
Inter Integrated Circuit (I2C) for KeyStone Devices User Guide
SPRUGV3
Interrupt Controller (INTC) for KeyStone Devices User Guide
SPRUGW4
Memory Protection Unit (MPU) for KeyStone Devices User Guide
SPRUGW5
Multicore Navigator for KeyStone Devices User Guide
SPRUGR9
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide
SPRUGW7
Network Coprocessor (NETCP) for KeyStone Devices User Guide
SPRUGZ6
Packet Accelerator (PA) for KeyStone Devices User Guide
SPRUGS4
Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide
SPRUGS6
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide
SPRUGV2
Power Management for KeyStone Devices
SPRABH0
Power Sleep Controller (PSC) for KeyStone Devices User Guide
SPRUGV4
Serial Peripheral Interface (SPI) for KeyStone Devices User Guide
SPRUGP2
Serial RapidIO (SRIO) for KeyStone Devices User Guide
SPRUGW1
Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide
SPRUGY4
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide
SPRUGP1
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems
SPRA387
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs
SPRA753
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
These documents describe the TMS320TCI6602 Multicore Fixed and Floating-Point Digital Signal Processor.
Copies of these documents are available on the Internet at www.ti.com
63
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
3 Device Configuration
On the TMS320TCI6602 device, certain device configurations like boot mode and endianess, are selected at device
power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.
3.1 Device Configuration at Device Reset
ADVANCE INFORMATION
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device
configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors
or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The device
configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid
contention, the control device must stop driving the device configuration pins of the DSP.And when driving by a
control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP
can be taken out of reset.
Also, please note that most of the device configuration pins are shared with other function pins
(LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0),
some time must be given following the rising edge of reset in order to drive these device configuration input pins
before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that
needs to be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the
clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal
pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external
pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in
which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on
page 81.
Table 3-1
TMS320TCI6602 Device Configuration Pins
Configuration Pin
LENDIAN
(1) (2)
IPD/IPU
(1)
Functional Description
H25
IPU
Device endian mode (LENDIAN).
0 = Device operates in big endian mode
1 = Device operates in little endian mode
J28, J29, J26, J25,
J27, J24, K27, K28,
K26, K29, L28, L29,
K25
IPD
Method of boot.
L27, K24
IPD
PCIe Subsystem mode selection.
00 = PCIe in end point mode
01 = PCIe legacy end point (support for legacy INTx)
10 = PCIe in root complex mode
11 = Reserved
(1) (2)
L24
IPD
PCIe subsystem enable/disable.
0 = PCIE Subsystem is disabled
1 = PCIE Subsystem is enabled
(1)
AE4
IPD
Network Coprocessor (PASS PLL) input clock select.
0 = CORECLK is used as the input to PASS PLL
1 = PASSCLK is used as the input to PASS PLL
BOOTMODE[12:0]
PCIESSMODE[1:0]
PCIESSEN
Pin No.
PACLKSEL
(1) (2)
(1) (2)
Some pins may not be used by bootloader and can be used as general purpose config
pins. Refer to the Bootloader for the C66x DSP User Guide (literature number SPRUGY5) for
how to determine the device enumeration ID value.
End of Table 3-1
1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on
pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 81.
2 These signal names are the secondary functions of these pins.
64
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320TCI6602 are controlled by the Power Sleep Controller (PSC). By default,
the PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a
low-leakage sleep mode. Software is required to turn these memories on. The software enables the modules (turns
on clocks and de-asserts reset) before these modules can be used.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide (literature
number SPRUGV4).
3.3 Device State Control Registers
The TMS320TCI6602 device has a set of registers that are used to provide the status or configure certain parts of its
peripherals. These registers are shown in Table 3-2.
Table 3-2
Device State Control Registers (Part 1 of 4)
Address Start
Address End
Size
Field
0x02620000
0x02620007
8B
Reserved
0x02620008
0x02620017
16B
Reserved
0x02620018
0x0262001B
4B
JTAGID
0x0262001C
0x0262001F
4B
Reserved
0x02620020
0x02620023
4B
DEVSTAT
0x02620024
0x02620037
20B
Reserved
0x02620038
0x0262003B
4B
KICK0
0x0262003C
0x0262003F
4B
KICK1
0x02620040
0x02620043
4B
DSP_BOOT_ADDR0
Description
See section 3.3.3
See section 3.3.1
See section 3.3.4
The boot address for C66x DSP CorePac 0
0x02620044
0x02620047
4B
DSP_BOOT_ADDR1
The boot address for C66x DSP CorePac 1
0x02620048
0x0262004B
4B
Reserved
Reserved
0x0262004C
0x0262004F
4B
Reserved
Reserved
0x02620050
0x02620053
4B
Reserved
Reserved
0x02620054
0x02620057
4B
Reserved
Reserved
0x02620058
0x0262005B
4B
Reserved
Reserved
0x0262005C
0x0262005F
4B
Reserved
Reserved
0x02620060
0x026200DF
128B
Reserved
0x026200E0
0x0262010F
48B
Reserved
0x02620110
0x02620117
8B
MACID
0x02620118
0x0262012F
24B
Reserved
0x02620130
0x02620133
4B
LRSTNMIPIN
See section 3.3.6
0x02620134
0x02620137
4B
RESET_STAT_CLR
See section 3.3.8
0x02620138
0x0262013B
4B
Reserved
0x0262013C
0x0262013F
4B
BOOTCOMPLETE
0x02620140
0x02620143
4B
Reserved
0x02620144
0x02620147
4B
RESET_STAT
0x02620148
0x0262014B
4B
LRSTNMIPINSTAT
See section 3.3.5
0x0262014C
0x0262014F
4B
DEVCFG
See section 3.3.2
Copyright 2011 Texas Instruments Incorporated
See section 7.22 ‘‘Gigabit Ethernet (GbE) Switch Subsystem’’ on
page 188
See section 3.3.9
See section 3.3.7
65
ADVANCE INFORMATION
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 3-2
www.ti.com
Device State Control Registers (Part 2 of 4)
ADVANCE INFORMATION
Address Start
Address End
Size
Field
Description
0x02620150
0x02620153
4B
PWRSTATECTL
See section 3.3.10
0x02620154
0x02620157
4B
SRIO_SERDES_STS
See ‘‘Related Documentation from Texas Instruments’’ on page 63
0x02620158
0x0262015B
4B
SMGII_SERDES_STS
0x0262015C
0x0262015F
4B
PCIE_SERDES_STS
0x02620160
0x02620163
4B
HYPERLINK_SERDES_STS
0x02620164
0x02620167
4B
Reserved
0x02620168
0x0262016B
4B
Reserved
0x0262016C
0x0262017F
20B
Reserved
0x02620180
0x02620183
4B
Reserved
0x02620184
0x0262018F
12B
Reserved
0x02620190
0x02620193
4B
Reserved
0x02620194
0x02620197
4B
Reserved
0x02620198
0x0262019B
4B
Reserved
0x0262019C
0x0262019F
4B
Reserved
0x026201A0
0x026201A3
4B
Reserved
0x026201A4
0x026201A7
4B
Reserved
0x026201A8
0x026201AB
4B
Reserved
0x026201AC
0x026201AF
4B
Reserved
0x026201B0
0x026201B3
4B
Reserved
0x026201B4
0x026201B7
4B
Reserved
0x026201B8
0x026201BB
4B
Reserved
0x026201BC
0x026201BF
4B
Reserved
0x026201C0
0x026201C3
4B
Reserved
0x026201C4
0x026201C7
4B
Reserved
0x026201C8
0x026201CB
4B
Reserved
0x026201CC
0x026201CF
4B
Reserved
0x026201D0
0x026201FF
48B
Reserved
0x02620200
0x02620203
4B
NMIGR0
0x02620204
0x02620207
4B
NMIGR1
0x02620208
0x0262020B
4B
NMIGR2
0x0262020C
0x0262020F
4B
NMIGR3
0x02620210
0x02620213
4B
NMIGR4
0x02620214
0x02620217
4B
NMIGR5
0x02620218
0x0262021B
4B
NMIGR6
0x0262021C
0x0262021F
4B
NMIGR7
0x02620220
0x0262023F
32B
Reserved
0x02620240
0x02620243
4B
IPCGR0
0x02620244
0x02620247
4B
IPCGR1
0x02620248
0x0262024B
4B
IPCGR2
0x0262024C
0x0262024F
4B
IPCGR3
0x02620250
0x02620253
4B
IPCGR4
0x02620254
0x02620257
4B
IPCGR5
0x02620258
0x0262025B
4B
IPCGR6
0x0262025C
0x0262025F
4B
IPCGR7
66
See section 3.3.11
See section 3.3.12
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Device State Control Registers (Part 3 of 4)
Address Start
Address End
Size
Field
0x02620260
0x0262027B
28B
Reserved
Description
0x0262027C
0x0262027F
4B
IPCGRH
See section 3.3.14
0x02620280
0x02620283
4B
IPCAR0
See section 3.3.13
0x02620284
0x02620287
4B
IPCAR1
0x02620288
0x0262028B
4B
IPCAR2
0x0262028C
0x0262028F
4B
IPCAR3
0x02620290
0x02620293
4B
IPCAR4
0x02620294
0x02620297
4B
IPCAR5
0x02620298
0x0262029B
4B
IPCAR6
0x0262029C
0x0262029F
4B
IPCAR7
0x026202A0
0x026202BB
28B
Reserved
0x026202BC
0x026202BF
4B
IPCARH
0x026202C0
0x026202FF
64B
Reserved
See section 3.3.15
0x02620300
0x02620303
4B
TINPSEL
See section 3.3.16
0x02620304
0x02620307
4B
TOUTPSEL
See section 3.3.17
See section 3.3.18
0x02620308
0x0262030B
4B
RSTMUX0
0x0262030C
0x0262030F
4B
RSTMUX1
0x02620310
0x02620313
4B
RSTMUX2
0x02620314
0x02620317
4B
RSTMUX3
0x02620318
0x0262031B
4B
RSTMUX4
0x0262031C
0x0262031F
4B
RSTMUX5
0x02620320
0x02620323
4B
RSTMUX6
0x02620324
0x02620327
4B
RSTMUX7
0x02620328
0x0262032B
4B
MAINPLLCTL0
0x0262032C
0x0262032F
4B
MAINPLLCTL1
0x02620330
0x02620333
4B
DDR3PLLCTL
0x02620334
0x02620337
4B
Reserved
0x02620338
0x0262033B
4B
PAPLLCTL
0x0262033C
0x0262033F
4B
Reserved
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 3-2
See section 7.6 ‘‘Main PLL and PLL Controller’’ on page 118
See section 7.7 ‘‘DD3 PLL’’ on page 130
See section 7.8 ‘‘PASS PLL’’ on page 133
67
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 3-2
www.ti.com
Device State Control Registers (Part 4 of 4)
Address Start
Address End
Size
Field
Description
0x02620340
0x02620343
4B
SGMII_SERDES_CFGPLL
See ‘‘Related Documentation from Texas Instruments’’ on page 63
0x02620344
0x02620347
4B
SGMII_SERDES_CFGRX0
0x02620348
0x0262034B
4B
SGMII_SERDES_CFGTX0
0x0262034C
0x0262034F
4B
SGMII_SERDES_CFGRX1
0x02620350
0x02620353
4B
SGMII_SERDES_CFGTX1
0x02620354
0x02620357
4B
Reserved
0x02620358
0x0262035B
4B
PCIE_SERDES_CFGPLL
ADVANCE INFORMATION
0x0262035C
0x0262035F
4B
Reserved
0x02620360
0x02620363
4B
SRIO_SERDES_CFGPLL
0x02620364
0x02620367
4B
SRIO_SERDES_CFGRX0
0x02620368
0x0262036B
4B
SRIO_SERDES_CFGTX0
0x0262036C
0x0262036F
4B
SRIO_SERDES_CFGRX1
0x02620370
0x02620373
4B
SRIO_SERDES_CFGTX1
0x02620374
0x02620377
4B
SRIO_SERDES_CFGRX2
0x02620378
0x0262037B
4B
SRIO_SERDES_CFGTX2
0x0262037C
0x0262037F
4B
SRIO_SERDES_CFGRX3
0x02620380
0x02620383
4B
SRIO_SERDES_CFGTX3
0x02620384
0x02620387
4B
Reserved
0x02620388
0x026203AF
28B
Reserved
0x026203B0
0x026203B3
4B
Reserved
0x026203B4
0x026203B7
4B
HYPERLINK_SERDES_CFGPLL
0x026203B8
0x026203BB
4B
HYPERLINK_SERDES_CFGRX0
0x026203BC
0x026203BF
4B
HYPERLINK_SERDES_CFGTX0
0x026203C0
0x026203C3
4B
HYPERLINK_SERDES_CFGRX1
0x026203C4
0x026203C7
4B
HYPERLINK_SERDES_CFGTX1
0x026203C8
0x026203CB
4B
HYPERLINK_SERDES_CFGRX2
0x026203CC
0x026203CF
4B
HYPERLINK_SERDES_CFGTX2
0x026203D0
0x026203D3
4B
HYPERLINK_SERDES_CFGRX3
0x026203D4
0x026203D7
4B
HYPERLINK_SERDES_CFGTX3
0x026203D8
0x026203DB
4B
Reserved
0x026203DC
0x026203FF
24B
Reserved
0x02620400
0x02620403
4B
PKTDMA_PRI_ALLOC
0x02620404
0x02620467
100B
Reserved
See ‘‘Related Documentation from Texas Instruments’’ on page 63
See 4.4 ‘‘Bus Priorities’’ on page 85
End of Table 3-2
68
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
3.3.1 Device Status Register
The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or
RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device Status Register is
shown in Figure 3-1 and described in Table 3-3.
Figure 3-1
Device Status Register
31
18
Reserved
17
16
PACLKSEL
PCIESSEN
PCIESSMODE[1:0
BOOTMODE[12:0]
R-x
R/W-xx
R/W-xxxxxxxxxxxx
R-0
15
14
13
1
0
LENDIAN
R-x
(1)
ADVANCE INFORMATION
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
Table 3-3
Device Status Register Field Descriptions
Bit
Field
Description
31-18
Reserved
Reserved. Read only, writes have no effect.
17
PACLKSEL
PA Clock select to select the reference clock for PA Sub-System PLL
0 = Selects CORECLK(P/N)
1 = Selects PASSCLK(P/N)
16
PCIESSEN
PCIe module enable
0 = PCIe module disabled
1 = PCIe module enabled
15-14
PCIESSMODE[1:0]
PCIe Mode selection pins
00b = PCIe in End-point mode
01b = PCIe in Legacy End-point mode (support for legacy INTx)
10b = PCIe in Root complex mode
11b = Reserved
13-1
BOOTMODE[12:0]
Determines the bootmode configured for the device. For more information on bootmode, refer to Section 2.5 ‘‘Boot
Modes Supported and PLL Settings’’ on page 26 and see the Bootloader for the C66x DSP User Guide (literature number
SPRUGY5).
0
LENDIAN
Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little
Endian mode.
0 = System is operating in Big Endian mode
1 = System is operating in Little Endian mode
End of Table 3-3
3.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets
and is locked after the first write. The Device Configuration Register is shown in Figure 3-2 and described in
Table 3-4.
Figure 3-2
Device Configuration Register (DEVCFG)
31
1
0
Reserved
SYSCLKOUTEN
R-0
R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset
Copyright 2011 Texas Instruments Incorporated
69
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 3-4
Bit
31:1
0
www.ti.com
Device Configuration Register Field Descriptions
Field
Description
Reserved
Reserved. Read only, writes have no effect.
SYSCLKOUTEN
SYSCLKOUT Enable
0 = No clock output
1 = Clock output enabled (default)
End of Table 3-4
3.3.3 JTAG ID (JTAGID) Register Description
ADVANCE INFORMATION
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the
JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3 and
described in Table 3-5.
Figure 3-3
JTAG ID (JTAGID) Register
31
28
27
12
11
1
0
VARIANT
PART NUMBER
MANUFACTURER
LSB
R-xxxxb
R-0000 0000 1001 1110b
0000 0010 111b
R-1
Legend: RW = Read/Write; R = Read only; -n = value after reset
Table 3-5
JTAG ID Register Field Descriptions
Bit
Field
Value
Description
31-28
VARIANT
xxxxb
Variant (4-Bit) value. The value of this field depends on the silicon revision being used.
Please refer to the specific silicon errata document for details.
27-12
PART NUMBER
0000 0000 1001 1110b
Part Number for boundary scan
11-1
MANUFACTURER
0000 0010 111b
Manufacturer
LSB
1b
This bit is read as a 1 for TMS320TCI6602
0
End of Table 3-5
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are
writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with
exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on
page 65 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable
(the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0.
Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to
Bootcfg MMRs.
The kicker mechanism is unlocked by the ROM code. Do not write any other different values afterward to these
registers because that will lock the kicker mechanism and block any writes to Bootcfg registers.
70
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6 .
Figure 3-4
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
18
17
16
Reserved
NMI1
NMI0
R, +0000 0000
R-0
R-0
15
2
1
0
Reserved
LR1
LR0
R, +0000 0000
R-0
R-0
Legend: R = Read only; -n = value after reset;
Bit
31-18
17
16
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
Field
Description
Reserved
Reserved
NMI1
CorePac 1 in NMI
NMI0
CorePac 0 in NMI
Reserved
Reserved
1
LR1
CorePac 1 in Local Reset
0
LR0
CorePac 0 in Local Reset
15-2
ADVANCE INFORMATION
Table 3-6
End of Table 3-6
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The
LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7.
Figure 3-5
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
18
17
16
Reserved
NMI1
NMI0
R, +0000 0000
WC,+0
WC,+0
15
2
1
0
Reserved
LR1
LR0
R, +0000 0000
WC,+0
WC,+0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Table 3-7
Bit
31-18
17
16
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
Field
Description
Reserved
Reserved
NMI1
CorePac 1 in NMI Clear
NMI0
CorePac 0 in NMI Clear
Reserved
Reserved
1
LR1
CorePac 1 in Local Reset Clear
0
LR0
CorePac 0 in Local Reset Clear
15-2
End of Table 3-7
3.3.7 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.
• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.
Copyright 2011 Texas Instruments Incorporated
71
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
•
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In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is
asserted.
The Reset Status Register is shown in Figure 3-6 and described in Table 3-8.
Figure 3-6
31
Reset Status Register (RESET_STAT)
30
2
1
0
GR
Reserved
LR1
LR0
R, +1
R, + 000 0000 0000 0000 0000 0000
R,+0
R,+0
Legend: R = Read only; -n = value after reset
ADVANCE INFORMATION
Table 3-8
Reset Status Register (RESET_STAT) Field Descriptions
Bit
31
Field
Description
GR
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
Reserved
Reserved.
1
LR1
CorePac 1 reset status
0 = CorePac 1 has not received a local reset.
1 = CorePac 1 received a local reset.
0
LR0
CorePac 0 reset status
0 = CorePac 0 has not received a local reset.
1 = CorePac 0 received a local reset.
30-2
End of Table 3-8
3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in Figure 3-7 and described in Table 3-9.
Figure 3-7
31
Reset Status Clear Register (RESET_STAT_CLR)
30
2
1
0
GR
Reserved
LR1
LR0
RW, +0
R, + 000 0000 0000 0000 0000 0000
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-9
Bit
31
30-2
72
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 1 of 2)
Field
Description
GR
Global Reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved
Reserved.
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 3-9
Bit
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 2 of 2)
Field
Description
1
LR1
CorePac 1 reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.
0
LR0
CorePac 0 reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
3.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the
completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-8 and described in
Table 3-10.
Figure 3-8
Boot Complete Register (BOOTCOMPLETE)
31
2
1
0
Reserved
BC1
BC0
R, + 0000 0000 0000 0000 0000 0000
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-10
Bit
Boot Complete Register (BOOTCOMPLETE) Field Descriptions
Field
Description
Reserved
Reserved.
1
BC1
CorePac 1 boot status
0 = CorePac 1 boot NOT complete
1 = CorePac 1 boot complete
0
BC0
CorePac 0 boot status
0 = CorePac 0 boot NOT complete
1 = CorePac 0 boot complete
31-2
End of Table 3-10
The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is
they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.
Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before
branching to the predefined location in memory.
Copyright 2011 Texas Instruments Incorporated
73
ADVANCE INFORMATION
End of Table 3-9
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
3.3.10 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this
register to differentiate between the various power saving modes. This register is cleared only by Power On Reset
and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 63 for more information. The Power State Control Register is
shown in Figure 3-9 and described in Table 3-11.
Figure 3-9
Power State Control Register (PWRSTATECTL)
31
3
ADVANCE INFORMATION
2
1
0
GENERAL_PURPOSE
HIBERNATION_MODE
HIBERNATION
STANDBY
RW, +0000 0000 0000 0000 0000 0000 0000 0
RW,+0
RW,+0
RW,+0
Legend: RW = Read/Write; -n = value after reset
Table 3-11
Bit
Power State Control Register (PWRSTATECTL) Field Descriptions
Field
Description
GENERAL_PURPOSE
Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 63.
2
HIBERNATION_MODE
Indicates whether the device is in hibernation mode 1 or mode 2.
0 = Hibernation mode 1
1 = Hibernation mode 2
1
HIBERNATION
Indicates whether the device is in hibernation mode or not.
0 = Not in hibernation mode
1 = Hibernation mode
0
STANDBY
Indicates whether the device is in standby mode or not.
0 = Not in standby mode
1 = Standby mode
31-3
End of Table 3-11
3.3.11 NMI Even Generation to CorePac (NMIGRx) Register
NMIGRx registers are used for generating NMI events to the corresponding CorePac. The TCI6602 has
two NMIGRx registers (NMIGR0 through NMIGR1). The NMIGR0 register generates an NMI event to CorePac0,
the NMIGR1 register generates an NMI event to CorePac1, and so on. Writing a 1 to the NMIG field generates a
NMI pulse. Writing a 0 has no effect and reads return 0 and have no other effect. The NMI Even Generation to
CorePac Register is shown in Figure 3-10 and described in Table 3-12.
Figure 3-10
NMI Generation Register (NMIGRx)
31
1
0
GENERAL_PURPOSE
NMIG
R, +0000 0000 0000 0000 0000 0000 0000 000
RW,+0
Legend: RW = Read/Write; -n = value after reset
74
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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Table 3-12
Bit
31-1
0
NMI Generation Register (NMIGRx) Field Descriptions
Field
Reserved
NMIG
Description
Reserved
NMI pulse generation.
Reads return 0
Writes:
0 = No effect
1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.
3.3.12 IPC Generation (IPCGRx) Registers
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The TCI6602 has two IPCGRx registers (IPCGR0 through IPCGR1). These registers can be used by external hosts
or CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an
interrupt pulse to CorePacx (0 <= x <= 1).
These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is
completely controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Generation Register is shown in Figure 3-11 and described in Table 3-13.
Figure 3-11
IPC Generation Registers (IPCGRx)
31
30
29
28
SRCS27
SRCS26
SRCS25
SRCS24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
1
0
SRCS23 – SRCS4
SRCS3
SRCS2
RCS1
SRCS0
Reserved
IPCG
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-13
Bit
31-4
IPC Generation Registers (IPCGRx) Field Descriptions
Field
Description
SRCSx
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
Reserved
IPCG
Inter-DSP interrupt generation.
Reads return 0.
Writes:
0 = No effect
1 = Creates an Inter-DSP interrupt.
End of Table 3-13
3.3.13 IPC Acknowledgement (IPCARx) Registers
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
Copyright 2011 Texas Instruments Incorporated
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ADVANCE INFORMATION
End of Table 3-12
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
The TCI6602 has two IPCARx registers (IPCAR0 through IPCAR1). These registers also provide a Source ID facility
by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and
meaning is entirely based on software convention. The register field descriptions are shown in the following tables.
Virtually anything can be a source for these registers as this is completely controlled by software. Any master that
has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in
Figure 3-12 and described in Table 3-14.
Figure 3-12
IPC Acknowledgement Registers (IPCARx)
ADVANCE INFORMATION
31
30
29
28
SRCC27
SRCC26
SRCC25
SRCC24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
0
SRCC23 – SRCC4
SRCC3
SRCC2
RCC1
SRCC0
Reserved
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-14
Bit
31-4
IPC Acknowledgement Registers (IPCARx) Field Descriptions
Field
Description
SRCCx
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-14
3.3.14 IPC Generation Host (IPCGRH) Register
IPCGRH register is provided to facilitate host DSP interrupt. Operation and use of IPCGRH is the same as
other IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event
output (HOUT).
The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (DSP/6) followed
by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 DSP/6 cycle pulse blocking window.
Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 DSP/6 cycle period. The
IPC Generation Host Register is shown in Figure 3-13 and described in Table 3-15.
Figure 3-13
IPC Generation Registers (IPCGRH)
31
30
29
28
SRCS27
SRCS26
SRCS25
SRCS24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
1
0
SRCS23 – SRCS4
SRCS3
SRCS2
RCS1
SRCS0
Reserved
IPCG
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
76
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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Table 3-15
Bit
IPC Generation Registers (IPCGRH) Field Descriptions
Field
31-4
Description
SRCSx
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
Reserved
IPCG
Host interrupt generation.
Reads return 0.
ADVANCE INFORMATION
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-15
3.3.15 IPC Acknowledgement Host (IPCARH) Register
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in
Table 3-16.
Figure 3-14
IPC Acknowledgement Register (IPCARH)
31
30
29
28
SRCC27
SRCC26
SRCC25
SRCC24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
0
SRCC23 – SRCC4
SRCC3
SRCC2
RCC1
SRCC0
Reserved
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-16
Bit
IPC Acknowledgement Register (IPCARH) Field Descriptions
Field
31-4
SRCCx
Description
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-16
3.3.16 Timer Input Selection Register (TINPSEL)
Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown
in Figure 3-15 and described in Table 3-17.
Figure 3-15
Timer Input Selection Register (TINPSEL)
31
8
Reserved
7
6
5
4
3
2
1
0
TINPHSEL3
TINPLSEL3
TINPHSEL2
TINPLSEL2
TINPHSEL1
TINPLSEL1
TINPHSEL0
TINPLSEL0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +1
RW, +1
RW, +0
R = Read only; RW = Read/Write; -n = value after reset
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TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 3-17
Bit
Timer Input Selection Field Description (TINPSEL)
Field
31-8
www.ti.com
Description
ADVANCE INFORMATION
Reserved
Reserved
7
TINPHSEL3
Input select for TIMER3 high.
0 = TIMI0
1 = TIMI1
6
TINPLSEL3
Input select for TIMER3 low.
0 = TIMI0
1 = TIMI1
5
TINPHSEL2
Input select for TIMER2 high.
0 = TIMI0
1 = TIMI1
4
TINPLSEL2
Input select for TIMER2 low.
0 = TIMI0
1 = TIMI1
3
TINPHSEL1
Input select for TIMER1 high.
0 = TIMI0
1 = TIMI1
2
TINPLSEL1
Input select for TIMER1 low.
0 = TIMI0
1 = TIMI1
1
TINPHSEL0
Input select for TIMER0 high.
0 = TIMI0
1 = TIMI1
0
TINPLSEL0
Input select for TIMER0 low.
0 = TIMI0
1 = TIMI1
End of Table 3-17
3.3.17 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-16 and described in Table 3-18.
Figure 3-16
Timer Output Selection Register (TOUTPSEL)
31
10
9
5
4
0
Reserved
TOUTPSEL1
TOUTPSEL0
R,+000000000000000000000000
RW,+00001
RW,+00000
Legend: R = Read only; RW = Read/Write; -n = value after reset
78
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Bit
Timer Output Selection Field Description (TOUTPSEL)
Field
Description
31-10
Reserved
Reserved
9-5
TOUTPSEL1
Output select for TIMO1
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
4-0
TOUTPSEL0
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000 to 11111: Reserved
Output select for TIMO0
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000 to 11111: Reserved
End of Table 3-18
3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through
RSTMUX1 for each of the two CorePacs on the TCI6602. These registers are located in Bootcfg memory space. The
Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17
Reset Mux Register RSTMUXx
31
10
9
8
7
5
4
3
1
0
Reserved
EVTSTATCLR
Reserved
DELAY
EVTSTAT
OMODE
LOCK
R, +0000 0000 0000 0000 0000 00
RC, +0
R, +0
RW, +100
R, +0
RW, +000
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
Table 3-19
Reset Mux Register Field Descriptions (Part 1 of 2)
Bit
Field
Description
31-10
Reserved
Reserved
9
EVTSTATCLR
8
Reserved
7-5
4
Clear event status.
0 = Writing O had no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
DELAY
Delay cycles between NMI & Local reset.
000b = 256 DSP/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
010b = 1024 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
011b = 2048 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
100b = 4096 DSP/6 cycles delay between NMI & local reset, when OMODE=100b (Default)
101b = 8192 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
110b = 16384 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
111b = 32768 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
EVTSTAT
Event status.
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
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Table 3-18
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 3-19
Bit
3-1
ADVANCE INFORMATION
0
www.ti.com
Reset Mux Register Field Descriptions (Part 2 of 2)
Field
Description
OMODE
Timer event operation mode.
000b = WD timer event input to the reset mux block does not cause any output event (default)
001b = Reserved
010b = WD timer event input to the reset mux block causes local reset input to CorePac
011b = WD timer event input to the reset mux block causes NMI input to CorePac
100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay
between NMI and local reset is set in DELAY bit field.
101b = WD timer event input to the reset mux block causes device reset to TCI6602
110b = Reserved
111b = Reserved
LOCK
Lock register fields.
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
End of Table 3-19
80
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3.4 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This
may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown
(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state),
it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing
external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In
addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user
in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown
resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs
connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net.
A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which,
by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the
target pulled value when maximum current from all devices on the net is flowing through the resistor. The
current to be considered includes leakage current plus, any other internal and external pullup/pulldown
resistors on the net.
• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the
external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to
the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems:
• A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this
resistor value is correct for their specific application.
• A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the
above criteria. Users should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for
the TMS320TCI6602 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 95.
To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-15 ‘‘Terminal
Functions — Signals and Control by Function’’ on page 37.
Copyright 2011 Texas Instruments Incorporated
81
ADVANCE INFORMATION
An external pullup/pulldown resistor needs to be used in the following situations:
• Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown
resistor to pull the signal to the opposite rail.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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4 System Interconnect
On the TMS320TCI6602 device, the C66x CorePacs, the EDMA3 transfer controllers, and the system peripherals
are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers
between master peripherals and slave peripherals. The switch fabrics also allow for seamless arbitration between the
system masters when accessing system slaves.
4.1 Internal Buses, Bridges, and Switch Fabrics
ADVANCE INFORMATION
Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus
and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width
and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of
a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is
also used to transfer data. Similarly, the data bus can also be used to access the register space of a peripheral.
The C66x CorePacs, the EDMA3 traffic controllers, and the various system peripherals can be classified into two
categories: masters and slaves.
Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data
transfers. Slaves on the other hand rely on the masters to perform transfers to and from them. Examples of masters
include the EDMA3 traffic controllers, SRIO, and network coprocessor packet DMA. Examples of slaves include the
2
SPI, UART, and I C.
The device contains two switch fabrics (the TeraNet) through which masters and slaves communicate. The data
switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to
move data across the system (for more information, see Section 4.2 ‘‘Data Switch Fabric Connections’’). The data
SCR is further divided into two smaller SCRs. One connects very high speed masters to slaves via 256-bit data buses
running at a CPU/2 frequency. The other connects masters to slaves via 128-bit data buses running at a CPU/3
frequency. Peripherals that match the native bus width of the SCR it is connected to can connect directly to the data
SCR; other peripherals require a bridge.
The configuration switch fabric, also known as the configuration switch central resource (SCR), is mainly used to
access peripheral registers (for more information, see Section 4.3 ‘‘Configuration Switch Fabric’’). The
configuration SCR connects the C66x CorePac and masters on the data switch fabric to slaves via
32-bit configuration buses running at a CPU/3 frequency. As with the data SCR, some peripherals require the use of
a bridge to interface to the configuration SCR.
Bridges perform a variety of functions:
• Conversion between configuration bus and data bus.
• Width conversion between peripheral bus width and SCR bus width.
• Frequency conversion between peripheral bus frequency and SCR bus frequency.
82
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Multicore Fixed and Floating-Point Digital Signal Processor
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4.2 Data Switch Fabric Connections
A detailed figure will be added here for a future release. Connection information is shown in the tables below.
Table 4-1
CPU/2 Data SCR Connection Matrix
Slave
Masters
HyperLink_Slave
MSMC_SMS
MSMC_SES
Br_1
Br_2
Br_3
Br_4
Y
Y
Y
N
Y
N
N
TPCC0 TC0_RD
TPCC0 TC0_WR
Y
Y
Y
N
Y
N
N
TPCC0 TC1_RD
Y
Y
Y
N
N
Y
N
TPCC0 TC1_WR
Y
Y
Y
N
N
Y
N
HyperLink_Master
N
Y
Y
Y
N
N
N
MSMC_master
Y
N
N
N
N
N
Y
From CPU/3 Data SCR Br_5
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_6
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_7
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_8
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_9
Y
Y
Y
N
N
N
N
From CPU/3 Data SCR Br_10
Y
Y
Y
N
N
N
N
End of Table 4-1
Table 4-2
DSP/3 Data SCR Connection Matrix (Part 1 of 2)
HyperLink Data
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
Br_14 (to Config SCR)
Br_13 (to Config SCR)
Br_12 (to Config SCR)
Br_10 (to DSP/2 Data SCR)
Br_9 (to DSP/2 Data SCR)
Br_8 (to DSP/2 Data SCR)
Br_7 (to DSP/2 Data SCR)
Br_6 (to DSP/2 Data SCR)
Br_5 (to DSP/2 Data SCR)
EMIF16
HyperLink Slave
QM Slave
PCIe Slave
SPI
Boot ROM
SRIO_Data_Slave
Masters
CorePac1_SDMA
CorePac0_SDMA
Slaves
N
N
Y
N
N
TPCC0_TC0_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
N
N
N
N
Y
N
N
TPCC0_TC0_WR
Y
Y
Y
N
Y
Y
N
Y
Y
N
N
N
N
N
N
Y
N
N
TPCC0_TC1_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
N
N
N
N
Y
N
N
TPCC0_TC1_WR
Y
Y
Y
N
Y
Y
N
Y
Y
N
N
N
N
N
N
Y
N
N
TPCC1_TC0_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
N
N
N
N
N
Y
N
N
TPCC1_TC0_WR
Y
Y
Y
N
Y
Y
N
Y
Y
Y
N
N
N
N
N
Y
N
N
TPCC1_TC1_RD
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
TPCC1_TC1_WR
Y
Y
Y
N
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
TPCC1_TC2_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
Y
N
N
N
N
N
Y
TPCC1_TC2_WR
Y
Y
Y
N
Y
Y
N
Y
Y
N
N
Y
N
N
N
N
N
Y
TPCC1_TC3_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
N
Y
N
N
Y
N
N
TPCC1_TC3_WR
Y
Y
Y
N
Y
Y
N
Y
Y
N
N
N
Y
N
N
Y
N
N
TPCC2_TC0_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
N
N
Y
N
Y
N
N
TPCC2_TC0_WR
Y
Y
Y
N
Y
Y
N
Y
Y
N
N
N
N
Y
N
Y
N
N
TPCC2_TC1_RD
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
Y
N
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To CPU/3 Data SCR
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 4-2
www.ti.com
DSP/3 Data SCR Connection Matrix (Part 2 of 2)
TPCC2_TC1_WR
Y
Y
Y
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Br_14 (to Config SCR)
Br_13 (to Config SCR)
Br_12 (to Config SCR)
Br_10 (to DSP/2 Data SCR)
Br_9 (to DSP/2 Data SCR)
Br_8 (to DSP/2 Data SCR)
Br_7 (to DSP/2 Data SCR)
Br_6 (to DSP/2 Data SCR)
Br_5 (to DSP/2 Data SCR)
EMIF16
HyperLink Slave
QM Slave
PCIe Slave
SPI
Boot ROM
SRIO_Data_Slave
Masters
CorePac1_SDMA
CorePac0_SDMA
Slaves
N
Y
N
ADVANCE INFORMATION
TPCC2_TC2_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
N
N
N
N
N
Y
N
N
TPCC2_TC2_WR
Y
Y
Y
N
Y
Y
N
Y
Y
Y
N
N
N
N
N
Y
N
N
TPCC2_TC3_RD
Y
Y
Y
Y
Y
Y
N
Y
Y
N
Y
N
N
N
N
N
N
Y
TPCC2_TC3_WR
Y
Y
Y
N
Y
Y
N
Y
Y
N
Y
N
N
N
N
N
N
Y
SRIO Messaging
Y
Y
N
N
N
N
Y
N
Y
N
N
N
N
Y
N
N
N
N
SRIO Data Master
Y
Y
N
N
Y
N
Y
Y
Y
N
N
N
N
Y
N
Y
N
N
PCIe Master
Y
Y
N
N
Y
N
Y
Y
Y
N
N
Y
N
N
N
Y
N
N
Packet Accelerator Data
Y
Y
N
N
N
N
Y
N
N
N
N
N
N
N
Y
N
N
N
MSMC Data (Br_4)
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
N
N
Queue Manager
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
N
N
N
N
N
TSIP 0
Y
Y
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
TSIP 1
Y
Y
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
End of Table 4-2
84
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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4.3 Configuration Switch Fabric
A detailed figure will be added here for a future release. All masters can talk to all slaves on the configuration switch
fabric.
4.4 Bus Priorities
All other masters provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA based
peripherals also have internal registers to define the priority level of their initiated transactions.
The Packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-1 and
Table 4-3.
Figure 4-1
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
3
2
0
Reserved
PKTDMA_PRI
R/W-00000000000000000000001000011
RW-000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4-3
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
Bit
Field
Description
31-3
Reserved
Reserved.
2-0
PKDTDMA_PRI
Control the priority level for the transactions from packet DMA master port, which access the external linking
RAM.
End of Table 4-3
For all other modules, see the respective User Guides in “Related Documentation from Texas Instruments” on
page 63 for programmable priority registers.
Copyright 2011 Texas Instruments Incorporated
85
ADVANCE INFORMATION
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers will be present to allow software configuration of the data traffic through the TeraNet. Note that a lower
number means higher priority - PRI = 000b = urgent, PRI = 111b = low.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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5 C66x CorePac
The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the
C66x CorePac) and address extension. Figure 5-1 shows a block diagram of the C66x CorePac.
Figure 5-1
C66x CorePac Block Diagram
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
In-Circuit Emulation
Boot
Controller
Instruction Decode
Data Path B
Data Path A
PLLC
LPSC
A Register File
B Register File
A31-A16
A15-A0
B31-B16
B15-B0
.M1
xx
xx
.M2
xx
xx
GPSC
.L1
.S1
.D1
.D2
.S2
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
.L2
Extended Memory
Controller (XMC)
C66x DSP Core
L2 Cache/
SRAM
512KB
MSM
SRAM
4096KB
DDR3
SRAM
DMA Switch
Fabric
External Memory
Controller (EMC)
Program Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
Unified Memory
Controller (UMC)
32KB L1P
Interrupt and Exception Controller
ADVANCE INFORMATION
The C66x CorePac consists of several components:
• The C66x DSP and associated C66x CorePac core
• Level-one and level-two memories (L1P, L1D, L2)
• Data Trace Formatter (DTF)
• Embedded Trace Buffer (ETB)
• Interrupt controller
• Power-down controller
• External memory controller
• Extended memory controller
• A dedicated power/sleep controller (LPSC)
CFG Switch
Fabric
32KB L1D
For more detailed information on the TMS320C66x CorePac on the TCI6602 device, see the C66x CorePac User
Guide (literature number SPRUGW0).
86
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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5.1 Memory Architecture
Each C66x CorePac of the TMS320TCI6602 device contains a 512KB level-2 memory (L2), a 32KB level-1 program
memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 4096KB multicore shared memory
(MSM). All memory on the TCI6602 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map
Summary for TMS320TCI6602’’ on page 19.
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader
for the C66x DSP User Guide (literature number SPRUGY5).
For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide (literature number
SPRUGY8).
5.1.1 L1P Memory
The L1P memory configuration for the TCI6602 device is as follows:
• 32K bytes with no wait states
Figure 5-2 shows the available SRAM/cache configurations for L1P.
Figure 5-2
TMS320TCI6602 L1P Memory Configurations
L1P mode bits
000
001
010
011
100
1/2
SRAM
All
SRAM
7/8
SRAM
L1P memory
Block base
address
00E0 0000h
16K bytes
3/4
SRAM
direct
mapped
cache
00E0 4000h
8K bytes
dm
cache
direct
mapped
cache
Copyright 2011 Texas Instruments Incorporated
direct
mapped
cache
00E0 6000h
4K bytes
00E0 7000h
4K bytes
00E0 8000h
87
ADVANCE INFORMATION
The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration
Register (L1PCFG) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac.
L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.
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Multicore Fixed and Floating-Point Digital Signal Processor
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5.1.2 L1D Memory
The L1D memory configuration for the TCI6602 device is as follows:
• 32K bytes with no wait states
Figure 5-3 shows the available SRAM/cache configurations for L1D.
Figure 5-3
TMS320TCI6602 L1D Memory Configurations
L1D mode bits
000
001
010
011
100
ADVANCE INFORMATION
1/2
SRAM
All
SRAM
7/8
SRAM
L1D memory
Block base
address
00F0 0000h
16K bytes
3/4
SRAM
2-way
cache
00F0 4000h
8K bytes
2-way
cache
00F0 6000h
4K bytes
2-way
cache
2-way
cache
00F0 7000h
4K bytes
00F0 8000h
5.1.3 L2 Memory
The L2 memory configuration for the TCI6602 device is as follows:
• Total memory size is 4096KB
• Each core contains 512KB of memory
• Local starting address for each core is 0080 0000h
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L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register
(L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is
configured as all SRAM after device reset.
Figure 5-4
TMS320TCI6602 L2 Memory Configurations
L2 Mode Bits
001
010
011
ALL
SRAM
15/16
SRAM
7/8
SRAM
3/4
SRAM
100
1/2
SRAM
101
ALL
Cache
L2 Memory
Block Base
Address
0080 0000h
ADVANCE INFORMATION
000
256Kbytes
4-Way
Cache
0084 0000h
128Kbytes
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
0086 0000h
64Kbytes
32Kbytes
32Kbytes
0087 0000h
0087 8000h
0087 FFFFh
Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by
the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled
within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address
location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can
access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000
only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.
For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000 and for C66x CorePac Core 1 this is
equivalent to 0x11800000. Local addresses should be used only for shared code or data, allowing a single image to
be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by
a particular core should always use the global address only.
5.1.4 MSMC SRAM
The MSMC SRAM configuration for the TCI6602 device is as follows:
• Memory size is 4096KB
• The MSMC SRAM can be configured as shared L2 and/or shared L3 memory
• Allows extension of external addresses from 2GB to up to 8GB
• Has built in memory protection features
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The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in
L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on
external memory address extension and memory protection features, see the Multicore Shared Memory Controller
(MSMC) for KeyStone Devices User Guide (literature number SPRUGW7).
5.1.5 L3 Memory
The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement
to block accesses from this portion to the ROM.
5.2 Memory Protection
ADVANCE INFORMATION
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2
memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB
each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in
the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In
addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct
DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by
other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a
secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether
memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 5-1.
Table 5-1
Available Memory Page Protection Schemes
AIDx Bit
Local Bit
0
0
Description
No access to memory page is permitted.
0
1
Only direct access by DSP is permitted.
1
0
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1
1
All accesses permitted.
End of Table 5-1
Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return zero, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide (literature number SPRUGW0).
90
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5.3 Bandwidth Management
The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x
CorePac. These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the
Priority Allocation Register (PRI_ALLOC) System peripherals with no fields in PRI_ALLOC have their own
registers to program their priorities, see section 4.4 ‘‘Bus Priorities’’ on page 85 for more details.
More information on the bandwidth management features of the C66x CorePac can be found in the C66x CorePac
User Guide (literature number SPRUGW0.)
5.4 Power-Down Control
The C66x CorePac supports the ability to power-down various parts of the C66x CorePac. The power-down
controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and
the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power
requirements.
Note—The TCI6602 does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the TMS320C66x CorePac
Reference Guide (literature number SPRUGW0).
5.5 C66x CorePac Revision
The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID)
located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table 5-2. The
C66x CorePac revision is dependant on the silicon revision being used.
Figure 5-5
CorePac Revision ID Register (MM_REVID) Address - 0181 2000h
31
16
15
0
VERSION
REVISION
R-n
R-n
Legend: R = Read; -n = value after reset
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ADVANCE INFORMATION
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to
the highest priority requestor. The following four resources are managed by the Bandwidth Management control
hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 5-2
www.ti.com
CorePac Revision ID Register (MM_REVID) Field Descriptions
Bit
Field
Description
31-16
VERSION
Version of the C66x CorePac implemented on the device.
15-0
REVISION
Revision of the C66x CorePac version implemented on the device.
End of Table 5-2
5.6 C66x CorePac Register Descriptions
See the C66x CorePac Reference Guide (literature number SPRUGW0) for register offsets and definitions.
ADVANCE INFORMATION
92
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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6 Device Operating Conditions
6.1 Absolute Maximum Ratings
Table 6-1
Absolute Maximum Ratings (1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
-0.3 V to TBD V
CVDD1
-0.3 V to TBD V
DVDD15
-0.3 V to TBD V
DVDD18
-0.3 V to TBD V
VREFSSTL
VDDT1, VDDT2, VDDT3
0.49 × DVDD15 to 0.51 × DVDD15
-0.3 V to TBD V
VDDT4, VDDT5, VDDT6
VDDR1, VDDR2, VDDR3
-0.3 V to TBD V
AVDDA1, AVDDA2, AVDDA3
-0.3 V to TBD V
VSS Ground
-0.3 V to TBD V
DDR3
-0.3 V to TBD V
2
Input voltage (VI) range:
Output voltage (VO) range:
Operating case temperature range, TC:
0V
LVCMOS (1.8V)
IC
-0.3 V to TBD V
LVDS
-0.3 V to TBD V
LJCB
-0.3 V to TBD V
SERDES
-0.3 V to TBD V
LVCMOS (1.8V)
-0.3 V to TBD V
DDR3
-0.3 V to TBD V
2
IC
-0.3 V to TBD V
SERDES
-0.3 V to TBD V
Commercial
Extended
0°C to 85°C
-40°C to 100°C
LVCMOS (1.8V)
Overshoot/undershoot
(3)
DDR3
2
20% Overshoot/Undershoot for 20% of
Signal Duty Cycle
IC
Storage temperature range, Tstg:
-65°C to 150°C
End of Table 6-1
1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
2 All voltage values are with respect to VSS.
3 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and
maximum undershoot value would be VSS - 0.20 × DVDD18
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ADVANCE INFORMATION
Supply voltage range (2):
CVDD
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
6.2 Recommended Operating Conditions
Recommended Operating Conditions (1)
Table 6-2
CVDD
SR Core Supply
CVDD1
Core Supply
(2)
Min
Nom
CVDD-0.05*CVDD
0.9-1.1
CVDD+0.05*CVDD
Max Unit
0.95
1
1.05
V
DVDD18
1.8-V supply I/O voltage
1.71
1.8
1.89
V
DVDD15
1.5-V supply I/O voltage
1.425
1.5
1.575
V
VREFSSTL
DDR3 reference voltage
0.49 × DVDD15
0.5 × DVDD15
0.51 × DVDD15
V
VDDRx (3)
SerDes regulator supply
1.425
1.5
1.575
V
ADVANCE INFORMATION
VDDAx
PLL analog supply
1.71
1.8
1.89
V
VDDTx
SerDes termination supply
0.95
1
1.05
V
VSS
Ground
0
0
0
V
LVCMOS (1.8 V)
VIH
High-level input voltage
I2C
DDR3 EMIF
0.65 × DVDD18
V
0.7 × DVDD18
V
VREFSSTL + 0.1
V
LVCMOS (1.8 V)
VIL
Low-level input voltage
DDR3 EMIF
0.35 × DVDD18
-0.3
VREFSSTL - 0.1
V
0.3 × DVDD18
V
0
85
°C
-40
100
°C
2
IC
TC
Operating case temperature
Commercial
Extended
V
End of Table 6-2
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE
802.3ae-2002.
2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
3 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
94
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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6.3 Electrical Characteristics
Table 6-3
Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Parameter
LVCMOS (1.8 V)
VOH
High-level output voltage
Test Conditions
(1)
IO = IOH
Min
Typ
Max Unit
DVDD18 - 0.45
DVDD15 - 0.4
DDR3
V
2 (2)
IC
VOL
Low-level output voltage
IO = IOL
DDR3
2
IC
0.4
IO = 3 mA, pulled up to 1.8 V
No IPD/IPU
LVCMOS (1.8 V)
II
(3)
Input current [DC]
2
Low-level output current [DC]
IOL
Internal pullup
Internal pulldown
IC
IOH High-level output current [DC]
0.45
0.1 × DVDD18 V < VI < 0.9 ×
DVDD18 V
-5
(4)
Off-state output current [DC]
5
50
100
170
-170
-100
-50
-10
10
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IOZ
LVCMOS (1.8 V)
V
0.4
μA
μA
mA
mA
TBD
-2
2
μA
End of Table 6-3
1
2
3
For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
I2C uses open collector IOs and does not have a VOH Minimum.
II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and
off-state (Hi-Z) output leakage current.
4 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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ADVANCE INFORMATION
LVCMOS (1.8 V)
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 6-4
www.ti.com
Power Supply to Peripheral I/O Mapping
(1) (2)
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Power Supply
I/O Buffer
Type
Associated Peripheral
CORECLK(P|N) PLL input buffer
SRIOSGMIICLK(P|N) SERDES PLL input buffer
CVDD
Supply Core Voltage
LJCB
DDRCLK(P|N) PLL input buffer
PCIECLK(P|N) SERDES PLL input buffer
MCMCLK(P|N) SERDES PLL input buffer
PASSCLK(P|N) PLL input buffer
ADVANCE INFORMATION
DVDD15
1.5-V supply I/O voltage
DDR3 (1.5 V)
All DDR3 memory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All TIMER0/TIMER1 peripheral I/O buffer
All SPI peripheral I/O buffer
All I2C peripheral I/O buffer
DVDD18
1.8-V supply I/O voltage
DDR3 (1.5 V)
All RESETs, NMI, Control peripheral I/O buffer
All Smart Reflex peripheral I/O buffer
All Hyperlink Sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
All TSIP0 and TSIP1 peripheral I/O buffer
All EMIF16 peripheral I/O buffer
DVDDT1
Hyperlink SERDES Termination and analogue front-end supply
SERDES/CML
DVDDT2
SRIO/SGMII/PCIE SERDES Termination and analogue front-end supply SERDES/CML
Hyperlink SERDES CML IO buffer
SRIO/SGMII/PCIE SERDES CML IO buffer
End of Table 6-4
1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and
clock input buffers.
2 Please see the Hardware Design Guide for KeyStone Devices (literature number SPRABI2) for more information about individual peripheral I/O.
96
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7 Peripheral Information and Electrical Specifications
This chapter covers the various peripherals on the TMS320TCI6602 DSP. Peripheral-specific information, timing
diagrams, electrical specifications, and register memory maps are described in this chapter.
7.1 Parameter Information
The data manual provides timing at the device pin. For output analysis, the transmission line and associated
parasitics (vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending
on the trace length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end
product design. For recommended transmission line lengths, see the appropriate application notes, user guides, and
design guides. A transmission line delay of 2 ns was used for all output measurements, except the DDR3, which was
evaluated using a 528-ps delay.
2
Figure 7-1 represents all device outputs, except differential or I C.
Figure 7-1
Test Load Circuit for AC Timing Measurements
Device
DDR3 Output Test Load
Transmission Line
Zo = 50 W
4 pF
Data Manual Timing
Reference Point
(Device Terminal)
Device
Output Test Load Excluding DDR3
Transmission Line
Zo = 50 W
5 pF
The load capacitance value stated is only for characterization and measurement of AC timing signals. This load
capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1 1.8-V Signal Transition Levels
All input and output timing parameters are referenced to 0.9 V for both 0 and 1 logic levels.
Figure 7-2
Input and Output Voltage Reference Levels for AC Timing Measurements
Vref = 0.9 V
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This section describes the conditions used to capture the electrical data seen in this chapter.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks.
Figure 7-3
Rise and Fall Transition Time Voltage Reference Levels
Vref = VIH MIN (or VOH MIN)
7.1.2 Timing Parameters and Board Routing Analysis
ADVANCE INFORMATION
The timing parameter values specified in this data sheet do not include delays by board routings. As a good board
design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS)
models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis
for a given system, see the Using IBIS Models for Timing Analysis application report (literature number TBD). If
needed, external logic hardware such as buffers may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 7-1 and Figure 7-4).
Table 7-1
Board-Level Timing Example
(see Figure 7-4)
No.
Description
1
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
4
External device hold time requirement
5
External device setup time requirement
6
Control signal route delay
7
External device hold time
8
External device access time
9
DSP hold time requirement
10
DSP setup time requirement
11
Data route delay
End of Table 7-1
98
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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Figure 7-4 shows a general transfer between the DSP and an external device. The figure also shows board route
delays and how they are perceived by the DSP and the external device
Figure 7-4
Board-Level Input/Output Timings
AECLKOUT
(Output from DSP)
1
AECLKOUT
(Input to External Device)
2
3
Control Signals
(Input to External Device)
6
5
4
ADVANCE INFORMATION
Control Signals (A)
(Output from DSP)
7
8
(B)
Data Signals
(Output from External Device)
10
(B)
Data Signals
(Input to DSP)
9
11
(A) Control signals include data for writes.
(B) Data signals are generated during reads from an external device.
7.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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Multicore Fixed and Floating-Point Digital Signal Processor
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7.3 Power Supplies
The following sections describe the proper power-supply sequencing and timing needed to properly power on the
TCI6602. The various power supply rails and their primary function is listed in Table 7-2.
Table 7-2
Name
Power Supply Rails on TMS320TCI6602
Primary Function
Voltage
Notes
ADVANCE INFORMATION
CVDD
SmartReflex core supply voltage
0.9 - 1.1 V Includes core voltage for DDR3 module
CVDD1
Core supply voltage for memory
array
1.0 V
Fixed supply at 1.0 V
VDDT1
HyperLink SerDes termination
supply
1.0 V
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
HyperLink is not in use.
VDDT2
SGMII/SRIO/PCIE SerDes
termination supply
1.0 V
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
SGMII/SRIO/PCIE is not in use.
DVDD15
1.5-V DDR3 IO supply
1.5 V
VDDR1
HyperLink SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
HyperLink is not in use.
VDDR2
PCIE SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIE
is not in use.
VDDR3
SGMII SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
SGMII is not in use.
VDDR4
SRIO SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SRIO
is not in use.
DVDD18
1.8-V IO supply
1.8V
AVDDA1
Main PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
AVDDA2
DDR3 PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
AVDDA3
PASS PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
VREFSSTL
0.75-V DDR3 reference voltage
0.75 V
Should track the 1.5-V supply. Use 1.5 V as source.
VSS
Ground
GND
End of Table 7-2
7.3.1 Power-Supply Sequencing
This section defines the requirements for a power up sequencing from a power-on reset condition. There are two
acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO
voltages as shown below.
1. CVDD
2. CVDD1, VDDT1-3
3. DVDD18, AVDD1, AVDD2
4. DVDD15, VDDR1-4
The second sequence provides compatibility with other TI processors with the IO voltage starting before the core
voltages as shown below.
1. DVDD18, AVDD1, AVDD2
2. CVDD
3. CVDD1, VDDT1-3
4. DVDD15, VDDR1-4
100
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If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled to ground
through a 1K ohm resistor. The P leg should be tied to CVDD to ensure it won't have any voltage present until
CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be
driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could
cause damage to the device.
The device initialization is broken into two phases. The first phase consists of the time period from the activation of
the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the
sequencing scenarios described above can be implemented during this phase. The figures below show both the
core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire
power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL
will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must
always go inactive before RESETFULL goes inactive as described below. The following section mentions SYSCLK1
in several places. SYSCLK1 here refers to the clock input that has been selected as the source for the Main PLL. See
Figure 7-11 for more details.
7.3.1.1 Core-Before-IO Power Sequencing
Figure 7-5 shows the power sequencing and reset control of TMS320TCI6602 for device initialization. POR may be
removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after
the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the
GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified.
SYSCLK1 must always be active before POR can be removed. Core-before-IO power sequencing is defined in
Table 7-3.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp
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The clock input buffers for CORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK and MCMCLK
use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until
CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the
device. Once CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either
high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the
clock inputs should be removed from the high impedance state shortly after CVDD is present.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Figure 7-5
www.ti.com
Core Before IO Power Sequencing
Power Stabilization Phase
Device Initialization Phase
POR
t7
RESETFULL
t8
ADVANCE INFORMATION
GPIO Config
Bits
t4b
t9
t10
RESET
t2c
t1
CVDD
t6
t2a
CVDD1
t3
DVDD18
t4a
DVDD15
t5
REFCLKP&N
t2b
DDRCLKP&N
RESETSTAT
Table 7-3
Core Before IO Power Sequencing (Part 1 of 2)
Time
System State
t1
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from
POR) is put into the reset state.
t2a
• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is
permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will
ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core
constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
t2b
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or be held in a static state with one leg high and one leg low.
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Core Before IO Power Sequencing (Part 2 of 2)
Time
System State
t2c
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t6.
t3
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin
before DVDD18 is valid could cause damage to the device.
t4a
• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the
voltage for DVDD15 must never exceed DVDD18.
t4b
• RESETFULL and RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, both RESETFULL and RESET
must be high before POR is driven high.
t5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
t6
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
t7
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
t8
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
t9
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL
t10
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL
End of Table 7-3
7.3.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-6 and defined in Table 7-4.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp.
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Table 7-3
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Figure 7-6
www.ti.com
IO Before Core Power Sequencing
Power Stabilization Phase
Device Initialization Phase
POR
t5
t7
RESETFULL
t8
ADVANCE INFORMATION
GPIO Config
Bits
t2a
t9
t10
RESET
t3c
t2b
CVDD
t6
t3a
CVDD1
t1
DVDD18
t4
DVDD15
t3b
REFCLKP&N
DDRCLKP&N
RESETSTAT
Table 7-4
IO Before Core Power Sequencing
Time
System State
t1
Begin Power Stabilization Phase
• Because POR is low, all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must
remain low through Power Stabilization Phase.
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before
DVDD18 could cause damage to the device.
t2a
• RESET may be driven high anytime after DVDD18 is at a valid level.
t2b
• CVDD (core AVS) ramps up.
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IO Before Core Power Sequencing
Time
System State
t3a
• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the
voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure
that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant)
ramps up before CVDD (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1.
t3b
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or held in a static state with one leg high and one leg low.
t3c
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t6.
t4
• DVDD15 (1.5 V) supply is ramped up following CVDD1.
t5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
t6
Begin Device Initialization
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
• POR must remain low.
t7
• RESETFULL is held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
t8
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
t9
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL
t10
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL
End Device Initialization Phase
End of Table 7-4
7.3.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of
the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for
more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the
reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation
state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the
device.
7.3.1.4 Clocking during power sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the
clocks is contingent on the state of the boot configuration pins. Table 7-5 describes the clock sequencing and the
conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until
CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the
other connected to CVDD.
Table 7-5
Clock Sequencing (Part 1 of 2)
Clock
Condition
Sequencing
DDRCLK
None
Must be present 16 μsec before POR transitions high.
CORECLK
PASSCLK
None
CORECLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.
PASSCLKSEL = 0
PASSCLK is not used and should be tied to a static state.
PASSCLKSEL = 1
PASSCLK is used as a source for the PASS PLL. It must be present before the PASS PLL is removed from
reset and programmed.
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Table 7-4
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-5
Clock
www.ti.com
Clock Sequencing (Part 2 of 2)
Condition
Sequencing
An SGMII port will be used.
SRIOSGMIICLK must be present 16 μsec before POR transitions high.
SGMII will not be used. SRIO SRIOSGMIICLK must be present 16 μsec before POR transitions high.
will be used as a boot device.
SRIOSGMIICLK SGMII will not be used. SRIO
will be used after boot.
ADVANCE INFORMATION
PCIECLK
MCMCLK
SRIOSGMIICLK is used as a source to the SRIO SERDES PLL. It must be present before the SRIO is
removed from reset and programmed.
SGMII will not be used. SRIO
will not be used.
SRIOSGMIICLK is not used and should be tied to a static state.
PCIE will be used as a boot
device.
PCIECLK must be present 16 μsec before POR transitions high.
PCIE will be used after boot.
PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from
reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
HyperLink will be used as a
boot device.
MCMCLK must be present 16usec before POR transitions high.
HyperLink will be used after
boot.
MCMCLK is used as a source to the MCM SERDES PLL. It must be present before the HyperLink is
removed from reset and programmed.
HyperLink will not be used.
MCMCLK is not used and should be tied to a static state.
End of Table 7-5
7.3.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a
large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the
supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,
POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can also affect long term reliability.
7.3.3 Power Supply Decoupling and Bulk Capacitors
In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are
required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or
bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply
Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone Devices (literature number SPRABI2).
7.3.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor structures
responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the
leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios.
This static power consumption is mainly determined by transistor type and process technology. Higher clock rates
also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a
specific usage scenario, clock rates, and I/O activity.
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the TMS320TCI6602 device is a feature that allows the core
voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each
TMS320TCI6602 device.
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To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required
to be implemented whenever the TMS320TCI6602 device is used. The voltage selection is done using 4 VCNTL pins
which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices application
report and the Hardware Design Guide for KeyStone Devices (literature number SPRABI2).
Table 7-6
SmartReflex 4-Pin VID Interface Switching Characteristics
(see Figure 7-7)
1
Parameter
td(Bn-SELECTL)
Min
Delay Time - VCNTL[2:0] (B[2:0]]) valid after VCNTL[3] (Select) low
2
toh(SELECTL-Bn)
Output Hold Time - VCNTL[2:0] (B[2:0]]) valid after VCNTL[3] (Select) low
3
td(Bn-SELECTH)
Delay Time - VCNTL[2:0] (B[2:0]]) valid after VCNTL[3] (Select) high
4
toh(SELECTH-Bn)
Output Hold Time - VCNTL[2:0] (B[2:0]]) valid after VCNTL[3] (Select) high
Max
ns
(1)
ms
300.00
ns
172020C
ms
0.07 172020C
0.07
Unit
300.00
End of Table 7-6
1 C = 1/SYSCLK1 frequency (See Figure 7-13)in ms
Figure 7-7
SmartReflex 4-Pin VID Interface Timing
4
VCNTL[3] (Select)
1
VCNTL[2:0] (B[2:0])
3
LSB VID[2:0]
MSB VID[5:3]
2
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7.4 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating
off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several
important power and clock operations.
For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User
Guide (literature number SPRUGV4).
7.4.1 Power Domains
ADVANCE INFORMATION
The device has several power domains that can be turned on for operation or off to minimize power dissipation. The
global power/sleep controller (GPSC) is used to control the power gating of various power domains.
Table 7-7 shows the TMS320TCI6602 power domains.
Table 7-7
Power Domains
Domain
Block(s)
Note
Power Connection
0
Most peripheral logic
Cannot be disabled
Always on
1
Per-core TETB and System TETB
RAMs can be powered down
Software control
2
Packet Coprocessor
Logic can be powered down
Software control
3
PCIe
Logic can be powered down
Software control
4
SRIO
Logic can be powered down
Software control
5
HyperLink
Logic can be powered down
Software control
6
Reserved
Reserved
Reserved
7
MSMC RAM
MSMC RAM can be powered down
Software control
8
C66x Core 0, L1/L2 RAMs
L2 RAMs can sleep
9
C66x Core 1, L1/L2 RAMs
L2 RAMs can sleep
Software control via C66x core. For details, see the
C66x CorePac Reference Guide.
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
End of Table 7-7
7.4.2 Clock Domains
Cock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating.
Table 7-8 shows the TMS320TCI6602 clock domains.
Table 7-8
Clock Domains (Part 1 of 2)
LPSC Number
Module(s)
Notes
0
Shared LPSC for all peripherals other than those listed in this table
Always on
1
SmartReflex
Always on
2
DDR3 EMIF
Always on
3
EMIF16 and SPI
Software control
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Clock Domains (Part 2 of 2)
LPSC Number
Module(s)
Notes
4
TSIP
Software control
5
Debug Subsystem and Tracers
Software control
6
Per-core TETB and System TETB
Software control
7
Packet Accelerator
Software control
8
Ethernet SGMIIs
Software control
9
Security Accelerator
Software control
10
PCIe
Software control
11
SRIO
Software control
12
HyperLink
Software control
13
Reserved
Reserved
14
MSMC RAM
Software control
15
C66x Core 0 and Timer 0
Always on
16
C66x Core 1 and Timer 1
Always on
17
Timer 2
Always on
18
Timer 3
Always on
19
Reserved
Reserved
20
Reserved
Reserved
21
Reserved
Reserved
22
Reserved
Reserved
No LPSC
Bootcfg, PSC, and PLL controller
These modules do not use LPSC
ADVANCE INFORMATION
Table 7-8
End of Table 7-8
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7.4.3 PSC Register Memory Map
Table 7-9 shows the PSC Register memory map.
Table 7-9
PSC Register Memory Map (Part 1 of 3)
Offset
Register
Description
0x000
PID
Peripheral Identification Register
0x004 - 0x010
Reserved
Reserved
0x014
VCNTLID
Voltage Control Identification Register
0x018 - 0x11C
Reserved
Reserved
ADVANCE INFORMATION
0x120
PTCMD
Power Domain Transition Command Register
0x124
Reserved
Reserved
0x128
PTSTAT
Power Domain Transition Status Register
0x12C - 0x1FC
Reserved
Reserved
0x200
PDSTAT0
Power Domain Status Register 0 (AlwaysOn)
0x204
PDSTAT1
Power Domain Status Register 1 (Per-core TETB and System TETB)
0x208
PDSTAT2
Power Domain Status Register 2 (Packet Coprocessor)
0x20C
PDSTAT3
Power Domain Status Register 3 (PCIe)
0x210
PDSTAT4
Power Domain Status Register 4 (SRIO)
0x214
PDSTAT5
Power Domain Status Register 5 (HyperLink)
0x218
PDSTAT6
Power Domain Status Register 6 (Reserved)
0x21C
PDSTAT7
Power Domain Status Register 7 (MSMC RAM)
0x220
PDSTAT8
Power Domain Status Register 8 (C66x Core 0)
0x224
PDSTAT9
Power Domain Status Register 9 (C66x Core 1)
0x228
Reserved
Reserved
0x22C
Reserved
Reserved
0x230
Reserved
Reserved
0x234
Reserved
Reserved
0x238
Reserved
Reserved
0x23C
Reserved
Reserved
0x240 - 0x2FC
Reserved
Reserved
0x300
PDCTL0
Power Domain Control Register 0 (AlwaysOn)
0x304
PDCTL1
Power Domain Control Register 1 (Per-core TETB and System TETB)
0x308
PDCTL2
Power Domain Control Register 2 (Packet Coprocessor)
0x30C
PDCTL3
Power Domain Control Register 3 (PCIe)
0x310
PDCTL4
Power Domain Control Register 4 (SRIO)
0x314
PDCTL5
Power Domain Control Register 5 (HyperLink)
0x318
PDCTL6
Power Domain Control Register 6 (Reserved)
0x31C
PDCTL7
Power Domain Control Register 7 (MSMC RAM)
0x320
PDCTL8
Power Domain Control Register 8 (C66x Core 0)
0x324
PDCTL9
Power Domain Control Register 9 (C66x Core 1)
0x328
Reserved
Reserved
0x32C
Reserved
Reserved
0x330
Reserved
Reserved
0x334
Reserved
Reserved
0x338
Reserved
Reserved
0x33C
Reserved
Reserved
110
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PSC Register Memory Map (Part 2 of 3)
Offset
Register
Description
0x340 - 0x7FC
Reserved
Reserved
0x800
MDSTAT0
Module Status Register 0 (Never Gated)
0x804
MDSTAT1
Module Status Register 1 (SmartReflex)
0x808
MDSTAT2
Module Status Register 2 (DDR3 EMIF)
0x80C
MDSTAT3
Module Status Register 3 (EMIF16 and SPI)
0x810
MDSTAT4
Module Status Register 4 (TSIP)
0x814
MDSTAT5
Module Status Register 5 (Debug Subsystem and Tracers)
0x818
MDSTAT6
Module Status Register 6 (Per-core TETB and System TETB)
0x81C
MDSTAT7
Module Status Register 7 (Packet Accelerator)
0x820
MDSTAT8
Module Status Register 8 (Ethernet SGMIIs)
0x824
MDSTAT9
Module Status Register 9 (Security Accelerator)
0x828
MDSTAT10
Module Status Register 10 (PCIe)
0x82C
MDSTAT11
Module Status Register 11 (SRIO)
0x830
MDSTAT12
Module Status Register 12 (HyperLink)
0x834
MDSTAT13
Module Status Register 13 (Reserved)
0x838
MDSTAT14
Module Status Register 14 (MSMC RAM)
0x83C
MDSTAT15
Module Status Register 15 (C66x Core 0 and Timer 0)
0x840
MDSTAT16
Module Status Register 16 (C66x Core 1 and Timer 1)
0x844
MDSTAT17
Module Status Register 17 ( Timer 2)
0x848
MDSTAT18
Module Status Register 18 (Timer 3)
0x84C
MDSTAT19
Reserved
0x850
MDSTAT20
Reserved
0x854
MDSTAT21
Reserved
0x858
MDSTAT22
Reserved
0x85C - 0x9FC
Reserved
Reserved
0xA00
MDCTL0
Module Control Register 0 (Never Gated)
0xA04
MDCTL1
Module Control Register 1 (SmartReflex)
0xA08
MDCTL2
Module Control Register 2 (DDR3 EMIF)
0xA0C
MDCTL3
Module Control Register 3 (EMIF16 and SPI)
0xA10
MDCTL4
Module Control Register 4 (TSIP)
0xA14
MDCTL5
Module Control Register 5 (Debug Subsystem and Tracers)
0xA18
MDCTL6
Module Control Register 6 (Per-core TETB and System TETB)
0xA1C
MDCTL7
Module Control Register 7 (Packet Accelerator)
0xA20
MDCTL8
Module Control Register 8 (Ethernet SGMIIs)
0xA24
MDCTL9
Module Control Register 9 (Security Accelerator)
0xA28
MDCTL10
Module Control Register 10 (PCIe)
0xA2C
MDCTL11
Module Control Register 11 (SRIO)
0xA30
MDCTL12
Module Control Register 12 (HyperLink)
0xA34
MDCTL13
Module Control Register 13 (Reserved)
0xA38
MDCTL14
Module Control Register 14 (MSMC RAM)
0xA3C
MDCTL15
Module Control Register 15 (C66x Core 0 and Timer 0)
0xA40
MDCTL16
Module Control Register 16 (C66x Core 1 and Timer 1)
0xA44
MDCTL17
Module Control Register 17 (Timer 2)
0xA48
MDCTL18
Module Control Register 18 (Timer 3)
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 7-9
111
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-9
www.ti.com
PSC Register Memory Map (Part 3 of 3)
Offset
Register
Description
0xA4C
MDCTL19
Reserved
0xA50
MDCTL20
Reserved
0xA54
MDCTL21
Reserved
0xA58
MDCTL22
Reserved
0xA5C - 0xFFC
Reserved
Reserved
End of Table 7-9
ADVANCE INFORMATION
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7.5 Reset Controller
The reset controller detects the different type of resets supported on the TMS320TCI6602 device and manages the
distribution of those resets throughout the device.
Table 7-10 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data /
Timing’’ on page 116
Table 7-10
Reset Types
Reset Type
Initiator
POR (Power On Reset) POR pin active low
RESETFULL pin active low
Hard Reset
RESET pin active low
Emulation
PLLCTL register (RSCTRL)
Watchdog Timers
Soft Reset
RESET pin active low
PLLCTL register (RSCTRL)
Watchdog Timers
C66x CorePac
local reset
Software (through
LPSC MMR)
Watchdog Timers
LRESET pin
Effect on Device When Reset Occurs
RESETSTAT Pin Status
Toggles RESETSTAT pin
Total reset of the chip. Everything on the device is reset to its default
state in response to this. Activates the POR signal on chip, which is used
to reset test/emu logic. Boot configurations are latched. ROM boot
process is initiated.
Resets everything except for test/emu logic and Reset Isolation
modules. Emulator and Reset Isolation modules stay alive during this
reset. This reset is also different from POR in that the PLLCTL assumes
power and clocks are stable when Device Reset is asserted. Boot
configurations are not latched. ROM boot process is initiated.
Toggles RESETSTAT pin
Software can program these initiators to be hard or soft. Hard reset is
the default, but can be programmed to be Soft reset. Soft Reset will
behave like Hard Reset except that PCIe MMRs,EMIF16 MMRs, DDR3
EMIF MMRs, and External Memory contents are retained. Boot
configurations are not latched. ROM boot process is initiated.
Toggles RESETSTAT pin
MMR bit in LPSC controls C66x CorePac local reset. Used by Watchdog Does not toggle
RESETSTAT pin
Timers (in the event of a timeout) to reset C66x CorePac. Can also be
initiated by LRESET device pin. C66x CorePac memory system and Slave
DMA port are still alive when C66x CorePac is in local reset. Provides a
local reset of the C66x CorePac, without destroying clock alignment or
memory contents. Does not initiate ROM boot process.
End of Table 7-10
7.5.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device
including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR,
RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on
reset, the Main PLL controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the
state of the PLL or the dividers in the PLL controller.
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The device has several types of resets:
• Power-on reset
• Hard reset
• Soft reset
• CPU local reset
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The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are
power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control
registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 65).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional time for the
Chip level PLLs to lock.
4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. The Chip level PLLs
is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, DDR3
PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL
controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system
reference clocks. After the pause, the system clocks are restarted at their default divide by settings.
6. The device is now out of reset and device execution begins as dictated by the selected boot mode.
Note—To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted
(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period
of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the
POR pin.
7.5.2 Hard Reset
A Hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules.
POR should also remain de-asserted during this time.
Hard reset is initiated by the following
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog timer
• Emulation
All the above initiators by default are configured to act as Hard reset. Except Emulation all the other 3 initiators can
be configured as Soft resets in the RSCFG register in PLLCTL.
The following sequence must be followed during a Hard reset:
1. The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is
able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules
affected by RESET, to prevent off-chip contention during the warm reset.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
together with the POR pin.
114
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7.5.3 Soft Reset
A soft reset will behave like a hard reset except that the PCIe MMRs and DDR3 EMIF MMRs contents are retained.
POR should also remain de-asserted during this time.
All the above initiators by default are configured to act as Hard reset. Except Emulation, all the other 3 initiators can
be configured as Soft resets in the RSCFG register in PLLCTL.
In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore,
the enabled/disabled state of the peripherals is not affected. The following external memory contents are maintained
during a soft reset:
• DDR3 MMRs: The DDR3 Memory Controller registers are not reset. In addition, the DDR3 SDRAM memory
content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.
• PCIe MMRs: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are not
reset.
During a soft reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate
through the system. Internal system clocks are not affected. PLLs also remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
controllers pause their system clocks for about 8 cycles.
At this point:
› The state of the peripherals before the soft reset is not changed.
› The I/O pins are controlled as dictated by the DEVSTAT register.
› The DDR3 MMRs and PCIe MMRs retain their previous values. Only the DDR3 Memory Controller
and PCIe state machines are reset by the soft reset.
› The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with
a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.
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Soft reset is initiated by the following
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog Timer
• Emulation
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7.5.4 Local Reset
The local reset can be used to reset a particular CorePac without resetting any other chip components.
ADVANCE INFORMATION
Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) Controller for KeyStone
Devices User Guide (literature number SPRUGV2):
• LRESET pin
• Watchdog Timer should cause one of the below based on Reset Multiplex ESTMUXn register setting (See TBD
for details):
– Local Reset
– NMI
– NMI followed by a time delay and then a local reset for the core selected
– Hard Reset by requesting reset via PLLCTL
• LPSC MMRs
7.5.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.
The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/Soft reset
7.5.6 Reset Controller Register
The reset controller register are part of the PLLCTL MMRs. All TCI6602 device-specific MMRs are covered in
Section 7.6.3 ‘‘Main PLL Control Register’’ on page 127. For more details on these registers and how to program
them, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2).
7.5.7 Reset Electrical Data / Timing
Table 7-11
Reset Timing Requirements (1)
(see Figure 7-8 and Figure 7-9)
No.
Min
Max
Unit
RESETFULL Pin Reset
1
tw(RESETFULL)
Pulse Width - Pulse width RESETFULL low
3
tw(RESET)
Pulse Width - Pulse width RESET low
500C
ns
500C
ns
Soft/Hard-Reset
End of Table 7-11
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
Table 7-12
Reset Switching Characteristics Over Recommended Operating Conditions (1)
(see Figure 7-8 and Figure 7-9)
No.
Parameter
Min
Max
Unit
RESETFULL Pin Reset
2
td(RESETFULLH-RESETSTATH)
Delay Time - RESETSTAT high after RESETFULL high
4
td(RESETH-RESETSTATH)
Delay Time - RESETSTAT high after RESET high
50000C ns
Soft/Hard Reset
50000C ns
End of Table 7-12
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
116
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Figure 7-8
RESETFULL Reset Timing
POR
1
RESETFULL
RESET
RESETSTAT
Figure 7-9
Soft/Hard-Reset Timing
POR
RESETFULL
2
RESET
4
RESETSTAT
Boot Configuration Timing Requirements (1)
Table 7-13
(See Figure 7-10)
No.
Min
Max
Unit
1
tsu(GPIOn-RESETFULL)
Setup Time - GPIO valid before RESETFULL asserted
12C
ns
2
th(RESETFULL-GPIOn)
Hold Time - GPIO valid after RESETFULL asserted
12C
ns
End of Table 7-13
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
Figure 7-10
Boot Configuration Timing
1
RESETFULL
GPIO[15:0]
2
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7.6 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL
controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide (literature number
SPRUGV2). Figure 7-11 shows the Main PLL and PLL Controller.
Figure 7-11
Main PLL and PLL Controller
PLL
xPLLM
PLLD
/2
CORECLK(N|P)
0
PLLOUT
ADVANCE INFORMATION
OUTPUT
DIVIDE
1
BYPASS
PLL Controller
POSTDIV
/1
SYSCLK1
PLLDIV1
C66x
CorePac
/x
PLLDIV2
SYSCLK2
/2
PLLDIV3
SYSCLK3
/3
PLLDIV4
SYSCLK4
/y
PLLDIV5
SYSCLK5
/64
PLLDIV6
SYSCLK6
/6
PLLDIV7
SYSCLK7
To Switch Fabric,
Peripherals,
Accelerators
/z
PLLDIV8
SYSCLK8
/12
PLLDIV9
SYSCLK9
/3
PLLDIV10
SYSCLK10
/6
PLLDIV11
118
SYSCLK11
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Note—The Main PLL controller registers can be accessed by any master in the device.
The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment,
and gating for the system clocks to the device. Figure 7-11 shows a block diagram of the main PLL controller. The
following paragraphs define the clocks and PLL controller parameters.
The inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output.
The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL
controller monitors the PLL status and provides an output signal indicating when the PLL is locked.
Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices (literature number
SPRABI2) for detailed recommendations. For the best performance, TI recommends that all the PLL external
components be on a single side of the board without jumpers, switches, or components other than those shown. For
reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2,
and the EMI Filter).
The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see
Section 7.6.4 ‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’.
CAUTION—The PLL controller module as described in the see the Phase Locked Loop (PLL) Controller for
KeyStone Devices User Guide (literature number SPRUGV2) includes a superset of features, some of which
are not supported on the TMS320TCI6602 device. The following sections describe the registers that are
supported; it should be assumed that any registers not included in these sections is not supported by the
device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any
reserved memory location or changing the value of reserved bits.
7.6.1 Main PLL Controller Device-Specific Information
7.6.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the
DDR3 and the network coprocessor (PASS)) requires a PLL controller to manage the various clock divisions, gating,
and synchronization. The Main PLL’s PLL controller has several SYSCLK outputs that are listed below, along with
the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note
that dividers are not programmable unless explicitly mentioned in the description below.
• SYSCLK1: Full-rate clock for the CorePacs.
• SYSCLK2: 1/x-rate clock for CorePac (emulation) and the ADTF module. Default rate for this will be 1/3. This
is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be
turned off by software.
• SYSCLK3: 1/2-rate clock used to clock the MSMC, HyperLink, CPU/2 SCR, DDR EMIF and CPU/2 EDMA.
• SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs will use this as
well.
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Note—NOTE: PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL controller
and PLLM[12:6] bits are controlled by the chip level MAINPLLCTL0 register. The complete 13-bit value is
latched when the GO operation is initiated in the PLL controller. Only PLLDIV2, PLLDIV5, and PLLDIV8
are programmable on the TCI6602 device. See the Phase Locked Loop (PLL) Controller for KeyStone
Devices User Guide in section 2.10 ‘‘Related Documentation from Texas Instruments’’ on page 63 for
more details on how to program the PLL controller.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
•
•
•
•
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•
•
•
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SYSCLK5: 1/y-rate clock for system trace module only. Default rate for this will be 1/5. It is configurable and
the max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turned
off by software.
SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3
EMIF.
SYSCLK7: 1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.
SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclck in the system. Default for this will be 1/64. This is
programmable from /24 to /80.
SYSCLK9: 1/12-rate clock for SmartReflex.
SYSCLK10: 1/3-rate clock for SRIO only.
SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5 and SYSCLK8 are programmable on theTMS320TCI6602 device.
Note—In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8
(SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the
system.
7.6.1.2 Main PLL Controller Operating Modes
The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by BYPASS bit of the PLL Secondary control register (SECCTL). In PLL mode, SYSCLK1 is generated
from the PLL output using the divider PLLD and the PLL multiplier PLLM. In bypass mode, PLL output is fed
directly to SYSCLK1.
All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must
be in place such that the DSP notifies the host when the PLL configuration has completed.
7.6.1.3 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become
stable after device powerup. The PLL should not be operated until this stabilization time has expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the
PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value,
see Table 7-14.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with
PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main PLL lock time
is given in Table 7-14.
Table 7-14
Main PLL Stabilization, Lock, and Reset Times
Min
PLL stabilization time
Max
100
PLL lock time
PLL reset time
Typ
μs
2000 × C
1000
Unit
(1)
ns
End of Table 7-14
1 C = SYSCLK(N|P) cycle time in ns.
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7.6.2 PLL Controller Memory Map
The memory map of the PLL controller is shown in Table 7-15. TMS320TCI6602-specific PLL Controller register
definitions can be found in the sections following Table 7-15. For other registers in the table, see the Phase Locked
Loop (PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2).
Table 7-15
ADVANCE INFORMATION
CAUTION—Note that only registers documented here are accessible on the TMS320TCI6602. Other
addresses in the PLL controller memory map including the reserved registers should not be modified.
Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved
memory location or changing the value of reserved bits. It is recommended to use read-modify-write
sequence to make any changes to the valid bits in the register.
PLL Controller Registers (Including Reset Controller) (Part 1 of 2)
Hex Address Range
Field
Register Name
0231 0000 - 0231 00E3
-
Reserved
0231 00E4
RSTYPE
Reset Type Status Register (Reset Controller)
0231 00E8
RSTCTRL
Software Reset Control Register (Reset Controller)
0231 00EC
RSTCFG
Reset Configuration Register (Reset Controller)
0231 00F0
RSISO
Reset Isolation Register (Reset Controller)
0231 00F0 - 0231 00FF
-
Reserved
0231 0100
PLLCTL
PLL Control Register
0231 0104
-
Reserved
0231 0108
SECCTL
PLL Secondary Control Register
0231 010C
-
Reserved
0231 0110
PLLM
PLL Multiplier Control Register
0231 0114
-
Reserved
0231 0118
PLLDIV1
Reserved
0231 011C
PLLDIV2
PLL controller divider 2 register
0231 0120
PLLDIV3
Reserved
0231 0124
-
Reserved
0231 0128
POSTDIV
PLL Post-Divider Register
0231 012C - 0231 0134
-
Reserved
0231 0138
PLLCMD
PLL Controller Command Register
0231 013C
PLLSTAT
PLL Controller Status Register
0231 0140
ALNCTL
PLL Controller Clock Align Control Register
0231 0144
DCHANGE
PLLDIV Ratio Change Status Register
0231 0148
CKEN
Reserved
0231 014C
CKSTAT
Reserved
0231 0150
SYSTAT
SYSCLK Status Register
0231 0154 - 0231 015C
-
Reserved
0231 0160
PLLDIV4
Reserved
0231 0164
PLLDIV5
PLL Controller Divider 5 Register
0231 0168
PLLDIV6
Reserved
0231 016C
PLLDIV7
Reserved
0231 0170
PLLDIV8
PLL Controller Divider 8 Register
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-15
www.ti.com
PLL Controller Registers (Including Reset Controller) (Part 2 of 2)
Hex Address Range
Field
Register Name
0231 0174 - 0231 0193
PLLDIV9 - PLLDIV16
Reserved
0231 0194 - 0231 01FF
-
Reserved
End of Table 7-15
7.6.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-12 and
described in Table 7-16.
ADVANCE INFORMATION
Figure 7-12
PLL Secondary Control Register (SECCTL))
31
24
23
22
19
18
0
Reserved
BYPASS
OUTPUT_DIVIDE
Reserved
R-0000 0000
RW-0
RW-0001
RW-001 0000 0000 0000 0000
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16
PLL Secondary Control Register (SECCTL) Field Descriptions
Bit
Field
Description
31-24
Reserved
Reserved
23
BYPASS
22-19
OUTPUT_DIVIDE
Output Divider ratio bits.
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h = ÷3. Divide frequency by 3.
3h = ÷4. Divide frequency by 4.
4h - Fh = ÷5 to ÷16. Divide frequency by 5 to divide frequency by 80.
18-0
Reserved
Reserved
Main PLL Bypass Enable
0 = Main PLL Bypass disabled
1 = Main PLL Bypass enabled
End of Table 7-16
7.6.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
The PLL controller divider registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in Figure 7-13 and described
in Table 7-17. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different
and mentioned in the footnote of Figure 7-13.
Figure 7-13
PLL Controller Divider Register (PLLDIVn)
31
16
Reserved
R-0
15
Dn
(1)
14
EN
R/W-1
8
Reserved
R-0
7
0
RATIO
R/W-n
(2)
Legend: R/W = Read/Write; R = Read only; -n = value after reset
1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8
122
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PLL Controller Divider Register (PLLDIVn) Field Descriptions
Bit
Field
Description
31-16
Reserved
Reserved.
15
DnEN
Divider Dn enable bit. (see footnote of Figure 7-13)
0 = Divider n is disabled.
1 = No clock output. Divider n is enabled.
14-8
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0
RATIO
Divider ratio bits. (see footnote of Figure 7-13)
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h = ÷3. Divide frequency by 3.
3h = ÷4. Divide frequency by 4.
4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.
ADVANCE INFORMATION
Table 7-17
End of Table 7-17
7.6.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-14 and described in Table 7-18.
Figure 7-14
PLL Controller Clock Align Control Register (ALNCTL)
31
8
7
6
5
4
3
2
1
0
Reserved
ALN8
Reserved
ALN5
Reserved
ALN2
Reserved
R-0
R/W-1
R-0
R/W-1
R-0
R/W-1
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-18
Bit
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Field
Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
ALN8
4
ALN5
1
ALN2
SYSCLKn alignment. Do not change the default values of these fields.
0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new
ratio immediately after the GOSET bit in PLLCMD is set.
1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.
The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
31-8
6-5
3-2
0
End of Table 7-18
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7.6.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE
status register. During the GO operation, the PLL controller will change only the divide ratio of the SYSCLKs with
the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other
clocks. The PLLDIV divider ratio change status register is shown in Figure 7-15 and described in Table 7-19.
Figure 7-15
PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
8
7
6
5
4
3
2
1
0
Reserved
SYS8
Reserved
SYS5
Reserved
SYS2
Reserved
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
ADVANCE INFORMATION
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-19
Bit
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Field
Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
SYS8
4
SYS5
1
SYS2
Identifies when the SYSCLKn divide ratio has been modified.
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
31-8
6-5
3-2
0
End of Table 7-19
7.6.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in Figure 7-16 and
described in Table 7-20.
SYSCLK Status Register (SYSTAT)
Figure 7-16
31
11
Reserved
10
9
SYS11ON SYS10ON
R-n
R-1
R-1
8
7
6
5
4
3
2
1
0
SYS9ON
SYS8ON
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-20
SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
Description
31-11
Reserved
10-0
SYS[N ]ON
(1)
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK[N] on status.
0 = SYSCLK[N] is gated.
1 = SYSCLK[N] is on.
End of Table 7-20
1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)
124
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7.6.2.6 Reset Type Status Register (RSTYPE)
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in
Figure 7-17 and described in Table 7-21.
Figure 7-17
31
Reset Type Status Register (RSTYPE)
29
28
27
12
11
8
7
3
2
1
0
Reserved
EMU-RST
Reserved
WDRST[N]
Reserved
PLLCTRLRST
RESET
POR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Table 7-21
ADVANCE INFORMATION
Legend: R = Read only; -n = value after reset
Reset Type Status Register (RSTYPE) Field Descriptions
Bit
Field
Description
31-29
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
28
EMU-RST
Reset initiated by emulation.
0 = Not the last reset to occur.
1 = The last reset to occur.
27-12
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
11
WDRST3
10
WDRST2
9
WDRST1
Reset initiated by watchdog timer[N].
0 = Not the last reset to occur.
1 = The last reset to occur.
8
WDRST0
7-3
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
2
PLLCTLRST
Reset initiated by PLLCTL.
0 = Not the last reset to occur.
1 = The last reset to occur.
1
RESET
RESET reset.
0 = RESET was not the last reset to occur.
1 = RESET was the last reset to occur.
0
POR
Power-on reset.
0 = Power-on reset was not the last reset to occur.
1 = Power-on reset was the last reset to occur.
End of Table 7-21
7.6.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value
is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register
(RSTCTRL) is shown in Figure 7-18 and described in Table 7-22.
Figure 7-18
Reset Control Register (RSTCTRL)
31
17
Reserved
R-0x0000
16
15
SWRST
R/W-0x
(1)
0
KEY
R/W-0x0003
Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
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Table 7-22
Bit
www.ti.com
Reset Control Register (RSTCTRL) Field Descriptions
Field
Description
31-17
Reserved
Reserved.
16
SWRST
Software reset
0 = Reset
1 = Not reset
15-0
KEY
Key used to enable writes to RSTCTRL and RSTCFG.
End of Table 7-22
ADVANCE INFORMATION
7.6.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL controller’s
RSTCTRL Register; i.e., a Hard reset or a Soft reset. By default, these resets will be Hard resets. The Reset
Configuration Register (RSTCFG) is shown in Figure 7-19 and described in Table 7-23.
Figure 7-19
Reset Configuration Register (RSTCFG)
31
14
Reserved
13
12
PLLCTLRSTTYPE
R-0
R/W-0
(2)
11
RESETTYPE
R/W-0
2
4
Reserved
R-0
3
0
WDTYPE[N
(1)
]
2
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)
2 Writes are conditional based on valid key. For details, see Section 7.6.2.7 ‘‘Reset Control Register (RSTCTRL)’’.
Table 7-23
Bit
Reset Configuration Register (RSTCFG) Field Descriptions
Field
Description
31-14
Reserved
Reserved.
13
PLLCTLRSTTYPE
PLL controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12
RESETTYPE
RESET initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
11-4
Reserved
Reserved.
3
WDTYPE3
2
WDTYPE2
1
WDTYPE1
Watchdog Timer [N] initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
0
WDTYPE0
End of Table 7-23
126
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.6.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non
power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current
values of PLL multiplier, divide ratios and other settings. The Reset Isolation Register (RSTCTRL) is shown in
Figure 7-20 and described in Table 7-24.
Reset Isolation Register (RSISO)
31
10
9
8
7
0
Reserved
SRIOISO
SRISO
Reserved
R-0
R/W-0
R/W-0
R-0
ADVANCE INFORMATION
Figure 7-20
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 7-24
Reset Isolation Register (RSISO) Field Descriptions
Bit
Field
Description
31-10
Reserved
Reserved.
9
SRIOISO
Isolate SRIO module
0 = Not reset isolated
1 = Reset Isolated
8
SRISO
Isolate SmartReflex
0 = Not reset isolated
1 = Reset Isolated
7-0
Reserved
Reserved.
End of Table 7-24
Note—The boot ROM code will enable the reset isolation for both SRIO and SmartReflex modules during
boot with the Reset Isolation Register. It is up to the user application to disable.
7.6.3 Main PLL Control Register
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL controller
for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go
through an un-locking sequence using KICK0/KICK1 registers. For valid configurable values into the
MAINPLLCTL0 and MAINPLLCTL1 registers see Section 2.5.3 ‘‘PLL Boot Configuration Settings’’ on page 31. See
section 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 70 for the address location of the registers
and locking and unlocking sequences for accessing the registers. The registers are reset on POR only.
Figure 7-21
Main PLL Control Register 0 (MAINPLLCTL0)
31
24
23
19
18
12
11
6
5
0
BWADJ[7:0]
Reserved
PLLM[12:6]
Reserved
PLLD
RW-0000 0101
RW-0000 0
RW-0000000
RW-000000
RW-000000
Legend: RW = Read/Write; -n = value after reset
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-25
www.ti.com
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
Bit
Field
Description
31-24
BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
23-19
Reserved
Reserved
18-12
PLLM[12:6]
A 13-bit bus that selects the values for the multiplication factor (see Note below)
11-6
Reserved
Reserved
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-25
ADVANCE INFORMATION
Figure 7-22
Main PLL Control Register 1 (MAINPLLCTL1)
31
7
6
5
4
3
0
Reserved
ENSAT
Reserved
BWADJ[11:8]
RW-0000000000000000000000000
RW-0
RW-00
RW-0000
Legend: RW = Read/Write; -n = value after reset
Table 7-26
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
Bit
Field
Description
31-7
Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper operation of PLL
5-4
Reserved
Reserved
3-0
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
End of Table 7-26
Note—PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL controller
and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The MAINPLLCTL0 register
PLLM[12:6] bits should be written just before writing to the PLLM register PLLM[5:0] bits in the controller
to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2) for the
recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Main PLL is
controlled by the SECCTL register in the PLL Controller. See the 7.6.2.1 ‘‘PLL Secondary Control Register
(SECCTL)’’ for more details.
7.6.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
Table 7-27
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 1 of 3)
(see Figure 7-23 and Figure 7-24)
No.
Min
Max
Unit
10
25
ns
CORECLK[P:N]
1
tc(CORCLKN)
Cycle Time _ CORECLKN cycle time
1
tc(CORECLKP)
Cycle Time _ CORECLKP cycle time
10
25
ns
3
tw(CORECLKN)
Pulse Width _ CORECLKN high
0.45*tc(CORECLKN)
0.55*tc(CORECLKN)
ns
2
tw(CORECLKN)
Pulse Width _ CORECLKN low
0.45*tc(CORECLKN)
0.55*tc(CORECLKN)
ns
2
tw(CORECLKP)
Pulse Width _ CORECLKP high
0.45*tc(CORECLKP)
0.55*tc(CORECLKP)
ns
3
tw(CORECLKP)
Pulse Width _ CORECLKP low
0.45*tc(CORECLKP)
0.55*tc(CORECLKP)
ns
128
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SPRS782A—August 2011
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Table 7-27
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 2 of 3)
(see Figure 7-23 and Figure 7-24)
No.
Min
Max
Unit
4
tr(CORECLKN_250mv)
Transition Time _ CORECLKN Rise time (250mV)
50
350
ps
4
tf(CORECLKN_250mv)
Transition Time _ CORECLKN Fall time (250mV)
50
350
ps
4
tr(CORECLKP_250mv)
Transition Time _ CORECLKP Rise time (250mV)
50
350
ps
4
tf(CORECLKP_250mv)
Transition Time _ CORECLKP Fall time (250mV)
50
350
ps
5
tj(CORECLKN)
Jitter, Peak_to_Peak _ Periodic CORECLKN
100
ps
5
tj(CORECLKP)
Jitter, Peak_to_Peak _ Periodic CORECLKP
100
ps
1
tc(SRIOSMGMIICLKN)
Cycle Time _ SRIOSMGMIICLKN cycle time
3.2
6.4
ns
1
tc(SRIOSMGMIICLKP)
Cycle Time _ SRIOSMGMIICLKP cycle time
3.2
6.4
ns
3
tw(SRIOSMGMIICLKN)
Pulse Width _ SRIOSMGMIICLKN high
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKN)
Pulse Width _ SRIOSMGMIICLKN low
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKP)
Pulse Width _ SRIOSMGMIICLKP high
0.45*tc(SRIOSGMIICLKP)
0.55*tc(SRIOSGMIICLKP)
ns
3
tw(SRIOSMGMIICLKP)
Pulse Width _ SRIOSMGMIICLKP low
0.45*tc(SRIOSGMIICLKP)
0.55*tc(SRIOSGMIICLKP)
ns
4
tr(SRIOSMGMIICLKN_25 Transition Time _ SRIOSMGMIICLKN Rise time (250mV)
0mv)
50
350
ps
4
tf(SRIOSMGMIICLKN_25 Transition Time _ SRIOSMGMIICLKN Fall time (250mV)
0mv)
50
350
ps
4
tr(SRIOSMGMIICLKP_25 Transition Time _ SRIOSMGMIICLKP Rise time (250mV)
0mv)
50
350
ps
4
tf(SRIOSMGMIICLKP_25 Transition Time _ SRIOSMGMIICLKP Fall time (250mV)
0mv)
50
350
ps
5
tj(SRIOSMGMIICLKN)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN
4 ps,RMS
5
tj(SRIOSMGMIICLKP)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP
4 ps,RMS
5
tj(SRIOSMGMIICLKN)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN (SRIO
Not Used)
8 ps,RMS
5
tj(SRIOSMGMIICLKP)
Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP (SRIO
Not Used)
8 ps,RMS
1
tc(MCMCLKN)
Cycle Time _ MCMCLKN cycle time
MCMCLK[P:N]
3.2
6.4
ns
1
tc(MCMCLKP)
Cycle Time _ MCMCLKP cycle time
3.2
6.4
ns
3
tw(MCMCLKN)
Pulse Width _ MCMCLKN high
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
2
tw(MCMCLKN)
Pulse Width _ MCMCLKN low
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
2
tw(MCMCLKP)
Pulse Width _ MCMCLKP high
0.45*tc(MCMCLKP)
0.55*tc(MCMCLKP)
ns
3
tw(MCMCLKP)
Pulse Width _ MCMCLKP low
0.45*tc(MCMCLKP)
0.55*tc(MCMCLKP)
ns
4
tr(MCMCLKN_250mv)
Transition Time _ MCMCLKN Rise time (250mV)
50
350
ps
4
tf(MCMCLKN_250mv)
Transition Time _ MCMCLKN Fall time (250mV)
50
350
ps
4
tr(MCMCLKP_250mv)
Transition Time _ MCMCLKP Rise time (250mV)
50
350
ps
4
tf(MCMCLKP_250mv)
Transition Time _ MCMCLKP Fall time (250mV)
50
350
ps
5
tj(MCMCLKN)
Jitter, Peak_to_Peak _ Periodic MCMCLKN
4 ps,RMS
5
tj(MCMCLKP)
Jitter, Peak_to_Peak _ Periodic MCMCLKP
4 ps,RMS
PCIECLK[P:N]
1
tc(PCIECLKN)
Cycle Time _ PCIECLKN cycle time
3.2
10
ns
1
tc(PCIECLKP)
Cycle Time _ PCIECLKP cycle time
3.2
10
ns
3
tw(PCIECLKN)
Pulse Width _ PCIECLKN high
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKN)
Pulse Width _ PCIECLKN low
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
Copyright 2011 Texas Instruments Incorporated
129
ADVANCE INFORMATION
SRIOSGMIICLK[P:N]
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-27
www.ti.com
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 3 of 3)
(see Figure 7-23 and Figure 7-24)
No.
Min
Max
Unit
ADVANCE INFORMATION
2
tw(PCIECLKP)
Pulse Width _ PCIECLKP high
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
3
tw(PCIECLKP)
Pulse Width _ PCIECLKP low
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
4
tr(PCIECLKN_250mv)
Transition Time _ PCIECLKN Rise time (250mV)
50
350
ps
4
tf(PCIECLKN_250mv)
Transition Time _ PCIECLKN Fall time (250mV)
50
350
ps
4
tr(PCIECLKP_250mv)
Transition Time _ PCIECLKP Rise time (250mV)
50
350
ps
4
tf(PCIECLKP_250mv)
Transition Time _ PCIECLKP Fall time (250mV)
50
350
ps
5
tj(PCIECLKN)
Jitter, Peak_to_Peak _ Periodic PCIECLKN
4 ps,RMS
5
tj(PCIECLKP)
Jitter, Peak_to_Peak _ Periodic PCIECLKP
4 ps,RMS
End of Table 7-27
Figure 7-23
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing
1
2
3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
Figure 7-24
5
PLL Transition Time
peak-to-peak differential input
voltage (250 mV to 2 V)
0
250 mV peak-to-peak
TR = 50 ps min to 350 ps max (10% to 90 %)
for the 250 mV peak-to-peak centered at zero crossing
7.7 DD3 PLL
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.
DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices (literature number
SPRABI2). For the best performance, TI recommends that all the PLL external components be on a single side of the
board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the
spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).
130
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Figure 7-25 shows the DDR3 PLL.
Figure 7-25
DDR3 PLL Block Diagram
DDR3 PLL
xPLLM
PLLD
/2
0
DDRCLK(N|P)
PLLOUT
DDR3
PHY
1
7.7.1 DDR3 PLL Control Register
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can
be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs
exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence using
KICK0/KICK1 registers. For suggested configurable values see section 3.3.4 ‘‘Kicker Mechanism (KICK0 and
KICK1) Register’’ on page 70 for the address location of the registers and locking and unlocking sequences for
accessing the registers. This register is reset on POR only
.
DDR3 PLL Control Register 0 (DDR3PLLCTL0) (1)
Figure 7-26
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
BYPASS
Reserved
PLLM
PLLD
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
RW,+000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
Table 7-28
DDR3 PLL Control Register 0 Field Descriptions
Bit
Field
Description
31-24
BWADJ[7:0]
BWADJ should be programmed to a value equal to half of PLLM[12:0] Ex PLLM=15 then BWADJ=7
23
BYPASS
Enable Bypass Mode
0 = Bypass Disabled
1 = Bypass Enabled
22-19
Reserved
Reserved
18-6
PLLM
A 13-bit bus that selects the values for the multiplication factor
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-28
Figure 7-27
DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31
7
6
5
4
3
0
Reserved
ENSAT
Reserved
BWADJ[11:8]
RW-0000000000000000000000000
RW-0
R-0
RW-0000
Legend: RW = Read/Write; -n = value after reset
Copyright 2011 Texas Instruments Incorporated
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BYPASS
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-29
www.ti.com
DDR3 PLL Control Register 1 Field Descriptions
Bit
Field
Description
31-7
Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper operation of PLL
5-4
Reserved
Reserved
3-0
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
End of Table 7-29
ADVANCE INFORMATION
7.7.2 DDR3 PLL Device-Specific Information
As shown in Figure 7-25, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory
controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3
PLL are affected as described in Section 7.5 ‘‘Reset Controller’’ on page 113. DDR3 PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
7.7.3 DDR3 PLL Input Clock Electrical Data/Timing
Table 7-30
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
(see Figure 7-28 and Figure 7-24)
Min
No.
Max
Unit
DDRCLK[P:N]
1
tc(DDRCLKN)
Cycle Time _ DDRCLKN cycle time
3.2
25
ns
1
tc(DDRCLKP)
Cycle Time _ DDRCLKP cycle time
3.2
25
ns
3
tw(DDRCLKN)
Pulse Width _ DDRCLKN high
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
ns
2
tw(DDRCLKN)
Pulse Width _ DDRCLKN low
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
ns
2
tw(DDRCLKP)
Pulse Width _ DDRCLKP high
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKP)
ns
3
tw(DDRCLKP)
Pulse Width _ DDRCLKP low
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKP)
ns
4
tr(DDRCLKN_250mv) Transition Time _ DDRCLKN Rise time (250mV)
50
350
ps
4
tf(DDRCLKN_250mv)
50
350
ps
4
tr(DDRCLKP_250mv)
Transition Time _ DDRCLKP Rise time (250mV)
50
350
ps
4
tf(DDRCLKP_250mv)
Transition Time _ DDRCLKP Fall time (250mV)
50
350
ps
5
tj(DDRCLKN)
Jitter, Peak_to_Peak _ Periodic DDRCLKN
0.025*tc(DDRCLKN)
ps
5
tj(DDRCLKP)
Jitter, Peak_to_Peak _ Periodic DDRCLKP
0.025*tc(DDRCLKN)
ps
Transition Time _ DDRCLKN Fall time (250mV)
End of Table 7-30
Figure 7-28
DDR3 PLL DDRCLK Timing
1
2
3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
132
5
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
7.8 PASS PLL
PASS PLL power is supplied externally via the Main PLL power-supply pin (AVDDA3). An external EMI filter
circuit must be added to all PLL supplies. Please see the Hardware Design Guide for KeyStone Devices (literature
number SPRABI2). for detailed recommendations. For the best performance, TI recommends that all the PLL
external components be on a single side of the board without jumpers, switches, or components other than those
shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external
components (C1, C2, and the EMI Filter).
Figure 7-29 shows the DDR3 PLL.
Figure 7-29
PASS PLL Block Diagram
PASS PLL
xPLLM
PLLD
//2
CORECLK(P|N)
/3
0
PASSCLK(P|N)
Network
Coprocessor
PLLOUT
PACLKSEL
1
BYPASS
7.8.1 PASS PLL Control Register
The PASS PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. PASS PLL can be
controlled using the PASSPLLCTL0 and PASSPLLCTL1 registers located in Bootcfg module. These MMRs exist
inside the Bootcfg space. To write to this register, software should go through an un-locking sequence using
KICK0/KICK1 registers. For suggested configurable values see PLL Section. See section 3.3.4 ‘‘Kicker Mechanism
(KICK0 and KICK1) Register’’ on page 70 for the address location of the registers and locking and unlocking
sequences for accessing the registers. This register is reset on POR only.
.
PASS PLL Control Register 0 (PASSPLLCTL0) (1)
Figure 7-30
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
BYPASS
Reserved
PLLM
PLLD
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
RW,+000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
Table 7-31
PASS PLL Control Register 0 Field Descriptions (Part 1 of 2)
Bit
Field
Description
31-24
BWADJ[7:0]
BWADJ should be programmed to a value equal to half of PLLM[12:0] Ex PLLM=15 then BWADJ=7
23
BYPASS
Enable Bypass Mode
0 = Bypass Disabled
1 = Bypass Enabled
22-19
Reserved
Reserved
Copyright 2011 Texas Instruments Incorporated
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The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select
the input source of PASS PLL as either the output of Main PLL mux or the PASSCLK clock reference sources. When
coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be programmed to a valid
frequency before being enabled and used.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-31
www.ti.com
PASS PLL Control Register 0 Field Descriptions (Part 2 of 2)
Bit
Field
Description
18-6
PLLM
A 13-bit bus that selects the values for the multiplication factor
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-31
Figure 7-31
PASS PLL Control Register 1 (PASSPLLCTL1)
31
7
6
5
4
3
0
ADVANCE INFORMATION
Reserved
ENSAT
Reserved
BWADJ[11:8]
RW-0000000000000000000000000
RW-0
R-0
RW-0000
Legend: RW = Read/Write; -n = value after reset
Table 7-32
PASS PLL Control Register 1 Field Descriptions
Bit
Field
Description
31-7
Reserved
Reserved
6
ENSAT
Must be set to 1 for proper operation of the PLL
5-4
Reserved
Reserved
3-0
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
End of Table 7-32
7.8.2 PASS PLL Device-Specific Information
As shown in Figure 7-29, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Network
Coprocessor. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS
PLL are affected as described in Section 7.5 ‘‘Reset Controller’’ on page 113. PASS PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
Table 7-33
PASS PLL Timing Requirements
(See Figure 7-32 and Figure 7-24)
No.
Parameter
Min
Max
Unit
PASSCLK[P:N]
1
tc(PASSCLKN)
Cycle Time _ PASSCLKN cycle time
3.2
6.4
ns
1
tc(PASSCLKP)
Cycle Time _ PASSCLKP cycle time
3.2
6.4
ns
3
tw(PASSCLKN)
Pulse Width _ PASSCLKN high
0.45*tc(PASSCLKN)
0.55*tc(PASSCLKN)
ns
2
tw(PASSCLKN)
Pulse Width _ PASSCLKN low
0.45*tc(PASSCLKN)
0.55*tc(PASSCLKN)
ns
2
tw(PASSCLKP)
Pulse Width _ PASSCLKP high
0.45*tc(PASSCLKP)
0.55*tc(PASSCLKP)
ns
3
tw(PASSCLKP)
Pulse Width _ PASSCLKP low
0.45*tc(PASSCLKP)
0.55*tc(PASSCLKP)
ns
4
tr(PASSCLKN_250mv) Transition Time _ PASSCLKN Rise time (250mV)
50
350
ps
4
tf(PASSCLKN_250mv)
Transition Time _ PASSCLKN Fall time (250mV)
50
350
ps
4
tr(PASSCLKP_250mv)
Transition Time _ PASSCLKP Rise time (250mV)
50
350
ps
4
tf(PASSCLKP_250mv)
Transition Time _ PASSCLKP Fall time (250mV)
50
350
ps
5
tj(PASSCLKN)
Jitter, Peak_to_Peak _ Periodic PASSCLKN
100
ps, pk-pk
5
tj(PASSCLKP)
Jitter, Peak_to_Peak _ Periodic PASSCLKP
100
ps, pk-pk
134
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Figure 7-32
PASS PLL Timing
1
2
3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
5
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA Channel Controllers on the TCI6602 DSP, TPCC0, TPCC1, and TPCC2. TPCC0 is optimized to
be used for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are to be used for the remaining
traffic.
Each EDMA3 Channel Controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
› Array (multiple bytes)
› Frame (multiple arrays)
› Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 128 PaRAM entries for TPCC0, 512 each for TPCC1 and TPCC2
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA 3 Channel Controller
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• 2 transfer controllers and 2 event queues with programmable system-level priority for TPCC0, 4 transfer
controllers and 4 event queues with programmable system-level priority per channel controller for TPCC1 and
TPCC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
Copyright 2011 Texas Instruments Incorporated
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7.9 Enhanced Direct Memory Access (EDMA3) Controller
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
In the context of this document, TPTCs associated with TPCC0 are referred to as TPCC0 TPTC0 and1. TPTCs
associated with TPCC1 and 2 are each referred to as TPCCx TPTC0 - 3, where x is 1 or 2. Each of the transfer
controllers has a direct connection to the switched central resource (SCR). Table 4-1 ‘‘CPU/2 Data SCR Connection
Matrix’’ on page 83 and Table 4-2 ‘‘DSP/3 Data SCR Connection Matrix’’ on page 83 lists the peripherals that can be
accessed by the transfer controllers.
7.9.1 EDMA3 Device-Specific Information
ADVANCE INFORMATION
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode must be used.
On the TCI6602 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder
Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not
supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all
peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct
Memory Access 3 (EDMA3) for KeyStone Devices User Guide (literature number SPRUGS5).
For the range of memory addresses that include EDMA3 Channel Controller (TPCC) Control Registers and
EDMA3 Transfer Controller (TPTC) Control Register see Section Table 2-2‘‘Memory Map Summary for
TMS320TCI6602’’ on page 19. For memory offsets and other details on TPCC and TPTC Control Registers entries,
see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide (literature number SPRUGS5)
for offset addresses on Parameter RAM (PaRAM) registers.
7.9.2 EDMA3 Channel Controller Configuration
Table 7-34 provides the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-34
EDMA3 Channel Controller Configuration
Description
EDMA3 CC0
EDMA3 CC1
EDMA3 CC2
Number of DMA channels in Channel Controller
16
64
64
Number of QDMA channels
8
8
8
Number of interrupt channels
16
64
64
Number of PaRAM set entries
128
512
512
Number of event queues
2
4
4
Number of Transfer Controllers
2
4
4
Memory Protection Existence
Yes
Yes
Yes
Number of Memory Protection and Shadow Regions
8
8
8
End of Table 7-34
7.9.3 EDMA3 Transfer Controller Configuration
Each transfer controller on a device is designed differently based on considerations like performance requirements,
system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the
transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the Data FIFO that is the temporary buffer for the in-flight data.
The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored
and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a
transfer controller.
• DSTREGDEPTH: This determines the number of Destination FIFO register set. The number of Destination
FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.
136
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TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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All four parameters listed above are fixed by the design of the device.
Table 7-35‘‘EDMA3 Transfer Controller Configuration’’ provides the configuration for each of the EDMA3 transfer
controllers present on the device.
EDMA3 Transfer Controller Configuration
Parameter
EDMA3 CC0
EDMA3 CC1
EDMA3 CC2
TC0
TC1
TC0
TC1
TC2
TC3
TC0
TC1
TC2
TC3
FIFOSIZE
1024 bytes
1024 bytes
1024 bytes
512 bytes
1024 bytes
512 bytes
1024 bytes
512 bytes
512 bytes
1024 bytes
BUSWIDTH
32 bytes
32 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
DSTREGDEPTH
4 entries
4 entries
4 entries
4 entries
4 entries
4 entries
4 entries
4 entries
4 entries
4 entries
DBS
128 bytes
128 bytes
128 bytes
64 bytes
128 bytes
64 bytes
128 bytes
64 bytes
64 bytes
128 bytes
End of Table 7-35
7.9.4 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2 that can be used to
service system peripherals and to move data between system memories. DMA channels can be triggered by
synchronization events generated by system peripherals. The following tables lists the source of the synchronization
event associated with each of the EDMA TPCC DMA channels. On the TCI6602, the association of each
synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed,
prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone
Devices User Guide (literature number SPRUGS5).
Table 7-36
TPCC0 Events for TCI6602
Event Number
Event
Event Description
0-7
Reserved
8
INTC3_OUT0
Interrupt controller output
9
INTC3_OUT1
Interrupt controller output
10
INTC3_OUT2
Interrupt controller output
11
INTC3_OUT3
Interrupt controller output
12
INTC3_OUT4
Interrupt controller output
13
INTC3_OUT5
Interrupt controller output
14
INTC3_OUT6
Interrupt controller output
15
INTC3_OUT7
Interrupt controller output
End of Table 7-36
Table 7-37
TPCC1 Events for TCI6602 (Part 1 of 2)
Event Number
Event
Event Description
0
SPIINT0
SPI interrupt
1
SPIINT1
SPI interrupt
2
SPIXEVT
Transmit event
3
SPIREVT
Receive event
4
I2CREVT
I2C receive event
5
I2CXEVT
I2C transmit event
6
GPINT0
GPIO interrupt
7
GPINT1
GPIO interrupt
Copyright 2011 Texas Instruments Incorporated
137
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Table 7-35
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-37
www.ti.com
TPCC1 Events for TCI6602 (Part 2 of 2)
ADVANCE INFORMATION
Event Number
Event
Event Description
8
GPINT2
GPIO interrupt
9
GPINT3
GPIO interrupt
10
GPINT4
GPIO interrupt
11
GPINT5
GPIO interrupt
12
GPINT6
GPIO interrupt
13
GPINT7
GPIO interrupt
14
SEMINT0
Semaphore interrupt
15
SEMINT1
Semaphore interrupt
16
SEMINT2
Semaphore interrupt
17
SEMINT3
Semaphore interrupt
18
SEMINT4
Semaphore interrupt
19
SEMINT5
Semaphore interrupt
20
SEMINT6
Semaphore interrupt
21
SEMINT7
Semaphore interrupt
22 - 37
Reserved
38
INTC2_OUT44
Interrupt controller output
39
INTC2_OUT45
Interrupt controller output
40
INTC2_OUT46
Interrupt controller output
41
INTC2_OUT47
Interrupt controller output
42
INTC2_OUT0
Interrupt controller output
43
INTC2_OUT1
Interrupt controller output
44
INTC2_OUT2
Interrupt controller output
45
INTC2_OUT3
Interrupt controller output
46
INTC2_OUT4
Interrupt controller output
47
INTC2_OUT5
Interrupt controller output
48
INTC2_OUT6
Interrupt controller output
49
INTC2_OUT7
Interrupt controller output
50
INTC2_OUT8
Interrupt controller output
51
INTC2_OUT9
Interrupt controller output
52
INTC2_OUT10
Interrupt controller output
53
INTC2_OUT11
Interrupt controller output
54
INTC2_OUT12
Interrupt controller output
55
INTC2_OUT13
Interrupt controller output
56
INTC2_OUT14
Interrupt controller output
57
INTC2_OUT15
Interrupt controller output
58
INTC2_OUT16
Interrupt controller output
59
INTC2_OUT17
Interrupt controller output
60
INTC2_OUT18
Interrupt controller output
61
INTC2_OUT19
Interrupt controller output
62
INTC2_OUT20
Interrupt controller output
63
INTC2_OUT21
Interrupt controller output
End of Table 7-37
138
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
TPCC2 Events for TCI6602 (Part 1 of 2)
Event Number
Event
Event Description
0
SPIINT0
SPI interrupt
1
SPIINT1
SPI interrupt
2
SPIXEVT
Transmit event
3
SPIREVT
Receive event
4
I2CREVT
I2C receive event
5
I2CXEVT
I2C transmit event
6
GPINT0
GPIO interrupt
7
GPINT1
GPIO interrupt
8
GPINT2
GPIO Interrupt
9
GPINT3
GPIO interrupt
10
GPINT4
GPIO interrupt
11
GPINT5
GPIO interrupt
12
GPINT6
GPIO interrupt
13
GPINT7
GPIO interrupt
14
SEMINT0
Semaphore interrupt
15
SEMINT1
Semaphore interrupt
16
SEMINT2
Semaphore interrupt
17
SEMINT3
Semaphore interrupt
18
SEMINT4
Semaphore interrupt
19
SEMINT5
Semaphore interrupt
20
SEMINT6
Semaphore interrupt
21
SEMINT7
Semaphore interrupt
22 - 37
Reserved
38
INTC2_OUT48
Interrupt controller output
39
INTC2_OUT49
Interrupt controller output
40
URXEVT
UART receive event
41
UTXEVT
UART transmit event
42
INTC2_OUT22
Interrupt controller output
43
INTC2_OUT23
Interrupt controller output
44
INTC2_OUT24
Interrupt controller output
45
INTC2_OUT25
Interrupt controller output
46
INTC2_OUT26
Interrupt controller output
47
INTC2_OUT27
Interrupt controller output
48
INTC2_OUT28
Interrupt controller output
49
INTC2_OUT29
Interrupt controller output
50
INTC2_OUT30
Interrupt controller output
51
INTC2_OUT31
Interrupt controller output
52
INTC2_OUT32
Interrupt controller output
53
INTC2_OUT33
Interrupt controller output
54
INTC2_OUT34
Interrupt controller output
55
INTC2_OUT35
Interrupt controller output
56
INTC2_OUT36
Interrupt controller output
57
INTC2_OUT37
Interrupt controller output
58
INTC2_OUT38
Interrupt controller output
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 7-38
139
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-38
www.ti.com
TPCC2 Events for TCI6602 (Part 2 of 2)
Event Number
Event
Event Description
59
INTC2_OUT39
Interrupt controller output
60
INTC2_OUT40
Interrupt controller output
61
INTC2_OUT41
Interrupt controller output
62
INTC2_OUT42
Interrupt controller output
63
INTC2_OUT43
Interrupt controller output
End of Table 7-38
ADVANCE INFORMATION
7.10 Interrupts
7.10.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the TCI6602 device are configured through the C66x CorePac Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through INTC blocks, INTC[2:0], with one controller per C66x CorePac.
This is clocked using CPU/6.
There are a large amount of events on the chip level. The chip level INTC provides a flexible way to combine and
remap those events. Multiple events can be combined to a single event through chip level INTC. However, an event
can only be mapped to a single event output from the chip level INTC. The chip level INTC also allows the software
to trigger system event through memory writes. The broadcast events to C66x CorePacs can be used for
synchronization among multiple cores or inter-processor communication purpose and etc. For more details on the
INTC features, please refer to the Interrupt Controller (INTC) for KeyStone Devices User Guide (literature number
SPRUGW4).
Note—Modules such as CP_MPU, CP_Tracer, and BOOT_CFG have level interrupts and EOI handshaking
interface. The EOI value is 0 for CP_MPU, CP_Tracer, and BOOT_CFG.
140
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Figure 7-33 shows the TCI6602 interrupt topology.
Figure 7-33
TMS320TCI6602 Interrupt Topology
8 Broadcast Events from INTC0
5 Reserved Secondary Events
71 Primary Events
Core0
INTC0
91 Core-only Secondary Events
17 Secondary Events
71 Primary Events
Core1
64 Common Events
ADVANCE INFORMATION
17 Secondary Events
2 Reserved Secondary Events
64 Common Events
38 Primary Events
INTC2
8 Reserved Secondary Events
26 Secondary Events
40 Primary Events
88 TPCC-only Events
24 Secondary Events
32 Queue Events
17 Reserved Secondary Events
32 Secondary Events
CPU/3
TPCC1
CPU/3
TPCC2
Hyper
Link
INTC3
8 Primary Events
63 Events
8 Secondary Events
CPU/2
TPCC0
Table 7-39 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
CorePac User Guide (literature number SPRUGW0).
Table 7-39
TMS320TCI6602 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
Event Number
Interrupt Event
Description
0
EVT0
Event combiner 0 output
1
EVT1
Event combiner 1 output
2
EVT2
Event combiner 2 output
3
EVT3
Event combiner 3 output
4
TETBHFULLINTn
5
TETBFULLINTn
(1)
TETB is half full
(1)
TETB is full
(1)
6
TETBACQINTn
7
TETBOVFLINTn (1)
8
TETBUNFLINTn
(1)
9
EMU_DTDMA
10
MSMC_mpf_errorn
11
EMU_RTDXRX
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
(2)
Copyright 2011 Texas Instruments Incorporated
Memory protection fault indicators for local core
RTDX receive complete
141
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-39
www.ti.com
TMS320TCI6602 System Event Mapping — C66x CorePac Primary Interrupts (Part 2 of 4)
Event Number
Interrupt Event
Description
12
EMU_RTDXTX
RTDX transmit complete
13
IDMA0
IDMA channel 0 interrupt
14
IDMA1
IDMA channel 1 interrupt
15
SEMERRn
16
SEMINTn
(3)
Semaphore error interrupt
(3)
Semaphore interrupt
(4)
Message signaled interrupt mode
ADVANCE INFORMATION
17
PCIExpress_MSI_INTn
18
TSIP0_ERRINT[n]
(5)
TSIP0 receive/transmit error interrupt
19
TSIP1_ERRINT[n]
(5)
TSIP1 receive/transmit error interrupt
20
INTDST(n+16) (6)
SRIO Interrupt
21
INTC0_OUT(32+0+11*n)
Interrupt Controller Output
22
INTC0_OUT(32+1+11*n)
Interrupt Controller Output
23
INTC0_OUT(32+2+11*n)
Interrupt Controller Output
24
INTC0_OUT(32+3+11*n)
Interrupt Controller Output
25
INTC0_OUT(32+4+11*n)
Interrupt Controller Output
26
INTC0_OUT(32+5+11*n)
Interrupt Controller Output
27
INTC0_OUT(32+6+11*n)
Interrupt Controller Output
28
INTC0_OUT(32+7+11*n)
Interrupt Controller Output
29
INTC0_OUT(32+8+11*n)
Interrupt Controller Output
30
INTC0_OUT(32+9+11*n)
Interrupt Controller Output
31
INTC0_OUT(32+10+11*n)
Interrupt Controller Output
32
QM_INT_LOW_0
QM Interrupt for 0~31 Queues
33
QM_INT_LOW_1
QM Interrupt for 32~63 Queues
34
QM_INT_LOW_2
QM Interrupt for 64~95 Queues
35
QM_INT_LOW_3
QM Interrupt for 96~127 Queues
36
QM_INT_LOW_4
QM Interrupt for 128~159 Queues
37
QM_INT_LOW_5
QM Interrupt for 160~191 Queues
38
QM_INT_LOW_6
QM Interrupt for 192~223 Queues
39
QM_INT_LOW_7
QM Interrupt for 224~255 Queues
40
QM_INT_LOW_8
QM Interrupt for 256~287 Queues
41
QM_INT_LOW_9
QM Interrupt for 288~319 Queues
42
QM_INT_LOW_10
QM Interrupt for 320~351 Queues
43
QM_INT_LOW_11
QM Interrupt for 352~383 Queues
44
QM_INT_LOW_12
QM Interrupt for 384~415 Queues
45
QM_INT_LOW_13
QM Interrupt for 416~447 Queues
46
QM_INT_LOW_14
QM Interrupt for 448~479 Queues
47
QM_INT_LOW_15
QM Interrupt for 480~511 Queues
48
QM_INT_HIGH_n
49
QM_INT_HIGH_(n+8) (7)
(7)
QM Interrupt for Queue 704+n
50
QM_INT_HIGH_(n+16)
(7)
51
QM_INT_HIGH_(n+24)
(7)
8
QM Interrupt for Queue 712+n8
QM Interrupt for Queue 720+n
8
QM Interrupt for Queue 728+n
8
TSIP0_RFSINT[n]
(5)
TSIP0 receive frame sync interrupt
53
TSIP0_RSFINT[n]
(5)
TSIP0 receive super frame interrupt
54
TSIP0_XFSINT[n]
(5)
TSIP0 transmit frame sync interrupt
TSIP0_XSFINT[n]
(5)
TSIP0 transmit super frame interrupt
52
55
142
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
TMS320TCI6602 System Event Mapping — C66x CorePac Primary Interrupts (Part 3 of 4)
Event Number
Interrupt Event
56
TSIP1_RFSINT[n]
(5)
Description
TSIP1 receive frame sync interrupt
57
TSIP1_RSFINT[n]
(5)
TSIP1 receive super frame interrupt
58
TSIP1_XFSINT[n] (5)
TSIP1 transmit frame sync interrupt
(5)
59
TSIP1_XSFINT[n]
60
Reserved
61
Reserved
62
INTC0_OUT(2+8*n)
TSIP1 transmit super frame interrupt
Interrupt Controller Output
63
INTC0_OUT(3+8*n)
Interrupt Controller Output
64
TINTLn (8)
Local timer interrupt low
65
TINTHn
66 - 81
Reserved
82
GPINT8
Local GPIO interrupt
83
GPINT9
Local GPIO interrupt
84
GPINT10
Local GPIO interrupt
85
GPINT11
Local GPIO interrupt
86
GPINT12
Local GPIO interrupt
87
GPINT13
Local GPIO interrupt
88
GPINT14
Local GPIO interrupt
89
GPINT15
Local GPIO interrupt
(8)
(9)
Local timer interrupt high
Local GPIO interrupt
90
GPINTn
91
IPC_LOCAL
Inter DSP interrupt from IPCGRn
92
INTC0_OUT(4+8*n)
Interrupt Controller Output
93
INTC0_OUT(5+8*n)
Interrupt Controller Output
94
INTC0_OUT(6+8*n)
Interrupt Controller Output
95
INTC0_OUT(7+8*n)
Interrupt Controller Output
96
INTERR
Dropped CPU interrupt event
97
EMC_IDMAERR
Invalid IDMA parameters
98
Reserved
99
Reserved
100
EFIINTA
EFI Interrupt from side A
101
EFIINTB
EFI Interrupt from side B
102
INTC0_OUT0
Interrupt Controller Output
103
INTC0_OUT1
Interrupt Controller Output
104
INTC0_OUT8
Interrupt Controller Output
105
INTC0_OUT9
Interrupt Controller Output
106
INTC0_OUT16
Interrupt Controller Output
107
INTC0_OUT17
Interrupt Controller Output
108
INTC0_OUT24
Interrupt Controller Output
109
INTC0_OUT25
Interrupt Controller Output
110
MDMAERREVT
VbusM error event
111
Reserved
112
TPCC0_EDMACC_AETEVT
TPCC0 AET event
113
PMC_ED
Single bit error detected during DMA read
114
TPCC1_EDMACC_AETEVT
TPCC1 AET Event
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 7-39
143
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-39
www.ti.com
TMS320TCI6602 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)
Event Number
Interrupt Event
Description
115
TPCC2_EDMACC_AETEVT
TPCC2 AET Event
ADVANCE INFORMATION
116
UMC_ED1
Corrected bit error detected
117
UMC_ED2
Uncorrected bit error detected
118
PDC_INT
Power down sleep interrupt
119
SYS_CMPA
SYS DSP memory protection fault event
120
PMC_CMPA
PMC DSP core protection fault event
121
PMC_DMPA
PMC memory protection fault event
122
DMC_CMPA
DMC DSP core protection fault event
123
DMC_DMPA
DMC memory protection fault event
124
UMC_CMPA
UMC DSP core protection fault event
125
UMC_DMPA
UMC memory protection fault event
126
EMC_CMPA
EMC DSP core protection fault event
127
EMC_BUSERR
EMC
End of Table 7-39
1
2
3
4
5
6
7
8
9
Core[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn
Core[n] will receive MSMC_mpf_errorn.
Core[n] will receive SEMINTn and SEMERRn.
Core[n] will receive PCIEXpress_MSI_INTn.
Core[n] will receive TSIPx_xxx[n]
Core[n] will receive INTDST(n+16)
n is core number.
Core[n] will receive TINTLn and TINTHn.
Core[n] will receive GPINTn.
Table 7-40
INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 1 of 5)
Input Event# on INTC
System Interrupt
Description
0
TPCC1 EDMACC_ERRINT
TPCC1 error interrupt
1
TPCC1 EDMACC_MPINT
TPCC1 memory protection interrupt
2
TPCC1 EDMATC_ERRINT0
TPCC1 TPTC0 error interrupt
3
TPCC1 EDMATC_ERRINT1
TPCC1 TPTC1 error interrupt
4
TPCC1 EDMATC_ERRINT2
TPCC1 TPTC2 error interrupt
5
TPCC1 EDMATC_ERRINT3
TPCC1 TPTC3 error interrupt
6
TPCC1 EDMACC_GINT
TPCC1 GINT
7
Reserved
8
TPCC1 TPCCINT0
9
TPCC1 TPCCINT1
TPCC1 individual completion interrupt
10
TPCC1 TPCCINT2
TPCC1 individual completion interrupt
11
TPCC1 TPCCINT3
TPCC1 individual completion interrupt
12
TPCC1 TPCCINT4
TPCC1 individual completion interrupt
13
TPCC1 TPCCINT5
TPCC1 individual completion interrupt
14
TPCC1 TPCCINT6
TPCC1 individual completion interrupt
15
TPCC1 TPCCINT7
TPCC1 individual completion interrupt
16
TPCC2 EDMACC_ERRINT
TPCC2 error interrupt
17
TPCC2 EDMACC_MPINT
TPCC2 memory protection interrupt
18
TPCC2 EDMATC_ERRINT0
TPCC2 TPTC0 error interrupt
19
TPCC2 EDMATC_ERRINT1
TPCC2 TPTC1 error interrupt
20
TPCC2 EDMATC_ERRINT2
TPCC2 TPTC2 error interrupt
144
TPCC1 individual completion interrupt
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 5)
Input Event# on INTC
System Interrupt
Description
21
TPCC2 EDMATC_ERRINT3
TPCC2 TPTC3 error interrupt
22
TPCC2 EDMACC_GINT
TPCC2 GINT
23
Reserved
24
TPCC2 TPCCINT0
TPCC2 individual completion interrupt
25
TPCC2 TPCCINT1
TPCC2 individual completion interrupt
26
TPCC2 TPCCINT2
TPCC2 individual completion interrupt
27
TPCC2 TPCCINT3
TPCC2 individual completion interrupt
28
TPCC2 TPCCINT4
TPCC2 individual completion interrupt
29
TPCC2 TPCCINT5
TPCC2 individual completion interrupt
30
TPCC2 TPCCINT6
TPCC2 individual completion interrupt
31
TPCC2 TPCCINT7
TPCC2 individual completion interrupt
32
TPCC0 EDMACC_ERRINT
TPCC0 error interrupt
33
TPCC0 EDMACC_MPINT
TPCC0 memory protection interrupt
34
TPCC0 EDMATC_ERRINT0
TPCC0 TPTC0 error interrupt
35
TPCC0 EDMATC_ERRINT1
TPCC0 TPTC1 error interrupt
36
TPCC0 EDMACC_GINT
TPCC0 GINT
37
Reserved
38
TPCC0 TPCCINT0
TPCC0 individual completion interrupt
39
TPCC0 TPCCINT1
TPCC0 individual completion interrupt
40
TPCC0 TPCCINT2
TPCC0 individual completion interrupt
41
TPCC0 TPCCINT3
TPCC0 individual completion interrupt
42
TPCC0 TPCCINT4
TPCC0 individual completion interrupt
43
TPCC0 TPCCINT5
TPCC0 individual completion interrupt
44
TPCC0 TPCCINT6
TPCC0 individual completion interrupt
45
TPCC0 TPCCINT7
TPCC0 individual completion interrupt
46
Reserved
47
QM_INT_PASS_TXQ_PEND_12
QM_SS_PASS pend event
48
PCIEXpress_ERR_INT
Protocol error interrupt
49
PCIEXpress_PM_INT
Power management interrupt
50
PCIEXpress_Legacy_INTA
Legacy interrupt mode
51
PCIEXpress_Legacy_INTB
Legacy interrupt mode
52
PCIEXpress_Legacy_INTC
Legacy interrupt mode
53
PCIEXpress_Legacy_INTD
Legacy interrupt mode
54
SPIINT0
SPI interrupt0
55
SPIINT1
SPI interrupt1
56
SPIXEVT
Transmit event
57
SPIREVT
Receive event
58
I2CINT
I2C interrupt
59
I2CREVT
I2C receive event
60
I2CXEVT
I2C transmit event
61
Reserved
62
Reserved
63
TETBHFULLINT
TETB is half full
64
TETBFULLINT
TETB is full
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 7-40
145
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-40
www.ti.com
INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 5)
Input Event# on INTC
System Interrupt
Description
65
TETBACQINT
Acquisition has been completed
66
TETBOVFLINT
Overflow condition occur
67
TETBUNFLINT
Underflow condition occur
68
MDIO_LINK_INTR0
PASS_MDIO interrupt
69
MDIO_LINK_INTR1
PASS_MDIO interrupt
70
MDIO_USER_INTR0
PASS_MDIO interrupt
71
MDIO_USER_INTR1
PASS_MDIO interrupt
ADVANCE INFORMATION
72
MISC_INTR
PASS_MISC interrupt
73
CP_Tracer_core_0_INTD
CP_Tracer sliding time window interrupt for individual core
74
CP_Tracer_core_1_INTD
CP_Tracer sliding time window interrupt for individual core
75
Rerserved
76
Reserved
77
CP_Tracer_DDR_INTD
CP_Tracer sliding time window interrupt for DDR3 EMIF1
78
CP_Tracer_MSMC_0_INTD
CP_Tracer sliding time window interrupt for MSMC SRAM bank0
79
CP_Tracer_MSMC_1_INTD
CP_Tracer sliding time window interrupt for MSMC SRAM bank1
80
CP_Tracer_MSMC_2_INTD
CP_Tracer sliding time window interrupt for MSMC SRAM bank2
81
CP_Tracer_MSMC_3_INTD
CP_Tracer sliding time window interrupt for MSMC SRAM bank3
81
CP_Tracer_CFG_INTD
CP_Tracer sliding time window interrupt for CFG0 SCR
82
CP_Tracer_QM_SS_CFG_INTD
CP_Tracer sliding time window interrupt for QM_SS CFG
84
CP_Tracer_QM_SS_DMA_INTD
CP_Tracer sliding time window interrupt for QM_SS slave
85
CP_Tracer_SEM_INTD
CP_Tracer sliding time window interrupt for semaphore
86
PSC_ALLINT
Power/sleep controller interrupt
87
MSMC_scrub_cerror
Correctable (1-bit) soft error detected during scrub cycle
88
BOOTCFG_INTD
Chip-level MMR error register
89
Reserved
Reserved
90
MPU0_INTD (MPU0_ADDR_ERR_INT and MPU0 addressing violation interrupt and protection violation interrupt.
MPU0_PROT_ERR_INT combined)
91
QM_INT_PASS_TXQ_PEND_13
92
MPU1_INTD (MPU1_ADDR_ERR_INT and MPU1 addressing violation interrupt and protection violation interrupt.
MPU1_PROT_ERR_INT combined)
93
QM_INT_PASS_TXQ_PEND_14
94
MPU2_INTD (MPU2_ADDR_ERR_INT and MPU2 addressing violation interrupt and protection violation interrupt.
MPU2_PROT_ERR_INT combined)
95
QM_INT_PASS_TXQ_PEND_15
96
MPU3_INTD (MPU3_ADDR_ERR_INT and MPU3 addressing violation interrupt and protection violation interrupt.
MPU3_PROT_ERR_INT combined)
97
QM_INT_PASS_TXQ_PEND_16
QM_SS_PASS pend event
QM_SS_PASS pend event
QM_SS_PASS pend event
QM_SS_PASS pend event
98
MSMC_dedc_cerror
Correctable (1-bit) soft error detected on SRAM read
99
MSMC_dedc_nc_error
Non-correctable (2-bit) soft error detected on SRAM read
100
MSMC_scrub_nc_error
Non-correctable (2-bit) soft error detected during scrub cycle
101
Reserved
102
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
103
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
104
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
105
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
146
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 5)
Input Event# on INTC
System Interrupt
Description
105
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
107
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
108
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
109
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
110
DDR3_ERR
DDR3 EMIF error interrupt
111
Hyperbridge_int_o
Hyperbridge interrupt
112
INTDST0
RapidIO interrupt
113
INTDST1
RapidIO interrupt
114
INTDST2
RapidIO interrupt
115
INTDST3
RapidIO interrupt
116
INTDST4
RapidIO interrupt
117
INTDST5
RapidIO interrupt
118
INTDST6
RapidIO interrupt
119
INTDST7
RapidIO interrupt
120
INTDST8
RapidIO interrupt
121
INTDST9
RapidIO interrupt
122
INTDST10
RapidIO interrupt
123
INTDST11
RapidIO interrupt
124
INTDST12
RapidIO interrupt
125
INTDST13
RapidIO interrupt
126
INTDST14
RapidIO interrupt
127
INTDST15
RapidIO interrupt
128
EASYNCERR
EMIF16 error interrupt
129
Reserved
130
Reserved
131
Reserved
ADVANCE INFORMATION
Table 7-40
132
Reserved
133
QM_INT_CDMA_0
QM Interrupt for CDMA starvation
134
QM_INT_CDMA_1
QM Interrupt for CDMA starvation
135
RapidIO_INT_CDMA_0
RapidIO Interrupt for CDMA starvation
136
PASS_INT_CDMA_0
PASS Interrupt for CDMA starvation
137
SmartReflex_intrreq0
SmartReflex sensor interrupt
138
SmartReflex_intrreq1
SmartReflex sensor interrupt
139
SmartReflex_intrreq2
SmartReflex sensor interrupt
140
SmartReflex_intrreq3
SmartReflex sensor interrupt
141
VPNoSMPSAck
VPVOLTUPDATE has been asserted but SMPS has not been responded to in a
defined time interval
142
VPEqValue
SRSINTERUPTZ is asserted, but the new voltage is not different from the
current SMPS voltage
143
VPMaxVdd
The new voltage required is equal to or greater than MaxVdd.
144
VPMinVdd
The new voltage required is equal to or less than MinVdd.
145
VPINIDLE
The FSM of Voltage processor is in idle.
146
VPOPPChangeDone
The average frequency error is within the desired limit.
147
Reserved
148
UARTINT
Copyright 2011 Texas Instruments Incorporated
UART interrupt
147
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-40
www.ti.com
INTC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 5 of 5)
Input Event# on INTC
System Interrupt
Description
149
URXEVT
UART receive event
ADVANCE INFORMATION
150
UTXEVT
UART transmit event
151
QM_INT_PASS_TXQ_PEND_17
QM_SS_PASS pend event
152
QM_INT_PASS_TXQ_PEND_18
QM_SS_PASS pend event
153
QM_INT_PASS_TXQ_PEND_19
QM_SS_PASS pend event
154
QM_INT_PASS_TXQ_PEND_20
QM_SS_PASS pend event
155
QM_INT_PASS_TXQ_PEND_21
QM_SS_PASS pend event
156
QM_INT_PASS_TXQ_PEND_22
QM_SS_PASS pend event
157
QM_INT_PASS_TXQ_PEND_23
QM_SS_PASS pend event
158
QM_INT_PASS_TXQ_PEND_24
QM_SS_PASS pend event
159
QM_INT_PASS_TXQ_PEND_25
QM_SS_PASS pend event
End of Table 7-40
Table 7-41
INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 1 of 4)
Input Event # on INTC System Interrupt
Description
0
GPINT8
GPIO interrupt
1
GPINT9
GPIO interrupt
2
GPINT10
GPIO interrupt
3
GPINT11
GPIO interrupt
4
GPINT12
GPIO interrupt
5
GPINT13
GPIO interrupt
6
GPINT14
GPIO interrupt
7
GPINT15
GPIO interrupt
8
TETBHFULLINT
TETB is half full
9
TETBFULLINT
TETB is full
10
TETBACQINT
Acquisition has been completed
11
TETBHFULLINT0
TETB is half full
12
TETBFULLINT0
TETB is full
13
TETBACQINT0
Acquisition has been completed
14
TETBHFULLINT1
TETB is half full
15
TETBFULLINT1
TETB is full
16
TETBACQINT1
Acquisition has been completed
17
TETBHFULLINT2
TETB is half full
18
TETBFULLINT2
TETB is full
19
TETBACQINT2
Acquisition has been completed
20
TETBHFULLINT3
TETB is half full
21
TETBFULLINT3
TETB is full
22
TETBACQINT3
Acquisition has been completed
23
Reserved
24
QM_INT_HIGH_16
QM interrupt
25
QM_INT_HIGH_17
QM interrupt
26
QM_INT_HIGH_18
QM interrupt
27
QM_INT_HIGH_19
QM interrupt
148
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 7-41
INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 2 of 4)
Description
28
QM_INT_HIGH_20
QM interrupt
29
QM_INT_HIGH_21
QM interrupt
30
QM_INT_HIGH_22
QM interrupt
31
QM_INT_HIGH_23
QM interrupt
32
QM_INT_HIGH_24
QM interrupt
33
QM_INT_HIGH_25
QM interrupt
34
QM_INT_HIGH_26
QM interrupt
35
QM_INT_HIGH_27
QM interrupt
36
QM_INT_HIGH_28
QM interrupt
37
QM_INT_HIGH_29
QM interrupt
38
QM_INT_HIGH_30
QM interrupt
39
QM_INT_HIGH_31
QM interrupt
40
mdio_link_intr0
PASS_mdio Interrupt
41
mdio_link_intr1
PASS_mdio Interrupt
42
mdio_user_intr0
PASS_mdio Interrupt
43
mdio_user_intr1
PASS_mdio Interrupt
44
misc_intr
PASS_misc Interrupt
45
Tracer_core_0_INTD
Tracer sliding time window interrupt for individual core
46
Tracer_core_1_INTD
Tracer sliding time window interrupt for individual core
47
Reserved
48
Reserved
49
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
50
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM bank0
51
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM bank1
52
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM bank2
53
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM bank3
54
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 SCR
55
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
56
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS slave port
57
Tracer_SEM_INTD
Tracer sliding time window interrupt for semaphore
58
SEMERR0
Semaphore interrupt
59
SEMERR1
Semaphore interrupt
60
SEMERR2
Semaphore interrupt
61
SEMERR3
Semaphore interrupt
62
BOOTCFG_INTD
BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT
63
PASS_INT_CDMA_0
PASS interrupt for CDMA starvation
64
MPU0_INTD (MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
MPU0 addressing violation interrupt and protection violation interrupt.
65
MSMC_scrub_cerror
Correctable (1-bit) soft error detected during scrub cycle
66
MPU1_INTD (MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
MPU1 addressing violation interrupt and protection violation interrupt.
67
RapidIO_INT_CDMA_0
RapidIO interrupt for CDMA starvation
68
MPU2_INTD (MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
MPU2 addressing violation interrupt and protection violation interrupt.
69
QM_INT_CDMA_0
QM interrupt for CDMA starvation
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Input Event # on INTC System Interrupt
149
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-41
www.ti.com
INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 3 of 4)
ADVANCE INFORMATION
Input Event # on INTC System Interrupt
Description
70
MPU3_INTD (MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
MPU3 addressing violation interrupt and protection violation interrupt.
71
QM_INT_CDMA_1
QM interrupt for CDMA starvation
72
MSMC_dedc_cerror
Correctable (1-bit) soft error detected on SRAM read
73
MSMC_dedc_nc_error
Non-correctable (2-bit) soft error detected on SRAM read
74
MSMC_scrub_nc_error
Non-correctable (2-bit) soft error detected during scrub cycle
75
Reserved
76
MSMC_mpf_error0
Memory protection fault indicators for each system master PrivID
77
MSMC_mpf_error1
Memory protection fault indicators for each system master PrivID
78
MSMC_mpf_error2
Memory protection fault indicators for each system master PrivID
79
MSMC_mpf_error3
Memory protection fault indicators for each system master PrivID
80
MSMC_mpf_error4
Memory protection fault indicators for each system master PrivID
81
MSMC_mpf_error5
Memory protection fault indicators for each system master PrivID
82
MSMC_mpf_error6
Memory protection fault indicators for each system master PrivID
83
MSMC_mpf_error7
Memory protection fault indicators for each system master PrivID
84
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
85
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
86
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
87
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
88
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
89
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
90
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
91
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
92
Reserved
93
INTDST0
RapidIO interrupt
94
INTDST1
RapidIO interrupt
95
INTDST2
RapidIO interrupt
96
INTDST3
RapidIO interrupt
97
INTDST4
RapidIO interrupt
98
INTDST5
RapidIO interrupt
99
INTDST6
RapidIO interrupt
100
INTDST7
RapidIO interrupt
101
INTDST8
RapidIO interrupt
102
INTDST9
RapidIO interrupt
103
INTDST10
RapidIO interrupt
104
INTDST11
RapidIO interrupt
105
INTDST12
RapidIO interrupt
106
INTDST13
RapidIO interrupt
107
INTDST14
RapidIO interrupt
108
INTDST15
RapidIO interrupt
109
INTDST16
RapidIO interrupt
110
INTDST17
RapidIO interrupt
111
INTDST18
RapidIO interrupt
112
INTDST19
RapidIO interrupt
150
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
INTC2 Event Inputs (Secondary Events for TPCC1 and TPCC2) (Part 4 of 4)
Input Event # on INTC System Interrupt
Description
113
INTDST20
RapidIO interrupt
114
INTDST21
RapidIO interrupt
115
INTDST22
RapidIO interrupt
116
INTDST23
RapidIO interrupt
117
EASYNCERR
EMIF16 error interrupt
118
TETBHFULLINT4
TETB is half full
119
TETBFULLINT4
TETB is full
120
TETBACQINT4
Acquisition has been completed
121
TETBHFULLINT5
TETB is half full
122
TETBFULLINT5
TETB is full
123
TETBACQINT5
Acquisition has been completed
124
TETBHFULLINT6
TETB is half full
125
TETBFULLINT6
TETB is full
126
TETBACQINT6
Acquisition has been completed
127
TETBHFULLINT7
TETB is half full
128
TETBFULLINT7
TETB is full
129
TETBACQINT7
Acquisition has been completed
130
Reserved
131
Reserved
132
Reserved
133
Reserved
134
SEMERR4
Semaphore error interrupt
135
SEMERR5
Semaphore error interrupt
136
SEMERR6
Semaphore error interrupt
137
SEMERR7
Semaphore error interrupt
138
QM_INT_HIGH_0
QM interrupt
139
QM_INT_HIGH_1
QM interrupt
140
QM_INT_HIGH_2
QM interrupt
141
QM_INT_HIGH_3
QM interrupt
142
QM_INT_HIGH_4
QM interrupt
143
QM_INT_HIGH_5
QM interrupt
ADVANCE INFORMATION
Table 7-41
End of Table 7-41
Table 7-42
INTC3 Event Inputs (Secondary Events for TPCC0 and HyperLink) (Part 1 of 3)
Input Event # on INTC
System Interrupt
Description
0
GPINT0
GPIO interrupt
1
GPINT1
GPIO interrupt
2
GPINT2
GPIO interrupt
3
GPINT3
GPIO interrupt
4
GPINT4
GPIO interrupt
5
GPINT5
GPIO interrupt
6
GPINT6
GPIO interrupt
7
GPINT7
GPIO interrupt
8
GPINT8
GPIO interrupt
Copyright 2011 Texas Instruments Incorporated
151
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-42
www.ti.com
INTC3 Event Inputs (Secondary Events for TPCC0 and HyperLink) (Part 2 of 3)
ADVANCE INFORMATION
Input Event # on INTC
System Interrupt
Description
9
GPINT9
GPIO interrupt
10
GPINT10
GPIO interrupt
11
GPINT11
GPIO interrupt
12
GPINT12
GPIO interrupt
13
GPINT13
GPIO interrupt
14
GPINT14
GPIO interrupt
15
GPINT15
GPIO interrupt
16
TETBHFULLINT
TETB is half full
17
TETBFULLINT
TETB is full
18
TETBACQINT
Acquisition has been completed
19
TETBHFULLINT0
TETB is half full
20
TETBFULLINT0
TETB is full
21
TETBACQINT0
Acquisition has been completed
22
TETBHFULLINT1
TETB is half full
23
TETBFULLINT1
TETB is full
24
TETBACQINT1
Acquisition has been completed
25
TETBHFULLINT2
TETB is half full
26
TETBFULLINT2
TETB is full
27
TETBACQINT2
Acquisition has been completed
28
TETBHFULLINT3
TETB is half full
29
TETBFULLINT3
TETB is full
30
TETBACQINT3
Acquisition has been completed
31
Tracer_core_0_INTD
Tracer sliding time window interrupt for individual core
32
Tracer_core_1_INTD
Tracer sliding time window interrupt for individual core
33
Reserved
34
Reserved
35
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
36
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM bank0
37
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM bank1
38
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM bank2
39
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM bank3
40
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 SCR
41
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
42
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS slave port
43
Tracer_SEM_INTD
Tracer sliding time window interrupt for semaphore
44
vusr_int_o
HyperLink interrupt
45
TETBHFULLINT4
TETB is half full
46
TETBFULLINT4
TETB is full
47
TETBACQINT4
Acquisition has been completed
48
TETBHFULLINT5
TETB is half full
49
TETBFULLINT5
TETB is full
50
TETBACQINT5
Acquisition has been completed
51
TETBHFULLINT6
TETB is half full
52
TETBFULLINT6
TETB is full
152
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
INTC3 Event Inputs (Secondary Events for TPCC0 and HyperLink) (Part 3 of 3)
Input Event # on INTC
System Interrupt
Description
53
TETBACQINT6
Acquisition has been completed
54
TETBHFULLINT7
TETB is half full
55
TETBFULLINT7
TETB is full
56
TETBACQINT7
Acquisition has been completed
57
Reserved
58
Reserved
59
Reserved
60
Reserved
61
DDR3_ERR
DDR3 EMIF Error interrupt
62
po_vp_smpsack_intr
Indicating that Volt_Proc receives the r-edge at its smpsack input.
End of Table 7-42
7.10.2 INTC Registers
This section includes the offsets for INTC registers. The base addresses for interrupt control registers are INTC0 0x0260 0000, INTC1 - 0x0260 4000, INTC2 - 0x0260 8000, and INTC3 - 0x0260 C000INTC0 - 0x0260 0000, INTC1
- 0x0260 4000
7.10.2.1 INTC0/INTC1 Register Map
Table 7-43
INTC0/INTC1 Register
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x4
CONTROL_REG
Control Register
0xc
HOST_CONTROL_REG
Host Control Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x208
RAW_STATUS_REG2
Raw Status Register 2
0x20c
RAW_STATUS_REG3
Raw Status Register 3
0x210
RAW_STATUS_REG4
Raw Status Register 4
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x288
ENA_STATUS_REG2
Enabled Status Register 2
0x28c
ENA_STATUS_REG3
Enabled Status Register 3
0x290
ENA_STATUS_REG4
Enabled Status Register 4
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x308
ENABLE_REG2
Enable Register 2
0x30c
ENABLE_REG3
Enable Register 3
Copyright 2011 Texas Instruments Incorporated
153
ADVANCE INFORMATION
Table 7-42
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-43
www.ti.com
INTC0/INTC1 Register
Address Offset
Register Mnemonic
Register Name
0x310
ENABLE_REG4
Enable Register 4
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x388
ENABLE_CLR_REG2
Enable Clear Register 2
0x38c
ENABLE_CLR_REG3
Enable Clear Register 3
ADVANCE INFORMATION
0x390
ENABLE_CLR_REG4
Enable Clear Register 4
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x440
CH_MAP_REG16
Interrupt Channel Map Register for 64 to 64+3
0x444
CH_MAP_REG17
Interrupt Channel Map Register for 68 to 68+3
0x448
CH_MAP_REG18
Interrupt Channel Map Register for 72 to 72+3
0x44c
CH_MAP_REG19
Interrupt Channel Map Register for 76 to 76+3
0x450
CH_MAP_REG20
Interrupt Channel Map Register for 80 to 80+3
0x454
CH_MAP_REG21
Interrupt Channel Map Register for 84 to 84+3
0x458
CH_MAP_REG22
Interrupt Channel Map Register for 88 to 88+3
0x45c
CH_MAP_REG23
Interrupt Channel Map Register for 92 to 92+3
0x460
CH_MAP_REG24
Interrupt Channel Map Register for 96 to 96+3
0x464
CH_MAP_REG25
Interrupt Channel Map Register for 100 to 100+3
0x468
CH_MAP_REG26
Interrupt Channel Map Register for 104 to 104+3
0x46c
CH_MAP_REG27
Interrupt Channel Map Register for 108 to 108+3
0x470
CH_MAP_REG28
Interrupt Channel Map Register for 112 to 112+3
0x474
CH_MAP_REG29
Interrupt Channel Map Register for 116 to 116+3
0x478
CH_MAP_REG30
Interrupt Channel Map Register for 120 to 120+3
0x47c
CH_MAP_REG31
Interrupt Channel Map Register for 124 to 124+3
0x480
CH_MAP_REG32
Interrupt Channel Map Register for 128 to 128+3
0x484
CH_MAP_REG33
Interrupt Channel Map Register for 132 to 132+3
0x488
CH_MAP_REG34
Interrupt Channel Map Register for 136 to 136+3
0x48c
CH_MAP_REG35
Interrupt Channel Map Register for 140 to 140+3
0x490
CH_MAP_REG36
Interrupt Channel Map Register for 144 to 144+3
0x494
CH_MAP_REG37
Interrupt Channel Map Register for 148 to 148+3
154
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
INTC0/INTC1 Register
Address Offset
Register Mnemonic
Register Name
0x498
CH_MAP_REG38
Interrupt Channel Map Register for 152 to 152+3
0x49c
CH_MAP_REG39
Interrupt Channel Map Register for 156 to 156+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x82c
HINT_MAP_REG11
Host Interrupt Map Register for 44 to 44+3
0x830
HINT_MAP_REG12
Host Interrupt Map Register for 48 to 48+3
0x834
HINT_MAP_REG13
Host Interrupt Map Register for 52 to 52+3
0x838
HINT_MAP_REG14
Host Interrupt Map Register for 56 to 56+3
0x83c
HINT_MAP_REG15
Host Interrupt Map Register for 60 to 60+3
0x840
HINT_MAP_REG16
Host Interrupt Map Register for 64 to 64+3
0x844
HINT_MAP_REG17
Host Interrupt Map Register for 68 to 68+3
0x848
HINT_MAP_REG18
Host Interrupt Map Register for 72 to 72+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
0x1508
ENABLE_HINT_REG2
Host Int Enable Register 2
ADVANCE INFORMATION
Table 7-43
End of Table 7-43
7.10.2.2 INTC2 Register Map
Table 7-44
INTC2 Register
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x208
RAW_STATUS_REG2
Raw Status Register 2
0x20c
RAW_STATUS_REG3
Raw Status Register 3
0x210
RAW_STATUS_REG4
Raw Status Register 4
0x280
ENA_STATUS_REG0
Enabled Status Register 0
Copyright 2011 Texas Instruments Incorporated
155
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-44
www.ti.com
INTC2 Register
ADVANCE INFORMATION
Address Offset
Register Mnemonic
Register Name
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x288
ENA_STATUS_REG2
Enabled Status Register 2
0x28c
ENA_STATUS_REG3
Enabled Status Register 3
0x290
ENA_STATUS_REG4
Enabled Status Register 4
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x308
ENABLE_REG2
Enable Register 2
0x30c
ENABLE_REG3
Enable Register 3
0x310
ENABLE_REG4
Enable Register 4
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x388
ENABLE_CLR_REG2
Enable Clear Register 2
0x38c
ENABLE_CLR_REG3
Enable Clear Register 3
0x390
ENABLE_CLR_REG4
Enable Clear Register 4
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x440
CH_MAP_REG16
Interrupt Channel Map Register for 64 to 64+3
0x444
CH_MAP_REG17
Interrupt Channel Map Register for 68 to 68+3
0x448
CH_MAP_REG18
Interrupt Channel Map Register for 72 to 72+3
0x44c
CH_MAP_REG19
Interrupt Channel Map Register for 76 to 76+3
0x450
CH_MAP_REG20
Interrupt Channel Map Register for 80 to 80+3
0x454
CH_MAP_REG21
Interrupt Channel Map Register for 84 to 84+3
0x458
CH_MAP_REG22
Interrupt Channel Map Register for 88 to 88+3
0x45c
CH_MAP_REG23
Interrupt Channel Map Register for 92 to 92+3
0x460
CH_MAP_REG24
Interrupt Channel Map Register for 96 to 96+3
0x464
CH_MAP_REG25
Interrupt Channel Map Register for 100 to 100+3
0x468
CH_MAP_REG26
Interrupt Channel Map Register for 104 to 104+3
0x46c
CH_MAP_REG27
Interrupt Channel Map Register for 108 to 108+3
0x470
CH_MAP_REG28
Interrupt Channel Map Register for 112 to 112+3
0x474
CH_MAP_REG29
Interrupt Channel Map Register for 116 to 116+3
156
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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INTC2 Register
Address Offset
Register Mnemonic
Register Name
0x478
CH_MAP_REG30
Interrupt Channel Map Register for 120 to 120+3
0x47c
CH_MAP_REG31
Interrupt Channel Map Register for 124 to 124+3
0x480
CH_MAP_REG32
Interrupt Channel Map Register for 128 to 128+3
0x484
CH_MAP_REG33
Interrupt Channel Map Register for 132 to 132+3
0x488
CH_MAP_REG34
Interrupt Channel Map Register for 136 to 136+3
0x48c
CH_MAP_REG35
Interrupt Channel Map Register for 140 to 140+3
0x490
CH_MAP_REG36
Interrupt Channel Map Register for 144 to 144+3
0x494
CH_MAP_REG37
Interrupt Channel Map Register for 148 to 148+3
0x498
CH_MAP_REG38
Interrupt Channel Map Register for 152 to 152+3
0x49c
CH_MAP_REG39
Interrupt Channel Map Register for 156 to 156+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x82c
HINT_MAP_REG11
Host Interrupt Map Register for 44 to 44+3
0x830
HINT_MAP_REG12
Host Interrupt Map Register for 48 to 48+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
ADVANCE INFORMATION
Table 7-44
End of Table 7-44
7.10.2.3 INTC3 Register Map
Table 7-45
INTC3 Register
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x300
ENABLE_REG0
Enable Register 0
Copyright 2011 Texas Instruments Incorporated
157
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-45
www.ti.com
INTC3 Register
ADVANCE INFORMATION
Address Offset
Register Mnemonic
Register Name
0x304
ENABLE_REG1
Enable Register 1
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
End of Table 7-45
7.10.3 Inter-Processor Register Map
Table 7-46
IPC Generation Registers (IPCGRx) (Part 1 of 2)
Address Start
Address End
Size
Register Name
Description
0x02620200
0x02620203
4B
NMIGR0
NMI Event Generation Register for Core 0
0x02620204
0x02620207
4B
NMIGR1
NMI Event Generation Register for Core 1
0x02620208
0x0262020B
4B
Reserved
Reserved
0x0262020C
0x0262020F
4B
Reserved
Reserved
0x02620210
0x02620213
4B
Reserved
Reserved
0x02620214
0x02620217
4B
Reserved
Reserved
0x02620218
0x0262021B
4B
Reserved
Reserved
158
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
IPC Generation Registers (IPCGRx) (Part 2 of 2)
Address Start
Address End
Size
Register Name
Description
0x0262021C
0x0262021F
4B
Reserved
Reserved
0x02620220
0x0262023F
32B
Reserved
Reserved
0x02620240
0x02620243
4B
IPCGR0
IPC Generation Register for Core 0
0x02620244
0x02620247
4B
IPCGR1
IPC Generation Register for Core 1
0x02620248
0x0262024B
4B
Reserved
Reserved
0x0262024C
0x0262024F
4B
Reserved
Reserved
0x02620250
0x02620253
4B
Reserved
Reserved
0x02620254
0x02620257
4B
Reserved
Reserved
0x02620258
0x0262025B
4B
Reserved
Reserved
0x0262025C
0x0262025F
4B
Reserved
Reserved
0x02620260
0x0262027B
28B
Reserved
Reserved
0x0262027C
0x0262027F
4B
IPCGRH
IPC Generation Register for Host
0x02620280
0x02620283
4B
IPCAR0
IPC Acknowledgement Register for Core 0
0x02620284
0x02620287
4B
IPCAR1
IPC Acknowledgement Register for Core 1
0x02620288
0x0262028B
4B
Reserved
Reserved
0x0262028C
0x0262028F
4B
Reserved
Reserved
0x02620290
0x02620293
4B
Reserved
Reserved
0x02620294
0x02620297
4B
Reserved
Reserved
0x02620298
0x0262029B
4B
Reserved
Reserved
0x0262029C
0x0262029F
4B
Reserved
Reserved
0x026202A0
0x026202BB
28B
Reserved
Reserved
0x026202BC
0x026202BF
4B
IPCARH
IPC Acknowledgement Register for Host
ADVANCE INFORMATION
Table 7-46
End of Table 7-46
7.10.4 NMI and LRESET
Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured
to select between the CorePacs available as shown in Table 7-47.
Table 7-47
LRESET and NMI Decoding (Part 1 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input
LRESETNMIEN Pin Input
Reset Mux Block Output
XXXX
X
X
1
No local reset or NMI assertion.
0000
0
X
0
Assert local reset to CorePac 0
0001
0
X
0
Assert local reset to CorePac 1
0010
0
X
0
0011
0
X
0
0100
0
X
0
0101
0
X
0
0110
0
X
0
0111
0
X
0
1xxx
0
X
0
Reserved
0000
1
1
0
De-assert local reset & NMI to CorePac 0
0001
1
1
0
De-assert local reset & NMI to CorePac 1
Copyright 2011 Texas Instruments Incorporated
Reserved
159
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-47
www.ti.com
LRESET and NMI Decoding (Part 2 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input
LRESETNMIEN Pin Input
0010
1
1
0
0011
1
1
0
0100
1
1
0
0101
1
1
0
0110
1
1
0
0111
1
1
0
1xxx
1
1
0
Reset Mux Block Output
Reserved
De-assert local reset & NMI to all CorePacs
ADVANCE INFORMATION
0000
1
0
0
Assert NMI to CorePac 0
0001
1
0
0
Assert NMI to CorePac 1
0010
1
0
0
0011
1
0
0
0100
1
0
0
0101
1
0
0
0110
1
0
0
0111
1
0
0
1xxx
1
0
0
Reserved
Assert NMI to all CorePacs
End of Table 7-47
7.10.5 External Interrupts Electrical Data/Timing
Table 7-48
NMI and Local Reset Timing Requirements (1)
(see Figure 7-34)
No.
Min
Max
Unit
1
tsu(LRESETz-LRESETNMIENzL)
Setup Time - LRESET valid before LRESETNMIEN low
TBD
μs
1
tsu(NMIz-LRESETNMIENzL)
Setup Time - NMI valid before LRESETNMIEN low
TBD
μs
1
tsu(CORESELn-LRESETNMIENzL)
Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
TBD
μs
2
th(LRESETNMIENzL-LRESETz)
Hold Time - LRESET valid after LRESETNMIEN low
TBD
μs
2
th(LRESETNMIENzL-NMIz)
Hold Time - NMI valid after LRESETNMIEN low
TBD
μs
2
th(LRESETNMIENzL-CORESELn)
Hold Time - CORESEL[2:0] valid after LRESETNMIEN low
TBD
μs
3
tw(LRESETNMIENz)
Pulse Width - LRESETNMIEN low width
TBD
μs
4
tc(LRESETNMIENzL-LRESETNMIENzL)
Cycle Time - time between LRESETNMIEN low
TBD
μs
End of Table 7-48
1 P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Figure 7-34
NMI and Local Reset Timing
1
2
CORESEL[3:0]/
LRESET/
NMI
3
LRESETNMIEN
4
160
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.11 Memory Protection Unit (MPU)
The TCI6602 supports four MPUs:
• One MPU is used to protect main CORE/3 CFG SCR (CFG space of all slave devices on the SCR is protected
by the MPU).
• Two MPUs are used for QM_SS (one for DATA PORT port and another is for CFG PORT port).
• One MPU is used for Semaphore.
ADVANCE INFORMATION
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and
details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide (literature
number SPRUGW5).
The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 7-49
MPU Default Configuration
MPU0
Main CFG SCR
Setting
MPU1
(QM_SS DATA PORT)
MPU2
(QM_SS CFG PORT)
MPU3
Semaphore
Default permission
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Number of allowed IDs supported
16
16
16
16
Number of programmable ranges supported
16
5
16
1
Compare width
1KB granularity
1KB granularity
1KB granularity
1KB granularity
Start Address
End Address
End of Table 7-49
Table 7-50
MPU Memory Regions
Memory Protection
MPU0
Main CFG SCR
0x01D00000
0x026203FF
MPU1
QM_SS DATA PORT
0x34000000
0x340BFFFF
MPU2
QM_SS CFG PORT
0x02A00000
0x02ABFFFF
MPU3
Semaphore
0x02640000
0x026407FF
Table 7-51 shows the privilege ID of each CORE and every mastering peripheral. Table 7-51 also shows the privilege
level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read
or write) of each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 7-51
Privilege ID
Privilege ID Settings (Part 1 of 2)
Master
Privilege Level
Security Level
Access Type
0
CorePac0
SW dependant, driven by MSMC
SW dependant
DMA
1
CorePac1
SW dependant, driven by MSMC
SW dependant
DMA
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
Network Coprocessor
Packet DMA
User
Non-secure
DMA
Copyright 2011 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-51
www.ti.com
Privilege ID Settings (Part 2 of 2)
ADVANCE INFORMATION
Privilege ID
Master
Privilege Level
Security Level
Access Type
9
SRIO_CPPI/SRIO_M
User/Driven by SRIO block, User mode and supervisor mode is
determined on a per-transaction basis. Only the transaction with
source ID matching the value in the SupervisorID register is granted
supervisor mode.
Non-secure
DMA
10
QM_CDMA/QM_second
User
Non-secure
DMA
11
PCIe
Supervisor
Non-secure
DMA
12
DAP
Driven by debug_SS
Driven by debug_SS
DMA
13
HyperLink
Supervisor
Non-secure
DMA
14
HyperLink
Supervisor
Non-secure
DMA
15
TSIP0/1
User
Non-secure
DMA
End of Table 7-51
Table 7-52 shows the master ID of each CORE and every mastering peripheral. Master IDs are used to determine
allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters,
master IDs are unique to each master.
Table 7-52
Master ID Settings (Part 1 of 3) (1)
Master ID
Master
0
CORE0
1
CORE1
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
CORE0_CFG
9
CORE1_CFG
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16
EDMA0_TC0 read
17
EDMA0_TC0 write
18
EDMA0_TC1 read
19
EDMA0_TC1 write
20
EDMA1_TC0 read
21
EDMA1_TC0 write
22
EDMA1_TC1 read
23
EDMA1_TC1 write
24
EDMA1_TC2 read
25
EDMA1_TC2 write
26
EDMA1_TC3 read
162
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Master ID Settings (Part 2 of 3)
Master ID
Master
27
EDMA1_TC3 write
28
EDMA2_TC0 read
29
EDMA2_TC0 write
30
EDMA2_TC1 read
31
EDMA2_TC1 write
32
EDMA2_TC2 read
33
EDMA2_TC2 write
34
EDMA1_TC3 read
35
EDMA1_TC3 write
36 - 37
Reserved
38 - 39
SRIO_CPPI
40 - 47
Reserved
48
DAP
49
TPCC0
50
TPCC1
51
TPCC2
52
MSMC
53
PCIe
54
SRIO_M
55
HyperLink
56 - 59
Network coprocessor packet DMA
(2)
60 - 85
Reserved
86
TSIP0
87
TSIP1
88 - 91
QM_CDMA
92 - 93
QM_second
94 - 127
Reserved
128
CPT_L2_0
129
CPT_L2_1
130
Reserved
131
Reserved
132
Reserved
133
Reserved
134
Reserved
135
Reserved
136
CPT_MSMC0
137
CPT_MSMC1
138
CPT_MSMC2
139
CPT_MSMC3
140
CPT_DDR
141
CPT_SM
142
CPT_QM_P
Copyright 2011 Texas Instruments Incorporated
ADVANCE INFORMATION
Table 7-52
(1)
(3)
163
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-52
www.ti.com
Master ID Settings (Part 3 of 3) (1)
Master ID
Master
143
CPT_QM_M
144
CPT_CFG
End of Table 7-52
1 Some of the CPPI-based peripherals require multiple master IDs. QMS_CDMA is assigned with 88,89,90,91, but only 88-89 are actually used. For PA_CPPI port, 56,57,58,59 are
assigned while only 1 (56) is actually used. There are two master ID values are assigned for the QM_second master port, one master ID for external linking RAM and the
other one for the PDSP/MCDM accesses.
2 The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.
3 All CP_traces are set to the same master ID and bit 7 of the master ID needs to be 1.
ADVANCE INFORMATION
7.11.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device specific MPU registers.
7.11.1.1 MPU Register Map
Table 7-53
MPU0 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
210h
PROG1_MPSAR
Programmable range 1, start address
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
250h
PROG5_MPSAR
Programmable range 5, start address
254h
PROG5_MPEAR
Programmable range 5, end address
258h
PROG5_MPPA
Programmable range 5, memory page protection attributes
260h
PROG6_MPSAR
Programmable range 6, start address
264h
PROG6_MPEAR
Programmable range 6, end address
268h
PROG6_MPPA
Programmable range 6, memory page protection attributes
270h
PROG7_MPSAR
Programmable range 7, start address
274h
PROG7_MPEAR
Programmable range 7, end address
164
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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MPU0 Registers (Part 2 of 2)
Offset
Name
Description
278h
PROG7_MPPA
Programmable range 7, memory page protection attributes
280h
PROG8_MPSAR
Programmable range 8, start address
284h
PROG8_MPEAR
Programmable range 8, end address
288h
PROG8_MPPA
Programmable range 8, memory page protection attributes
290h
PROG9_MPSAR
Programmable range 9, start address
294h
PROG9_MPEAR
Programmable range 9, end address
298h
PROG9_MPPA
Programmable range 9, memory page protection attributes
2A0h
PROG10_MPSAR
Programmable range 10, start address
2A4h
PROG10_MPEAR
Programmable range 10, end address
2A8h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2B0h
PROG11_MPSAR
Programmable range 11, start address
2B4h
PROG11_MPEAR
Programmable range 11, end address
2B8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2C0h
PROG12_MPSAR
Programmable range 12, start address
2C4h
PROG12_MPEAR
Programmable range 12, end address
2C8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2D0h
PROG13_MPSAR
Programmable range 13, start address
2D4h
PROG13_MPEAR
Programmable range 13, end address
2Dh
PROG13_MPPA
Programmable range 13, memory page protection attributes
2E0h
PROG14_MPSAR
Programmable range 14, start address
2E4h
PROG14_MPEAR
Programmable range 14, end address
2E8h
PROG14_MPPA
Programmable range 14, memory page protection attributes
2F0h
PROG15_MPSAR
Programmable range 15, start address
2F4h
PROG15_MPEAR
Programmable range 15, end address
2F8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
ADVANCE INFORMATION
Table 7-53
End of Table 7-53
Table 7-54
MPU1 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
210h
PROG1_MPSAR
Programmable range 1, start address
Copyright 2011 Texas Instruments Incorporated
165
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-54
www.ti.com
MPU1 Registers (Part 2 of 2)
Offset
Name
Description
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
ADVANCE INFORMATION
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-54
Table 7-55
MPU2 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
210h
PROG1_MPSAR
Programmable range 1, start address
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
250h
PROG5_MPSAR
Programmable range 5, start address
254h
PROG5_MPEAR
Programmable range 5, end address
258h
PROG5_MPPA
Programmable range 5, memory page protection attributes
166
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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MPU2 Registers (Part 2 of 2)
Offset
Name
Description
260h
PROG6_MPSAR
Programmable range 6, start address
264h
PROG6_MPEAR
Programmable range 6, end address
268h
PROG6_MPPA
Programmable range 6, memory page protection attributes
270h
PROG7_MPSAR
Programmable range 7, start address
274h
PROG7_MPEAR
Programmable range 7, end address
278h
PROG7_MPPA
Programmable range 7, memory page protection attributes
280h
PROG8_MPSAR
Programmable range 8, start address
284h
PROG8_MPEAR
Programmable range 8, end address
288h
PROG8_MPPA
Programmable range 8, memory page protection attributes
290h
PROG9_MPSAR
Programmable range 9, start address
294h
PROG9_MPEAR
Programmable range 9, end address
298h
PROG9_MPPA
Programmable range 9, memory page protection attributes
2A0h
PROG10_MPSAR
Programmable range 10, start address
2A4h
PROG10_MPEAR
Programmable range 10, end address
2A8h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2B0h
PROG11_MPSAR
Programmable range 11, start address
2B4h
PROG11_MPEAR
Programmable range 11, end address
2B8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2C0h
PROG12_MPSAR
Programmable range 12, start address
2C4h
PROG12_MPEAR
Programmable range 12, end address
2C8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2D0h
PROG13_MPSAR
Programmable range 13, start address
2D4h
PROG13_MPEAR
Programmable range 13, end address
2Dh
PROG13_MPPA
Programmable range 13, memory page protection attributes
2E0h
PROG14_MPSAR
Programmable range 14, start address
2E4h
PROG14_MPEAR
Programmable range 14, end address
2E8h
PROG14_MPPA
Programmable range 14, memory page protection attributes
2F0h
PROG15_MPSAR
Programmable range 15, start address
2F4h
PROG15_MPEAR
Programmable range 15, end address
2F8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
ADVANCE INFORMATION
Table 7-55
End of Table 7-55
Table 7-56
MPU3 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
Copyright 2011 Texas Instruments Incorporated
167
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-56
www.ti.com
MPU3 Registers (Part 2 of 2)
Offset
Name
Description
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-56
ADVANCE INFORMATION
7.11.1.2 Device-Specific MPU Registers
7.11.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Figure 7-35
Configuration Register (CONFIG)
31
24
23
20
19
16
15
12
11
1
0
ADDR_WIDTH
NUM_FIXED
NUM_PROG
NUM_AIDS
Reserved
ASSUME_ALLOWED
MPU0
R-0
R-0
R-16
R-16
R-0
R-1
MPU1
R-0
R-0
R-5
R-16
R-0
R-1
MPU2
R-0
R-0
R-16
R-16
R-0
R-1
MPU3
R-0
R-0
R-1
R-16
R-0
R-1
Reset Values
Legend: R = Read only; -n = value after reset
Table 7-57
Configuration Register (CONFIG) Field Descriptions
Bit
Field
Description
31 – 24
ADDR_WIDTH
Address alignment for range checking
0 = 1KB alignment
6 = 64KB alignment
23 – 20
NUM_FIXED
Number of fixed address ranges
19 – 16
NUM_PROG
Number of programmable address ranges
15 – 12
NUM_AIDS
Number of supported AIDs
11 – 1
Reserved
Reserved. These bits will always reads as 0.
0
ASSUME_ALLOWED
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the
transfer is assumed to be allowed or not.
0 = Assume disallowed
1 = Assume allowed
168
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.11.2 MPU Programmable Range Registers
7.11.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The programmable address start register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also
writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines
the width of the address field in MPSAR and MPEAR.
Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
Reserved
R/W
R
Legend: R = Read only; R/W = Read/Write
Table 7-58
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
Bit
Field
Description
31 – 10
START_ADDR
Start address for range n.
9–0
Reserved
Reserved and these bits always read as 0.
End of Table 7-58
Table 7-59
Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
Register
MPU0
MPU1
MPU2
MPU3
PROG0_MPSAR
0x01D0_0000
0x3400_0000
0x02A0_0000
0x0264_0000
PROG1_MPSAR
0x01F0_0000
0x3402_0000
0x02A2_0000
N/A
PROG2_MPSAR
0x0200_0000
0x3406_0000
0x02A4_0000
N/A
PROG3_MPSAR
0x01E0_0000
0x3406_8000
0x02A6_0000
N/A
PROG4_MPSAR
0x021C_0000
0x340B_8000
0x02A6_8000
N/A
PROG5_MPSAR
0x021F_0000
N/A
0x02A6_9000
N/A
PROG6_MPSAR
0x0220_0000
N/A
0x02A6_A000
N/A
PROG7_MPSAR
0x0231_0000
N/A
0x02A6_B000
N/A
PROG8_MPSAR
0x0232_0000
N/A
0x02A6_C000
N/A
PROG9_MPSAR
0x0233_0000
N/A
0x02A6_E000
N/A
PROG10_MPSAR
0x0235_0000
N/A
0x02A8_0000
N/A
PROG11_MPSAR
0x0240_0000
N/A
0x02A9_0000
N/A
PROG12_MPSAR
0x0250_0000
N/A
0x02AA_0000
N/A
PROG13_MPSAR
0x0253_0000
N/A
0x02AA_8000
N/A
PROG14_MPSAR
0x0260_0000
N/A
0x02AB_0000
N/A
PROG15_MPSAR
0x0262_0000
N/A
0x02AB_8000
N/A
End of Table 7-59
Copyright 2011 Texas Instruments Incorporated
169
ADVANCE INFORMATION
Figure 7-36
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
7.11.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also only writeable by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Figure 7-37
Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
ADVANCE INFORMATION
END_ADDR
Reserved
R/W
R
Legend: R = Read only; R/W = Read/Write
Table 7-60
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
Bit
Field
Description
31 – 10
END_ADDR
End address for range n.
9–0
Reserved
Reserved and these bits always read as 3FFh.
End of Table 7-60
Table 7-61
Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
Register
MPU0
MPU1
MPU2
MPU3
PROG0_MPEAR
0x01D8_03FF
0x3401_FFFF
0x02A1_FFFF
0x0264_07FF
PROG1_MPEAR
0x01F7_FFFF
0x3405_FFFF
0x02A3_FFFF
N/A
PROG2_MPEAR
0x0209_FFFF
0x3406_7FFF
0x02A5_FFFF
N/A
PROG3_MPEAR
0x01EB_FFFF
0x340B_7FFF
0x02A6_7FFF
N/A
PROG4_MPEAR
0x021E_0FFF
0x340B_FFFF
0x02A6_8FFF
N/A
PROG5_MPEAR
0x021F_7FFF
N/A
0x02A6_9FFF
N/A
PROG6_MPEAR
0x022F_03FF
N/A
0x02A6_AFFF
N/A
PROG7_MPEAR
0x0231_03FF
N/A
0x02A6_BFFF
N/A
PROG8_MPEAR
0x0232_03FF
N/A
0x02A6_DFFF
N/A
PROG9_MPEAR
0x0233_03FF
N/A
0x02A6_FFFF
N/A
PROG10_MPEAR
0x0235_0FFF
N/A
0x02A8_FFFF
N/A
PROG11_MPEAR
0x024B_3FFF
N/A
0x02A9_FFFF
N/A
PROG12_MPEAR
0x0252_03FF
N/A
0x02AA_7FFF
N/A
PROG13_MPEAR
0x0254_03FF
N/A
0x02AA_FFFF
N/A
PROG14_MPEAR
0x0260_FFFF
N/A
0x02AB_7FFF
N/A
PROG15_MPEAR
0x0262_07FF
N/A
0x02AB_FFFF
N/A
End of Table 7-61
170
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.11.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
The programmable address memory protection page attribute register holds the permissions for the region. This
register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also only
writeable by a non-debug secure entity. The NS bit is only writeable by a non-debug secure entity. For debug accesses
the register is writeable only when NS = 1 or EMU = 1.
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
31
26
25
24
23
22
21
20
19
18
17
16
15
Reserved
AID15
AID14
AID13
AID12
AID11
AID10
AID9
AID8
AID7
AID6
AID5
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID4
AID3
AID2
AID1
AID0
AIDX
Reserved
NS
EMU
SR
SW
SX
UR
UW
UX
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Legend: R = Read only; R/W = Read/Write
Table 7-62
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 1 of 2)
Bit
Field
Description
31 – 26
Reserved
Reserved. These bits will always reads as 0.
25
AID15
Controls access from ID = 15
0 = Access denied.
1 = Access granted.
24
AID14
Controls access from ID = 14
0 = Access denied.
1 = Access granted.
23
AID13
Controls access from ID = 13
0 = Access denied.
1 = Access granted.
22
AID12
Controls access from ID = 12
0 = Access denied.
1 = Access granted.
21
AID11
Controls access from ID = 11
0 = Access denied.
1 = Access granted.
20
AID10
Controls access from ID = 10
0 = Access denied.
1 = Access granted.
19
AID9
Controls access from ID = 9
0 = Access denied.
1 = Access granted.
18
AID8
Controls access from ID = 8
0 = Access denied.
1 = Access granted.
17
AID7
Controls access from ID = 7
0 = Access denied.
1 = Access granted.
16
AID6
Controls access from ID = 6
0 = Access denied.
1 = Access granted.
Copyright 2011 Texas Instruments Incorporated
171
ADVANCE INFORMATION
Figure 7-38
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-62
www.ti.com
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 2 of 2)
ADVANCE INFORMATION
Bit
Field
Description
15
AID5
Controls access from ID = 5
0 = Access denied.
1 = Access granted.
14
AID4
Controls access from ID = 4
0 = Access denied.
1 = Access granted.
13
AID3
Controls access from ID = 3
0 = Access denied.
1 = Access granted.
12
AID2
Controls access from ID = 2
0 = Access denied.
1 = Access granted.
11
AID1
Controls access from ID = 1
0 = Access denied.
1 = Access granted.
10
AID0
Controls access from ID = 0
0 = Access denied.
1 = Access granted.
9
AIDX
Controls access from ID > 15
0 = Access denied.
1 = Access granted.
8
Reserved
Always reads as 0.
7
NS
Non-secure access permission
0 = Only secure access allowed.
1 = Non-secure access allowed.
6
EMU
Emulation (debug) access permission. This bit is ignored if NS = 1
0 = Debug access not allowed.
1 = Debug access allowed.
5
SR
Supervisor Read permission
0 = Access not allowed.
1 = Access allowed.
4
SW
Supervisor Write permission
0 = Access not allowed.
1 = Access allowed.
3
SX
Supervisor Execute permission
0 = Access not allowed.
1 = Access allowed.
2
UR
User Read permission
0 = Access not allowed.
1 = Access allowed
1
UW
User Write permission
0 = Access not allowed.
1 = Access allowed.
0
UX
User Execute permission
0 = Access not allowed.
1 = Access allowed.
End of Table 7-621
172
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values
Register
MPU0
MPU1
MPU2
MPU3
PROG0_MPPA
0x03FF_FCB6
0x03FF_FC80
0x03FF_FCA4
0x0003_FCB6
PROG1_MPPA
0x03FF_FC80
0x000F_FCB6
0x000F_FCB6
N/A
PROG2_MPPA
0x03FF_FCB6
0x03FF_FCB4
0x000F_FCB6
N/A
PROG3_MPPA
0x03FF_FCB6
0x03FF_FC80
0x03FF_FCB4
N/A
PROG4_MPPA
0x03FF_FC80
0x03FF_FCB6
0x03FF_FCB4
N/A
PROG5_MPPA
0x03FF_FC80
N/A
0x03FF_FCB4
N/A
PROG6_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
PROG7_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
PROG8_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
PROG9_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
PROG10_MPPA
0x03FF_FCB4
N/A
0x03FF_FCA4
N/A
PROG11_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
PROG12_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
PROG13_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
PROG14_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
PROG15_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB6
N/A
ADVANCE INFORMATION
Table 7-63
End of Table 7-63
Copyright 2011 Texas Instruments Incorporated
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7.12 DDR3 Memory Controller
The 64-bit DDR3 Memory Controller bus of the TMS320TCI6602 is used to interface to JEDEC standard-compliant
DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus
with any other types of peripherals.
7.12.1 DDR3 Memory Controller Device-Specific Information
The TMS320TCI6602 includes one 64-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can
operate at 800 Mega Transfers per Second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.
ADVANCE INFORMATION
Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit,
32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3
SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the
interface:
• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)
• 64-bit: Four 16-bit SDRAMs
• 64-bit: Eight 8-bit SDRAMs
• 32-bit: Two 16-bit SDRAMs
• 32-bit: Four 8-bit SDRAMs
• 16-bit: One 16-bit SDRAM
• 16-bit: Two 8-bit SDRAM
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as
I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O
buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible
DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if
master A passes a software message via a buffer in external memory and does not wait for an indication that the write
completes, before signaling to master B that the message is ready, when master B attempts to read the software
message, then the master B read may bypass the master A write and, thus, master B may read stale data and,
therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to
complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of
the read in step 3 ensures that the previous write was done.
174
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TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.12.2 DDR3 Memory Controller Electrical Data/Timing
The KeyStone DSP DDR3 Implementation Guidelines (literature number SPRABI1)specifies a complete DDR3
interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified
in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure
all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here
for this interface.
7.13 I2C Peripheral
The inter-integrated circuit (I2C) module provides an interface between DSP and other devices compliant with
2
2
Philips Semiconductors Inter-IC bus (I C bus) specification version 2.1 and connected by way of an I C bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module.
2
7.13.1 I C Device-Specific Information
2
The TMS320TCI6602 device includes an I C peripheral module.
2
Note—When using the I
C module, ensure there are external pullup resistors on the SDA and SCL pins.
2
The I C modules on the TCI6602 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may
be used to communicate with other controllers in a system or to implement a user interface.
2
2
The I C port is compatible with Philips I C specification revision 2.1 (January 2000) and supports:
• Fast mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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2
Figure 7-39 shows a block diagram of the I C module.
Figure 7-39
I2C Module Block Diagram
2
I C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
2
I CPSC
Control
Bit Clock
Generator
ADVANCE INFORMATION
SCL
Noise
Filter
2
I C Clock
I COAR
Own
Address
I2CSAR
Slave
Address
I2CMDR
Mode
2
2
I CCLKH
I2CCLKL
2
I CCNT
Transmit
I2CXSR
2
I CDXR
Transmit
Shift
I2CEMDR
Extended
Mode
Transmit
Buffer
SDA
Interrupt/DMA
Noise
Filter
I2C Data
Data
Count
I2CDRR
2
I CRSR
2
Interrupt
Mask/Status
2
Interrupt
Status
I CIMR
Receive
Receive
Buffer
I CSTR
Receive
Shift
I CIVR
2
Interrupt
Vector
Shading denotes control/status registers.
2
7.13.2 I C Peripheral Register Description(s)
Table 7-64
I2C Registers (Part 1 of 2)
Hex Address Range
Register
Register Name
0253 0000
ICOAR
I2C own address register
0253 0004
ICIMR
I C interrupt mask/status register
0253 0008
ICSTR
I C interrupt status register
0253 000C
ICCLKL
I2C clock low-time divider register
0253 0010
ICCLKH
I C clock high-time divider register
0253 0014
ICCNT
I C data count register
0253 0018
ICDRR
I2C data receive register
0253 001C
ICSAR
I C slave address register
0253 0020
ICDXR
I C data transmit register
0253 0024
ICMDR
I2C mode register
0253 0028
ICIVR
I C interrupt vector register
0253 002C
ICEMDR
I C extended mode register
0253 0030
ICPSC
I2C prescaler register
176
2
2
2
2
2
2
2
2
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 7-64
2
I C Registers (Part 2 of 2)
Hex Address Range
Register
Register Name
0253 0034
ICPID1
I2C peripheral identification register 1 [Value: 0x0000 0105]
0253 0038
ICPID2
I C peripheral identification register 2 [Value: 0x0000 0005]
0253 003C - 0253 007F
-
Reserved
2
End of Table 7-64
2
7.13.3 I C Electrical Data/Timing
2
Table 7-65
I2C Timing Requirements (1)
(see Figure 7-40)
Standard Mode
No.
Min
1
2
3
Max
Fast Mode
Min
Max Units
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
μs
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μs
4
tw(SCLL)
Pulse duration, SCL low
5
tw(SCLH)
Pulse duration, SCL high
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
4.7
1.3
μs
4
0.6
μs
250
2
(3)
100
0 (3)
μs
(5)
300
ns
20 + 0.1Cb (5)
300
ns
20 + 0.1Cb
(5)
300
ns
20 + 0.1Cb
(5)
300
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (For I C bus devices)
0
8
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
10
tr(SCL)
Rise time, SCL
1000
11
tf(SDA)
Fall time, SDA
300
tf(SCL)
Fall time, SCL
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
14
tw(SP)
15
Cb
(5)
1.3
300
4
μs
0.6
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
ns
0.9 (4)
7
12
3.45
(2)
0
400
ns
μs
50
ns
400
pF
End of Table 7-65
2
1 The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down
2
2
2 A Fast-mode I C-bus™ device can be used in a Standard-mode I C-bus™ system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
4 The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Copyright 2011 Texas Instruments Incorporated
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7.13.3.1 Inter-Integrated Circuits (I C) Timing
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
I2C Receive Timings
Figure 7-40
11
9
SDA
8
6
4
14
13
5
10
SCL
1
3
12
7
ADVANCE INFORMATION
2
3
Stop
Table 7-66
Start
Repeated
Start
2
I C Switching Characteristics
Stop
(1)
(see Figure 7-41)
Standard Mode
No.
Parameter
Min
Fast Mode
Max
Min
Max Unit
16
tc(SCL)
Cycle time, SCL
10
2.5
ms
17
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low (for a repeated START
condition)
4.7
0.6
ms
18
th(SDAL-SCLL)
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
4
0.6
ms
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
ms
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
ms
21
td(SDAV-SDLH)
Delay time, SDA valid to SCL high
250
100
ns
2
22
tv(SDLL-SDAV)
Valid time, SDA valid after SCL low (For I C bus devices)
23
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
0
0
4.7
1.3
0.9
ms
ms
24
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
(1)
300
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
(1)
300
ns
(1)
300
ns
300
ns
10
pF
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
27
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb (1)
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
29
Cp
Capacitance for each I C pin
2
4
0.6
10
ms
End of Table 7-66
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
178
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Figure 7-41
2
I C Transmit Timings
26
24
SDA
23
21
19
28
20
25
SCL
18
27
22
17
18
Stop
Start
Copyright 2011 Texas Instruments Incorporated
Repeated
Start
ADVANCE INFORMATION
16
Stop
179
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.14 SPI Peripheral
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
TCI6602 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
7.14.1 SPI Electrical Data/Timing
7.14.1.1 SPI Timing
Table 7-67
SPI Timing Requirements
ADVANCE INFORMATION
See Figure 7-42)
No.
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 1
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 1
2
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 0
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 1
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 0
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 1
5
ns
End of Table 7-67
Table 7-68
SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-42 and Figure 7-43)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
tc(SPC)
Cycle Time, SPIx_CLK, All Master Modes
1/66MHz
ns
2
tw(SPCH)
Pulse Width High, SPIx_CLK, All Master Modes
7
ns
3
tw(SPCL)
Pulse Width Low, SPIx_CLK, All Master Modes
7
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 0.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 1.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 0
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 1
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK. Polarity = 0 Phase = 0
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 0 Phase = 1
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 0
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 1
5
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 1
0.5*tc - 2
ns
180
ns
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
Table 7-68
SPI Switching Characteristics (Part 2 of 2)
(See Figure 7-42 and Figure 7-43)
No.
Parameter
Min
Max
Unit
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 1
0.5*tc - 2
ns
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 0
2*P2 - 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 0
2*P2 - 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 0
1*P2 - 5
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 0
1*P2 - 5
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
tw(SCSH)
Minimum inactive time on SPIx_SCS\ pin between two transfers when
SPIx_SCS\ is not held using the CSHOLD feature.
2*P2 - 5
2*P2 + 5
1*P2 + 5
1*P2 + 5
ns
ns
ns
ns
ns
End of Table 7-68
Copyright 2011 Texas Instruments Incorporated
181
ADVANCE INFORMATION
2*P2 + 5
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Figure 7-42
www.ti.com
SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
2
MASTER MODE
POLARITY = 0 PHASE = 0
3
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
6
MO(1)
MO(n-1)
MO(n)
8
MI(0)
MI(1)
MI(n-1)
MI(n)
ADVANCE INFORMATION
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
6
5
SPIx_SIMO
MO(0)
7
SPIx_SOMI
MO(1)
MO(n-1)
MI(1)
MI(n-1)
MO(n)
8
MI(0)
4
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
5
SPIx_SIMO
6
MO(0)
7
SPIx_SOMI
MO(1)
MO(n-1)
MO(n)
8
MI(0)
MI(1)
MI(n-1)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
Figure 7-43
6
MO(1)
MO(n-1)
MI(1)
MI(n-1)
MO(n)
8
MI(0)
MI(n)
SPI Additional Timings for 4 Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MI(0)
MO(1)
MO(n-1)
MO(n)
MI(1)
MI(n-1)
MI(n)
SPIx_SCS
182
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
7.15 HyperLink Peripheral
The TMS320TCI6602 includes the HyperLink bus for companion chip/die interfaces. This is a four-lane SerDes
interface designed to operate at 12.5 Gbps per lane from pin-to-pin and at 18 Gbps per lane from die-to-die.
The interface is used to connect with external accelerators. The HyperLink links must be connected with DC
coupling.
The interface includes the Serial Station Management Interfaces used to send power management and flow messages
between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output
buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.
HyperLink Peripheral Timing Requirements
See Figure 7-44,Figure 7-45,Figure 7-46
No.
Parameter
Min
Max
Unit
FL Interface
1
tc(MCMTXFLCLK)
Clock Period - MCMTXFLCLK (C1)
2
tw(MCMTXFLCLKH)
High Pulse Width - MCMTXFLCLK
0.4*C1 0.6*C1
6
ns
3
tw(MCMTXFLCLKL)
Low Pulse Width - MCMTXFLCLK
0.4*C1 0.6*C1
6
tsu(MCMTXFLDAT-MCMTXFLCLKH)
Setup Time - MCMTXFLDAT valid before MCMTXFLCLK high
7
th(MCMTXFLCLKH-MCMTXFLDAT)
Hold Time - MCMTXFLDAT valid after MCMTXFLCLK high
1
ns
6
tsu(MCMTXFLDAT-MCMTXFLCLKL)
Setup Time - MCMTXFLDAT valid before MCMTXFLCLK low
1
ns
7
th(MCMTXFLCLKL-MCMTXFLDAT)
Hold Time - MCMTXFLDAT valid after MCMTXFLCLK low
1
ns
6
ns
1
ns
ns
ns
PM Interface
1
tc(MCMRXPMCLK)
Clock Period - MCMRXPMCLK (C3)
2
tw(MCMRXPMCLK)
High Pulse Width - MCMRXPMCLK
0.4*C3 0.6*C3
3
tw(MCMRXPMCLK)
Low Pulse Width - MCMRXPMCLK
0.4*C3 0.6*C3
6
tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup Time - MCMRXPMDAT valid before MCMRXPMCLK high
1
ns
7
th(MCMRXPMCLKH-MCMRXPMDAT)
Hold Time - MCMRXPMDAT valid after MCMRXPMCLK high
1
ns
6
tsu(MCMRXPMDAT-MCMRXPMCLKL)
Setup Time - MCMRXPMDAT valid before MCMRXPMCLK low
1
ns
7
th(MCMRXPMCLKL-MCMRXPMDAT)
Hold Time - MCMRXPMDAT valid after MCMRXPMCLK low
1
ns
ns
ns
End of Table 7-69
Table 7-70
HyperLink Peripheral Switching Characteristics (Part 1 of 2)
See Figure 7-44,Figure 7-45,Figure 7-46
No.
Parameter
Min
Max
Unit
FL Interface
1
tc(MCMRXFLCLK)
Clock Period - MCMRXFLCLK (C2)
6
ns
2
tw(MCMRXFLCLKH)
High Pulse Width - MCMRXFLCLK
0.4*C2 0.6*C2
ns
3
tw(MCMRXFLCLKL)
Low Pulse Width - MCMRXFLCLK
0.4*C2 0.6*C2
ns
4
tosu(MCMRXFLDAT-MCMRXFLCLKH)
Setup Time - MCMRXFLDAT valid before MCMRXFLCLK high
1.1
ns
5
toh(MCMRXFLCLKH-MCMRXFLDAT)
Hold Time - MCMRXFLDAT valid after MCMRXFLCLK high
1.1
ns
4
tosu(MCMRXFLDAT-MCMRXFLCLKL)
Setup Time - MCMRXFLDAT valid before MCMRXFLCLK low
1.1
ns
5
toh(MCMRXFLCLKL-MCMRXFLDAT)
Hold Time - MCMRXFLDAT valid after MCMRXFLCLK low
1.1
ns
1
tc(MCMTXPMCLK)
Clock Period - MCMTXPMCLK (C4)
6
ns
2
tw(MCMTXPMCLK)
High Pulse Width - MCMTXPMCLK
0.4*C4 0.6*C4
ns
3
tw(MCMTXPMCLK)
Low Pulse Width - MCMTXPMCLK
0.4*C4 0.6*C4
ns
4
tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup Time - MCMTXPMDAT valid before MCMTXPMCLK high
PM Interface
Copyright 2011 Texas Instruments Incorporated
1.1
ns
183
ADVANCE INFORMATION
Table 7-69
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-70
www.ti.com
HyperLink Peripheral Switching Characteristics (Part 2 of 2)
See Figure 7-44,Figure 7-45,Figure 7-46
No.
Parameter
Min
Max
Unit
5
toh(MCMTXPMCLKH-MCMTXPMDAT)
Hold Time - MCMTXPMDAT valid after MCMTXPMCLK high
1.1
ns
4
tosu(MCMTXPMDAT-MCMTXPMCLKL)
Setup Time - MCMTXPMDAT valid before MCMTXPMCLK low
1.1
ns
5
toh(MCMTXPMCLKL-MCMTXPMDAT)
Hold Time - MCMTXPMDAT valid after MCMTXPMCLK low
1.1
ns
End of Table 7-70
Figure 7-44
HyperLink Station Management Clock Timing
ADVANCE INFORMATION
1
2
Figure 7-45
3
HyperLink Station Management Transmit Timing
4
5
4
5
6
7
?_CLK
?_DAT
Figure 7-46
HyperLink Station Management Receive Timing
6
7
?_CLK
?_DAT
184
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7.16 UART Peripheral
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes
control capability and a processor interrupt system that can be tailored to minimize software management of the
communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter
(UART) for KeyStone Devices User Guide in 2.10 ‘‘Related Documentation from Texas Instruments’’ on page 63.
Table 7-71
UART Timing Requirements
(see Figure 7-47 and Figure 7-48)
No.
Parameter
Min
Max
Unit
Receive Timing
4
tw(RXSTART)
Pulse width, receive start bit
0.96U
1.05U
ns
5
tw(RXH)
Pulse width, receive data/parity bit high
0.96U
1.05U
ns
5
tw(RXL)
Pulse width, receive data/parity bit low
0.96U
1.05U
ns
6
tw(RXSTOP1)
Pulse width, receive stop bit 1
0.96U
1.05U
ns
6
tw(RXSTOP15)
Pulse width, receive stop bit 1.5
0.96U
1.05U
ns
6
tw(RXSTOP2)
Pulse width, receive stop bit 2
0.96U
1.05U
ns
(1)
P
ns
Autoflow Timing Requirements
8
td(CTSL-TX)
Delay time, CTS asserted to START bit transmit
P
End of Table 7-71
1 P = CPU/6
Figure 7-47
UART Receive Timing Waveform
5
4
RXD
Figure 7-48
Stop/Idle
Start
5
Bit 0
Bit 1
Bit N-1
Bit N
6
Parity
Stop
Idle
Start
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
8
TXD
Bit N-1
Bit N
Stop
Start
Bit 0
CTS
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ADVANCE INFORMATION
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and
UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550
asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per
byte for the receiver FIFO.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-72
www.ti.com
UART Switching Characteristics
(See Figure 7-49 and Figure 7-50)
No.
Parameter
Min
Max
Unit
Transmit Timing
1
tw(TXSTART)
Pulse width, transmit start bit
U-2
U+2
ns
2
tw(TXH)
Pulse width, transmit data/parity bit high
U-2
U+2
ns
ADVANCE INFORMATION
2
tw(TXL)
Pulse width, transmit data/parity bit low
U-2
U+2
ns
3
tw(TXSTOP1)
Pulse width, transmit stop bit 1
U-2
U+2
ns
3
tw(TXSTOP15)
Pulse width, transmit stop bit 1.5
1.5 * (U - 2) 1.5 * ('U + 2)
ns
3
tw(TXSTOP2)
Pulse width, transmit stop bit 2
2 * (U - 2)
2 * ('U + 2)
ns
P (1)
P
ns
Autoflow Timing Requirements
7
Delay time, STOP bit received to RTS deasserted
td(RX-RTSH)
End of Table 7-72
1 P = CPU/6
Figure 7-49
UART Transmit Timing Waveform
1
TXD
Figure 7-50
Start
Stop/Idle
2
Bit 0
2
Bit 1
Bit N-1
Bit N
3
Parity
Stop
Idle
Start
UART RTS (Request-to-Send Output) — Autoflow Timing Waveform
7
RXD
Bit N-1
Bit N
Stop
Start
CTS
7.17 PCIe Peripheral
The two-lane PCI express (PCIe) module on the device provides an interface between the DSP and other
PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed data
transfer at rates of 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component
Interconnect Express (PCIe) for KeyStone Devices User Guide (literature number SPRUGS6).
7.18 TSIP Peripheral
The telecom serial interface port (TSIP) module provides a glueless interface to common telecom serial data streams.
For more information, see the Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide (literature number
SPRUGY4).
7.19 EMIF16 Peripheral
The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For
more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide (literature number
SPRUGZ3).
186
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7.20 Packet Accelerator
The packet accelerator provides L2 to L4 classification functionalities. It supports classification for Ethernet, VLAN,
MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It
maintains 8K multiple-in, multiple-out hardware queues. It also provides checksum capability as well as some QoS
capabilities. It enables a single IP address to be used for a multi-core device. It can process up to 1.5 M pps. The
packet accelerator is coupled with the network coprocessor. For more information, see the Packet Accelerator (PA)
for KeyStone Devices User Guide (literature number SPRUGS4).
The security accelerator provides wire-speed processing on 1-Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air
interface security protocols. It functions on the packet level with the packet and the associated security context being
one of these above three types. The security accelerator is coupled with network coprocessor, and receives the packet
descriptor containing the security context in the buffer descriptor, and the data to be encrypted/decrypted in the
linked buffer descriptor. For more information, see the Security Accelerator (SA) for KeyStone Devices User Guide
(literature number SPRUGY6)
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7.21 Security Accelerator
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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7.22 Gigabit Ethernet (GbE) Switch Subsystem
The Gigabit Ethernet (GbE) switch subsystem provide an efficient interface between the TMS320TCI6602 DSP and
the networked community. The GbE switch subsystem supports 10Base-T (10 Mbits/second [Mbps]), and
100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with
hardware flow control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with network
coprocessor. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User
Guide (literature number SPRUGV9)
Each device has a unique MAC address. There are two registers to hold these values, MACID1 (0x02620110) and
MACID2 (0x02600114). All bits of these registers are defined as follows:
ADVANCE INFORMATION
Figure 7-51
MACID1 Register
31
0
MACID[31:0]
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 7-73
MACID1 Register Field Descriptions
Bit
Field
Description
31-0
MAC ID[31-0]
MAC ID
End of Table 7-73
Figure 7-52
MACID2 Register
31
24
23
18
17
16
15
0
Reserved
Reserved
FLOW
BCAST
MACID[47:32]
R+, xxxx xxxx
R,+rr rrrr
R,+z
R,+y
R,+xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 7-74
MACID2 Register Field Descriptions
Bit
Field
Description
31-24
Reserved
Indeterminate
23-18
Reserved
000000
17
FLOW
MAC flow control
0 = Off
1 = On
16
BCAST
Default m/b-cast reception
0 = Broadcast
1 = Disabled
15-0
MAC ID[47-0]
MAC ID
End of Table 7-74
188
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
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There is one Time Synchronization (CPTS) submodule in the Ethernet switch module for Time Synchronization.
Programming this register selects the clock source for the CPTS_RCLK. Please see the Gigabit Ethernet (GbE) Switch
Subsystem for KeyStone Devices User Guide (literature number SPRUGV9) for the register address and other details
about the Time Synchronization module. The register CPTS_RFTCLK_SEL for reference clock selection of Time
Synchronization submodule is shown in Figure 7-53.
Figure 7-53
CPTS_RFTCLK_SEL Register
31
3
2
0
Reserved
CPTS_RFTCLK_SEL
R-0
RW - 0
Table 7-75
ADVANCE INFORMATION
Legend: R = Read only; -x, value is indeterminate
CPTS_RFTCLK_SEL Register Field Descriptions
Bit
Field
Description
31-3
Reserved
Reserved. Read as zero.
2-0
CPTS_RFTCLK_SEL
Reference Clock Select. This signal is used to control an external multiplexer that selects one of 8 clocks for
time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is
cleared to zero in the TS_CTL register.
000 = SYSCLK2
001 = SYSCLK3
010 = TIMI0
011 = TIMI1
100 = TSIP0 CLK_A
101 = TSIP0 CLK_B
110 = TSIP1 CLK_A
111 = TSIP1 CLK_B
End of Table 7-75
Copyright 2011 Texas Instruments Incorporated
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7.23 Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application
software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the GbE
switch subsystem, retrieve the negotiation results, and configure required parameters in the GbE switch subsystem
module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface,
with very little maintenance from the core processor. For more information, see the Gigabit Ethernet (GbE) Switch
Subsystem for KeyStone Devices User Guide (literature number SPRUGV9)
Table 7-76
MDIO Timing Requirements
See Figure 7-54
ADVANCE INFORMATION
No.
1
Parameter
Min
Max
Unit
tc(MDCLK)
Cycle time, MDCLK
400
ns
tw(MDCLKH)
Pulse duration, MDCLK high
180
ns
tw(MDCLKL)
Pulse duration, MDCLK low
180
ns
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
10
ns
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
ns
tt(MDCLK)
Transition time, MDCLK
5
ns
End of Table 7-76
Figure 7-54
MDIO Input Timing
1
MDCLK
4
5
MDIO
(Input)
Table 7-77
MDIO Switching Characteristics
See Figure 7-55
No.
7
Parameter
td(MDCLKL-MDIO)
Min
Delay time, MDCLK low to MDIO data output valid
Max
Unit
100
ns
End of Table 7-77
Figure 7-55
MDIO Output Timing
1
MDCLK
7
MDIO
(Ouput)
190
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7.24 Timers
The timers can be used to:
• Time events
• Count events
• Generate pulses
• Interrupt the CPU
• Send synchronization events to the EDMA3 channel controller
The TMS320TCI6602 device has four 64-bit timers in total. Timer0 and Timer1 are dedicated to each of the two
CorePacs as a watchdog timer and can also be used as general-purpose timers. Each of the other two timers can also
be configured as a general-purpose timer only, with each timer programmed as a 64-bit timer or as two separate
32-bit timers.
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge)
and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable
period.
When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two
32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low
counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in Watchdog mode, the timer counts down to zero and generates an event. It is a requirement
that software writes to the timer before the count expires, after which the count begins again. If the count ever
reaches 0, the timer event output is asserted. Reset initiated by a watch dog timer can be set by programming ‘‘Reset
Type Status Register (RSTYPE)’’ on page 125 and the type of reset initiated can set by programming ‘‘Reset
Configuration Register (RSTCFG)’’ on page 126. For more information, see the 64-bit Timer (Timer 64) for KeyStone
Devices User Guide (literature number SPRUGV5).
7.24.2 Timers Electrical Data/Timing
The tables and figure below describe the timing requirements and switching characteristics of Timer0 through
Timer3 peripherals.
Table 7-78
Timer Input Timing Requirements
(see Figure 7-56)
No.
Min
Max
Unit
1
tw(TINPH)
Pulse duration, high
12C
ns
2
tw(TINPL)
Pulse duration, low
12C
ns
End of Table 7-78
Table 7-79
Timer Output Switching Characteristics
(see Figure 7-56)
No.
Parameter
Min
Max
Unit
3
tw(TOUTH)
Pulse duration, high
12C - 3
ns
4
tw(TOUTL)
Pulse duration, low
12C - 3
ns
End of Table 7-79
Copyright 2011 Texas Instruments Incorporated
191
ADVANCE INFORMATION
7.24.1 Timers Device-Specific Information
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Figure 7-56
www.ti.com
Timer Timing
1
2
TIMIx
3
4
TIMOx
ADVANCE INFORMATION
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7.25 Serial RapidIO (SRIO) Port
7.26 General-Purpose Input/Output (GPIO)
7.26.1 GPIO Device-Specific Information
On the TMS320TCI6602, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more
detailed information on device/peripheral configuration and the TCI6602 device pin muxing, see ‘‘Device
Configuration’’ on page 64. For more information on GPIO, see the General Purpose Input/Output (GPIO) for
KeyStone Devices User Guide (literature number SPRUGV1)
7.26.2 GPIO Electrical Data/Timing
Table 7-80
GPIO Input Timing Requirements
No.
Min
Max
Unit
1
tw(GPOH)
Pulse duration, GPOx high
12C
ns
2
tw(GPOL)
Pulse duration, GPOx low
12C
ns
End of Table 7-80
Table 7-81
GPIO Output Switching Characteristics
No.
(1)
Parameter
Min
Max
Unit
1
tw(GPOH)
Pulse duration, GPOx high
36C - 8
ns
2
tw(GPOL)
Pulse duration, GPOx low
36C - 8
ns
End of Table 7-81
1 Over recommended operating conditions.
Figure 7-57
GPIO Timing
1
2
GPIx
3
4
GPOx
Copyright 2011 Texas Instruments Incorporated
193
ADVANCE INFORMATION
The SRIO port on the TMS320TCI6602 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous
interconnect environment, providing even more connectivity and control among the components. RapidIO is based
on the memory and device addressing concepts of processor buses where the transaction processing is managed
completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency,
reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless
interfaces. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide (literature number
SPRUGW1).
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
7.27 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the DSP C66x
CorePacs. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write
sequence is not broken. The semaphore block has unique interrupts to each of the cores to identify when that core
has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to
allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports 8 masters and contains 32 semaphores to be used within the system.
ADVANCE INFORMATION
There are two methods of accessing a semaphore resource:
•
•
Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the
semaphore is not granted.
Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt
notifies the CPU that it is available.
7.28 Emulation Features and Capability
7.28.1 Advanced Event Triggering (AET)
The TMS320TCI6602 device supports Advanced Event Triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting
the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events
such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely
generate events for complex sequences.
For more information on AET, see the following documents:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report (literature
number SPRA753)
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor
Systems application report (literature number SPRA387)
7.28.2 Trace
The TCI6602 device supports Trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information
for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the 60-Pin Emulation Header
Technical Reference (literature number SPRU655).
194
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7.28.2.1 Trace Electrical Data/Timing
Table 7-82
Trace Switching Characteristics
(1)
(see Figure 7-58)
Parameter
1
tw(DPnH)
1
2
Min Max Unit
Pulse duration, DPn/EMUn high
2.4
ns
tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
1.5
ns
tw(DPnL)
Pulse duration, DPn/EMUn low
2.4
ns
2
tw(DPnL)10%
Pulse duration, DPn/EMUn low detected at 10% Voh
3
tsko(DPn)
Output skew time, time delay difference between DPn/EMUn pins configured as trace
1.5
tskp(DPn)
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays.
tσλδπ_ο(DPn)
Output slew rate DPn/EMUn
-500
ns
500
600
3.3
ps
ps
V/ns
End of Table 7-82
1 Over recommended operating conditions.
Figure 7-58
Trace Timing
A
TPLH
TPHL
1
2
B
3
C
7.28.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported
allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary
scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes
(SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.28.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the TCI6602 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly
initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high.
However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup
resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and
externally drive TRST high before attempting any emulation or boundary scan operations.
Copyright 2011 Texas Instruments Incorporated
195
ADVANCE INFORMATION
No.
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
7.28.3.2 JTAG Electrical Data/Timing
Table 7-83
JTAG Test Port Timing Requirements
(see Figure 7-59)
No.
Min
1
tc(TCK)
Cycle time, TCK
1a
tw(TCKH)
1b
tw(TCKL)
Max
Unit
20
ns
Pulse duration, TCK high (40% of tc)
8
ns
Pulse duration, TCK low(40% of tc)
8
ns
ADVANCE INFORMATION
3
tsu(TDI-TCK)
input setup time, TDI valid to TCK high
2
ns
3
tsu(TMS-TCK)
input setup time, TMS valid to TCK high
2
ns
4
th(TCK-TDI)
input hold time, TDI valid from TCK high
10
ns
4
th(TCK-TMS)
input hold time, TMS valid from TCK high
10
ns
End of Table 7-83
JTAG Test Port Switching Characteristics (1)
Table 7-84
(see Figure 7-59)
No.
2
Parameter
Min
Delay time, TCK low to TDO valid
td(TCKL-TDOV)
Max
8
Unit
ns
End of Table 7-84
1 Over recommended operating conditions.
Figure 7-59
JTAG Test-Port Timing
1
1b
1a
TCK
2
TDO
3
4
TDI / TMS
Table 7-85
HS-RTDX Switching Characteristics (1)
(see Figure 7-60)
No.
4
Parameter
Min
Max
Unit
td(TCKH-DPn)
Delay time, TCK high to DPn/EMUn transition
3
25
ns
tdis(TCKH-DPZ)
Disable time, TCK high to DPn/EMUn hi-z
3
25
ns
tena(TCKH-DP)
Enable time, TCK high to DPn/EMUn driven
3
25
ns
tsldp_o(DPn)
Output slew rate DPn/EMUn
1
25
V/ns
End of Table 7-85
1 Over recommended operating conditions.
196
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Figure 7-60
HS-RTDX Timing
1
TCK
2
3
4
ADVANCE INFORMATION
DP[n] /
EMU[n]
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A Revision History
ADVANCE INFORMATION
Revision A
Added note to RSISO register that both SRIOISO and SRISO will be set by boot ROM code during boot (Page 127)
Modified PCIe peripherals introduction in Features section (Page 11)
Removed AIF2ISO from Reset Isolation Register (Page 127)
Added information of on-chip divider (=3) for PA in the PLL Boot Configuration Settings section (Page 31)
Changed "no support for MSI" to "support for legacy INTx" for PCIe in legacy EP mode description in Device Status Register Field Descriptions table (Page 69)
Changed "no support for MSI" to "support for legacy INTx" for PCIe legacy end point description in Device Configuration Pins table
(Page 64)
Added "The packet accelerator is coupled with network coprocessor" in the Packet Accelerator section (Page 187)
Added Network Coprocessor document link (Page 63)
Changed 2 to OUTPUT_DIVIDE in the clock formula in PLL Boot Configuration Settiongs section (Page 31)
Changed EMAC to GbE switch subsystem (Page 188)
Changed EMAC to Gigabit Ethernet (GbE) Switch Subsystem (Page 190)
Changed EMAC to Gigabit Ethernet Switch (Page 63)
Changed EMAC to Network Coprocessor Packet DMA (Page 82)
Changed Ethernet MAC Subsystem to Gigabit Ethernet Switch Subsystem in Features (Page 11)
Changed PA_SS into Network Coprocessor Packet DMA in Device Master Settings table (Page 161)
Changed PA_SS into PASS in the Clock Sequencing table (Page 105)
Changed PASS into Network Coprocessor (PASS) (Page 119)
Changed PS_SS_CLK PLL to PASS_CLK PLL in Terminal Functions table (Page 37)
Changed Packet Accelerator into Network Coprocessor and corrected the memory address in the memory map summary table (Page 19)
Changed Packet Accelerator into Network Coprocessor in the Device Configuration Pins table. (Page 64)
Changed Packet Subsystem to Network Coprocessor (PASS PLL) in Terminal Functions table (Page 37)
Changed packet accelerator into network coprocessor in Security Accelerator section (Page 187)
Changed packet accelerator subsystem into Network Coprocessor (Page 133)
Deleted section 5.5 "C66x CorePac Resets" to avoid confusion and the reset details are covered in "Reset Controller" section (Page 86)
Removed EMAC in Characteristics of the device Processor table (Page 15)
Added BGA Package row into Characteristics of Processor table (Page 15)
Corrected End and Bytes of DDR3 EMIF Configuration section in Memory Map Summary table (Page 19)
Corrected BAR number from BAR1/2 to BAR2/3 and BAR3/4 to BAR4/5 in PCIe Window Sizes table (Page 29)
Deleted EDMA3 Peripheral Register Description section, which is covered in EDMA user’s guide (Page 135)
Added SERDES PLL Status and Config registers (Page 65)
Added "to DDR3 memory space" to the first step of workaround (Page 174)
Added "with TCCMOD=0" after "e.g. EDMA3 transfer controllers" (Page 174)
Added CPTS_RFTCLK_SEL register in GbE Switch Subsystem section (Page 188)
Changed "DSP/2" to "CPU/2" and "DSP/3" to "CPU/3" (Page 82)
Changed the word "can" to "must" in the sentence "for most applications increment mode can be used" to specify it is a hard rule.
(Page 136)
Changed "sleep boot" to "No boot" in Sub-Mode field of No boot/EMIF16 Configuration Bit Field Descriptions table (Page 27)
Changed Section 2.5.2.1title from "Sleep/EMIF16" to "No Boot/EMIF16" (Page 27)
Corrections Applied to I2C Passive Mode Device Configuration Bit Fields (Page 30)
Corrections Applied to I2C Passive Mode Device Configuration Field Descriptions (Page 30)
Modified description of value 0 to EMIF16/No Boot in Boot Device Values table (Page 26)
Corrected SRIO configuration memory map from 0x02900000~0x02907FFF to 0x02900000~0x02920FFF (Page 19)
Added thermal values into the Thermal Resistance Characteristics table. (Page 200)
Added DDR3PLLCTL1 register and field description table (Page 131)
Added PASSPLLCTL1 register and field descriptions (Page 134)
Added more description to pin PTV15 in the Terminal Functions table (Page 38)
Added Master ID Settings table. (Page 162)
Added the table of Power Supply to Peripheral I/O Mapping (Page 96)
Changed PROGn_MPEAR register table format and reset value format (Page 170)
198
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Changed PROGn_MPSAR registers table format and reset value format (Page 169)
Modified reset values of PROGn_MPPA registers (Page 173)
Modified the figure of SmartReflex 4-Pin VID Interface Timing (Page 107)
Modified the table of SmartReflex 4-Pin VID Interface Switching Characteristics (Page 107)
Added PROG4 registers set into MPU1 Registers table (Page 165)
Changed number of programmable ranges supported from 4 to 5 for MPU1 (Page 161)
Modified Table 2-13 to include 1000 MHz and 1250 MHz columns. (Page 31)
Modified reset values in MPU Configuration Register table (Page 168)
Added BWADJ[11:8] to MAINPLLCTL1 register table and description. (Page 128)
Changed PROG3_MPEA to PROG3_MPEAR in MPU1 Registers table (Page 165)
Changed Privilege ID from the second column to the first column (Page 161)
Changed Programmable range enumeration from 1-N based to 0-N based in MPU Register Map. (Page 164)
Changed SRIO_CPPI and SRIO_M rows to the single row (Page 161)
Changed the master from Reserved to HyperLink with Privilege ID 13 and 14 (Page 161)
Modified BWADJ descriptions in MAINPLLCTL0 and MAINPLLCTL1 registers (Page 127)
Modified SECCTL register reference place in the note. (Page 128)
Corrected Clock Sequencing table - Removed ALTCORECLK reference, Corrected SYSCLK as CORECLK. (Page 105)
Corrections Applied to I2C Boot Device Configuration Bit Fields (Page 29)
Corrections Applied to Sleep / EMIF16 Boot Device Configuration Bit Fields (Page 27)
Updated Device Configuration Pins Table; PACLKSEL Functional Description (Page 64)
Updated Reset Electrical Data / Timing section. Included updated reset requirements. (Page 116)
Updated Reset Electrical Data; Included updated Reset Requirements. (Page 116)
Updated Table 2-3 Boot Mode Pins: Boot Device Values description of the Ethernet (SGMII) boots. (Page 26)
Removed the SRIOSMGIICLK, MCMCLK, and PCIECLK transisition timing values with respect to VOH and VOL within the Main PLL Controller timing requirements. (Page 128)
Updated Terminal Descriptions of TSIP Pins (Page 47)
Added MAINPLLCTL1, Renamed DDR3PLLCTL0 to DDR3PLLCT, Renamed PAPLLCTL0 to PAPLLCTL (Page 65)
Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 19)
Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 19)
Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR (Page 100)
Added section NMI and LRSET. (Page 159)
Corrected Extended Temperature range - Changed 105C to 100C for the top end. (Page 11)
Added BWADJ bit field to DDR3 PLL Control Register. (Page 131)
Added BWADJ bit field to PASS PLL Control Register. (Page 133)
Added MAINPLLCTL1 register table and description. (Page 127)
Added Note on level interrupts and use of EOI handshaking. (Page 140)
Added more detailed information on valid levels for CLKs and IOs during the power sequencing. (Page 101)
Corrected Address Range of I2C MMRs (Page 176)
Corrected PACLKSEL bitfield description. (Page 69)
Corrected RSV01 should be pulled up to 1.8V and RSV08 should be tied to GND (Page 48)
Revision 0 (First Issue)
Changed CVDD Range;Correct CVDD and CVDD1 Descriptions (CVDD: Core Supply -> SR Core Supply) (CVDD1: SR Core Supply -> Core
Supply) (Page 94)
Added more detailed information on valid levels for CLKs and IOs during the power sequencing. (Page 101)
Added to table "Terminal Functions - Signals and Control by Function", signals - RSV0A and RSV0B. (Page 37)
Corrected the timing pointers to point the correct figure (Page 116)
Changed incorrect reserved address in Memory Map Summary - 02780400 -> 02778400 (Page 19)
Corrected Commericial Temperature range - Changed 100C to 85C for the top end. (Page 11)
Copyright 2011 Texas Instruments Incorporated
199
ADVANCE INFORMATION
www.ti.com
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
www.ti.com
B Mechanical Data
B.1 Thermal Data
Table B-1 shows the thermal resistance characteristics for the PBGA - CYP mechanical package.
Table B-1
Thermal Resistance Characteristics (PBGA Package) [CYP]
No.
°C/W
1
RθJC
Junction-to-case
0.18
2
RθJB
Junction-to-board
3.71
End of Table B-1
ADVANCE INFORMATION
B.2 Packaging Information
The following packaging information reflects the most current released data available for the designated device(s).
This data is subject to change without notice and without revision of this document.
200
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