TI TMS320C6654

TMS320C6654
Fixed and Floating-Point Digital Signal Processor
Data Manual
PRODUCT PREVIEW information applies to products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Literature Number: SPRS841
March 2012
TMS320C6654
Data Manual
SPRS841—March 2012
www.ti.com
Release History
Revision
Date
Description/Comments
SPRS814
March 2012
Initial release
For detailed revision information, see ‘‘Revision History’’ on page A-217.
2
Release History
Copyright 2012 Texas Instruments Incorporated
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS841—March 2012
Contents
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.1 KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1
2.2
2.3
2.4
2.5
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DSP Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5.3 PLL Boot Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.7.1 Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.7.2 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.9 Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.10 Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.3.2 Device Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.3.11 NMI Event Generation to CorePac (NMIGRx) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.3.12 IPC Generation (IPCGRx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
3.3.19 Device Speed (DEVSPEED) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
3.3.20 Pin Control 0 (PIN_CONTROL_0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
3.3.21 Pin Control 1 (PIN_CONTROL_1) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
3.3.22 UPP Clock Source (UPP_CLOCK) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
4
System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
4.1
4.2
4.3
4.4
Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Switch Fabric Connections Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
TeraNet Switch Fabric Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
4.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
4.4.2 EMAC / UPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Copyright 2012 Texas Instruments Incorporated
Contents
3
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
5
www.ti.com
C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
5.1.4 MSM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5 C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.6 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1
6.2
6.3
6.4
7
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.1 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.7 Reset Electrical Data / Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.4 Main PLL and PLL Controller Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.5 Main PLL Controller/PCIe Clock Input Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.2 DDR3 PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.3 DDR3 PLL Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.4 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.3 EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.4 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.2 CIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.5 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Copyright 2012 Texas Instruments Incorporated
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.9 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11.2 I2C Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.1 EMIF16 Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 Ethernet Media Access Controller (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.1 EMAC Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.2 EMAC Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.3 EMAC Electrical Data/Timing (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17 Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17.1 MDIO Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17.2 MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21 Emulation Features and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.1 McBSP Peripheral Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.2 McBSP Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23 Universal Parallel Port (UPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23.1 UPP Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
B.1
B.2
Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Copyright 2012 Texas Instruments Incorporated
Contents
5
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
List of Figures
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 2-17
Figure 2-18
Figure 2-19
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 3-18
Figure 3-19
Figure 3-20
Figure 3-21
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 5-1
Figure 5-2
Figure 5-3
6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DSP Core Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
EMIF16 / UART / No Boot Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
No Boot Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
UART Boot Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
EMIF16 Boot Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Ethernet (SGMII) Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
NAND Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PCI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I2C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
CZH/GZH 625-Pin BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Pin Map Quadrants (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Upper Left Quadrant—A (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Upper Right Quadrant—B (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Lower Right Quadrant—C (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Lower Left Quadrant—D (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
C66x DSP Device Nomenclature (including the TMS320C6654). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
NMI Generation Register (NMIGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IPC Acknowledgement Registers (IPCARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Reset Mux Register RSTMUXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Device Speed Register (DEVSPEED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Pin Control 0 Register (PIN_CONTROL_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Pin Control 1Register (PIN_CONTROL_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Pin Control 1Register (PIN_CONTROL_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
TeraNet 3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
TeraNet 3P_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
TeraNet 3P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
TeraNet 3P_Tracer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
TeraNet 6P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
EMAC / UPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
List of Figures
Copyright 2012 Texas Instruments Incorporated
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Figure 5-4
Figure 5-5
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25
Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30
Figure 7-31
Figure 7-32
Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
Figure 7-39
Figure 7-40
Figure 7-41
Figure 7-42
Figure 7-43
Figure 7-44
Figure 7-45
Figure 7-46
Figure 7-47
Figure 7-48
Figure 7-49
Figure 7-50
Figure 7-51
Figure 7-52
L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CorePac Revision ID Register (MM_REVID) Address - 0181 2000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Soft/Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Main PLL Control Register 0 (MAINPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Main PLL Control Register 1 (MAINPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Main PLL Controller/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Main PLL Clock Input Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
DDR3 PLL Control Register 0 (DDR3PLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
DDR3 PLL Control Register 1 (DDR3PLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
TMS320C6654 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
NMI and Local Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
SPI Additional Timings for 4 Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
UART RTS (Request-to-Send Output) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
EMIF16 Asynchronous Memory Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
EMIF16 Asynchronous Memory Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
EMIF16 EM_WAIT Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
EMIF16 EM_WAIT Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
EMAC, MDIO, and EMAC Control Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Copyright 2012 Texas Instruments Incorporated
List of Figures
7
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 7-53
Figure 7-54
Figure 7-55
Figure 7-56
8
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UPP Single Data Rate (SDR) Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
UPP Double Data Rate (DDR) Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
UPP Single Data Rate (SDR) Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
UPP Double Data Rate (DDR) Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
List of Figures
Copyright 2012 Texas Instruments Incorporated
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
List of Tables
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
Table 3-17
Table 3-18
Table 3-19
Table 3-20
Table 3-21
Table 3-22
Table 3-23
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 5-1
Table 5-2
Table 6-1
Table 6-2
Characteristics of the TMS320C6654 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
EMIF16 / UART / No Boot Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
No Boot Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
UART Boot Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
EMIF16 Boot Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Ethernet (SGMII) Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
NAND Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PCI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
C66x DSP System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Terminal Functions — Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Terminal Functions — By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
TMS320C6654 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
IPC Generation Registers (IPCGRH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Device Speed Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Pin Control 0 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Pin Control 1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Pin Control 1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Switch Fabric Connection Matrix Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Switch Fabric Connection Matrix Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
EMAC / UPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Copyright 2012 Texas Instruments Incorporated
List of Tables
9
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 6-3
Table 6-4
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
Table 7-22
Table 7-23
Table 7-24
Table 7-25
Table 7-26
Table 7-27
Table 7-28
Table 7-29
Table 7-30
Table 7-31
Table 7-32
Table 7-33
Table 7-34
Table 7-35
Table 7-36
Table 7-37
Table 7-38
Table 7-39
Table 7-40
Table 7-41
Table 7-42
Table 7-43
Table 7-44
Table 7-45
Table 7-46
Table 7-47
Table 7-48
Table 7-49
Table 7-50
Table 7-51
Table 7-52
10
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Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Power Supply Rails on TMS320C6654 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Reset Configuration Register (RSTCFG) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Main PLL Controller/PCIe Clock Input Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
DDR3 PLL Control Register 0 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
DDR3 PLL Control Register 1 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
EDMA3 Transfer Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
EDMA3_CC Events for C6654 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
TMS320C6654 System Event Mapping — C66x CorePac Primary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
CIC1 Event Inputs (Secondary Events for EDMA3_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
CIC0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
CIC1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
NMI and Local Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
MPU4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
List of Tables
Copyright 2012 Texas Instruments Incorporated
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 7-53
Table 7-54
Table 7-55
Table 7-56
Table 7-57
Table 7-58
Table 7-59
Table 7-60
Table 7-61
Table 7-62
Table 7-63
Table 7-64
Table 7-65
Table 7-66
Table 7-67
Table 7-68
Table 7-69
Table 7-70
Table 7-71
Table 7-72
Table 7-73
Table 7-74
Table 7-75
Table 7-76
Table 7-77
Table 7-78
Table 7-79
Table 7-80
Table 7-81
Table 7-82
Table 7-83
Table 7-84
Table 7-85
Table 7-86
Table B-1
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Programmable Range n End Address Register (PROGn_MPEAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions . . . . . . . . . . . .178
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .180
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
I2C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
I2C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
EMIF16 Asynchronous Memory Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Ethernet MAC (EMAC) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
EMAC Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
EMAC Descriptor Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
SGMII Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
EMIC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
MDIO Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
MDIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
McBSP/FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
McBSP Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Universal Parallel Port (UPP) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
UPP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
UPP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Thermal Resistance Characteristics (PBGA Package) [CZH/GZH] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Copyright 2012 Texas Instruments Incorporated
List of Tables
11
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
12
List of Tables
www.ti.com
Copyright 2012 Texas Instruments Incorporated
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
• One TMS320C66x™ DSP Core Subsystem (CorePac)
With
– 850 MHz C66x Fixed/Floating-Point CPU Core
› 27.2 GMAC/Core for Fixed Point @ 850 MHz
› 13.6 GFLOP/Core for Floating Point @ 850 MHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– Memory Protection Unit for DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Peripherals
– PCIe Gen2
› Single Port Supporting 1 or 2 Lanes
› Supports Up To 5 GBaud Per Lane
– Gigabit Ethernet (GbE) Subsystem
› One SGMII Port
› Supports 10/100/1000 Mbps Operation
– 32-Bit DDR3 Interface
› DDR3-1066
› 8G Byte Addressable Memory Space
– 16-Bit EMIF
› Support For Up To 256MB NAND Flash and
128MB NOR Flash
› Support For Asynchronous SRAM up to 1MB
– Universal Parallel Port
› Two Channels of 8 bits or 16 bits Each
› Supports SDR and DDR Transfers
– Two UART Interfaces
– Two Multichannel Buffered Serial Ports (McBSP)
– I2C Interface
– 32 GPIO Pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Two On-Chip PLLs
– SoC Security Support
• Commercial Temperature:
– 0°C to 85°C
• Extended Temperature:
– - 40°C to 100°C
• Extended Low Temperature:
– - 55°C to 100°C
PRODUCT PREVIEW information applies to products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
Copyright 2012 Texas Instruments Incorporated
PRODUCT PREVIEW
1 Features
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
1.1 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores
with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
PRODUCT PREVIEW
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.2 Device Description
The TMS320C6654 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore
architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850
MHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and
automation, and other applications requiring high performance, TI's TMS320C6654 DSP offers up to 850 MHz
cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward
compatible with all existing C6000 family of fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory
subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize
intra-device and inter-device communication that allows the various DSP resources to operate efficiently and
seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data
management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and
contention-free internal data movement. The multicore shared memory controller allows access to shared and
external memory directly without drawing from switch fabric capacity.
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition,
the C66x core integrates floating point capability and the per core raw computational performance is an
industry-leading 32 MACS/cycle and 16 flops/cycle. It can execute 8 single precision floating point MAC operations
per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. The C66x core
incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented
processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal
processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's
previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software
development cycles for applications migrating to faster hardware.
The C6654 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache,
there is 1024KB of dedicated memory per core that can be configured as mapped RAM or cache. All L2 memories
incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit
DDR-3 external memory interface (EMIF) running at 1066 MHz and has ECC DRAM support.
14
Features
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS841—March 2012
This family supports a number of high speed standard interfaces, PCI Express Gen2, and Gigabit Ethernet. It also
includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port, and a 16-bit asynchronous
EMIF, along with general purpose CMOS IO.
PRODUCT PREVIEW
The C6654 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source
code execution.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Features
15
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
Figure 1-1
Functional Block Diagram
C6654
Memory Subsystem
32-Bit
DDR3 EMIF
MSMC
Debug & Trace
Boot ROM
PRODUCT PREVIEW
Semaphore
C66x™
CorePac
Timers
Security /
Key Manager
Power
Management
PLL
32KB L1
P-Cache
´2
32KB L1
D-Cache
1024KB L2 Cache
EDMA
1 Core @ 850 MHz
TeraNet
Multicore Navigator
PCIe ´2
McBSP ´2
SPI
UART ´2
I2C
UPP
GPIO
EMIF16
Queue
Manager
Packet
DMA
Ethernet
MAC
SGMII
16
Features
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2 Device Overview
2.1 Device Characteristics
Characteristics of the TMS320C6654 Processor
HARDWARE FEATURES
DDR3 Memory Controller (32-bit bus width)
[1.5 V I/O] (clock source = DDRREFCLKN|P)
DDR3 Maximum Data Rate
Peripheral
TMS320C6654
1
1066
EDMA3 (64 independent channels) [DSP/3 clock rate]
1
PCIe (2 lanes)
1
10/100/1000 Ethernet
1
Management Data Input/Output (MDIO)
1
EMIF16
1
McBSP
2
SPI
1
UART
2
UPP
1
I2 C
1
64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency)
General-Purpose Input/Output port (GPIO)
PRODUCT PREVIEW
Table 2-1
8 (each configurable as two 32-bit timers)
32
32KB L1 Program Memory [SRAM/Cache]
On-Chip Memory
CorePac Memory
32KB L1 Data Memory [SRAM/Cache]
1024KB L2 Unified Memory/Cache
ROM Memory
128KB L3 ROM
C66x CorePac
Revision ID
CorePac Revision ID Register (address location: 0181 2000h)
See Section 5.5 ‘‘C66x CorePac Revision’’ on
page 102.
JTAG BSDL_ID
JTAGID register (address location: 0262 0018h)
See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register
Description’’ on page 71
Frequency
MHz
Cycle Time
ns
Core (V)
Voltage
I/O (V)
Process
Technology
μm
BGA Package
21 mm × 21mm
Product Status
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
(1)
850 (0.85 GHz)
1.175 (0.85 GHz)
SmartReflex variable supply
1.0 V, 1.5 V, and 1.8 V
0.040 μm
625-Pin Flip-Chip Plastic BGA (CZH or GZH)
PP
End of Table 2-1
1 PRODUCT PREVIEW information applies to products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
17
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.2 DSP Core Description
The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through
enhancements and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data.
On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions.
C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to
perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also
supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process
multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g
execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP
programmers through the use of TI's optimized C/C++ compiler.
PRODUCT PREVIEW
The C66x DSP consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The
two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The
general-purpose registers can be used for data or can be data address pointers. The data types supported include
packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data.
40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and
the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data
values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the
remaining 96 MSBs in the next 3 upper registers.
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.
Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit
multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies
with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field
multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding
capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with
rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions
that multiply a complex number with a complex conjugate of another number with rounding capability.
Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable
of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability.
A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.
Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes
one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a
mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an
operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The
C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing
one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x
.M unit can also perform one the following floating-point operations each clock cycle: one, two, or four
single-precision multiplies or a complex single-precision multiply.
The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic,
logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were
added yielding performance enhancements of the floating point addition and subtraction instructions, including the
ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and
single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger
18
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS841—March 2012
The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall
until the completion of all the DSP-triggered memory transactions, including:
• Cache line fills
• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints
• Victim write backs
• Block or global coherence operations
• Cache mode changes
• Outstanding XMC prefetch requests
This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides
ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that
depend on ordering, and manual coherence operations.
For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following
documents:
• C66x CPU and Instruction Set Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 64.
• C66x DSP Cache User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
• C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
19
PRODUCT PREVIEW
operands, instructions were also added to double the number of these conversions that can be done. The .L unit also
has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of
complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the
conjugate of a complex number.
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Figure 2-1 shows the DSP core functional units and data paths.
Figure 2-1
DSP Core Data Paths
Note:
Default bus width
is 64 bits
(i.e. a register pair)
src1
.L1
Register
File A
(A0, A1, A2,
...A31)
src2
dst
ST1
src1
.S1
src2
dst
src1
src1_hi
PRODUCT PREVIEW
Data Path A
.M1
src2
src2_hi
dst2
dst1
LD1
32
src1
DA1
32
.D1
dst
32
src2
32
32
2´
1´
src2
DA2
32
.D2
dst
src1
Register
File B
(B0, B1, B2,
...B31)
32
32
32
32
32
LD2
dst1
dst2
src2_hi
.M2
src2
src1_hi
src1
Data Path B
dst
.S2
src2
src1
ST2
dst
.L2
src2
src1
32
Control
Register
32
20
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the TMS320C6654 device.
Memory Map Summary (Part 1 of 5)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
Description
00000000
007FFFFF
0 00000000
0 007FFFFF
8M
Reserved
00800000
008FFFFF
0 00800000
0 008FFFFF
1M
Local L2 SRAM
00900000
00DFFFFF
0 00900000
0 00DFFFFF
5M
Reserved
00E00000
00E07FFF
0 00E00000
0 00E07FFF
32K
Local L1P SRAM
00E08000
00EFFFFF
0 00E08000
0 00EFFFFF
1M-32K
Reserved
00F00000
00F07FFF
0 00F00000
0 00F07FFF
32K
Local L1D SRAM
00F08000
017FFFFF
0 00F08000
0 017FFFFF
9M-32K
Reserved
01800000
01BFFFFF
0 01800000
0 01BFFFFF
4M
C66x CorePac Registers
01C00000
01CFFFFF
0 01C00000
0 01CFFFFF
1M
Reserved
01D00000
01D0007F
0 01D00000
0 01D0007F
128
Trace 0
01D00080
01D07FFF
0 01D00080
0 01D07FFF
32K-128
Reserved
01D08000
01D0807F
0 01D08000
0 01D0807F
128
Reserved
01D08080
01D3FFFF
0 01D08080
0 01D3FFFF
224K-128
Reserved
01D40000
01D4007F
0 01D40000
0 01D4007F
128
Trace 1
01D40080
01D47FFF
0 01D40080
0 01D47FFF
32K-128
Reserved
01D48000
01D4807F
0 01D48000
0 01D4807F
128
Trace 2
01D48080
01D4FFFF
0 01D48080
0 01D4FFFF
32K-128
Reserved
01D50000
01D5007F
0 01D50000
0 01D5007F
128
Reserved
01D50080
01D57FFF
0 01D50080
0 01D57FFF
32K-128
Reserved
01D58000
01D5807F
0 01D58000
0 01D5807F
128
Trace 3
01D58080
01D5FFFF
0 01D58080
0 01D5FFFF
4464K -128
Reserved
021B4000
021B47FF
0 021B4000
0 021B47FF
2K
McBSP0 Registers
021B4800
021B5FFF
0 021B4800
0 021B5FFF
6K
Reserved
021B6000
021B67FF
0 021B6000
0 021B67FF
2K
McBSP0 FIFO Registers
021B6800
021B7FFF
0 021B6800
0 021B7FFF
6K
Reserved
021B8000
021B87FF
0 021B8000
0 021B87FF
2K
McBSP1 Registers
021B8800
021B9FFF
0 021B8800
0 021B9FFF
6K
Reserved
021BA000
021BA7FF
0 021BA000
0 021BA7FF
2K
McBSP1 FIFO Registers
021BA800
021BFFFF
0 021BA800
0 021BFFFF
22K
Reserved
021C0000
021C03FF
0 021C0000
0 021C03FF
1K
Reserved
021C0400
021CFFFF
0 021C0400
0 021CFFFF
63K
Reserved
021D0000
021D00FF
0 021D0000
0 021D00FF
256
Reserved
021D0100
021D3FFF
0 021D0100
0 021D3FFF
16K - 256
Reserved
021D4000
021D40FF
0 021D4000
0 021D40FF
256
Reserved
021D4100
021FFFFF
0 021D4100
0 021FFFFF
176K - 256
Reserved
02200000
0220007F
0 02200000
0 0220007F
128
Timer0
02200080
0220FFFF
0 02200080
0 0220FFFF
64K-128
Reserved
02210000
0221007F
0 02210000
0 0221007F
128
Timer1
02210080
0221FFFF
0 02210080
0 0221FFFF
64K-128
Reserved
02220000
0222007F
0 02220000
0 0222007F
128
Timer2
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
PRODUCT PREVIEW
Table 2-2
Device Overview
21
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-2
www.ti.com
Memory Map Summary (Part 2 of 5)
Logical 32-bit Address
Physical 36-bit Address
PRODUCT PREVIEW
Start
End
Start
End
Bytes
Description
02220080
0222FFFF
0 02220080
0 0222FFFF
64K-128
Reserved
02230000
0223007F
0 02230000
0 0223007F
128
Timer3
02230080
0223FFFF
0 02230080
0 0223FFFF
64K-128
Reserved
02240000
0224007F
0 02240000
0 0224007F
128
Timer4
02240080
0224FFFF
0 02240080
0 0224FFFF
64K-128
Reserved
02250000
0225007F
0 02250000
0 0225007F
128
Timer5
02250080
0225FFFF
0 02250080
0 0225FFFF
64K-128
Reserved
02260000
0226007F
0 02260000
0 0226007F
128
Timer6
02260080
0226FFFF
0 02260080
0 0226FFFF
64K-128
Reserved
02270000
0227007F
0 02270000
0 0227007F
128
Timer7
02270080
0230FFFF
0 02270080
0 0230FFFF
640K - 128
Reserved
02310000
023101FF
0 02310000
0 023101FF
512
PLL Controller
02310200
0231FFFF
0 02310200
0 0231FFFF
64K-512
Reserved
02320000
023200FF
0 02320000
0 023200FF
256
GPIO
02320100
0232FFFF
0 02320100
0 0232FFFF
64K-256
Reserved
02330000
023303FF
0 02330000
0 023303FF
1K
SmartReflex
02330400
0234FFFF
0 02330400
0 0234FFFF
127K
Reserved
02350000
02350FFF
0 02350000
0 02350FFF
4K
Power Sleep Controller (PSC)
02351000
0235FFFF
0 02351000
0 0235FFFF
64K-4K
Reserved
02360000
023603FF
0 02360000
0 023603FF
1K
Memory Protection Unit (MPU) 0
02360400
02367FFF
0 02360400
0 02367FFF
31K
Reserved
02368000
023683FF
0 02368000
0 023683FF
1K
Memory Protection Unit (MPU) 1
02368400
0236FFFF
0 02368400
0 0236FFFF
31K
Reserved
02370000
023703FF
0 02370000
0 023703FF
1K
Memory Protection Unit (MPU) 2
02370400
02377FFF
0 02370400
0 02377FFF
31K
Reserved
02378000
023783FF
0 02378000
0 023783FF
1K
Memory Protection Unit (MPU) 3
02378400
0237FFFF
0 02378400
0 0237FFFF
31K
Reserved
02380000
023803FF
0 02380000
0 023803FF
1K
Memory Protection Unit (MPU) 4
02380400
0243FFFF
0 02380400
0 0243FFFF
767K
Reserved
02440000
02443FFF
0 02440000
0 02443FFF
16K
DSP trace formatter 0
02444000
0244FFFF
0 02444000
0 0244FFFF
48K
Reserved
02450000
02453FFF
0 02450000
0 02453FFF
16K
Reserved
02454000
02521FFF
0 02454000
0 02521FFF
824K
Reserved
02522000
02522FFF
0 02522000
0 02522FFF
4K
Efuse
02523000
0252FFFF
0 02523000
0 0252FFFF
52K
Reserved
02530000
0253007F
0 02530000
0 0253007F
128
I C data & control
02530080
0253FFFF
0 02530080
0 0253FFFF
64K-128
Reserved
02540000
0254003F
0 02540000
0 0254003F
64
UART 0
02540400
0254FFFF
0 02540400
0 0254FFFF
64K-64
Reserved
02550000
0255003F
0 02550000
0 0255003F
64
UART 1
02550040
0257FFFF
0 02550040
0 0257FFFF
192K-64
Reserved
02580000
02580FFF
0 02580000
0 02580FFF
4K
UPP
02581000
025FFFFF
0 02581000
0 025FFFFF
508K
Reserved
22
Device Overview
2
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Memory Map Summary (Part 3 of 5)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
Description
02600000
02601FFF
0 02600000
0 02601FFF
8K
Chip Interrupt Controller (CIC) 0
02602000
02603FFF
0 02602000
0 02603FFF
8K
Reserved
02604000
02605FFF
0 02604000
0 02605FFF
8K
Chip Interrupt Controller (CIC) 1
02606000
02607FFF
0 02606000
0 02607FFF
8K
Reserved
02608000
02609FFF
0 02608000
0 02609FFF
8K
Reserved
0260A000
0261FFFF
0 0260A000
0 0261FFFF
88K
Reserved
02620000
026207FF
0 02620000
0 026207FF
2K
Chip-Level Registers
02620800
0263FFFF
0 02620800
0 0263FFFF
126K
Reserved
02640000
026407FF
0 02640000
0 026407FF
2K
Semaphore
02640800
0273FFFF
0 02640800
0 0273FFFF
1022K
Reserved
02740000
02747FFF
0 02740000
0 02747FFF
32K
EDMA Channel Controller (EDMA3CC)
02748000
0278FFFF
0 02748000
0 0278FFFF
288K
Reserved
02790000
027903FF
0 02790000
0 027903FF
1K
EDMA3CC Transfer Controller EDMA3TC0
02790400
02797FFF
0 02790400
0 02797FFF
31K
Reserved
02798000
027983FF
0 02798000
0 027983FF
1K
EDMA3CC Transfer Controller EDMA3TC1
02798400
0279FFFF
0 02798400
0 0279FFFF
31K
Reserved
027A0000
027A03FF
0 027A0000
0 027A03FF
1K
EDMA3CC Transfer Controller EDMA3TC2
027A0400
027A7FFF
0 027A0400
0 027A7FFF
31K
Reserved
027A8000
027A83FF
0 027A8000
0 027A83FF
1K
EDMA3CC Transfer Controller EDMA3TC3
027A8400
027CFFFF
0 027A8400
0 027CFFFF
159K
Reserved
027D0000
027D0FFF
0 027D0000
0 027D0FFF
4K
TI embedded trace buffer (TETB) - CorePac0
027D1000
027DFFFF
0 027D1000
0 027DFFFF
60K
Reserved
027E0000
027E0FFF
0 027E0000
0 027E0FFF
4K
Reserved
027E1000
0284FFFF
0 027E1000
0 0284FFFF
444K
Reserved
02850000
02857FFF
0 02850000
0 02857FFF
32K
TI embedded trace buffer (TETB) — system
02858000
028FFFFF
0 02858000
0 028FFFFF
672K
Reserved
02900000
02920FFF
0 02900000
0 02920FFF
132K
Reserved
02921000
029FFFFF
0 02921000
0 029FFFFF
1M-132K
Reserved
02A00000
02AFFFFF
0 02A00000
0 02AFFFFF
1M
Queue manager subsystem configuration
02B00000
02C07FFF
0 02B00000
0 02C07FFF
1056K
Reserved
02C08000
02C8BFFF
0 02C08000
0 02C8BFFF
16K
EMAC subsystem configuration
02C0C000
07FFFFFF
0 02C0C000
0 07FFFFFF
84M - 48K
Reserved
08000000
0800FFFF
0 08000000
0 0800FFFF
64K
Extended memory controller (XMC) configuration
08010000
0BBFFFFF
0 08010000
0 0BBFFFFF
60M-64K
Reserved
0BC00000
0BCFFFFF
0 0BC00000
0 0BCFFFFF
1M
Multicore shared memory controller (MSMC) config
0BD00000
0BFFFFFF
0 0BD00000
0 0BFFFFFF
3M
Reserved
0C000000
0C1FFFFF
0 0C000000
0 0C1FFFFF
1M
Reserved
0C200000
107FFFFF
0 0C200000
0 107FFFFF
71 M
Reserved
10800000
108FFFFF
0 10800000
0 108FFFFF
1M
CorePac0 L2 SRAM
10900000
10DFFFFF
0 10900000
0 10DFFFFF
5M
Reserved
10E00000
10E07FFF
0 10E00000
0 10E07FFF
32K
CorePac0 L1P SRAM
10E08000
10EFFFFF
0 10E08000
0 10EFFFFF
1M-32K
Reserved
10F00000
10F07FFF
0 10F00000
0 10F07FFF
32K
CorePac0 L1D SRAM
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
PRODUCT PREVIEW
Table 2-2
23
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-2
www.ti.com
Memory Map Summary (Part 4 of 5)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
Description
10F08000
117FFFFF
0 10F08000
0 117FFFFF
9M-32K
Reserved
11800000
118FFFFF
0 11800000
0 118FFFFF
1M
Reserved
11900000
11DFFFFF
0 11900000
0 11DFFFFF
5M
Reserved
11E00000
11E07FFF
0 11E00000
0 11E07FFF
32K
Reserved
11E08000
11EFFFFF
0 11E08000
0 11EFFFFF
1M-32K
Reserved
11F00000
11F07FFF
0 11F00000
0 11F07FFF
32K
Reserved
PRODUCT PREVIEW
11F08000
1FFFFFFF
0 11F08000
0 1FFFFFFF
225M-32K
Reserved
20000000
200FFFFF
0 20000000
0 200FFFFF
1M
System trace manager (STM) configuration
20100000
207FFFFF
0 20100000
0 207FFFFF
7M
Reserved
20800000
208FFFFF
0 20080000
0 208FFFFF
1M
Reserved
20900000
20AFFFFF
0 20900000
0 20AFFFFF
2M
Reserved
20B00000
20B1FFFF
0 20B00000
0 20B1FFFF
128K
Boot ROM
20B20000
20BEFFFF
0 20B20000
0 20BEFFFF
832K
Reserved
20BF0000
20BF01FF
0 20BF0000
0 20BF01FF
512
SPI
20BF0400
20BFFFFF
0 20BF0400
0 20BFFFFF
64K -512
Reserved
20C00000
20C000FF
0 20C00000
0 20C000FF
256
EMIF16 configuration
20C00100
20FFFFFF
0 20C00100
0 20FFFFFF
4M - 256
Reserved
21000000
210001FF
1 00000000
1 000001FF
512
DDR3 EMIF configuration
21000200
213FFFFF
0 21000200
0 213FFFFF
4M-512
Reserved
21400000
214000FF
0 21400000
0 214000FF
256
Reserved
21400100
217FFFFF
0 21400100
0 217FFFFF
4M-256
Reserved
21800000
21807FFF
0 21800000
0 21807FFF
32K
PCIe config
21808000
33FFFFFF
0 21808000
0 33FFFFFF
8M-32K
Reserved
22000000
22000FFF
0 22000000
0 22000FFF
4K
McBSP0 FIFO Data
22000100
223FFFFF
0 22000100
0 223FFFFF
4M-4K
Reserved
22400000
22400FFF
0 22400000
0 22400FFF
4K
McBSP1 FIFO Data
22400100
229FFFFF
0 22400100
0 229FFFFF
6M-4K
Reserved
22A00000
22A0FFFF
0 22A00000
0 22A0FFFF
64K
Reserved
22A01000
22AFFFFF
0 22A01000
0 22AFFFFF
1M-64K
Reserved
22B00000
22B0FFFF
0 22B00000
0 22B0FFFF
64K
Reserved
22B01000
33FFFFFF
0 22B01000
0 33FFFFFF
277M-64K
Reserved
34000000
341FFFFF
0 34000000
0 341FFFFF
2M
Queue manager subsystem data
34200000
3FFFFFFF
0 34200000
0 3FFFFFFF
190M
Reserved
40000000
4FFFFFFF
0 40000000
0 4FFFFFFF
256M
Reserved
50000000
5FFFFFFF
0 50000000
0 5FFFFFFF
256M
Reserved
60000000
6FFFFFFF
0 60000000
0 6FFFFFFF
256M
PCIe data
70000000
73FFFFFF
0 70000000
0 73FFFFFF
64M
EMIF16 CS2 data space, supports NAND, NOR, or SRAM
memory (1)
74000000
77FFFFFF
0 74000000
0 77FFFFFF
64M
EMIF16 CS3 data space, supports NAND, NOR, or SRAM
(1)
memory
78000000
7BFFFFFF
0 78000000
0 7BFFFFFF
64M
EMIF16 CS4 data space, supports NAND, NOR, or SRAM
(1)
memory
24
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 2-2
Memory Map Summary (Part 5 of 5)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
Description
7C000000
7FFFFFFF
0 7C000000
0 7FFFFFFF
64M
EMIF16 CS5 data space, supports NAND, NOR or SRAM
(1)
memory
80000000
FFFFFFFF
8 00000000
8 7FFFFFFF
2G
DDR3 EMIF data
End of Table 2-2
1 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. More than 32MB allowed by NAND flash
The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect
the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section
7.4 ‘‘Reset Controller’’ on page 119. The bootloader uses a section of the L2 SRAM (start address 0x0087 2DC0 and
end address 0x0087 FFFF) during initial booting of the device. For more details on the type of configurations stored
in this reserved L2 section see the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 64.
The C6654 supports several boot processes that begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software-driven and use
the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be
completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
2.5 Boot Modes Supported and PLL Settings
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[2:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:
• Public ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base
address. After performing the boot process (e.g., from I2C ROM, Ethernet, or RapidIO), C66x CorePac0 then
begins execution from the provided boot entry point. For C6657 only, the other C66x CorePac is released from
reset and begins executing an IDLE from the L3 ROM. It is then released from IDLE based on interrupts
generated by C66x CorePac0. See the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation
from Texas Instruments’’ on page 64 for more details.
• Secure ROM Boot - On secure devices, the C66x CorePac0 is released from reset and begin executing from
secure ROM. Software in the secure ROM will free up internal RAM pages, after which C66x CorePac0
initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the
bootloaded image prior to beginning execution.
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TI Confidential—NDA Restrictions
Device Overview
25
PRODUCT PREVIEW
2.4 Boot Sequence
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by
the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the
associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].
Figure 2-2
Boot Mode Pin Decoding
Boot Mode Pins
12
11
10
9
8
7
2
PLL Mult I C /SPI Ext Dev Cfg
6
5
4
3
2
Device Configuration
1
0
Boot Device
2.5.1 Boot Device Field
PRODUCT PREVIEW
The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 shows the supported boot
modes.
Table 2-3
Boot Mode Pins: Boot Device Values
Bit
Field
Description
2-0
Boot Device
Device boot mode
0 = EMIF16 / UART / No Boot
1 = Reserved
2 = Ethernet (SGMII)
3 = NAND
4 = PCIe
5 = I2C
6 = SPI
7 = Reserved
End of Table 2-3
2.5.2 Device Configuration Field
The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit
definitions depend on the boot mode.
2.5.2.1 EMIF16 / UART / No Boot Device Configuration
Figure 2-3
EMIF16 / UART / No Boot Configuration Fields
9
8
7
6
Sub-Mode Specific Configuration
Table 2-4
5
4
3
Sub-Mode
EMIF16 / UART / No Boot Configuration Field Descriptions
Bit
Field
Description
9-6
Sub-Mode
Specific
Configuration
Configures the selected sub-mode. See sections 2.5.2.1.1 ‘‘No Boot Mode’’, 2.5.2.1.2 ‘‘UART Boot Mode’’, and
2.5.2.1.3 ‘‘EMIF16 Boot Mode’’
5-3
Sub-Mode
Sub mode selection.
0 = No boot
1 = UART port 0 boot
2 - 3 = Reserved
4 = EMIF16 boot
5 = UART port 1 boot
6 - 7 = Reserved
End of Table 2-4
26
Device Overview
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.5.2.1.1 No Boot Mode
Figure 2-4
No Boot Configuration Fields
9
8
7
6
7
6
Reserved
Table 2-5
No Boot Configuration Field Descriptions
Bit
Field
9-6
Reserved
Description
Reserved
PRODUCT PREVIEW
End of Table 2-5
2.5.2.1.2 UART Boot Mode
Figure 2-5
UART Boot Configuration Fields
9
8
Speed
Table 2-6
Parity
UART Boot Configuration Field Descriptions
Bit
Field
Description
9-8
Speed
UART interface speed.
0 = 115200 baud
1 = 38400 baud
2 = 19200 baud
3 = 9600 baud
7-6
Parity
UART parity used during boot.
0 = None
1 = Odd
2 = Even
4 = None
End of Table 2-6
2.5.2.1.3 EMIF16 Boot Mode
Figure 2-6
EMIF16 Boot Configuration Fields
9
8
Wait Enable
Width Select
Table 2-7
7
6
Chip Select
EMIF16 Boot Configuration Field Descriptions (Part 1 of 2)
Bit
Field
Description
9
Wait Enable
Extended Wait mode for EMIF16.
0 = Wait enable disabled (EMIF16 sub mode)
1 = Wait enable enabled (EMIF16 sub mode)
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Device Overview
27
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-7
www.ti.com
EMIF16 Boot Configuration Field Descriptions (Part 2 of 2)
Bit
Field
Description
8
Width Select
EMIF data width for EMIF16.
0 = 8-bit wide EMIF (EMIF16 sub mode)
1 = 16-bit wide EMIF (EMIF16 sub mode)
7-6
Chip Select
EMIF Chip Select used during EMIF 16 boot.
0 = CS2
1 = CS3
2 = CS4
4 = CS5
End of Table 2-7
PRODUCT PREVIEW
2.5.2.2 Ethernet (SGMII) Boot Device Configuration
Figure 2-7
Ethernet (SGMII) Device Configuration Fields
9
8
7
SerDes Clock Mult
Table 2-8
6
5
4
Ext connection
3
Device ID
Ethernet (SGMII) Configuration Field Descriptions
Bit
Field
Description
9-8
SerDes Clock Mult
SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.
0 = ×8 for input clock of 156.25 MHz
1 = ×5 for input clock of 250 MHz
2 = ×4 for input clock of 312.5 MHz
3 = Reserved
7-6
Ext connection
External connection mode
0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave, and MAC to PHY
2 = MAC to MAC, forced link
3 = MAC to fiber connection
5-3
Device ID
This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.
End of Table 2-8
2.5.2.3 NAND Boot Device Configuration
Figure 2-8
NAND Device Configuration Fields
9
8
7
6
st
1 Block
Table 2-9
Bit
9-5
28
5
4
3
2
Reserved
IC
NAND Configuration Field Descriptions (Part 1 of 2)
Field
st
1 Block
Device Overview
Description
NAND Block to be read first by the boot ROM.
0 = Block 0
...
31 = Block 31
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 2-9
Bit
NAND Configuration Field Descriptions (Part 2 of 2)
Field
Description
2
4
IC
NAND parameters read from I2C EEPROM
2
0 = Parameters are not read from I C
1 = Parameters are read from I2C
3
Reserved
Reserved
End of Table 2-9
2.5.2.4 PCI Boot Device Configuration
Extra device configuration is provided in the PCI bits in the DEVSTAT register.
PCI Device Configuration Fields
9
8
7
Ref Clock
Table 2-10
6
5
4
PRODUCT PREVIEW
Figure 2-9
3
BAR Config
Reserved
PCI Device Configuration Field Descriptions
Bit
Field
Description
9
Ref Clock
PCIe reference clock configuration
0 = 100 MHz
1 = 250 MHz
8-5
BAR Config
PCIe BAR registers configuration
4-3
Reserved
Reserved
This value can range from 0 to 0xf. See Table 2-11.
End of Table 2-10
Table 2-11
BAR Config / PCIe Window Sizes
32-Bit Address Translation
BAR1
BAR2
BAR3
BAR4
0b0000
BAR cfg
BAR0
32
32
32
32
0b0001
16
16
32
64
0b0010
16
32
32
64
0b0011
32
32
32
64
0b0100
16
16
64
64
0b0101
16
32
64
64
0b0110
32
32
64
64
32
32
64
128
64
64
128
256
0b1001
4
128
128
128
0b1010
4
128
128
256
0b1011
4
128
256
256
64-Bit Address Translation
BAR2/3
BAR4/5
0b1100
256
256
0b1101
512
512
0b1110
1024
1024
0b1111
2048
2048
0b0111
0b1000
PCIe MMRs
BAR5
Clone of BAR4
End of Table 2-11
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Device Overview
29
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2
2.5.2.5 I C Boot Device Configuration
2.5.2.5.1 I2C Master Mode
2
In master mode, the I C device configuration uses ten bits of device configuration instead of seven as used in other
boot modes. In this mode, the device will make the initial read of the I2C EEPROM while the PLL is in bypass mode.
The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.
I2C Master Mode Device Configuration Bit Fields
Figure 2-10
12
11
Mode
Table 2-12
10
Address
9
8
7
Speed
6
5
4
3
Parameter Index
I2C Master Mode Device Configuration Field Descriptions
PRODUCT PREVIEW
Bit
Field
Description
12
Mode
I C operation mode
0 = Master mode
2
1 = Passive mode (see section 2.5.2.5.2 ‘‘I C Passive Mode’’)
11 - 10
Address
I2C bus address configuration
2
2
0 = Boot from I C EEPROM at I C bus address 0x50
1 = Boot from I2C EEPROM at I2C bus address 0x51
2
2
2= Boot from I C EEPROM at I C bus address 0x52
2
3= Boot from I C EEPROM at I2C bus address 0x53
9
Speed
I C data rate configuration
0 = I2C slow mode. Initial data rate is SYSCLKIN / 5000 until PLLs and clocks are programmed
2
1 = I C fast mode. Initial data rate is SYSCLKIN / 250 until PLLs and clocks are programmed
8-3
Parameter Index
Identifies the index of the configuration table initially read from the I C EEPROM
2
2
2
This value can range from 0 to 31.
End of Table 2-12
2.5.2.5.2 I2C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
I2C Passive Mode Device Configuration Bit Fields
Figure 2-11
12
11
10
Mode
Table 2-13
9
8
7
6
Address
5
4
3
Reserved
I2C Passive Mode Device Configuration Field Descriptions
Bit
Field
Description
12
Mode
I C operation mode
2
0 = Master mode (see section 2.5.2.5.1 ‘‘I C Master Mode’’)
1 = Passive mode
11 - 5
Address
I2C bus address accepted during boot. Value may range from 0x00 to 0x7F
4-3
Reserved
Reserved
2
End of Table 2-13
30
Device Overview
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.5.2.6 SPI Boot Device Configuration
In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.
SPI Device Configuration Bit Fields
12
11
Mode
Table 2-14
10
9
4, 5 Pin
Addr Width
8
7
Chip Select
6
5
4
3
Parameter Table Index
SPI Device Configuration Field Descriptions
Bit
Field
Description
12-11
Mode
Clk Pol / Phase
0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data
is latched on the rising edge of SPICLK.
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data
is latched on the falling edge of SPICLK.
10
4, 5 Pin
SPI operation mode configuration
0 = 4-pin mode used
1 = 5-pin mode used
9
Addr Width
SPI address width configuration
0 = 16-bit address values are used
1 = 24-bit address values are used
8-7
Chip Select
The chip select field value
6-3
Parameter Table Index
Specifies which parameter table is loaded
End of Table 2-14
Copyright 2012 Texas Instruments Incorporated
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Device Overview
31
PRODUCT PREVIEW
Figure 2-12
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.5.3 PLL Boot Configuration Settings
The PLL default settings are determined by the BOOTMODE[12:10] bits. The following table shows settings for
various input clock frequencies.
Table 2-15
C66x DSP System PLL Configuration (1)
850 MHz Device
PRODUCT PREVIEW
BOOTMODE [12:10]
Input Clock Freq (MHz)
0b000
50.00
0
PLLD
33
PLLM
850
DSP ƒ
0b001
66.67
1
50
850.04
0b010
80.00
3
84
850
0b011
100.00
0
16
850
0b100
156.25
49
543
850
0b101
250.00
4
33
850
0b110
312.50
49
271
850
0b111
122.88
5
82
849.92
End of Table 2-15
1 The PLL boot configuration table above may not include all the frequency values that the device supports.
OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting
for the device (with OUTPUT_DIVIDE=2, by default).
CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1))
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL is controlled by chip level
MMRs. For details on how to set up the PLL see section 7.5 ‘‘Main PLL and PLL Controller’’ on page 126. For details
on the operation of the PLL controller module, see the Phase Locked Loop (PLL)
Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.
32
Device Overview
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.7 Terminals
2.7.1 Package Terminals
Figure 2-13 shows the TMS320C6654CZH and GZH ball grid area (BGA) packages (bottom view).
Figure 2-13
CZH/GZH 625-Pin BGA Package (Bottom View)
AD
AB
Y
AE
AC
AA
W
V
T
U
R
P
N
PRODUCT PREVIEW
M
L
K
J
H
F
D
G
E
C
B
A
3
1
2
5
4
9
7
6
8
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24
2.7.2 Pin Map
Figure 2-15 through Figure 2-18 show the TMS320C6654 pin assignments in four quadrants (A, B, C, and D).
Figure 2-14
Pin Map Quadrants (Bottom View)
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
A
B
D
C
Device Overview
33
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 2-15
www.ti.com
Upper Left Quadrant—A (Bottom View)
PRODUCT PREVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
AE
VSS
SGMII0
RXN
SGMII0
RXP
VSS
RIORXN2
RIORXP2
VSS
RIORXP0
RIORXN0
VSS
PCIERXP0
PCIERXN0
VSS
AD
VSS
VSS
VSS
RIORXN3
RIORXP3
VSS
RIORXP1
RIORXN1
VSS
PCIERXN1
PCIERXP1
VSS
SRIOSGMII
CLKP
AC
VSS
SGMII0
TXN
SGMII0
TXP
VSS
RIOTXN2
RIOTXP2
VSS
RIOTXP0
RIOTXN0
VSS
PCIETXP0
PCIETXN0
VSS
AB
EMIFD14
VSS
RSV19
RIOTXN3
RIOTXP3
VSS
RIOTXN1
RIOTXP1
VSS
PCIETXP1
PCIETXN1
VSS
SPIDOUT
AA
EMIFD13
EMIFD15
VDDR3
VSS
VDDR4
VSS
RSV17
VSS
VDDR2
VSS
RSV18
SPISCS0
SPICLK
Y
EMIFD09
EMIFD11
DVDD18
RSV13
RSV12
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
DVDD18
W
EMIFD06
EMIFD08
VSS
EMIFD10
EMIFD12
DVDD18
VSS
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
V
EMIFD02
EMIFD03
EMIFD04
EMIFD05
EMIFD07
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
U
EMIFA21
EMIFA22
EMIFA23
EMIFD00
EMIFD01
DVDD18
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
T
EMIFA19
VSS
DVDD18
EMIFA18
EMIFA20
VSS
DVDD18
VSS
CVDD1
VSS
CVDD
VSS
CVDD
R
EMIFA17
EMIFA16
EMIFA14
EMIFA15
EMIFA13
DVDD18
VSS
VSS
VSS
CVDD
VSS
CVDD
VSS
P
EMIFA12
EMIFA11
EMIFA09
EMIFA05
EMIFA03
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
N
EMIFA10
EMIFA08
DVDD18
VSS
EMIF
WAIT0
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
A
34
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Upper Right Quadrant—B (Bottom View)
14
15
16
17
18
19
20
21
22
23
24
25
SRIOSGMII
CLKN
PCIECLKN
UARTCTS1
TDI
TMS
CORECLKN
TIMO1
TIMI1
DX1
FSX1
CLKX1
VSS
AE
PCIECLKP
UARTRTS1
VSS
TCK
CORECLKP
TDO
TIMI0
DR1
FSR1
CLKR1
FSR0
EMU16
AD
UARTRXD1
UARTTXD1
DVDD18
UARTCTS
RSV04
TIMO0
DVDD18
CLKS1
DX0
CLKS0
EMU17
EMU13
AC
SPIDIN
UARTRXD
MDIO
UARTRTS
RSV05
TRST
VSS
DR0
EMU15
DVDD18
VSS
EMU12
AB
SPISCS1
UARTTXD
MDCLK
SCL
SDA
SYSCLKOUT
FSX0
CLKR0
RSV01
EMU14
EMU10
EMU11
AA
VSS
AVDDA1
VSS
DVDD18
POR
RSV08
CLKX0
EMU18
EMU09
EMU07
EMU06
EMU05
Y
DVDD18
VSS
DVDD18
VSS
DVDD18
VSS
DVDD18
GPIO14
EMU08
EMU03
EMU04
EMU02
W
VSS
CVDD
VSS
CVDD
VSS
DVDD18
VSS
GPIO15
GPIO13
GPIO10
EMU00
EMU01
V
CVDD
VSS
CVDD
VSS
CVDD1
VSS
DVDD18
GPIO11
GPIO08
GPIO09
GPIO05
GPIO03
U
VSS
CVDD
VSS
CVDD1
VSS
DVDD18
VSS
GPIO12
GPIO06
GPIO04
DVDD18
GPIO00
T
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
GPIO07
VSS
GPIO02
VSS
GPIO01
R
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
MCMTXN0
VSS
MCMRXN0
VSS
P
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDT1
MCMTXN1
MCMTXP0
VSS
MCMRXP0
MCMRXP1
N
PRODUCT PREVIEW
Figure 2-16
B
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
35
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 2-17
www.ti.com
Lower Right Quadrant—C (Bottom View)
C
PRODUCT PREVIEW
VSS
CVDD
VSS
CVDD
VSS
VDDT1
VDDR1
MCM
TXP1
VSS
VSS
VSS
MCMRXN1
M
CVDD
VSS
CVDD
VSS
CVDD
VSS
VDDT1
VSS
MCMTXP2
VSS
MCMRXP3
VSS
L
VSS
CVDD
VSS
CVDD1
VSS
VDDT1
VSS
MCMTXP3
MCMTXN2
VSS
MCMRXN3
MCMRXP2
K
CVDD
VSS
CVDD
VSS
CVDD1
VSS
RSV16
MCMTXN3
VSS
VSS
VSS
MCMRXN2
J
VSS
CVDD
VSS
CVDD
VSS
DVDD18
VSS
VSS
RSV11
VSS
DVDD18
VSS
H
DVDD15
VSS
DVDD15
VSS
DVDD15
RSV0A
RSV0B
RSV15
RSV10
VCNTL3
MCMTX
PMDAT
MCMREF
CLKOUTP
G
VSS
PTV15
VSS
DVDD15
VSS
DVDD15
AVDDA2
RSV14
RSV20
VCNTL2
MCMTX
PMCLK
MCMREF
CLKOUTN
F
DDRODT0
DDRA03
DDRA02
DDRA15
DDRA14
DDRA10
DDRA09
DVDD18
VCNTL0
VCNTL1
MCMRX
PMCLK
MCMTX
FLCLK
E
DDRCAS
DVDD15
DDRA00
DDRBA1
DDRA12
DVDD15
DDRA08
VSS
DDRSL
RATE1
RSV21
MCMRX
PMDAT
MCMTX
FLDAT
D
DDRCE1
VSS
DDRA06
DVDD15
DDRBA0
VSS
DDRA13
DVDD15
DDRSL
RATE0
RSV09
MCMRX
FLDAT
MCMCLKP
C
DDRCLK
OUTN0
DDRCE0
DDRRESET
VSS
DDRA04
DDRBA2
DDRA11
DDRCLK
OUTN1
DDRCLKN
RSV06
MCMRX
FLCLK
MCMCLKN
B
DDRCLK
OUTP0
DDRRAS
DDRCKE0
DDRA05
DDRA07
DDRA01
DDRCKE1
DDRCLK
OUTP1
DDRCLKP
RSV07
DVDD18
VSS
A
14
15
16
17
18
19
20
21
22
23
24
25
36
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Figure 2-18
Lower Left Quadrant—D (Bottom View)
M
EMIFA07
EMIFA06
EMIFA01
EMIFWAIT1
EMIFCE3
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
L
EMIFA04
EMIFA02
EMIFBE1
EMIFOE
EMIF
RNW
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
K
EMIFA00
VSS
DVDD18
EMIFWE
EMIFCE0
VSS
DVDD18
VSS
CVDD1
VSS
CVDD
VSS
CVDD
J
EMIFBE0
EMIFCE2
RSV02
DVDD18
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
H
NMI
RSV03
BOOT
COMPLETE
RESET
RESETSTAT
VSS
DVDD18
VSS
CVDD
VSS
CVDD
VSS
CVDD
G
EMIFCE1
HOUT
DVDD18
LRESET
CORESEL1
DVDD18
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
F
LRESET
NMIEN
DDRD25
VSS
DDRD18
DDRDQM2
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
E
DDRDQM3
DDRD24
DDRD31
DDRD19
DDRD16
DDRD08
DDR
DQM1
DDRD09
DDRD04
DDRD05
VSS
VREFSSTL
DDRWE
D
DDRD28
DVDD15
DDRD29
DVDD15
DDRD23
DDRD12
DDRD14
DVDD15
DDRD02
DDR
DQS0P
DDRCB00
DDRODT1
DVDD15
C
DDRD27
VSS
DDRD30
VSS
DDRD22
DVDD15
DDRD13
VSS
DDRD01
DDR
DQS0N
DDRCB02
DDRDQM8
VSS
B
DDRD26
DDR
DQS3N
DDRD17
DDR
DQS2P
DDRD21
VSS
DDR
DQS1P
DDRD15
DDRD03
DVDD15
DDRD07
DDRCB01
DDR
DQS8P
A
VSS
DDR
DQS3P
DDRD20
DDR
DQS2N
DDRD11
DDRD10
DDR
DQS1N
DDR
DQM0
DDRD00
VSS
DDRD06
DDRCB03
DDR
DQS8N
1
2
3
4
5
6
7
8
9
10
11
12
13
RESETFULL CORESEL0
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
PRODUCT PREVIEW
D
37
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.8 Terminal Functions
The terminal functions table (Table 2-17) identifies the external signal names, the associated pin (ball) numbers, the
pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin
descriptions. This table is arranged by function. The power terminal functions table (Table 2-18) lists the various
power supply pins and ground pins and gives functional pin descriptions. Table 2-19 shows all pins arranged by
signal name. Table 2-20 shows all pins arranged by ball number.
There are 73 pins that have a secondary function as well as a primary function. The secondary function is indicated
with a dagger (†). There is one pin that has a tertiary function as well as primary and secondary functions. The
tertiary function is indicated with a double dagger (‡).
PRODUCT PREVIEW
For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and
pullup/pulldown resistors, see section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 86.
Use the symbol definitions in Table 2-16 when reading Table 2-17.
Table 2-16
I/O Functional Symbol Definitions
Functional
Symbol
IPD or IPU
A
Table 2-17
Column Heading
Definition
Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can
be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and
situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for
KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 64.
IPD/IPU
Analog signal
Type
Ground
Type
Input terminal
Type
O
Output terminal
Type
S
Supply voltage
Type
Z
Three-state terminal or high impedance
Type
GND
I
End of Table 2-16
Table 2-17
Terminal Functions — Signals and Control by Function (Part 1 of 13)
Signal Name
Ball No. Type
IPD/IPU
Description
LENDIAN †
T25
IOZ
UP
Endian configuration pin (Pin shared with GPIO[0])
BOOTMODE00 †
R25
IOZ
Down
BOOTMODE01†
R23
IOZ
Down
BOOTMODE02 †
U25
IOZ
Down
BOOTMODE03 †
T23
IOZ
Down
BOOTMODE04 †
U24
IOZ
Down
BOOTMODE05 †
T22
IOZ
Down
BOOTMODE06 †
R21
IOZ
Down
BOOTMODE07 †
U22
IOZ
Down
BOOTMODE08 †
U23
IOZ
Down
BOOTMODE09 †
V23
IOZ
Down
BOOTMODE10 †
U21
IOZ
Down
BOOTMODE11 †
T21
IOZ
Down
BOOTMODE12 †
V22
IOZ
Down
Boot Configuration Pins
38
Device Overview
See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 25 for more details
(Pins shared with GPIO[1:13])
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 2-17
Terminal Functions — Signals and Control by Function (Part 2 of 13)
Signal Name
Ball No. Type
IPD/IPU
PCIESSMODE0 †
W21
IOZ
Down
Description
PCIESSMODE1 †
V21
IOZ
Down
PCIESSEN ‡
AD20
I
Down
CORECLKP
AD18
I
CORECLKN
AE19
I
SRIOSGMIICLKP
AD13
I
SRIOSGMIICLKN
AE14
I
DDRCLKP
A22
I
DDRCLKN
B22
I
PCIECLKP
AD14
I
PCIECLKN
AE15
I
MCMCLKP
C25
I
MCMCLKN
B25
I
AVDDA1
Y15
P
AVDDA2
F20
P
SYSCLKOUT
AA19
OZ
Down
System Clock Output to be used as a general purpose output clock for debug purposes
HOUT
G2
OZ
UP
Interrupt output pulse created by IPCGRH
NMI
H1
I
UP
Non-maskable Interrupt
LRESET
G4
I
UP
Warm Reset
LRESETNMIEN
F1
I
UP
Enable for core selects
Select for the target core for LRESET and NMI. For more details see Table 7-40‘‘NMI and Local Reset
Timing Requirements’’ on page 165
PCIe Mode selection pins (Pins shared with GPIO[14:15])
PCIe module enable (Pin shared with TIMI0 and GPIO16)
Clock / Reset
Core Clock Input to main PLL.
SGMII Reference Clock to drive the SGMII SerDes
PCIe Clock Input to drive PCIe SerDes
Reserved
SYS_CLK PLL Power Supply Pin
DDR_CLK PLL Power Supply Pin
CORESEL0
J5
I
Down
CORESEL1
G5
I
Down
RESETFULL
J4
I
UP
Full Reset
RESET
H4
I
UP
Warm Reset of non isolated portion on the IC
POR
Y18
I
RESETSTAT
H5
O
UP
Reset Status Output
BOOTCOMPLETE
H3
OZ
Down
Boot progress indication output
PTV15
F15
A
Power-on Reset
PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15 pin and
ground is used to closely tune the output impedance of the DDR interface drivers to 50ohms.
Presently the recommended value for this 1% resistor is 45.3 ohms.
DDR
DDRDQM0
A8
OZ
DDRDQM1
E7
OZ
DDRDQM2
F5
OZ
DDRDQM3
E1
OZ
DDRDQM8
C12
OZ
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
DDR EMIF Data Masks
Device Overview
39
PRODUCT PREVIEW
DDR Reference Clock Input to DDR PLL
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-17
www.ti.com
Terminal Functions — Signals and Control by Function (Part 3 of 13)
PRODUCT PREVIEW
Signal Name
Ball No. Type
DDRDQS0P
D10
IOZ
DDRDQS0N
C10
IOZ
DDRDQS1P
B7
IOZ
DDRDQS1N
A7
IOZ
DDRDQS2P
B4
IOZ
DDRDQS2N
A4
IOZ
DDRDQS3P
A2
IOZ
DDRDQS3N
B2
IOZ
DDRDQS8P
B13
IOZ
DDRDQS8N
A13
IOZ
DDRCB00
D11
IOZ
DDRCB01
B12
IOZ
DDRCB02
C11
IOZ
DDRCB03
A12
IOZ
DDRD00
A9
IOZ
DDRD01
C9
IOZ
DDRD02
D9
IOZ
DDRD03
B9
IOZ
DDRD04
E9
IOZ
DDRD05
E10
IOZ
DDRD06
A11
IOZ
DDRD07
B11
IOZ
DDRD08
E6
IOZ
DDRD09
E8
IOZ
DDRD10
A6
IOZ
DDRD11
A5
IOZ
DDRD12
D6
IOZ
DDRD13
C7
IOZ
DDRD14
D7
IOZ
DDRD15
B8
IOZ
DDRD16
E5
IOZ
DDRD17
B3
IOZ
DDRD18
F4
IOZ
DDRD19
E4
IOZ
DDRD20
A3
IOZ
DDRD21
B5
IOZ
DDRD22
C5
IOZ
DDRD23
D5
IOZ
DDRD24
E2
IOZ
DDRD25
F2
IOZ
DDRD26
B1
IOZ
DDRD27
C1
IOZ
DDRD28
D1
IOZ
DDRD29
D3
IOZ
40
Device Overview
IPD/IPU
Description
DDR EMIF Data Strobe
DDR EMIF Check Bits
DDR EMIF Data Bus
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Terminal Functions — Signals and Control by Function (Part 4 of 13)
Signal Name
Ball No. Type
DDRD30
C3
IOZ
DDRD31
E3
IOZ
DDRCE0
B15
OZ
DDRCE1
C14
OZ
DDRBA0
C18
OZ
DDRBA1
D17
OZ
DDRBA2
B19
OZ
DDRA00
D16
OZ
DDRA01
A19
OZ
DDRA02
E16
OZ
DDRA03
E15
OZ
DDRA04
B18
OZ
DDRA05
A17
OZ
IPD/IPU
Description
DDR EMIF Data Bus
DDR EMIF Chip Enables
DDR EMIF Bank Address
DDRA06
C16
OZ
DDRA07
A18
OZ
DDRA08
D20
OZ
DDRA09
E20
OZ
DDRA10
E19
OZ
DDRA11
B20
OZ
DDRA12
D18
OZ
DDRA13
C20
OZ
DDRA14
E18
OZ
DDRA15
E17
OZ
DDRCAS
D14
OZ
DDR EMIF Column Address Strobe
DDRRAS
A15
OZ
DDR EMIF Row Address Strobe
DDRWE
E13
OZ
DDR EMIF Write Enable
DDRCKE0
A16
OZ
DDR EMIF Clock Enable
DDR EMIF Clock Enable
DDRCKE1
A20
OZ
DDRCLKOUTP0
A14
OZ
DDRCLKOUTN0
B14
OZ
DDRCLKOUTP1
A21
OZ
DDRCLKOUTN1
B21
OZ
DDRODT0
E14
OZ
PRODUCT PREVIEW
Table 2-17
DDR EMIF Address Bus
DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDRODT1
D12
OZ
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDRRESET
B16
OZ
DDR Reset signal
DDRSLRATE0
C22
I
Down
DDRSLRATE1
D22
I
Down
VREFSSTL
E12
P
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
DDR Slew rate control
Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)
Device Overview
41
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-17
Signal Name
www.ti.com
Terminal Functions — Signals and Control by Function (Part 5 of 13)
Ball No. Type
IPD/IPU
Description
EMIF16
PRODUCT PREVIEW
EMIFRW
L5
OZ
UP
EMIFCE0
K5
OZ
UP
EMIFCE1
G1
OZ
UP
EMIFCE2
J2
OZ
UP
EMIFCE3
M5
OZ
UP
EMIFOE
L4
OZ
UP
EMIFWE
K4
OZ
UP
EMIFBE0
J1
OZ
UP
EMIFBE1
L3
OZ
UP
EMIFWAIT0
N5
I
Down
EMIFWAIT1
M4
I
Down
EMIF16 Control Signals
EMIF16 Control Signal
This EMIF16 pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘UPP’’ on page 43
EMIFA00
K1
OZ
Down
EMIFA01
M3
OZ
Down
EMIFA02
L2
OZ
Down
EMIFA03
P5
OZ
Down
EMIFA04
L1
OZ
Down
EMIFA05
P4
OZ
Down
EMIFA06
M2
OZ
Down
EMIFA07
M1
OZ
Down
EMIFA08
N2
OZ
Down
EMIFA09
P3
OZ
Down
EMIFA10
N1
OZ
Down
EMIFA11
P2
OZ
Down
EMIFA12
P1
OZ
Down
EMIFA13
R5
OZ
Down
EMIFA14
R3
OZ
Down
EMIFA15
R4
OZ
Down
EMIFA16
R2
OZ
Down
EMIFA17
R1
OZ
Down
EMIFA18
T4
OZ
Down
EMIFA19
T1
OZ
Down
EMIFA20
T5
OZ
Down
EMIFA21
U1
OZ
Down
EMIFA22
U2
OZ
Down
EMIFA23
U3
OZ
Down
42
Device Overview
EMIF16 Address
These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this
table: ‘‘UPP’’ on page 43
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Terminal Functions — Signals and Control by Function (Part 6 of 13)
Signal Name
Ball No. Type
IPD/IPU
EMIFD00
U4
IOZ
Down
Description
EMIFD01
U5
IOZ
Down
EMIFD02
V1
IOZ
Down
EMIFD03
V2
IOZ
Down
EMIFD04
V3
IOZ
Down
EMIFD05
V4
IOZ
Down
EMIFD06
W1
IOZ
Down
EMIF16 Data
EMIFD07
V5
IOZ
Down
EMIFD08
W2
IOZ
Down
These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this
table: ‘‘UPP’’ on page 43.
EMIFD09
Y1
IOZ
Down
EMIFD10
W4
IOZ
Down
EMIFD11
Y2
IOZ
Down
EMIFD12
W5
IOZ
Down
EMIFD13
AA1
IOZ
Down
EMIFD14
AB1
IOZ
Down
EMIFD15
AA2
IOZ
Down
UPP
UPP_2XTXCLK †
M4
I
Down
UPP Transmit Reference Clock (2x Transmit Rate)
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH0_CLK †
R2
OZ
Down
UPP Channel 0 Clock
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH0_START †
R1
OZ
Down
UPP Channel 0 Start
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH0_ENABLE †
T4
OZ
Down
UPP Channel 0 Enable
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH0_WAIT †
T1
OZ
Down
UPP Channel 0 Wait
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH1_CLK †
T5
OZ
Down
UPP Channel 1 Clock
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH1_START †
U1
OZ
Down
UPP Channel 1 Start
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH1_ENABLE †
U2
OZ
Down
UPP Channel 1 Enable
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
UPP_CH1_WAIT †
U3
OZ
Down
UPP Channel 1 Wait
This UPP pin has a primary function assigned to it as mentioned elsewhere in this table: ‘‘EMIF16’’
on page 42.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
43
PRODUCT PREVIEW
Table 2-17
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-17
www.ti.com
Terminal Functions — Signals and Control by Function (Part 7 of 13)
PRODUCT PREVIEW
Signal Name
Ball No. Type
IPD/IPU
UPPD00 †
U4
IOZ
Down
UPPD01 †
U5
IOZ
Down
UPPD02 †
V1
IOZ
Down
UPPD03 †
V2
IOZ
Down
UPPD04 †
V3
IOZ
Down
UPPD05 †
V4
IOZ
Down
UPPD06 †
W1
IOZ
Down
UPPD07 †
V5
IOZ
Down
UPPD08 †
W2
IOZ
Down
UPPD09 †
Y1
IOZ
Down
UPPD10 †
W4
IOZ
Down
UPPD11 †
Y2
IOZ
Down
UPPD12 †
W5
IOZ
Down
UPPD13 †
AA1
IOZ
Down
UPPD14 †
AB1
IOZ
Down
UPPD15 †
AA2
IOZ
Down
UPPXD00 †
K1
IOZ
Down
UPPXD01 †
M3
IOZ
Down
UPPXD02 †
L2
IOZ
Down
UPPXD03 †
P5
IOZ
Down
UPPXD04 †
L1
IOZ
Down
UPPXD05 †
P4
IOZ
Down
UPPXD06 †
M2
IOZ
Down
UPPXD07 †
M1
IOZ
Down
UPPXD08 †
N2
IOZ
Down
UPPXD09 †
P3
IOZ
Down
UPPXD10 †
N1
IOZ
Down
UPPXD11 †
P2
IOZ
Down
UPPXD12 †
P1
IOZ
Down
UPPXD13 †
R5
IOZ
Down
UPPXD14 †
R3
IOZ
Down
UPPXD15 †
R4
IOZ
Down
44
Device Overview
Description
UPP Data
These UPP pins have a primary function assigned to it as mentioned elsewhere in this table:
‘‘EMIF16’’ on page 42.
UPP Extended Data
These UPP pins have a primary function assigned to it as mentioned elsewhere in this table:
‘‘EMIF16’’ on page 42.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 2-17
Signal Name
Terminal Functions — Signals and Control by Function (Part 8 of 13)
Ball No. Type
IPD/IPU
Description
EMU00
V24
IOZ
UP
EMU01
V25
IOZ
UP
EMU02
W25
IOZ
UP
EMU03
W23
IOZ
UP
EMU04
W24
IOZ
UP
EMU05
Y25
IOZ
UP
EMU06
Y24
IOZ
UP
EMU07
Y23
IOZ
UP
EMU08
W22
IOZ
UP
EMU09
Y22
IOZ
UP
EMU10
AA24
IOZ
UP
EMU11
AA25
IOZ
UP
EMU12
AB25
IOZ
UP
EMU13
AC25
IOZ
UP
EMU14
AA23
IOZ
UP
EMU15
AB22
IOZ
UP
EMU16
AD25
IOZ
UP
EMU17
AC24
IOZ
UP
EMU18
Y21
IOZ
UP
PRODUCT PREVIEW
EMU
Emulation and Trace Port
General Purpose Input/Output (GPIO)
GPIO00
T25
IOZ
UP
GPIO01
R25
IOZ
Down
GPIO02
R23
IOZ
Down
GPIO03
U25
IOZ
Down
GPIO04
T23
IOZ
Down
GPIO05
U24
IOZ
Down
GPIO06
T22
IOZ
Down
GPIO07
R21
IOZ
Down
GPIO08
U22
IOZ
Down
GPIO09
U23
IOZ
Down
GPIO10
V23
IOZ
Down
GPIO11
U21
IOZ
Down
GPIO12
T21
IOZ
Down
GPIO13
V22
IOZ
Down
GPIO14
W21
IOZ
Down
GPIO15
V21
IOZ
Down
GPIO16 †
AD20
IOZ
Down
General Purpose Input/Output
These GPIO pins have secondary functions assigned to them as mentioned elsewhere in this
table:‘‘Boot Configuration Pins’’ on page 38.
General Purpose Input/Output
This GPIO pin has a primary function assigned to it as mentioned elsewhere in this table (‘‘Timer’’
on page 49) and a tertiary function assigned to it as mentioned elsewhere in this table (‘‘Boot
Configuration Pins’’ on page 38).
GPIO17 †
AE21
IOZ
Down
General Purpose Input/Output
GPIO18 †
AC19
IOZ
Down
GPIO19 †
AE20
IOZ
Down
These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table:
‘‘Timer’’ on page 49.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
45
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-17
www.ti.com
Terminal Functions — Signals and Control by Function (Part 9 of 13)
PRODUCT PREVIEW
Signal Name
Ball No. Type
IPD/IPU
GPIO20 †
AB15
IOZ
Down
GPIO21 †
AA15
IOZ
Down
GPIO22 †
AC17
IOZ
Down
GPIO23 †
AB17
IOZ
Down
GPIO24 †
AC14
IOZ
Down
GPIO25 †
AC15
IOZ
Down
GPIO26 †
AE16
IOZ
Down
GPIO27 †
AD15
IOZ
Down
GPIO28 †
AA12
IOZ
Up
GPIO29 †
AA14
IOZ
Up
GPIO30 †
AB14
IOZ
Down
GPIO31 †
AB13
IOZ
Down
MCMRXN0
P24
I
MCMRXP0
N24
I
MCMRXN1
M25
I
MCMRXP1
N25
I
MCMRXN2
J25
I
MCMRXP2
K25
I
MCMRXN3
K24
I
MCMRXP3
L24
I
MCMTXN0
P22
O
MCMTXP0
N22
O
MCMTXN1
N21
O
MCMTXP1
M21
O
MCMTXN2
K22
O
MCMTXP2
L22
O
MCMTXN3
J21
O
MCMTXP3
K21
O
Description
General Purpose Input/Output
These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table:
‘‘UART’’ on page 49.
General Purpose Input/Output
These GPIO pins have primary functions assigned to them as mentioned elsewhere in this
table:‘‘SPI’’ on page 48.
Reserved — leave unconnected
Reserved — leave unconnected
MCMRXFLCLK
B24
O
Down
MCMRXFLDAT
C24
O
Down
MCMTXFLCLK
E25
I
Down
MCMTXFLDAT
D25
I
Down
MCMRXPMCLK
E24
I
Down
MCMRXPMDAT
D24
I
Down
MCMTXPMCLK
F24
O
Down
MCMTXPMDAT
G24
O
Down
MCMREFCLKOUTP
G25
O
MCMREFCLKOUTN
F25
O
Reserved — leave unconnected
Reserved — leave unconnected
2
I C
2
SCL
AA17
IOZ
I C Clock
SDA
AA18
IOZ
I2C Data
46
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 2-17
Signal Name
Terminal Functions — Signals and Control by Function (Part 10 of 13)
Ball No. Type
IPD/IPU
Description
JTAG
TCK
AD17
I
Up
JTAG Clock Input
TDI
AE17
I
Up
JTAG Data Input
TDO
AD19
OZ
Up
JTAG Data Output
TMS
AE18
I
Up
JTAG Test Mode Input
TRST
AB19
I
Down
JTAG Reset
CLKR0
AA21
IOZ
Down
McBSP Receive Clock
CLKX0
Y20
IOZ
Down
McBSP Transmit Clock
CLKS0
AC23
IOZ
Down
McBSP Slow Clock
FSR0
AD24
IOZ
Down
McBSP Receive Frame Sync
FSX0
AA20
IOZ
Down
McBSP Transmit Frame Sync
DR0
AB21
I
Down
McBSP Receive Data
DX0
AC22
OZ
Down
McBSP Transmit Data
CLKR1
AD23
IOZ
Down
McBSP Receive Clock
CLKX1
AE24
IOZ
Down
McBSP Transmit Clock
CLKS1
AC21
IOZ
Down
McBSP Slow Clock
FSR1
AD22
IOZ
Down
McBSP Receive Frame Sync
FSX1
AE23
IOZ
Down
McBSP Transmit Frame Sync
DR1
AD21
I
Down
McBSP Receive Data
DX1
AE22
OZ
Down
McBSP Transmit Data
MDIO
AB16
IOZ
Up
MDIO Data
MDCLK
AA16
O
Down
MDIO Clock
PRODUCT PREVIEW
McBSP
MDIO
PCIe
PCIERXN0
AE12
I
PCIERXP0
AE11
I
PCIERXN1
AD10
I
PCIERXP1
AD11
I
PCIETXN0
AC12
O
PCIETXP0
AC11
O
PCIETXN1
AB11
O
PCIETXP1
AB10
O
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
PCIexpress Receive Data (2 links)
PCIexpress Transmit Data (2 links)
Device Overview
47
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-17
www.ti.com
Terminal Functions — Signals and Control by Function (Part 11 of 13)
PRODUCT PREVIEW
Signal Name
Ball No. Type
RIORXN0
AE9
I
RIORXP0
AE8
I
RIORXN1
AD8
I
RIORXP1
AD7
I
RIORXN2
AE5
I
RIORXP2
AE6
I
RIORXN3
AD4
I
RIORXP3
AD5
I
RIOTXN0
AC9
O
RIOTXP0
AC8
O
RIOTXN1
AB7
O
RIOTXP1
AB8
O
RIOTXN2
AC5
O
RIOTXP2
AC6
O
RIOTXN3
AB4
O
RIOTXP3
AB5
O
SGMII0RXN
AE2
I
SGMII0RXP
AE3
I
SGMII0TXN
AC2
O
SGMII0TXP
AC3
O
IPD/IPU
Description
Reserved — leave unconnected
Reserved — leave unconnected
SGMII
Ethernet MAC SGMII Receive Data
Ethernet MAC SGMII Transmit Data
SmartReflex
VCNTL0
E22
OZ
VCNTL1
E23
OZ
VCNTL2
F23
OZ
VCNTL3
G23
OZ
SPISCS0
AA12
OZ
Voltage Control Outputs to variable core power supply
SPI
Up
SPI Interface Enable 0
This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General
Purpose Input/Output (GPIO)’’ on page 45.
SPISCS1
AA14
OZ
Up
SPI Interface Enable 1
This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General
Purpose Input/Output (GPIO)’’ on page 45.
SPICLK
AA13
OZ
Down
SPI Clock
SPIDIN
AB14
I
Down
SPI Data In
This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General
Purpose Input/Output (GPIO)’’ on page 45.
SPIDOUT
AB13
OZ
Down
SPI Data Out
This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table: ‘‘General
Purpose Input/Output (GPIO)’’ on page 45.
48
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 2-17
Signal Name
Terminal Functions — Signals and Control by Function (Part 12 of 13)
Ball No. Type
IPD/IPU
Description
Timer
TIMI0
AD20
I
Down
Timer Inputs
TIMI1
AE21
I
Down
These Timer pins have secondary functions assigned to them as mentioned elsewhere in this
table: ‘‘General Purpose Input/Output (GPIO)’’ on page 45
TIMO0
AC19
OZ
Down
Timer Outputs
TIMO1
AE20
OZ
Down
These Timer pins have secondary functions assigned to them as mentioned elsewhere in this
table: ‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTRXD
AB15
I
Down
UART Serial Data In
UART
UARTTXD
AA15
OZ
Down
PRODUCT PREVIEW
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UART Serial Data Out
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTCTS
AC17
I
Down
UART Clear To Send
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTRTS
AB17
OZ
Down
UART Request To Send
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTRXD1
AC14
I
Down
UART Serial Data In
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTTXD1
AC15
OZ
Down
UART Serial Data Out
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTCTS1
AE16
I
Down
UART Clear To Send
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
UARTRTS1
AD15
OZ
Down
UART Request To Send
This UART pin has a secondary function assigned to it as mentioned elsewhere in this table:
‘‘General Purpose Input/Output (GPIO)’’ on page 45
Reserved
RSV01
AA22
IOZ
Up
Reserved - pullup to DVDD18
RSV02
J3
OZ
Down
Reserved - leave unconnected
RSV03
H2
OZ
Down
Reserved - leave unconnected
RSV04
AC18
O
RSV05
AB18
O
Reserved - leave unconnected
RSV06
B23
O
Reserved - leave unconnected
RSV07
A23
O
RSV08
Y19
OZ
Down
RSV09
C23
OZ
Down
RSV10
G22
A
RSV11
H22
A
Reserved - leave unconnected
RSV12
Y5
A
Reserved - leave unconnected
RSV13
Y4
A
Reserved - leave unconnected
RSV14
F21
A
Reserved - leave unconnected
RSV15
G21
A
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - connect to GND
Device Overview
49
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-17
www.ti.com
Terminal Functions — Signals and Control by Function (Part 13 of 13)
Signal Name
Ball No. Type
RSV16
J20
A
IPD/IPU
Reserved - leave unconnected
Description
RSV17
AA7
A
Reserved - leave unconnected
RSV18
AA11
A
Reserved - leave unconnected
RSV19
AB3
A
Reserved - leave unconnected
RSV20
F22
IOZ
Reserved - leave unconnected
RSV21
D23
IOZ
Reserved - leave unconnected
RSV0A
G19
A
Reserved - leave unconnected
RSV0B
G20
A
Reserved - leave unconnected
End of Table 2-17
PRODUCT PREVIEW
50
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Terminal Functions — Power and Ground
Supply
Ball No.
Volts Description
AVDDA1
Y15
1.8
PLL Supply - CORE_PLL
AVDDA2
F20
1.8
PLL Supply - DDR3_PLL
CVDD
H9, H11, H13, H15, H17, J10, J12, J14, J16, K11, K13, K15, L8, L10, L12, L14, L16, L18, M9, M11, 0.85 SmartReflex core supply voltage
M13, M15, M17, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, R10, R12, R14, R16, to 1.1
R18, T11, T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, V17
CVDD1
J8, J18, K9, K17, T9, T17, U8, U18
1.0
Fixed core supply voltage for
memory array
DVDD15
B10, C6, C17, C21, D2, D4, D8, D13, D15, D19, F7, F9, F11, F13, F17, F19, G8, G10, G12, G14,
G16, G18
1.5
DDR IO supply
DVDD18
A24, E21, G3, G6, H7, H19, H24, J6, K3, K7, L6, M7, N3, N6, P7, R6, R20, T3, T7, T19, T24, U6,
U20, V7, V19, W6, W14, W16, W18, W20, Y3, Y13, Y17, AB23, AC16, AC20
1.8
IO supply
VDDR1
M20
1.5
Reserved — connect to DVDD15
VDDR2
AA9
1.5
PCIe SerDes regulator supply
VDDR3
AA3
1.5
SGMII SerDes regulator supply
VDDR4
AA5
1.5
Reserved — connect to DVDD15
VDDT1
K19, L20, M19, N20
1.0
Reserved — connect to CVDD1
VDDT2
W8, W10, W12, Y7, Y9, Y11
1.0
SGMII/PCIe SerDes termination
supply
VREFSSTL
E12
0.75
VSS
A1, A10, A25, B6, B17, C2, C4, C8, C13, C15, C19, D21, E11, F3, F6, F8, F10, F12, F14, F16, F18, GND
G7, G9, G11, G13, G15, G17, H6, H8, H10, H12, H14, H16, H18, H20, H21, H23, H25, J7, J9, J11,
J13, J15, J17, J19, J22, J23, J24, K2, K6, K8, K10, K12, K14, K16, K18, K20, K23, L7, L9, L11, L13,
L15, L17, L19, L21, L23, L25, M6, M8, M10, M12, M14, M16, M18, M22, M23, M24, N4, N7, N9,
N11, N13, N15, N17, N19, N23, P6, P8, P10, P12, P14, P16, P18, P20, P21, P23, P25, R7, R8, R9,
R11, R13, R15, R17, R19, R22, R24, T2, T6, T8, T10, T12, T14, T16, T18, T20, U7, U9, U11, U13,
U15, U17, U19, V6, V8, V10, V12, V14, V16, V18, V20, W3, W7, W9, W11, W13, W15, W17, W19,
Y6, Y8, Y10, Y12, Y14, Y16, AA4, AA6, AA8, AA10, AB2, AB6, AB9, AB12, AB20, AB24, AC1, AC4,
AC7, AC10, AC13, AD1, AD2, AD3, AD6, AD9, AD12, AD16, AE1, AE4, AE7, AE10, AE13, AE25
DDR3 reference voltage
Ground
End of Table 2-18
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
51
PRODUCT PREVIEW
Table 2-18
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-19
www.ti.com
Terminal Functions
— By Signal Name
(Part 1 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 2 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 3 of 11)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
AVDDA1
Y15
DDRA04
B18
DDRD12
D6
AVDDA2
F20
DDRA05
A17
DDRD13
C7
D7
Signal Name
BOOTCOMPLETE
BOOTMODE00 †
BOOTMODE01 †
BOOTMODE02 †
BOOTMODE03 †
PRODUCT PREVIEW
H3
DDRA06
C16
DDRD14
R25
DDRA07
A18
DDRD15
B8
DDRA08
D20
DDRD16
E5
DDRA09
E20
DDRD17
B3
DDRA10
E19
DDRD18
F4
DDRA11
B20
DDRD19
E4
DDRA12
D18
DDRD20
A3
DDRA13
C20
DDRD21
B5
DDRA14
E18
DDRD22
C5
DDRA15
E17
DDRD23
D5
E2
R23
U25
T23
BOOTMODE04 †
U24
BOOTMODE05 †
T22
BOOTMODE06 †
R21
BOOTMODE07 †
U22
BOOTMODE08 †
U23
DDRBA0
C18
DDRD24
BOOTMODE09 †
V23
DDRBA1
D17
DDRD25
F2
BOOTMODE10 †
U21
DDRBA2
B19
DDRD26
B1
BOOTMODE11 †
T21
DDRCAS
D14
DDRD27
C1
D1
BOOTMODE12 †
CLKR0
V22
DDRCB00
D11
DDRD28
AA21
DDRCB01
B12
DDRD29
D3
C3
CLKR1
AD23
DDRCB02
C11
DDRD30
CLKS0
AC23
DDRCB03
A12
DDRD31
E3
DDRCE0
B15
DDRDQM0
A8
DDRCE1
C14
DDRDQM1
E7
DDRCKE0
A16
DDRDQM2
F5
DDRCKE1
A20
DDRDQM3
E1
DDRCLKN
B22
DDRDQM8
C12
DDRCLKOUTN0
B14
DDRDQS0N
C10
DDRCLKOUTN1
B21
DDRDQS0P
D10
DDRCLKOUTP0
A14
DDRDQS1N
A7
DDRCLKOUTP1
A21
DDRDQS1P
B7
DDRCLKP
A22
DDRDQS2N
A4
DDRD00
A9
DDRDQS2P
B4
DDRD01
C9
DDRDQS3N
B2
DDRD02
D9
DDRDQS3P
A2
DDRD03
B9
DDRDQS8N
A13
DDRD04
E9
DDRDQS8P
B13
DDRD05
E10
DDRODT0
E14
DDRD06
A11
DDRODT1
D12
DDRD07
B11
DDRRAS
A15
DDRD08
E6
DDRRESET
B16
DDRD09
E8
DDRSLRATE0
C22
DDRD10
A6
DDRSLRATE1
D22
DDRD11
A5
DDRWE
E13
CLKS1
AC21
CLKX0
Y20
CLKX1
AE24
CORECLKN
AE19
CORECLKP
AD18
CORESEL0
J5
CORESEL1
G5
CVDD
H9, H11, H13, H15,
H17, J10, J12, J14,
J16, K11, K13, K15,
L8, L10, L12, L14,
L16, L18, M9, M11,
M13, M15, M17, N8,
N10, N12, N14, N16,
N18, P9, P11, P13,
P15, P17, P19, R10,
R12, R14, R16, R18,
T11, T13, T15, U10,
U12, U14, U16, V9,
V11, V13, V15, V17
CVDD1
J8, J18, K9, K17, T9,
T17, U8, U18
DDRA00
D16
DDRA01
A19
DDRA02
DDRA03
52
Device Overview
E16
E15
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-19
Signal Name
Terminal Functions
— By Signal Name
(Part 4 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 5 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 6 of 11)
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
DR0
AB21
EMIFCE2
J2
FSR0
AD24
DR1
AD21
EMIFCE3
M5
FSR1
AD22
DVDD15
B10, C6, C17, C21,
D2, D4, D8, D13,
D15, D19, F7, F9,
F11, F13, F17, F19,
G8, G10, G12, G14,
G16, G18
EMIFD00
U4
FSX0
AA20
EMIFD01
U5
FSX1
AE23
EMIFD02
V1
GPIO00
T25
EMIFD03
V2
GPIO01
R25
A24, E21, G3, G6,
H7, H19, H24, J6,
K3, K7, L6, M7, N3,
N6, P7, R6, R20, T3,
T7, T19, T24, U6,
U20, V7, V19, W6,
W14, W16, W18,
W20, Y3, Y13, Y17,
AB23, AC16, AC20
EMIFD04
V3
GPIO02
R23
EMIFD05
V4
GPIO03
U25
EMIFD06
W1
GPIO04
T23
EMIFD07
V5
GPIO05
U24
EMIFD08
W2
GPIO06
T22
EMIFD09
Y1
GPIO07
R21
EMIFD10
W4
GPIO08
U22
EMIFD11
Y2
GPIO09
U23
EMIFD12
W5
GPIO10
V23
EMIFD13
AA1
GPIO11
U21
EMIFD14
AB1
GPIO12
T21
EMIFD15
AA2
GPIO13
V22
EMIFOE
L4
GPIO14
W21
EMIFRNW
L5
GPIO15
V21
EMIFWAIT0
N5
GPIO16 †
AD20
EMIFWAIT1
M4
GPIO17 †
AE21
EMIFWE
K4
GPIO18 †
AC19
EMU00
V24
GPIO19 †
AE20
EMU01
V25
GPIO20 †
AB15
EMU02
W25
GPIO21 †
AA15
EMU03
W23
GPIO22 †
AC17
EMU04
W24
GPIO23 †
AB17
EMU05
Y25
GPIO24 †
AC14
EMU06
Y24
GPIO25 †
AC15
EMU07
Y23
GPIO26 †
AE16
EMU08
W22
GPIO27 †
AD15
EMU09
Y22
GPIO28 †
AA12
EMU10
AA24
GPIO29 †
AA14
EMU11
AA25
GPIO30 †
AB14
EMU12
AB25
GPIO31 †
AB13
EMU13
AC25
HOUT
G2
EMU14
AA23
LENDIAN †
T25
EMU15
AB22
LRESETNMIEN
F1
EMU16
AD25
LRESET
G4
EMU17
AC24
MCMCLKN
B25
EMU18
Y21
MCMCLKP
C25
DVDD18
DX0
AC22
DX1
AE22
EMIFA00
K1
EMIFA01
M3
EMIFA02
L2
EMIFA03
P5
EMIFA04
L1
EMIFA05
P4
EMIFA06
M2
EMIFA07
M1
EMIFA08
N2
EMIFA09
P3
EMIFA10
N1
EMIFA11
P2
EMIFA12
P1
EMIFA13
R5
EMIFA14
R3
EMIFA15
R4
EMIFA16
R2
EMIFA17
R1
EMIFA18
T4
EMIFA19
T1
EMIFA20
T5
EMIFA21
U1
EMIFA22
U2
EMIFA23
U3
EMIFBE0
J1
EMIFBE1
L3
EMIFCE0
K5
EMIFCE1
G1
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
PRODUCT PREVIEW
www.ti.com
53
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-19
www.ti.com
Terminal Functions
— By Signal Name
(Part 7 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 8 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 9 of 11)
PRODUCT PREVIEW
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
Ball Number
MCMREFCLKOUTN
F25
RESETFULL
J4
SCL
AA17
MCMREFCLKOUTP
G25
RESETSTAT
H5
SDA
AA18
MCMRXFLCLK
B24
RESET
H4
SGMII0RXN
AE2
MCMRXFLDAT
C24
RIORXN0
AE9
SGMII0RXP
AE3
MCMRXN0
P24
RIORXN1
AD8
SGMII0TXN
AC2
MCMRXN1
M25
RIORXN2
AE5
SGMII0TXP
AC3
MCMRXN2
J25
RIORXN3
AD4
SPICLK
AA13
MCMRXN3
K24
RIORXP0
AE8
SPIDIN
AB14
MCMRXP0
N24
RIORXP1
AD7
SPIDOUT
AB13
MCMRXP1
N25
RIORXP2
AE6
SPISCS0
AA12
MCMRXP2
K25
RIORXP3
AD5
SPISCS1
AA14
MCMRXP3
L24
RIOTXN0
AC9
SRIOSGMIICLKN
AE14
MCMRXPMCLK
E24
RIOTXN1
AB7
SRIOSGMIICLKP
AD13
MCMRXPMDAT
D24
RIOTXN2
AC5
SYSCLKOUT
AA19
MCMTXFLCLK
E25
RIOTXN3
AB4
TCK
AD17
MCMTXFLDAT
D25
RIOTXP0
AC8
TDI
AE17
MCMTXN0
P22
RIOTXP1
AB8
TDO
AD19
MCMTXN1
N21
RIOTXP2
AC6
TIMI0
AD20
MCMTXN2
K22
RIOTXP3
AB5
TIMI1
AE21
MCMTXN3
J21
RSV01
AA22
TIMO0
AC19
MCMTXP0
N22
RSV02
J3
TIMO1
AE20
MCMTXP1
M21
RSV03
H2
TMS
AE18
MCMTXP2
L22
RSV04
AC18
TRST
AB19
MCMTXP3
K21
RSV05
AB18
UARTCTS
AC17
MCMTXPMCLK
F24
RSV06
B23
UARTCTS1
AE16
MCMTXPMDAT
G24
RSV07
A23
UARTRTS
AB17
MDCLK
AA16
RSV08
Y19
UARTRTS1
AD15
MDIO
AB16
RSV09
C23
UARTRXD
AB15
NMI
H1
RSV0A
G19
UARTRXD1
AC14
PCIECLKN
AE15
RSV0B
G20
UARTTXD
AA15
PCIECLKP
AD14
RSV10
G22
UARTTXD1
AC15
PCIERXN0
AE12
RSV11
H22
UPP_2XTXCLK †
M4
PCIERXN1
AD10
RSV12
Y5
UPP_CH0_CLK †
R2
PCIERXP0
AE11
RSV13
Y4
UPP_CH0_ENABLE †
T4
PCIERXP1
AD11
RSV14
F21
UPP_CH0_START †
R1
PCIESSEN ‡
AD20
RSV15
G21
UPP_CH0_WAIT †
T1
PCIETXN0
AC12
RSV16
J20
UPP_CH1_CLK †
T5
PCIETXN1
AB11
RSV17
AA7
UPP_CH1_ENABLE †
U2
PCIETXP0
AC11
RSV18
AA11
UPP_CH1_START †
U1
PCIETXP1
AB10
RSV19
AB3
UPP_CH1_WAIT †
U3
POR
Y18
RSV20
F22
UPPD00 †
U4
PTV15
F15
RSV21
D23
UPPD01 †
U5
54
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Terminal Functions
— By Signal Name
(Part 10 of 11)
Table 2-19
Terminal Functions
— By Signal Name
(Part 11 of 11)
Signal Name
Ball Number
Signal Name
Ball Number
UPPD02 †
V1
VDDT2
W8
UPPD03 †
V2
VDDT2
W10
UPPD04 †
V3
VDDT2
W12
UPPD05 †
V4
VDDT2
Y7
UPPD06 †
W1
VDDT2
Y9
UPPD07 †
V5
VDDT2
Y11
UPPD08 †
W2
VREFSSTL
E12
UPPD09 †
Y1
VSS
UPPD10 †
W4
UPPD11 †
Y2
A1, A10, A25, B6,
B17, C2, C4, C8, C13,
C15, C19, D21, E11,
F3, F6, F8, F10, F12,
F14, F16, F18, G7,
G9, G11, G13, G15,
G17, H6, H8, H10,
H12, H14, H16, H18,
H20, H21, H23, H25,
J7, J9, J11, J13, J15,
J17, J19, J22, J23,
J24, K2, K6, K8, K10,
K12, K14, K16, K18,
K20, K23, L7, L9,
L11, L13, L15, L17,
L19, L21, L23, L25,
M6, M8, M10, M12,
M14, M16, M18,
M22, M23, M24, N4,
N7, N9, N11, N13,
N15, N17, N19, N23,
P6, P8, P10, P12,
P14, P16, P18, P20,
P21, P23, P25, R7,
R8, R9, R11, R13,
R15, R17, R19, R22,
R24, T2, T6, T8, T10,
T12, T14, T16, T18,
T20, U7, U9, U11,
U13, U15, U17, U19,
V6, V8, V10, V12,
V14, V16, V18, V20,
W3, W7, W9, W11,
W13, W15, W17,
W19, Y6, Y8, Y10,
Y12, Y14, Y16, AA4,
AA6, AA8, AA10,
AB2, AB6, AB9,
AB12, AB20, AB24,
AC1, AC4, AC7,
AC10, AC13, AD1,
AD2, AD3, AD6,
AD9, AD12, AD16,
AE1, AE4, AE7,
AE10, AE13, AE25
UPPD12 †
W5
UPPD13 †
AA1
UPPD14 †
AB1
UPPD15 †
AA2
UPPXD00 †
K1
UPPXD01 †
M3
UPPXD02 †
L2
UPPXD03 †
P5
UPPXD04 †
L1
UPPXD05 †
P4
UPPXD06 †
M2
UPPXD07 †
M1
UPPXD08 †
N2
UPPXD09 †
P3
UPPXD10 †
N1
UPPXD11 †
P2
UPPXD12 †
P1
UPPXD13 †
R5
UPPXD14 †
R3
UPPXD15 †
R4
VCNTL0
E22
VCNTL1
E23
VCNTL2
F23
VCNTL3
G23
VDDR1
M20
VDDR2
AA9
VDDR3
AA3
VDDR4
AA5
VDDT1
K19, L20, M19, N20
VDDT2
W8, W10, W12, Y7,
Y9, Y11
VDDT1
M19
VDDT1
N20
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
PRODUCT PREVIEW
Table 2-19
End of Table 2-19
Device Overview
55
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-20
Terminal Functions
— By Ball Number
(Part 1 of 17)
www.ti.com
Table 2-20
Terminal Functions
— By Ball Number
(Part 2 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 3 of 17)
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
A1
VSS
B18
DDRA04
D10
DDRDQS0P
A2
DDRDQS3P
B19
DDRBA2
D11
DDRCB00
A3
DDRD20
B20
DDRA11
D12
DDRODT1
A4
DDRDQS2N
B21
DDRCLKOUTN1
D13
DVDD15
A5
DDRD11
B22
DDRCLKN
D14
DDRCAS
A6
DDRD10
B23
RSV06
D15
DVDD15
A7
DDRDQS1N
B24
MCMRXFLCLK
D16
DDRA00
A8
DDRDQM0
B25
MCMCLKN
D17
DDRBA1
A9
DDRD00
C1
DDRD27
D18
DDRA12
A10
VSS
C2
VSS
D19
DVDD15
A11
DDRD06
C3
DDRD30
D20
DDRA08
A12
DDRCB03
C4
VSS
D21
VSS
A13
DDRDQS8N
C5
DDRD22
D22
DDRSLRATE1
A14
DDRCLKOUTP0
C6
DVDD15
D23
RSV21
A15
DDRRAS
C7
DDRD13
D24
MCMRXPMDAT
A16
DDRCKE0
C8
VSS
D25
MCMTXFLDAT
A17
DDRA05
C9
DDRD01
E1
DDRDQM3
A18
DDRA07
C10
DDRDQS0N
E2
DDRD24
A19
DDRA01
C11
DDRCB02
E3
DDRD31
A20
DDRCKE1
C12
DDRDQM8
E4
DDRD19
A21
DDRCLKOUTP1
C13
VSS
E5
DDRD16
A22
DDRCLKP
C14
DDRCE1
E6
DDRD08
A23
RSV07
C15
VSS
E7
DDRDQM1
A24
DVDD18
C16
DDRA06
E8
DDRD09
A25
VSS
C17
DVDD15
E9
DDRD04
B1
DDRD26
C18
DDRBA0
E10
DDRD05
B2
DDRDQS3N
C19
VSS
E11
VSS
B3
DDRD17
C20
DDRA13
E12
VREFSSTL
B4
DDRDQS2P
C21
DVDD15
E13
DDRWE
B5
DDRD21
C22
DDRSLRATE0
E14
DDRODT0
B6
VSS
C23
RSV09
E15
DDRA03
B7
DDRDQS1P
C24
MCMRXFLDAT
E16
DDRA02
B8
DDRD15
C25
MCMCLKP
E17
DDRA15
B9
DDRD03
D1
DDRD28
E18
DDRA14
B10
DVDD15
D2
DVDD15
E19
DDRA10
B11
DDRD07
D3
DDRD29
E20
DDRA09
B12
DDRCB01
D4
DVDD15
E21
DVDD18
B13
DDRDQS8P
D5
DDRD23
E22
VCNTL0
B14
DDRCLKOUTN0
D6
DDRD12
E23
VCNTL1
B15
DDRCE0
D7
DDRD14
E24
MCMRXPMCLK
B16
DDRRESET
D8
DVDD15
E25
MCMTXFLCLK
B17
VSS
D9
DDRD02
F1
LRESETNMIEN
Ball Number
PRODUCT PREVIEW
56
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Ball Number
Terminal Functions
— By Ball Number
(Part 4 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 5 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 6 of 17)
Signal Name
Ball Number
Signal Name
Ball Number
Signal Name
F2
DDRD25
G19
RSV0A
J11
VSS
F3
VSS
G20
RSV0B
J12
CVDD
F4
DDRD18
G21
RSV15
J13
VSS
F5
DDRDQM2
G22
RSV10
J14
CVDD
F6
VSS
G23
VCNTL3
J15
VSS
F7
DVDD15
G24
MCMTXPMDAT
J16
CVDD
F8
VSS
G25
MCMREFCLKOUTP
J17
VSS
F9
DVDD15
H1
NMI
J18
CVDD1
F10
VSS
H2
RSV03
J19
VSS
F11
DVDD15
H3
BOOTCOMPLETE
J20
RSV16
F12
VSS
H4
RESET
J21
MCMTXN3
F13
DVDD15
H5
RESETSTAT
J22
VSS
F14
VSS
H6
VSS
J23
VSS
F15
PTV15
H7
DVDD18
J24
VSS
F16
VSS
H8
VSS
J25
MCMRXN2
F17
DVDD15
H9
CVDD
K1
EMIFA00
F18
VSS
H10
VSS
K1
UPPXD00 †
F19
DVDD15
H11
CVDD
K2
VSS
F20
AVDDA2
H12
VSS
K3
DVDD18
F21
RSV14
H13
CVDD
K4
EMIFWE
F22
RSV20
H14
VSS
K5
EMIFCE0
F23
VCNTL2
H15
CVDD
K6
VSS
F24
MCMTXPMCLK
H16
VSS
K7
DVDD18
F25
MCMREFCLKOUTN
H17
CVDD
K8
VSS
G1
EMIFCE1
H18
VSS
K9
CVDD1
G2
HOUT
H19
DVDD18
K10
VSS
G3
DVDD18
H20
VSS
K11
CVDD
G4
LRESET
H21
VSS
K12
VSS
G5
CORESEL1
H22
RSV11
K13
CVDD
G6
DVDD18
H23
VSS
K14
VSS
G7
VSS
H24
DVDD18
K15
CVDD
G8
DVDD15
H25
VSS
K16
VSS
G9
VSS
J1
EMIFBE0
K17
CVDD1
G10
DVDD15
J2
EMIFCE2
K18
VSS
G11
VSS
J3
RSV02
K19
VDDT1
G12
DVDD15
J4
RESETFULL
K20
VSS
G13
VSS
J5
CORESEL0
K21
MCMTXP3
G14
DVDD15
J6
DVDD18
K22
MCMTXN2
G15
VSS
J7
VSS
K23
VSS
G16
DVDD15
J8
CVDD1
K24
MCMRXN3
G17
VSS
J9
VSS
K25
MCMRXP2
G18
DVDD15
J10
CVDD
L1
EMIFA04
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Overview
PRODUCT PREVIEW
Table 2-20
57
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-20
Ball Number
Terminal Functions
— By Ball Number
(Part 7 of 17)
www.ti.com
Table 2-20
Signal Name
Ball Number
L1
UPPXD04 †
L2
EMIFA02
L2
UPPXD02 †
L3
EMIFBE1
L4
EMIFOE
L5
EMIFRNW
L6
L7
Terminal Functions
— By Ball Number
(Part 8 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 9 of 17)
PRODUCT PREVIEW
Signal Name
Ball Number
M13
CVDD
P2
EMIFA11
M14
VSS
P2
UPPXD11 †
M15
CVDD
P3
EMIFA09
M16
VSS
P3
UPPXD09 †
M17
CVDD
P4
EMIFA05
M18
VSS
P4
UPPXD05 †
DVDD18
M19
VDDT1
P5
EMIFA03
VSS
M20
VDDR1
P5
UPPXD03 †
L8
CVDD
M21
MCMTXP1
P6
VSS
L9
VSS
M22
VSS
P7
DVDD18
L10
CVDD
M23
VSS
P8
VSS
L11
VSS
M24
VSS
P9
CVDD
L12
CVDD
M25
MCMRXN1
P10
VSS
L13
VSS
N1
EMIFA10
P11
CVDD
L14
CVDD
N1
UPPXD10 †
P12
VSS
L15
VSS
N2
EMIFA08
P13
CVDD
L16
CVDD
N2
UPPXD08 †
P14
VSS
L17
VSS
N3
DVDD18
P15
CVDD
L18
CVDD
N4
VSS
P16
VSS
L19
VSS
N5
EMIFWAIT0
P17
CVDD
L20
VDDT1
N6
DVDD18
P18
VSS
L21
VSS
N7
VSS
P19
CVDD
L22
MCMTXP2
N8
CVDD
P20
VSS
L23
VSS
N9
VSS
P21
VSS
L24
MCMRXP3
N10
CVDD
P22
MCMTXN0
L25
VSS
N11
VSS
P23
VSS
M1
EMIFA07
N12
CVDD
P24
MCMRXN0
M1
UPPXD07 †
N13
VSS
P25
VSS
M2
EMIFA06
N14
CVDD
R1
EMIFA17
M2
UPPXD06 †
N15
VSS
R1
UPP_CH0_START †
M3
EMIFA01
N16
CVDD
R2
EMIFA16
M3
UPPXD01 †
N17
VSS
R2
UPP_CH0_CLK †
M4
EMIFWAIT1
N18
CVDD
R3
EMIFA14
M4
UPP2XTXCLK †
N19
VSS
R3
UPPXD14 †
M5
EMIFCE3
N20
VDDT1
R4
EMIFA15
M6
VSS
N21
MCMTXN1
R4
UPPXD15 †
M7
DVDD18
N22
MCMTXP0
R5
EMIFA13
M8
VSS
N23
VSS
R5
UPPXD13 †
M9
CVDD
N24
MCMRXP0
R6
DVDD18
M10
VSS
N25
MCMRXP1
R7
VSS
M11
CVDD
P1
EMIFA12
R8
VSS
M12
VSS
P1
UPPXD12 †
R9
VSS
58
Device Overview
Signal Name
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Ball Number
Terminal Functions
— By Ball Number
(Part 10 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 11 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 12 of 17)
Signal Name
Ball Number
Signal Name
Ball Number
R10
CVDD
T21
GPIO12
U25
GPIO03
R11
VSS
T21
BOOTMODE11 †
U25
BOOTMODE02 †
R12
CVDD
T22
GPIO06
V1
EMIFD02
R13
VSS
T22
BOOTMODE05 †
V1
UPPD02 †
R14
CVDD
T23
GPIO04
V2
EMIFD03
R15
VSS
T23
BOOTMODE03 †
V2
UPPD03 †
R16
CVDD
T24
DVDD18
V3
EMIFD04
R17
VSS
T25
GPIO00
V3
UPPD04 †
R18
CVDD
T25
LENDIAN †
V4
EMIFD05
R19
VSS
U1
EMIFA21
V4
UPPD05 †
R20
DVDD18
U1
UPP_CH1_START †
V5
EMIFD07
R21
GPIO07
U2
EMIFA22
V5
UPPD07 †
R21
BOOTMODE06 †
U2
UPP_CH1_ENABLE †
V6
VSS
R22
VSS
U3
EMIFA23
V7
DVDD18
R23
GPIO02
U3
UPP_CH1_WAIT †
V8
VSS
R23
BOOTMODE01 †
U4
EMIFD00
V9
CVDD
R24
VSS
U4
UPPD00 †
V10
VSS
R25
GPIO01
U5
EMIFD01
V11
CVDD
R25
BOOTMODE00 †
U5
UPPD01 †
V12
VSS
T1
EMIFA19
U6
DVDD18
V13
CVDD
T1
UPP_CH0_WAIT †
U7
VSS
V14
VSS
T2
VSS
U8
CVDD1
V15
CVDD
T3
DVDD18
U9
VSS
V16
VSS
T4
EMIFA18
U10
CVDD
V17
CVDD
T4
UPP_CH0_ENABLE †
U11
VSS
V18
VSS
T5
EMIFA20
U12
CVDD
V19
DVDD18
T5
UPP_CH1_CLK †
U13
VSS
V20
VSS
T6
VSS
U14
CVDD
V21
GPIO15
T7
DVDD18
U15
VSS
V21
PCIESSMODE1 †
T8
VSS
U16
CVDD
V22
GPIO13
T9
CVDD1
U17
VSS
V22
BOOTMODE12 †
T10
VSS
U18
CVDD1
V23
GPIO10
T11
CVDD
U19
VSS
V23
BOOTMODE09 †
T12
VSS
U20
DVDD18
V24
EMU00
T13
CVDD
U21
GPIO11
V25
EMU01
T14
VSS
U21
BOOTMODE10 †
W1
EMIFD06
T15
CVDD
U22
GPIO08
W1
UPPD06 †
T16
VSS
U22
BOOTMODE07 †
W2
EMIFD08
T17
CVDD1
U23
GPIO09
W2
UPPD08 †
T18
VSS
U23
BOOTMODE08 †
W3
VSS
T19
DVDD18
U24
GPIO05
W4
EMIFD10
T20
VSS
U24
BOOTMODE04 †
W4
UPPD10 †
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Signal Name
Device Overview
PRODUCT PREVIEW
Table 2-20
59
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 2-20
Ball Number
Terminal Functions
— By Ball Number
(Part 13 of 17)
www.ti.com
Table 2-20
Signal Name
Ball Number
W5
EMIFD12
W5
UPPD12 †
W6
DVDD18
W7
VSS
W8
W9
Terminal Functions
— By Ball Number
(Part 14 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 15 of 17)
PRODUCT PREVIEW
Signal Name
Ball Number
Signal Name
Y18
POR
AB4
RIOTXN3
Y19
RSV08
AB5
RIOTXP3
Y20
CLKX0
AB6
VSS
Y21
EMU18
AB7
RIOTXN1
VDDT2
Y22
EMU09
AB8
RIOTXP1
VSS
Y23
EMU07
AB9
VSS
W10
VDDT2
Y24
EMU06
AB10
PCIETXP1
W11
VSS
Y25
EMU05
AB11
PCIETXN1
W12
VDDT2
AA1
EMIFD13
AB12
VSS
W13
VSS
AA1
UPPD13 †
AB13
SPIDOUT
W14
DVDD18
AA2
EMIFD15
AB13
GPIO31 †
W15
VSS
AA2
UPPD15 †
AB14
SPIDIN
W16
DVDD18
AA3
VDDR3
AB14
GPIO30 †
W17
VSS
AA4
VSS
AB15
UARTRXD
W18
DVDD18
AA5
VDDR4
AB15
GPIO20 †
W19
VSS
AA6
VSS
AB16
MDIO
W20
DVDD18
AA7
RSV17
AB17
UARTRTS
W21
GPIO14 †
AA8
VSS
AB17
GPIO23 †
W21
PCIESSMODE0 †
AA9
VDDR2
AB18
RSV05
W22
EMU08
AA10
VSS
AB19
TRST
W23
EMU03
AA11
RSV18
AB20
VSS
W24
EMU04
AA12
SPISCS0
AB21
DR0
W25
EMU02
AA12
GPIO28 †
AB22
EMU15
Y1
EMIFD09
AA13
SPICLK
AB23
DVDD18
Y1
UPPD09 †
AA14
SPISCS1
AB24
VSS
Y2
EMIFD11
AA14
GPIO29 †
AB25
EMU12
Y2
UPPD11 †
AA15
UARTTXD
AC1
VSS
Y3
DVDD18
AA15
GPIO21 †
AC2
SGMII0TXN
Y4
RSV13
AA16
MDCLK
AC3
SGMII0TXP
Y5
RSV12
AA17
SCL
AC4
VSS
Y6
VSS
AA18
SDA
AC5
RIOTXN2
Y7
VDDT2
AA19
SYSCLKOUT
AC6
RIOTXP2
Y8
VSS
AA20
FSX0
AC7
VSS
Y9
VDDT2
AA21
CLKR0
AC8
RIOTXP0
Y10
VSS
AA22
RSV01
AC9
RIOTXN0
Y11
VDDT2
AA23
EMU14
AC10
VSS
Y12
VSS
AA24
EMU10
AC11
PCIETXP0
Y13
DVDD18
AA25
EMU11
AC12
PCIETXN0
Y14
VSS
AB1
EMIFD14
AC13
VSS
Y15
AVDDA1
AB1
UPPD14 †
AC14
UARTRXD1
Y16
VSS
AB2
VSS
AC14
GPIO24 †
Y17
DVDD18
AB3
RSV19
AC15
UARTTXD1
60
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Ball Number
Terminal Functions
— By Ball Number
(Part 16 of 17)
Table 2-20
Terminal Functions
— By Ball Number
(Part 17 of 17)
Signal Name
Ball Number
Signal Name
AC15
GPIO25 †
AE2
SGMII0RXN
AC16
DVDD18
AE3
SGMII0RXP
AC17
UARTCTS
AE4
VSS
AC17
GPIO22 †
AE5
RIORXN2
AC18
RSV04
AE6
RIORXP2
AC19
TIMO0
AE7
VSS
AC19
GPIO18 †
AE8
RIORXP0
AC20
DVDD18
AE9
RIORXN0
AC21
CLKS1
AE10
VSS
AC22
DX0
AE11
PCIERXP0
AC23
CLKS0
AE12
PCIERXN0
AC24
EMU17
AE13
VSS
AC25
EMU13
AE14
SRIOSGMIICLKN
AD1
VSS
AE15
PCIECLKN
AD2
VSS
AE16
UARTCTS1
AD3
VSS
AE16
GPIO26 †
AD4
RIORXN3
AE17
TDI
AD5
RIORXP3
AE18
TMS
AD6
VSS
AE19
CORECLKN
AD7
RIORXP1
AE20
TIMO1
AD8
RIORXN1
AE20
GPIO19 †
AD9
VSS
AE21
TIMI1
AD10
PCIERXN1
AE21
GPIO17 †
AD11
PCIERXP1
AE22
DX1
AD12
VSS
AE23
FSX1
AD13
SRIOSGMIICLKP
AE24
CLKX1
AD14
PCIECLKP
AE25
VSS
AD15
UARTRTS1
End of Table 2-20
AD15
GPIO27 †
AD16
VSS
AD17
TCK
AD18
CORECLKP
AD19
TDO
AD20
TIMI0
AD20
GPIO16 †
AD20
PCIESSEN ‡
AD21
DR1
AD22
FSR1
AD23
CLKR1
AD24
FSR0
AD25
EMU16
AE1
VSS
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
PRODUCT PREVIEW
Table 2-20
Device Overview
61
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.9 Development and Support
2.9.1 Development Support
In case the customer would like to develop their own features and software on the C6654 device, TI offers an
extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
PRODUCT PREVIEW
The following products support development of C6000™ DSP-based applications:
• Software Development Tools:
– Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly
Code Generation, and Debug plus additional development tools.
– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
• Hardware Development Tools:
– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
– EVM (Evaluation Module)
2.9.2 Device Support
2.9.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices
and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,
TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
• TMX: Experimental device that is not necessarily representative of the final device's electrical specifications
• TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
• TMS: Fully qualified production device
Support tool development evolutionary flow:
• TMDX: Development-support product that has not yet completed Texas Instruments internal qualification
testing.
• TMDS: Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
62
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for
example, CZH), the temperature range (for example, blank is the default case temperature range), and the device
speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).
For device part numbers and further ordering information for TMS320C6654 in the CZH or GZH package type, see
the TI website www.ti.com or contact your TI sales representative.
Figure 2-19 provides a legend for reading the complete device name for any C66x KeyStone device.
C66x DSP Device Nomenclature (including the TMS320C6654)
TMX
320 C6654
PREFIX
TMX = Experimental device
TMS = Qualified device
DEVICE FAMILY
320 = TMS320 DSP family
DEVICE
C66x DSP: C6654
SILICON REVISION
Blank = Initial Silicon 1.0
SECURITY
Blank = General purpose device
S = Secure device
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
(
) (
) CZH
(
)
(
)
DEVICE SPEED RANGE
8 = 850 MHz
PRODUCT PREVIEW
Figure 2-19
TEMPERATURE RANGE
Blank = 0°C to +85°C (default case temperature)
A = Extended temperature range
(-40°C to +100°C)
L = Extended low temperature range
(-55°C to +100°C)
PACKAGE TYPE
CZH = 625-pin plastic ball grid array,
with Pb-free die bumps and solder balls
GZH = 625-pin plastic ball grid array
Device Overview
63
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2.10 Related Documentation from Texas Instruments
These documents describe the TMS320C6654 Fixed and Floating-Point Digital Signal Processor. Copies of these
documents are available on the Internet at www.ti.com
PRODUCT PREVIEW
64-bit Timer (Timer 64) for KeyStone Devices User Guide
SPRUGV5
Bootloader for the C66x DSP User Guide
SPRUGY5
C66x CorePac User Guide
SPRUGW0
C66x CPU and Instruction Set Reference Guide
SPRUGH7
C66x DSP Cache User Guide
SPRUGY8
DDR3 Design Guide for KeyStone Devices
SPRABI1
DDR3 Memory Controller for KeyStone Devices User Guide
SPRUGV8
DSP Power Consumption Summary for KeyStone Devices
SPRABL4
Embedded Trace for KeyStone Devices User Guide
SPRUGZ2
Emulation and Trace Headers Technical Reference
SPRU655
Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide
SPRUGS5
External Memory Interface (EMIF16) for KeyStone Devices User Guide
SPRUGZ3
General Purpose Input/Output (GPIO) for KeyStone Devices User Guide
SPRUGV1
Gigabit Ethernet (GbE) Subsystem for KeyStone Devices User Guide
SPRUGV9
Hardware Design Guide for KeyStone Devices
SPRABI2
Inter Integrated Circuit (I2C) for KeyStone Devices User Guide
SPRUGV3
Chip Interrupt Controller (CIC) for KeyStone Devices User Guide
SPRUGW4
Memory Protection Unit (MPU) for KeyStone Devices User Guide
SPRUGW5
Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User Guide
Multicore Navigator for KeyStone Devices User Guide
SPRUGR9
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide
SPRUGW7
Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide
SPRUGS6
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide
SPRUGV2
Power Sleep Controller (PSC) for KeyStone Devices User Guide
SPRUGV4
Semaphore2 Hardware Module for KeyStone Devices User Guide
SPRUGS3
Serial Peripheral Interface (SPI) for KeyStone Devices User Guide
SPRUGP2
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide
SPRUGP1
Universal Parallel Port (UPP) for KeyStone Devices User Guide
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems
SPRA387
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs
SPRA753
Using IBIS Models for Timing Analysis
SPRA839
64
Device Overview
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
3 Device Configuration
On the TMS320C6654 device, certain device configurations like boot mode and endianess, are selected at device
power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device
configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors
or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The device
configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid
contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a
control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP
can be taken out of reset.
Also, please note that most of the device configuration pins are shared with other function pins
(LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0),
some time must be given following the rising edge of reset in order to drive these device configuration input pins
before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that
needs to be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the
clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal
pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external
pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in
which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on
page 86.
Table 3-1
TMS320C6654 Device Configuration Pins
Configuration Pin
LENDIAN
(1) (2)
BOOTMODE[12:0]
PCIESSMODE[1:0]
PCIESSEN
(1) (2)
(1) (2)
(1) (2)
Pin No.
IPD/IPU
(1)
Functional Description
T25
IPU
Device endian mode (LENDIAN).
0 = Device operates in big endian mode
1 = Device operates in little endian mode
R25, R3, U25, T23,
U24, T22, R21,
U22, U23, V23,
U21, T21, V22
IPD
Method of boot.
W21, V21
IPD
PCIe Subsystem mode selection.
00 = PCIe in end point mode
01 = PCIe legacy end point (support for legacy INTx)
10 = PCIe in root complex mode
11 = Reserved
AD20
IPD
PCIe subsystem enable/disable.
0 = PCIE Subsystem is disabled
1 = PCIE Subsystem is enabled
Some pins may not be used by bootloader and can be used as general purpose config
pins. Refer to the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from
Texas Instruments’’ on page 64 for how to determine the device enumeration ID value.
End of Table 3-1
1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on
pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 86.
2 These signal names are the secondary functions of these pins.
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
Device Configuration
65
PRODUCT PREVIEW
3.1 Device Configuration at Device Reset
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320C6654 are controlled by the Power Sleep Controller (PSC). By default, the
PCIe is held in reset and clock-gated. The memory in this module is also in a low-leakage sleep mode. Software is
required to turn this memory on. The software enables the module (turns on clocks and de-asserts reset) before this
module can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
PRODUCT PREVIEW
3.3 Device State Control Registers
The TMS320C6654 device has a set of registers that are used to provide the status or configure certain parts of its
peripherals. These registers are shown in Table 3-2.
Table 3-2
Device State Control Registers (Part 1 of 4)
Address Start
Address End
Size
Field
0x02620000
0x02620007
8B
Reserved
0x02620008
0x02620017
16B
Reserved
0x02620018
0x0262001B
4B
JTAGID
0x0262001C
0x0262001F
4B
Reserved
0x02620020
0x02620023
4B
DEVSTAT
0x02620024
0x02620037
20B
Reserved
0x02620038
0x0262003B
4B
KICK0
0x0262003C
0x0262003F
4B
KICK1
0x02620040
0x02620043
4B
DSP_BOOT_ADDR0
The boot address for C66x DSP CorePac0
0x02620044
0x02620047
4B
Reserved
Reserved
0x02620048
0x0262004B
4B
Reserved
0x0262004C
0x0262004F
4B
Reserved
0x02620050
0x02620053
4B
Reserved
0x02620054
0x02620057
4B
Reserved
0x02620058
0x0262005B
4B
Reserved
0x0262005C
0x0262005F
4B
Reserved
0x02620060
0x026200DF
128B
Reserved
0x026200E0
0x0262010F
48B
Reserved
0x02620110
0x02620117
8B
MACID
0x02620118
0x0262012F
24B
Reserved
0x02620130
0x02620133
4B
LRSTNMIPINSTAT_CLR
See section 3.3.6
0x02620134
0x02620137
4B
RESET_STAT_CLR
See section 3.3.8
0x02620138
0x0262013B
4B
Reserved
0x0262013C
0x0262013F
4B
BOOTCOMPLETE
0x02620140
0x02620143
4B
Reserved
0x02620144
0x02620147
4B
RESET_STAT
0x02620148
0x0262014B
4B
LRSTNMIPINSTAT
See section 3.3.5
0x0262014C
0x0262014F
4B
DEVCFG
See section 3.3.2
66
Device Configuration
Description
See section 3.3.3
See section 3.3.1
See section 3.3.4
See section 7.16 ‘‘Ethernet Media Access Controller (EMAC)’’ on
page 195
See section 3.3.9
See section 3.3.7
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 3-2
Device State Control Registers (Part 2 of 4)
Address Start
Address End
Size
Field
Description
0x02620150
0x02620153
4B
PWRSTATECTL
See section 3.3.10
0x02620154
0x02620157
4B
Reserved
0x02620158
0x0262015B
4B
SMGII_SERDES_STS
0x0262015C
0x0262015F
4B
PCIE_SERDES_STS
0x02620160
0x02620163
4B
Reserved
0x02620164
0x02620167
4B
Reserved
0x02620168
0x0262016B
4B
Reserved
0x0262016F
4B
UPP_CLOCK
0x02620170
0x02620183
20B
Reserved
0x02620184
0x0262018F
12B
Reserved
0x02620190
0x02620193
4B
Reserved
0x02620194
0x02620197
4B
Reserved
0x02620198
0x0262019B
4B
Reserved
0x0262019C
0x0262019F
4B
Reserved
0x026201A0
0x026201A3
4B
Reserved
0x026201A4
0x026201A7
4B
Reserved
0x026201A8
0x026201AB
4B
Reserved
0x026201AC
0x026201AF
4B
Reserved
0x026201B0
0x026201B3
4B
Reserved
0x026201B4
0x026201B7
4B
Reserved
0x026201B8
0x026201BB
4B
Reserved
0x026201BC
0x026201BF
4B
Reserved
0x026201C0
0x026201C3
4B
Reserved
0x026201C4
0x026201C7
4B
Reserved
0x026201C8
0x026201CB
4B
Reserved
0x026201CC
0x026201CF
4B
Reserved
0x026201D0
0x026201FF
48B
Reserved
0x02620200
0x02620203
4B
NMIGR0
0x02620204
0x02620207
4B
Reserved
0x02620208
0x0262020B
4B
Reserved
0x0262020C
0x0262020F
4B
Reserved
0x02620210
0x02620213
4B
Reserved
0x02620214
0x02620217
4B
Reserved
0x02620218
0x0262021B
4B
Reserved
0x0262021C
0x0262021F
4B
Reserved
0x02620220
0x0262023F
32B
Reserved
0x02620240
0x02620243
4B
IPCGR0
0x02620244
0x02620247
4B
Reserved
0x02620248
0x0262024B
4B
Reserved
0x0262024C
0x0262024F
4B
Reserved
0x02620250
0x02620253
4B
Reserved
0x02620254
0x02620257
4B
Reserved
0x02620258
0x0262025B
4B
Reserved
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
See section 3.3.22
PRODUCT PREVIEW
0x0262016C
See ‘‘Related Documentation from Texas Instruments’’ on page 64
See section 3.3.11
See section 3.3.12
Device Configuration
67
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 3-2
www.ti.com
Device State Control Registers (Part 3 of 4)
Address Start
Address End
Size
Field
0x0262025C
0x0262025F
4B
Reserved
0x02620260
0x0262027B
28B
Reserved
Description
PRODUCT PREVIEW
0x0262027C
0x0262027F
4B
IPCGRH
See section 3.3.14
0x02620280
0x02620283
4B
IPCAR0
See section 3.3.13
0x02620284
0x02620287
4B
Reserved
0x02620288
0x0262028B
4B
Reserved
0x0262028C
0x0262028F
4B
Reserved
0x02620290
0x02620293
4B
Reserved
0x02620294
0x02620297
4B
Reserved
0x02620298
0x0262029B
4B
Reserved
0x0262029C
0x0262029F
4B
Reserved
0x026202A0
0x026202BB
28B
Reserved
0x026202BC
0x026202BF
4B
IPCARH
0x026202C0
0x026202FF
64B
Reserved
0x02620300
0x02620303
4B
TINPSEL
See section 3.3.16
See section 3.3.15
0x02620304
0x02620307
4B
TOUTPSEL
See section 3.3.17
0x02620308
0x0262030B
4B
RSTMUX0
See section 3.3.18
0x0262030C
0x0262030F
4B
Reserved
0x02620310
0x02620313
4B
Reserved
0x02620314
0x02620317
4B
Reserved
0x02620318
0x0262031B
4B
Reserved
0x0262031C
0x0262031F
4B
Reserved
0x02620320
0x02620323
4B
Reserved
0x02620324
0x02620327
4B
Reserved
0x02620328
0x0262032B
4B
MAINPLLCTL0
0x0262032C
0x0262032F
4B
MAINPLLCTL1
0x02620330
0x02620333
4B
DDR3PLLCTL
0x02620334
0x02620337
4B
Reserved
0x02620338
0x0262033B
4B
Reserved
0x0262033C
0x0262033F
4B
Reserved
0x02620340
0x02620343
4B
SGMII_SERDES_CFGPLL
0x02620344
0x02620347
4B
SGMII_SERDES_CFGRX0
0x02620348
0x0262034B
4B
SGMII_SERDES_CFGTX0
0x0262034C
0x0262034F
4B
Reserved
0x02620350
0x02620353
4B
Reserved
0x02620354
0x02620357
4B
Reserved
0x02620358
0x0262035B
4B
PCIE_SERDES_CFGPLL
0x0262035C
0x0262035F
4B
Reserved
68
Device Configuration
See section 7.5 ‘‘Main PLL and PLL Controller’’ on page 126
See section 7.6 ‘‘DD3 PLL’’ on page 139
See ‘‘Related Documentation from Texas Instruments’’ on page 64
Copyright 2012 Texas Instruments Incorporated
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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Device State Control Registers (Part 4 of 4)
Address Start
Address End
Size
Field
0x02620360
0x02620363
4B
Reserved
0x02620364
0x02620367
4B
Reserved
0x02620368
0x0262036B
4B
Reserved
0x0262036C
0x0262036F
4B
Reserved
0x02620370
0x02620373
4B
Reserved
0x02620374
0x02620377
4B
Reserved
0x02620378
0x0262037B
4B
Reserved
0x0262037C
0x0262037F
4B
Reserved
0x02620380
0x02620383
4B
Reserved
0x02620384
0x02620387
4B
Reserved
0x02620388
0x026203AF
28B
Reserved
0x026203B0
0x026203B3
4B
Reserved
0x026203B4
0x026203B7
4B
Reserved
0x026203B8
0x026203BB
4B
Reserved
0x026203BC
0x026203BF
4B
Reserved
0x026203C0
0x026203C3
4B
Reserved
0x026203C4
0x026203C7
4B
Reserved
0x026203C8
0x026203CB
4B
Reserved
0x026203CC
0x026203CF
4B
Reserved
0x026203D0
0x026203D3
4B
Reserved
0x026203D4
0x026203D7
4B
Reserved
0x026203D8
0x026203DB
4B
Reserved
0x026203DC
0x026203F7
28B
Reserved
0x026203F8
0x026203FB
4B
DEVSPEED
0x026203FC
0x026203FF
4B
Reserved
Description
PRODUCT PREVIEW
Table 3-2
See section 3.3.19
0x02620400
0x02620403
4B
PKTDMA_PRI_ALLOC
0x02620404
0x02620467
100B
Reserved
See section 4.4 ‘‘Bus Priorities’’ on page 94
0x02620468
0x0262057f
280B
Reserved
0x02620580
0x02620583
4B
PIN_CONTROL_0
See section 3.3.20
0x02620584
0x02620587
4B
PIN_CONTROL_1
See section 3.3.21
0x02620588
0x0262058B
4B
EMAC_UPP_PRI_ALLOC
See section 4.4 ‘‘Bus Priorities’’ on page 94
End of Table 3-2
3.3.1 Device Status Register
The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or
RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device Status Register is
shown in Figure 3-1 and described in Table 3-3.
Figure 3-1
Device Status Register
31
17
Reserved
16
15
14
13
1
0
PCIESSEN
PCIESSMODE[1:0
BOOTMODE[12:0]
LENDIAN
R-x
R/W-xx
R/W-xxxxxxxxxxxx
R-x (1)
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 3-3
Bit
www.ti.com
Device Status Register Field Descriptions
Field
Description
PRODUCT PREVIEW
31-17
Reserved
Reserved. Read only, writes have no effect.
16
PCIESSEN
PCIe module enable
0 = PCIe module disabled
1 = PCIe module enabled
15-14
PCIESSMODE[1:0]
PCIe Mode selection pins
00b = PCIe in End-point mode
01b = PCIe in Legacy End-point mode (support for legacy INTx)
10b = PCIe in Root complex mode
11b = Reserved
13-1
BOOTMODE[12:0]
Determines the bootmode configured for the device. For more information on bootmode, refer to Section 2.5 ‘‘Boot
Modes Supported and PLL Settings’’ on page 25 and see the Bootloader for the C66x DSP User Guide in 2.10 ‘‘Related
Documentation from Texas Instruments’’ on page 64
0
LENDIAN
Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little
Endian mode.
0 = System is operating in Big Endian mode
1 = System is operating in Little Endian mode
End of Table 3-3
3.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets
and is locked after the first write. The Device Configuration Register is shown in Figure 3-2 and described in
Table 3-4.
Figure 3-2
Device Configuration Register (DEVCFG)
31
1
0
Reserved
SYSCLKOUTEN
R-0
R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-4
Device Configuration Register Field Descriptions
Bit
Field
Description
31-1
Reserved
Reserved. Read only, writes have no effect.
0
SYSCLKOUTEN
SYSCLKOUT Enable
0 = No clock output
1 = Clock output enabled (default)
End of Table 3-4
70
Device Configuration
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3.3.3 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the
JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3 and
described in Table 3-5.
Figure 3-3
JTAG ID (JTAGID) Register
31
28
27
12
11
1
0
VARIANT
PART NUMBER
MANUFACTURER
LSB
R-xxxxb
R-1011 1001 0111 1010b
0000 0010 111b
R-1
Legend: RW = Read/Write; R = Read only; -n = value after reset
JTAG ID Register Field Descriptions
Bit
Field
Value
Description
31-28
VARIANT
xxxxb
Variant (4-Bit) value.
27-12
PART NUMBER
1011 1001 0111 1010b
Part Number for boundary scan
11-1
MANUFACTURER
0000 0010 111b
Manufacturer
0
LSB
1b
This bit is read as a 1 for TMS320C6654
PRODUCT PREVIEW
Table 3-5
End of Table 3-5
Note—The value of the VARIANT and PART NUMBER fields depend on the silicon revision being used.
See the Silicon Errata for details.
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are
writable (they are only readable). On the C6654, the exception to this are the IPC registers such as IPCGRx and
IPCARx. These registers are not protected by the kicker mechanism. This mechanism requires two MMR writes to
the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See
Table 3-2 ‘‘Device State Control Registers’’ on page 66 for the address location. Once released then all the Bootcfg
MMRs having write permissions are writable (the read only MMRs are still read only). The first KICK0 data is
0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will
lock the kicker mechanism and block any writes to Bootcfg MMRs. To ensure protection to all Bootcfg MMRs,
software must always re-lock the kicker mechanism after completing the MMR writes.
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3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown and described in the following tables.
Figure 3-4
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
18
17
16
Reserved
Reserved
NMI0
R, +0000 0000
R-0
R-0
15
2
1
0
Reserved
Reserved
LR0
R, +0000 0000
R-0
R-0
Legend: R = Read only; -n = value after reset;
Table 3-6
Bit
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
PRODUCT PREVIEW
Field
Description
31-18
Reserved
Reserved
17
Reserved
Reserved
16
NMI0
CorePac0 in NMI
15-2
Reserved
Reserved
1
Reserved
Reserved
0
LR0
CorePac0 in Local Reset
End of Table 3-6
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The
LRESETNMI PIN Status Clear Register is shown and described in the following tables.
Figure 3-5
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
18
17
16
Reserved
Reserved
NMI0
R, +0000 0000
WC,+0
WC,+0
15
2
1
0
Reserved
Reserved
LR0
R, +0000 0000
WC,+0
WC,+0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Table 3-7
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
Bit
Field
Description
31-18
Reserved
Reserved
17
Reserved
Reserved
16
NMI0
CorePac0 in NMI Clear
15-2
Reserved
Reserved
1
Reserved
Reserved
0
LR0
CorePac0 in Local Reset Clear
End of Table 3-7
72
Device Configuration
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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3.3.7 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.
• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.
• In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is
asserted.
The Reset Status Register is shown and described in the following tables.
31
Reset Status Register (RESET_STAT)
30
2
1
0
GR
Reserved
Reserved
LR0
R, +1
R, + 000 0000 0000 0000 0000 0000
R,+0
R,+0
PRODUCT PREVIEW
Figure 3-6
Legend: R = Read only; -n = value after reset
Table 3-8
Reset Status Register (RESET_STAT) Field Descriptions
Bit
Field
Description
31
GR
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
30-2
Reserved
Reserved.
1
Reserved
Reserved.
0
LR0
CorePac0 reset status
0 = CorePac0 has not received a local reset.
1 = CorePac0 received a local reset.
End of Table 3-8
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3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown and described in the following tables.
Figure 3-7
31
Reset Status Clear Register (RESET_STAT_CLR)
30
2
1
0
GR
Reserved
Reserved
LR0
RW, +0
R, + 000 0000 0000 0000 0000 0000
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-9
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
PRODUCT PREVIEW
Bit
Field
Description
31
GR
Global reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
30-2
Reserved
Reserved.
1
Reserved
Reserved.
0
LR0
CorePac0 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
End of Table 3-9
3.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the
completion of the ROM booting process. The Boot Complete Register is shown and described in the following tables.
Figure 3-8
Boot Complete Register (BOOTCOMPLETE)
31
2
1
0
Reserved
Reserved
BC0
R, + 0000 0000 0000 0000 0000 0000
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-10
Boot Complete Register (BOOTCOMPLETE) Field Descriptions
Bit
Field
Description
31-2
Reserved
Reserved.
1
Reserved
Reserved
0
BC0
CorePac0 boot status
0 = CorePac0 boot NOT complete
1 = CorePac0 boot complete
End of Table 3-10
The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is
they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.
74
Device Configuration
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Fixed and Floating-Point Digital Signal Processor
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Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before
branching to the predefined location in memory.
3.3.10 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this
register to differentiate between the various power saving modes. This register is cleared only by POR and will
survive all other device resets. See the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from
Texas Instruments’’ on page 64 for more information. The Power State Control Register is shown in Figure 3-9 and
described in Table 3-11.
Power State Control Register (PWRSTATECTL)
31
3
2
1
0
GENERAL_PURPOSE
HIBERNATION_MODE
HIBERNATION
STANDBY
RW, +0000 0000 0000 0000 0000 0000 0000 0
RW,+0
RW,+0
RW,+0
Legend: RW = Read/Write; -n = value after reset
Table 3-11
Power State Control Register (PWRSTATECTL) Field Descriptions
Bit
Field
Description
31-3
GENERAL_PURPOSE
Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
2
HIBERNATION_MODE
Indicates whether the device is in hibernation mode 1 or mode 2.
0 = Hibernation mode 1
1 = Hibernation mode 2
1
HIBERNATION
Indicates whether the device is in hibernation mode or not.
0 = Not in hibernation mode
1 = Hibernation mode
0
STANDBY
Indicates whether the device is in standby mode or not.
0 = Not in standby mode
1 = Standby mode
End of Table 3-11
3.3.11 NMI Event Generation to CorePac (NMIGRx) Register
NMIGRx registers are used for generating NMI events to the CorePac. The C6654 has only NMIGR0, which
generates an NMI event to the CorePac. Writing a 1 to the NMIG field generates a NMI pulse. Writing a 0 has no
effect and reads return 0 and have no other effect. The NMI Even Generation to CorePac Register is shown in
Figure 3-10 and described in Table 3-12.
Figure 3-10
NMI Generation Register (NMIGRx)
31
1
0
Reserved
NMIG
R, +0000 0000 0000 0000 0000 0000 0000 000
RW,+0
Legend: RW = Read/Write; -n = value after reset
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PRODUCT PREVIEW
Figure 3-9
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 3-12
www.ti.com
NMI Generation Register (NMIGRx) Field Descriptions
Bit
Field
Description
31-1
Reserved
Reserved
0
NMIG
NMI pulse generation.
Reads return 0
Writes:
0 = No effect
1 = Sends an NMI pulse to the CorePac
End of Table 3-12
3.3.12 IPC Generation (IPCGRx) Registers
PRODUCT PREVIEW
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The C6654 has only IPCGR0. This register can be used by external hosts to generate interrupts to the CorePac. A
write of 1 to the IPCG field of the IPCGRx register will generate an interrupt pulse to the CorePac.
This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified.
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is
completely controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Generation Register is shown in Figure 3-11 and described in Table 3-13.
Figure 3-11
IPC Generation Registers (IPCGRx)
31
30
29
28
SRCS27
SRCS26
SRCS25
SRCS24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
1
0
SRCS23 – SRCS4
SRCS3
SRCS2
SRCS1
SRCS0
Reserved
IPCG
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-13
IPC Generation Registers (IPCGRx) Field Descriptions
Bit
Field
Description
31-4
SRCSx
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
Reserved
Reserved
0
IPCG
Inter-DSP interrupt generation.
Reads return 0.
Writes:
0 = No effect
1 = Creates an Inter-DSP interrupt.
End of Table 3-13
76
Device Configuration
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Fixed and Floating-Point Digital Signal Processor
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3.3.13 IPC Acknowledgement (IPCARx) Registers
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
The C6654 has only IPCAR0. This register also provides a Source ID facility by which up to 28 different sources of
interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software
convention. The register field descriptions are shown in the following tables. Virtually anything can be a source for
these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space
can write to these registers. The IPC Acknowledgement Register is shown in Figure 3-12 and described in
Table 3-14.
IPC Acknowledgement Registers (IPCARx)
31
30
29
28
SRCC27
SRCC26
SRCC25
SRCC24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
0
SRCC23 – SRCC4
SRCC3
SRCC2
SRCC1
SRCC0
Reserved
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +0000
PRODUCT PREVIEW
Figure 3-12
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-14
IPC Acknowledgement Registers (IPCARx) Field Descriptions
Bit
Field
Description
31-4
SRCCx
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-14
3.3.14 IPC Generation Host (IPCGRH) Register
IPCGRH register is provided to facilitate host DSP interrupt. Operation and use of IPCGRH is the same as
other IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event
output (HOUT).
The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6)
followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking
window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle
period. The IPC Generation Host Register is shown in Figure 3-13 and described in Table 3-15.
Figure 3-13
IPC Generation Registers (IPCGRH)
31
30
29
28
SRCS27
SRCS26
SRCS25
SRCS24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
1
0
SRCS23 – SRCS4
SRCS3
SRCS2
SRCS1
SRCS0
Reserved
IPCG
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 3-15
www.ti.com
IPC Generation Registers (IPCGRH) Field Descriptions
Bit
Field
Description
31-4
SRCSx
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
Reserved
Reserved
0
IPCG
Host interrupt generation.
Reads return 0.
PRODUCT PREVIEW
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-15
3.3.15 IPC Acknowledgement Host (IPCARH) Register
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in
Table 3-16.
Figure 3-14
IPC Acknowledgement Register (IPCARH)
31
30
29
28
SRCC27
SRCC26
SRCC25
SRCC24
RW +0
RW +0
RW +0
RW +0
27
8
7
6
5
4
3
0
SRCC23 – SRCC4
SRCC3
SRCC2
SRCC1
SRCC0
Reserved
RW +0 (per bit field)
RW +0
RW +0
RW +0
RW +0
R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-16
IPC Acknowledgement Register (IPCARH) Field Descriptions
Bit
Field
Description
31-4
SRCCx
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-16
78
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Fixed and Floating-Point Digital Signal Processor
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3.3.16 Timer Input Selection Register (TINPSEL)
Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown
in Figure 3-15 and described in Table 3-17
Figure 3-15
Timer Input Selection Register (TINPSEL)
31
16
Reserved
R, +1010 1010 1010 1010
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TINPH
SEL7
TINPL
SEL7
TINPH
SEL6
TINPL
SEL6
TINPH
SEL5
TINPL
SEL5
TINPH
SEL4
TINPL
SEL4
TINPH
SEL3
TINPL
SEL3
TINPH
SEL2
TINPL
SEL2
TINPH
SEL1
TINPL
SEL1
TINPH
SEL0
TINPL
SEL0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
RW, +1
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-17
Bit
Timer Input Selection Field Description (TINPSEL) (Part 1 of 2)
Field
31-16 Reserved
Description
Reserved
15
TINPHSEL7
Input select for TIMER7 high.
0 = TIMI0
1 = TIMI1
14
TINPLSEL7
Input select for TIMER7 low.
0 = TIMI0
1 = TIMI1
13
TINPHSEL6
Input select for TIMER6 high.
0 = TIMI0
1 = TIMI1
12
TINPLSEL6
Input select for TIMER6 low.
0 = TIMI0
1 = TIMI1
11
TINPHSEL5
Input select for TIMER5 high.
0 = TIMI0
1 = TIMI1
10
TINPLSEL5
Input select for TIMER5 low.
0 = TIMI0
1 = TIMI1
9
TINPHSEL4
Input select for TIMER4 high.
0 = TIMI0
1 = TIMI1
8
TINPLSEL4
Input select for TIMER4 low.
0 = TIMI0
1 = TIMI1
7
TINPHSEL3
Input select for TIMER3 high.
0 = TIMI0
1 = TIMI1
6
TINPLSEL3
Input select for TIMER3 low.
0 = TIMI0
1 = TIMI1
5
TINPHSEL2
Input select for TIMER2 high.
0 = TIMI0
1 = TIMI1
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Device Configuration
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PRODUCT PREVIEW
spacer
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 3-17
www.ti.com
Timer Input Selection Field Description (TINPSEL) (Part 2 of 2)
PRODUCT PREVIEW
Bit
Field
Description
4
TINPLSEL2
Input select for TIMER2 low.
0 = TIMI0
1 = TIMI1
3
TINPHSEL1
Input select for TIMER1 high.
0 = TIMI0
1 = TIMI1
2
TINPLSEL1
Input select for TIMER1 low.
0 = TIMI0
1 = TIMI1
1
TINPHSEL0
Input select for TIMER0 high.
0 = TIMI0
1 = TIMI1
0
TINPLSEL0
Input select for TIMER0 low.
0 = TIMI0
1 = TIMI1
80
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Fixed and Floating-Point Digital Signal Processor
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3.3.17 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-16 and described in Table 3-18.
Figure 3-16
Timer Output Selection Register (TOUTPSEL)
31
10
9
5
4
0
Reserved
TOUTPSEL1
TOUTPSEL0
R,+000000000000000000000000
RW,+00001
RW,+00000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Timer Output Selection Field Description (TOUTPSEL)
Bit
Field
Description
31-10
Reserved
Reserved
9-5
TOUTPSEL1
Output select for TIMO1
0x0: TOUTL0
0x1: TOUTH0
0x2: TOUTL1
0x3: TOUTH1
0x4: TOUTL2
0x5: TOUTH2
0x6: TOUTL3
0x7: TOUTH3
0x8: TOUTL4
0x9: TOUTH4
0xA: TOUTL5
0xB: TOUTH5
0xC: TOUTL6
0xD: TOUTH6
0xE: TOUTL7
0xF: TOUTH7
0x10 to 0x1F: Reserved
Output select for TIMO0
0x0: TOUTL0
0x1: TOUTH0
0x2: TOUTL1
0x3: TOUTH1
0x4: TOUTL2
0x5: TOUTH2
0x6: TOUTL3
0x7: TOUTH3
0x8: TOUTL4
0x9: TOUTH4
0xA: TOUTL5
0xB: TOUTH5
0xC: TOUTL6
0xD: TOUTH6
0xE: TOUTL7
0xF: TOUTH7
0x10 to 0x1F: Reserved
4-0
TOUTPSEL0
PRODUCT PREVIEW
Table 3-18
End of Table 3-18
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0. This register is
located in Bootcfg memory space. The Reset Mux Register is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17
Reset Mux Register RSTMUXx
31
10
9
8
7
5
4
3
1
0
Reserved
EVTSTATCLR
Reserved
DELAY
EVTSTAT
OMODE
LOCK
R, +0000 0000 0000 0000 0000 00
RC, +0
R, +0
RW, +100
R, +0
RW, +000
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
Table 3-19
Reset Mux Register Field Descriptions
PRODUCT PREVIEW
Bit
Field
Description
31-10
Reserved
Reserved
9
EVTSTATCLR
Clear event status
0 = Writing 0 has no effect
1 = Writing 1 clears the EVTSTAT bit
8
Reserved
Reserved
7-5
DELAY
Delay cycles between NMI & local reset
000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)
101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
4
EVTSTAT
Event status.
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
3-1
OMODE
Timer event operation mode
000b = WD timer event input to the reset mux block does not cause any output event (default)
001b = Reserved
010b = WD timer event input to the reset mux block causes local reset input to CorePac
011b = WD timer event input to the reset mux block causes NMI input to CorePac
100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay
between NMI and local reset is set in DELAY bit field.
101b = WD timer event input to the reset mux block causes device reset to C6654
110b = Reserved
111b = Reserved
0
LOCK
Lock register fields
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
End of Table 3-19
82
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Fixed and Floating-Point Digital Signal Processor
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3.3.19 Device Speed (DEVSPEED) Register
The Device Speed Register indicates the device speed grade. The Device Speed Register is shown in Figure 3-18 and
described in Table 3-20.
Figure 3-18
Device Speed Register (DEVSPEED)
31
30
23
22
0
Reserved
DEVSPEED
Reserved
R-n
R-n
R-n
Legend: R = Read only; RW = Read/Write; -n = value after reset
Device Speed Register Field Descriptions
Bit
Field
Description
31
Reserved
Reserved. Read only
30-23
DEVSPEED
Indicates the speed of the device (Read Only)
1xxx xxxxb = 850 MHz
01xx xxxxb = Reserved
001x xxxxb = Reserved
0001 xxxxb = Reserved
0000 1xxxb = Reserved
0000 01xxb = Reserved
0000 001xb = Reserved
0000 0001b = 850 MHz
0000 0000b = 850 MHz
22-0
Reserved
Reserved. Read only
PRODUCT PREVIEW
Table 3-20
End of Table 3-20
3.3.20 Pin Control 0 (PIN_CONTROL_0) Register
The Pin Control 0 Register controls the pin muxing between GPIO[16:31] and TIMER / UART / SPI pins. The Pin
Control 0 Register is shown in Figure 3-19 and described in Table 3-21.
Figure 3-19
Pin Control 0 Register (PIN_CONTROL_0)
31
30
29
28
27
26
25
24
GPIO31_SPIDOU GPIO30_SPIDIN_ GPIO29_SPICS1_ GPIO28_SPICS0_ GPIO27_UARTRT GPIO26_UARTCT GPIO25_UARTTX GPIO24_UARTRX
T_MUX
MUX
MUX
MUX
S1_MUX
S1_MUX
1_MUX
1_MUX
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
22
21
20
19
18
17
16
GPIO18_TIMO0_
MUX
GPIO17_TIMI1_
MUX
GPIO16_TIMI0_
MUX
RW-0
RW-0
RW-0
spacer
23
GPIO23_UARTRT GPIO22_UARTCT GPIO21_UARTTX GPIO20_UARTRX GPIO19_TIMO1_
S0_MUX
S0_MUX
0_MUX
0_MUX
MUX
RW-0
RW-0
RW-0
RW-0
RW-0
spacer
15
0
Reserved
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
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Fixed and Floating-Point Digital Signal Processor
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Table 3-21
www.ti.com
Pin Control 0 Register Field Descriptions
PRODUCT PREVIEW
Bit
Field
Description
31
GPIO31_SPIDOUT_MUX
SPI or GPIO mux control
0 = SPIDOUT pin enabled
1 = GPIO31 pin enabled
30
GPIO30_SPIDIN_MUX
SPI or GPIO mux control
0 = SPIDIN pin enabled
1 = GPIO30 pin enabled
29
GPIO29_SPICS1_MUX
SPI or GPIO mux control
0 = SPICS1 pin enabled
1 = GPIO29 pin enabled
28
GPIO28_SPICS0_MUX
SPI or GPIO mux control
0 = SPICS0 pin enabled
1 = GPIO28 pin enabled
27
GPIO27_UARTRTS1_MUX
UART or GPIO mux control
0 = UARTRTS1 pin enabled
1 = GPIO27 pin enabled
26
GPIO26_UARTCTS1_MUX
UART or GPIO mux control
0 = UARTCTS1 pin enabled
1 = GPIO26 pin enabled
25
GPIO25_UARTTX1_MUX
UART or GPIO mux control
0 = UARTTX1 pin enabled
1 = GPIO25 pin enabled
24
GPIO24_UARTRX1_MUX
UART or GPIO mux control
0 = UARTRX1 pin enabled
1 = GPIO24 pin enabled
23
GPIO23_UARTRTS0_MUX
UART or GPIO mux control
0 = UARTRTS0 pin enabled
1 = GPIO23 pin enabled
22
GPIO22_UARTCTS0_MUX
UART or GPIO mux control
0 = UARTCTS0 pin enabled
1 = GPIO22 pin enabled
21
GPIO21_UARTTX0_MUX
UART or GPIO mux control
0 = UARTTX0 pin enabled
1 = GPIO21 pin enabled
20
GPIO20_UARTRX0_MUX
UART or GPIO mux control
0 = UARTRX0 pin enabled
1 = GPIO20 pin enabled
19
GPIO19_TIMO1_MUX
TIMER or GPIO mux control
0 = TIMO1 pin enabled
1 = GPIO19 pin enabled
18
GPIO18_TIMO0_MUX
TIMER or GPIO mux control
0 = TIMO0 pin enabled
1 = GPIO18 pin enabled
17
GPIO17_TIMI1_MUX
TIMER or GPIO mux control
0 = TIMI1 pin enabled
1 = GPIO17 pin enabled
16
GPIO16_TIMI0_MUX
TIMER or GPIO mux control
0 = TIMI0 pin enabled
1 = GPIO16 pin enabled
15-0
Reserved
Reserved
End of Table 3-21
84
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Fixed and Floating-Point Digital Signal Processor
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3.3.21 Pin Control 1 (PIN_CONTROL_1) Register
The Pin Control 0 Register controls the pin muxing between UPP and EMIF16 pins. The Pin Control 1 Register is
shown in Figure 3-20 and described in Table 3-22.
Figure 3-20
Pin Control 1Register (PIN_CONTROL_1)
31
1
0
Reserved
UPP_EMIF16_MUX
R-0
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Pin Control 1 Register Field Descriptions
Bit
Field
Description
31-1
Reserved
Reserved
0
UPP_EMIF_MUX
UPP or EMIF16 mux control
0 = EMIF16 pins enabled
1 = UPP pins enabled
PRODUCT PREVIEW
Table 3-22
End of Table 3-22
3.3.22 UPP Clock Source (UPP_CLOCK) Register
The UPP Clock Source Register controls whether the UPP transmit clock is internally or externally sourced. The
UPP Clock Source Register is shown in Figure 3-21 and described in Table 3-23.
Figure 3-21
Pin Control 1Register (PIN_CONTROL_1)
31
1
0
Reserved
UPP_TX_CLKSRC
R-0
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-23
Pin Control 1 Register Field Descriptions
Bit
Field
Description
31-1
Reserved
Reserved
0
UPP_TX_CLKSRC
UPP clock source selection
0 = from internal SYSCLK4 (CPU/3)
1 = from external UPP_2XTXCLK pin
End of Table 3-23
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3.4 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This
may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown
(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown
resistor to pull the signal to the opposite rail.
PRODUCT PREVIEW
For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state),
it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing
external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In
addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user
in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown
resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs
connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net.
A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which,
by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the
target pulled value when maximum current from all devices on the net is flowing through the resistor. The
current to be considered includes leakage current plus, any other internal and external pullup/pulldown
resistors on the net.
• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the
external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to
the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems:
• A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this
resistor value is correct for their specific application.
• A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the
above criteria. Users should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for
the TMS320C6654 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 105.
To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-17 ‘‘Terminal
Functions — Signals and Control by Function’’ on page 38.
86
Device Configuration
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4 System Interconnect
On the TMS320C6654 device, the C66x CorePac, the EDMA3 transfer controller, and the system peripherals are
interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contention-free
internal data movement. The TeraNet allows for low-latency, concurrent data transfers between master peripherals
and slave peripherals. The TeraNet also allows for seamless arbitration between the system masters when accessing
system slaves.
4.1 Internal Buses and Switch Fabrics
The C66x CorePac, the EDMA3 traffic controller, and the various system peripherals can be classified into two
categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely
on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the masters to perform transfers to and
from them. Examples of masters include the EDMA3 traffic controller and PCI Express. Examples of slaves include
2
the SPI, UART, and I C.
The masters and slaves in the device are communicating through the TeraNet (switch fabric). The device contains
two switch fabrics. The data switch fabric (data TeraNet) and the configuration switch fabric (configuration
TeraNet). The data TeraNet, is a high-throughput interconnect mainly used to move data across the system. The
data TeraNet connects masters to slaves via data buses. The configuration TeraNet, is mainly used to access
peripheral registers. The configuration TeraNet connects masters to slaves via configuration buses. Note that the
data TeraNet also connects to the configuration TeraNet. For more details see 4.2 ‘‘Switch Fabric Connections
Matrix’’ on page 88.
Copyright 2012 Texas Instruments Incorporated
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System Interconnect
87
PRODUCT PREVIEW
Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus
and a configuration bus interface, while others have only one type of interface. Further, the bus interface width and
speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a
peripheral and the data buses are used mainly for data transfers.
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
4.2 Switch Fabric Connections Matrix
The tables below list the master and slave end point connections.
Intersecting cells may contain one of the following:
• Y — There is a connection between this master and that slave.
• - — There is NO connection between this master and that slave.
• n — A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 4-1
Switch Fabric Connection Matrix Section 1
-
1
-
Timer
Y
Tracer
-
QMSS__CFG
-
Semaphore
-
EDMA3TC(0-3)
Y
EDMA3CC
Mcbsp1_FIFO_Data
Y
TETB0
Mcbsp0_FIFO_Data
Y
TETB_D
EMIF16
Y
STM
SPI
Y
MSMC_SES
Boot_ROM
EDMA3CC_TC0_RD
QM_Slave
PCIe0_Slave
PRODUCT PREVIEW
Masters
CorePac0_SDMA
Slaves
1
1
1
1
1
1,4
EDMA3CC_TC0_WR
Y
Y
-
Y
Y
-
-
-
Y
1
-
-
1
1
1
1
1
1, 4
EDMA3CC_TC1_RD
Y
Y
Y
Y
Y
2, 4
2, 4
-
Y
-
-
2
2
2
-
-
-
-
EDMA3CC_TC1_WR
Y
Y
-
Y
Y
2, 4
2, 4
-
Y
-
-
-
2
2
-
-
-
-
EDMA3CC_TC2_RD
Y
Y
Y
Y
Y
1, 4
1, 4
-
Y
-
1
-
1
1
1
1
1
1, 4
EDMA3CC_TC2_WR
Y
Y
-
Y
Y
1, 4
1, 4
-
Y
-
-
-
1
1
1
1
1
1, 4
EDMA3CC_TC3_RD
Y
Y
Y
Y
Y
-
-
2
Y
-
-
-
2
2
-
-
-
-
EDMA3CC_TC3_WR
Y
Y
-
Y
Y
-
-
2
Y
2
-
-
2
2
-
-
-
-
PCIe_Master
Y
-
-
Y
Y
1, 4
1, 4
1
Y
1
1
1
1
1
1
1
1
1, 4
EMAC
3
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
-
-
MSMC_Data_Master
Y
Y
Y
Y
Y
1, 4
1, 4
1
-
1
-
-
-
-
-
-
-
-
QM packet DMA
Y
-
-
-
-
-
-
1
Y
-
-
-
-
-
-
-
-
-
QM_Second
Y
-
Y
Y
Y
-
-
1
Y
-
-
-
-
-
-
-
-
-
DAP_Master
Y
Y
Y
Y
Y
1, 4
1, 4
1
Y
1
1
1
1
1
1
1
1
1, 4
CorePac0_CFG
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
Tracer_Master
-
-
-
-
-
-
-
-
-
1
Y
Y
Y
Y
Y
Y
Y
4
UPP
3
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
End of Table 4-1
88
System Interconnect
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 4-2
Switch Fabric Connection Matrix Section 2
I C
2
SEC_CTL
SEC_KEY_MGR
Efuse
Boot_CFG
PSC
PLL
CIC
MPU0-3
MPU4
Debug_SS_CFG
SmartReflex
UART_CFG (0-1)
McBSP_CFG(0-1)
McBSP_FIFO_CFG(0-1)
EMAC_CFG
UPP_CFG
EDMA3CC_TC0_RD
1,4
1,4
1,4
1,4
-
1,4
1,4
1,4
1,4
1
1,4
-
-
1,4
1,4
1,4
1,4
1
EDMA3CC_TC0_WR
1, 4
1, 4
1, 4
1, 4
-
1, 4
1, 4
1, 4
1, 4
1
1, 4
-
-
1, 4
1, 4
1, 4
1, 4
1
EDMA3CC_TC1_RD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC_TC1_WR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC_TC2_RD
1, 4
1, 4
1, 4
1, 4
-
1, 4
1, 4
1, 4
1, 4
1
1, 4
-
-
1, 4
1, 4
1, 4
1, 4
1
EDMA3CC_TC2_WR
1, 4
1, 4
1, 4
1, 4
-
1, 4
1, 4
1, 4
1, 4
1
1, 4
-
-
1, 4
1, 4
1, 4
1, 4
1
EDMA3CC_TC3_RD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC_TC3_WR
PCIe_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1, 4
1, 4
1, 4
1, 4
-
1, 4
1, 4
1, 4
1, 4
1
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1
-
EMAC
-
-
-
-
-
-
-
-
-
-
-
-
-
MSMC_Data_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
QM packet DMA
-
-
-
-
-
-
-
-
-
-
-
-
-
QM_Second
-
-
-
-
-
-
-
-
-
-
-
-
-
DAP_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1
EDMA3CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CorePac0_CFG
4
4
4
4
4
4
4
4
4
Y
4
4
4
4
4
4
4
Y
Tracer_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UPP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
End of Table 4-2
Copyright 2012 Texas Instruments Incorporated
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System Interconnect
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PRODUCT PREVIEW
Masters
GPIO
Slaves
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
4.3 TeraNet Switch Fabric Connections
The figures below show the connections between masters and slaves through various sections of the TeraNet.
Figure 4-1
TeraNet 3A
XMC
UPP
M
PRODUCT PREVIEW
PCIe
M
QM_SS
Packet DMA
M
QM_SS
Second
M
Debug_SS
M
TC_0
EDMA
CC
TC_1
TC_2
TC_3
M
M
M
M
TNet_3_D
CPU/3
S
SES
Bridge 3
S
SMS
M
S
MSMC
M
DDR3
Tracer_MSMC0
CPU/3
M
Tracer_MSMC1
Tracer_MSMC2
Tracer_MSMC3
Tracer_DDR
TeraNet 3_A
EMAC
Tracer_L2_0
MPU_1
Tracer_QM_M
TNet_6P_A
CPU/3
MPU_4
S
CorePac_0
S
QM_SS
S
PCIe
S
McBSP0
S
McBSP1
S
SPI
S
Boot_ROM
S
EMIF
Tracer_TN_6P_A
Bridge_1
To TeraNet_3P_A
Bridge_2
Figure 4-2
90
TeraNet 3P_A
System Interconnect
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
Bridge_2
From TeraNet_3_A
M
TeraNet 3P_A
CorePac_0
MPU0
S
MPU1
S
MPU2
S
MPU3
S
TC (× 4)
S
CC
MPU_2
S
QM_SS
MPU_3
S
Semaphore
TNet_3P_C
CPU/3
Tracer_QM_CFG
Tracer_SM
TETB (Debug_SS)
TETB (core)
To TeraNet_3P_Tracer
MPU_0
To TeraNet_3P_B
Tracer_CFG
TeraNet 3P_B
From TeraNet_3P_A
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TeraNet 3P_B
CPU/3
Figure 4-3
S
CPU/3
Bridge_1
PRODUCT PREVIEW
SPRS841—March 2012
www.ti.com
S
Tracer (×11)
S
UPP
To TeraNet_6P_B
Bridge_4
System Interconnect
91
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
TeraNet 3P_Tracer
From TeraNet_3P_A
PRODUCT PREVIEW
92
Tracer_
MSMC_0
M
Tracer_
MSMC_1
M
Tracer_
MSMC_2
M
Tracer_
MSMC_3
M
Tracer_CFG
M
Tracer_DDR
M
Tracer_SM
M
Tracer_
QM_M
M
Tracer_
QM_P
M
Tracer_L2_0
M
Tracer_TN_
6P_A
M
System Interconnect
TeraNet 3P_Tracer CPU/3
Figure 4-4
S
Debug_SS
STM
S
Debug_SS
TETB
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
TeraNet 6P_B
Bridge_4
TeraNet 6P_B CPU/6
From TeraNet_3P_B
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
S
SmartReflex
S
GPIO
S
IC
S
UART (× 2)
S
BOOTCFG
S
PSC
S
PLL_CTL
S
Debug_SS
S
CIC (× 3)
S
Timer (× 8)
S
MPU4
S
EMAC
S
McBSP × 2
S
SEC_CTL
S
SEC_KEY_MGR
S
Efuse
2
System Interconnect
PRODUCT PREVIEW
Figure 4-5
93
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
4.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means
higher priority - PRI = 000b = urgent, PRI = 111b = low.
Most master ports provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-based
peripherals also have internal registers to define the priority level of their initiated transactions.
Some masters do not have apriority allocation register of their own. For these masters, a priority allocation register
is provided for them and described in the sections below. For all other modules, see the respective User Guides in
“Related Documentation from Texas Instruments” on page 64 for programmable priority registers.
PRODUCT PREVIEW
4.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
The packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-6 and
Table 4-3.
Figure 4-6
Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
3
2
0
Reserved
PKTDMA_PRI
R/W-00000000000000000000001000011
RW-000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4-3
Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
Bit
Field
Description
31-3
Reserved
Reserved.
2-0
PKDTDMA_PRI
Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.
End of Table 4-3
4.4.2 EMAC / UPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
The EMAC and UPP are master ports that do not have priority allocation registers inside the IP. The priority level
for transaction from these master ports is described by EMAC_UPP_PRI_ALLOC register in Figure 4-7 and
Table 4-4.
Figure 4-7
31
EMAC / UPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC)
27 26
24 23
19 18
16 15
11 10
8 7
3 2
0
Reserved
EMAC_EPRI
Reserved
EMAC_PRI
Reserved
UPP_EPRI
Reserved
UPP_PRI
R-00000
RW-110
R-00000
RW-111
R-00000
RW-110
R-00000
RW-111
Legend: R = Read only; R/W = Read/Write; -n = value after reset
94
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 4-4
Bit
EMAC / UPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
Field
Description
31-27
Reserved
Reserved.
26-24
EMAC_EPRI
Control the maximum priority level for the transactions from EMAC master port.
23-19
Reserved
Reserved.
18-16
EMACA_PRI
Control the priority level for the transactions from EMAC master port.
15-11
Reserved
Reserved.
10-8
UPP_EPRI
Control the maximum priority level for the transactions from UPP master port.
7-3
Reserved
Reserved.
2-0
UPP_PRI
Control the priority level for the transactions from UPP master port.
PRODUCT PREVIEW
End of Table 4-4
Copyright 2012 Texas Instruments Incorporated
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System Interconnect
95
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
5 C66x CorePac
The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the
C66x CorePac) and address extension. Figure 5-1 shows a block diagram of the C66x CorePac.
Figure 5-1
C66x CorePac Block Diagram
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
In-Circuit Emulation
Boot
Controller
Instruction Decode
Data Path B
Data Path A
PLLC
LPSC
A Register File
B Register File
A31-A16
A15-A0
B31-B16
B15-B0
.M1
xx
xx
.M2
xx
xx
GPSC
.L1
.S1
.D1
.D2
.S2
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
.L2
Extended Memory
Controller (XMC)
C66x DSP Core
L2 Cache/
SRAM
1024KB
DDR3
SRAM
DMA Switch
Fabric
External Memory
Controller (EMC)
Program Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
Unified Memory
Controller (UMC)
32KB L1P
Interrupt and Exception Controller
PRODUCT PREVIEW
The C66x CorePac consists of several components:
• The C66x DSP and associated C66x CorePac core
• Level-one and level-two memories (L1P, L1D, L2)
• Data Trace Formatter (DTF)
• Embedded Trace Buffer (ETB)
• Interrupt Controller
• Power-down controller
• External Memory Controller
• Extended Memory Controller
• A dedicated power/sleep controller (LPSC)
CFG Switch
Fabric
32KB L1D
For more detailed information on the TMS320C66x CorePac on the C6654 device, see the C66x CorePac User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 64.
96
C66x CorePac
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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5.1 Memory Architecture
The C66x CorePac in the device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P),
and a 32KB level-1 data memory (L1D). All memory on the C6654 has a unique location in the memory map (see
Table 2-2 ‘‘Memory Map Summary’’ on page 21.
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be
reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the
L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way
set-associative cache, while L1P is a direct-mapped cache.
PRODUCT PREVIEW
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader
for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
5.1.1 L1P Memory
The L1P memory configuration for the C6654 device is as follows:
• 32K bytes with no wait states
Figure 5-2 shows the available SRAM/cache configurations for L1P.
Figure 5-2
L1P Memory Configurations
L1P mode bits
000
001
010
011
100
1/2
SRAM
All
SRAM
7/8
SRAM
L1P memory
Block base
address
00E0 0000h
16K bytes
3/4
SRAM
direct
mapped
cache
00E0 4000h
8K bytes
dm
cache
direct
mapped
cache
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
direct
mapped
cache
00E0 6000h
4K bytes
00E0 7000h
4K bytes
00E0 8000h
C66x CorePac
97
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
5.1.2 L1D Memory
The L1D memory configuration for the C6654 device is as follows:
• 32K bytes with no wait states
Figure 5-3 shows the available SRAM/cache configurations for L1D.
Figure 5-3
L1D Memory Configurations
L1D mode bits
000
001
010
011
100
PRODUCT PREVIEW
1/2
SRAM
All
SRAM
7/8
SRAM
L1D memory
Block base
address
00F0 0000h
16K bytes
3/4
SRAM
2-way
cache
00F0 4000h
8K bytes
2-way
cache
00F0 6000h
4K bytes
2-way
cache
2-way
cache
00F0 7000h
4K bytes
00F0 8000h
5.1.3 L2 Memory
The L2 memory configuration for the C6654 device is as follows:
• Total memory is 1024KB
• Each core contains 1024KB of memory
• Local starting address for each core is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register
(L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is
configured as all SRAM after device reset.
98
C66x CorePac
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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Figure 5-4
L2 Memory Configurations
L2 Mode Bits
000
001
010
011
100
101
110
L2 Memory
Block Base
Address
0080 0000h
1/2
SRAM
PRODUCT PREVIEW
512K bytes
3/4
SRAM
ALL
SRAM
31/32
SRAM
15/16
SRAM
7/8
SRAM
4-Way
Cache
0088 0000h
256K bytes
4-Way
Cache
008C 0000h
128K bytes
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
008E 0000h
64K bytes
32K bytes
32K bytes
008F 0000h
008F 8000h
008F FFFFh
Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by
the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled
within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address
location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can
access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000
only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.
For C66x CorePac Core 0, address 0x00800000 is equivalent to 0x10800000. Local addresses should be used only for
shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or
a memory region allocated during run-time by a particular core should always use the global address only.
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C66x CorePac
99
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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5.1.4 MSM Controller
The MSM configuration for the device is as follows:
• Allows extension of external addresses from 2GB to up to 8GB
• Has built in memory protection features
For more details on external memory address extension and memory protection features, see the Multicore Shared
Memory Controller (MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 64.
5.1.5 L3 Memory
The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement
to block accesses from this portion to the ROM.
PRODUCT PREVIEW
5.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2
memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB
each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in
the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In
addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct
DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by
other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a
secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether
memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 5-1.
Table 5-1
Available Memory Page Protection Schemes
AIDx Bit
Local Bit
0
0
Description
No access to memory page is permitted.
0
1
Only direct access by DSP is permitted.
1
0
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1
1
All accesses permitted.
End of Table 5-1
Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return 0, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
100
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5.3 Bandwidth Management
The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x
CorePac. These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the
Priority Allocation Register (PRI_ALLOC), see section 4.4 ‘‘Bus Priorities’’ on page 94 for more details. System
peripherals with no fields in the PRI_ALLOC have their own registers to program their priorities.
More information on the bandwidth management features of the C66x CorePac can be found in the C66x CorePac
User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
5.4 Power-Down Control
The C66x CorePac supports the ability to power down various parts of the C66x CorePac. The power down
controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and
the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power
requirements.
Note—The C6654 does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the TMS320C66x CorePac
Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
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PRODUCT PREVIEW
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to
the highest priority requestor. The following four resources are managed by the Bandwidth Management control
hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
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5.5 C66x CorePac Revision
The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID)
located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table 5-2. The
C66x CorePac revision is dependant on the silicon revision being used.
Figure 5-5
CorePac Revision ID Register (MM_REVID) Address - 0181 2000h
31
16
15
0
VERSION
REVISION
R-n
R-n
Legend: R = Read; -n = value after reset
Table 5-2
CorePac Revision ID Register (MM_REVID) Field Descriptions
PRODUCT PREVIEW
Bit
Field
Description
31-16
VERSION
Version of the C66x CorePac implemented on the device.
15-0
REVISION
Revision of the C66x CorePac version implemented on the device.
End of Table 5-2
5.6 C66x CorePac Register Descriptions
See the C66x CorePac Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 for register
offsets and definitions.
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6 Device Operating Conditions
6.1 Absolute Maximum Ratings
Table 6-1
Absolute Maximum Ratings (1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
Supply voltage range :
-0.3 V to 1.3 V
CVDD1
-0.3 V to 1.3 V
DVDD15
-0.3 V to 2.45 V
DVDD18
-0.3 V to 2.45 V
VREFSSTL
0.49 × DVDD15 to 0.51 × DVDD15
VDDT1, VDDT2
-0.3 V to 1.3 V
VDDR1, VDDR2, VDDR3, VDDR4
-0.3 V to 2.45 V
AVDDA1, AVDDA2
-0.3 V to 2.45 V
VSS Ground
0V
LVCMOS (1.8V)
Input voltage (VI) range:
-0.3 V to DVDD18+0.3 V
DDR3
-0.3 V to 2.45 V
I2C
-0.3 V to 2.45 V
LVDS
-0.3 V to DVDD18+0.3 V
LJCB
-0.3 V to 1.3 V
SerDes
-0.3 V to CVDD1+0.3 V
LVCMOS (1.8V)
Output voltage (VO) range:
-0.3 V to DVDD18+0.3 V
DDR3
-0.3 V to 2.45 V
2
IC
-0.3 V to 2.45 V
SerDes
-0.3 V to CVDD1+0.3 V
Commercial
Operating case temperature range, TC:
(3)
ESD stress voltage, VESD :
0°C to 85°C
Extended
HBM (human body model)
-40°C to 100°C
(4)
CDM (charged device model)
±1000 V
(5)
±250 V
LVCMOS (1.8V)
Overshoot/undershoot (6)
DDR3
2
20% Overshoot/Undershoot for 20% of
Signal Duty Cycle
IC
Storage temperature range, Tstg:
-65°C to 150°C
End of Table 6-1
1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
2 All voltage values are with respect to VSS.
3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
4 Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD
control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
5 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control
process. Pins listed as 250 V may actually have higher performance.
6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and
maximum undershoot value would be VSS - 0.20 × DVDD18
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(2)
CVDD
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6.2 Recommended Operating Conditions
Recommended Operating Conditions (1)
Table 6-2
850MHz - Device
(2)
Min
Nom
SRVnom (3) × 0.95
0.85-1.1
CVDD
SR Core Supply
CVDD1
Core supply voltage for memory array
0.95
DVDD18
1.8-V supply I/O voltage
1.71
Max Unit
SRVnom × 1.05
V
1
1.05
V
1.8
1.89
V
DVDD15
1.5-V supply I/O voltage
1.425
1.5
1.575
V
VREFSSTL
DDR3 reference voltage
0.49 × DVDD15
0.5 × DVDD15
0.51 × DVDD15
V
SerDes regulator supply
VDDRx
VDDAx
(4)
PRODUCT PREVIEW
1.425
1.5
1.575
V
PLL analog supply
1.71
1.8
1.89
V
0.95
1
1.05
V
0
0
0
V
VDDTx
SerDes termination supply
VSS
Ground
VIH
High-level input voltage
LVCMOS (1.8 V)
2
IC
DDR3 EMIF
0.65 × DVDD18
V
0.7 × DVDD18
V
VREFSSTL + 0.1
LVCMOS (1.8 V)
VIL
Low-level input voltage
DDR3 EMIF
-0.3
2
IC
Commercial
TC
Operating case temperature
Extended
V
0.35 × DVDD18
V
VREFSSTL - 0.1
V
0.3 × DVDD18
V
0
85
°C
-40
100
°C
End of Table 6-2
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE
802.3ae-2002.
2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
3 SRVnom refers to the unique SmartReflex core supply voltage between 0.85 V and 1.1 V set from the factory for each individual device.
4 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
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6.3 Electrical Characteristics
Table 6-3
Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Parameter
LVCMOS (1.8 V)
VOH
High-level output voltage
Test Conditions
(1)
IO = IOH
DDR3
Min
Typ
Max Unit
DVDD18 - 0.45
DVDD15 - 0.4
V
2 (2)
IC
VOL
Low-level output voltage
0.45
DDR3
2
II (3)
IO = IOL
0.4
IC
IO = 3 mA, pulled up to 1.8 V
No IPD/IPU
-5
LVCMOS (1.8 V)
Internal pullup
50
100
170
-170
-100
-50
I2 C
0.1 × DVDD18 V < VI < 0.9 ×
DVDD18 V
Input current [DC]
Internal pulldown
-10
LVCMOS (1.8 V)
IOH
V
0.4
5
10
μA
μA
-6
High-level output current [DC] DDR3
-8
mA
2 (4)
IC
IOL
Low-level output current [DC]
LVCMOS (1.8 V)
6
DDR3
8
2
IC
IOZ
(5)
Off-state output current [DC]
3
LVCMOS (1.8 V)
-2
2
DDR3
-2
2
-2
2
2
IC
mA
μA
End of Table 6-3
1
2
3
For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
2
I C uses open collector IOs and does not have a VOH Minimum.
II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and
off-state (Hi-Z) output leakage current.
2
4 I C uses open collector IOs and does not have a IOH Maximum.
5 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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LVCMOS (1.8 V)
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6.4 Power Supply to Peripheral I/O Mapping
Table 6-4
Power Supply to Peripheral I/O Mapping
(1) (2)
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Power Supply
I/O Buffer Type
Associated Peripheral
CORECLK(P|N) PLL input buffer
CVDD
Supply Core Voltage
LJCB
SRIOSGMIICLK(P|N) SerDes PLL input buffer
DDRCLK(P|N) PLL input buffer
PCIECLK(P|N) SERDES PLL input buffer
DVDD15
1.5-V supply I/O voltage
DDR3 (1.5 V)
All DDR3 memory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
PRODUCT PREVIEW
All Timer peripheral I/O buffer
All SPI peripheral I/O buffer
All RESETs, NMI, Control peripheral I/O buffer
DVDD18
1.8-V supply I/O voltage
LVCMOS (1.8 V)
All SmartReflex peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
All McBSP peripheral I/O buffer
All EMIF16 peripheral I/O buffer
All UPP peripheral I/O buffer
VDDT2
SGMII/PCIE SerDes termination and analogue front-end supply
Open-drain (1.8V)
All I2C peripheral I/O buffer
SerDes/CML
SGMII/PCIE SerDes CML IO buffer
End of Table 6-4
1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and
clock input buffers.
2 Please see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 64 for more information about individual
peripheral I/O.
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7 Peripheral Information and Electrical Specifications
This chapter covers the various peripherals on the TMS320C6654 DSP. Peripheral-specific information, timing
diagrams, electrical specifications, and register memory maps are described in this chapter.
7.1 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.Odd, indeed.ra44
7.2 Power Supplies
Table 7-1
Name
Power Supply Rails on TMS320C6654
Primary Function
Voltage
Notes
CVDD
SmartReflex core supply voltage
0.85 - 1.1 V Includes core voltage for DDR3 module
CVDD1
Core supply voltage for memory
array
1.0 V
Fixed supply at 1.0 V
VDDT1
Reserved
1.0 V
Connect to CVDD1
VDDT2
SGMII/PCIE SerDes termination
supply
1.0 V
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
SGMII/PCIE is not in use.
DVDD15
1.5-V DDR3 IO supply
1.5 V
VDDR1
Reserved
1.5 V
Connect to DVDD15
VDDR2
PCIE SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIE
is not in use.
VDDR3
SGMII SerDes regulator supply
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
SGMII is not in use.
VDDR4
Reserved
1.5 V
Connect to DVDD15
DVDD18
1.8-V IO supply
1.8V
AVDDA1
Main PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
AVDDA2
DDR3 PLL supply
1.8 V
Filtered version of DVDD18. Special considerations for noise.
VREFSSTL
0.75-V DDR3 reference voltage
0.75 V
Should track the 1.5-V supply. Use 1.5 V as source.
VSS
Ground
GND
End of Table 7-1
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The following sections describe the proper power-supply sequencing and timing needed to properly power on the
C6654. The various power supply rails and their primary function is listed in Table 7-1.
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7.2.1 Power-Supply Sequencing
This section defines the requirements for a power up sequencing from a power-on reset condition. There are two
acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO
voltages as shown below.
1. CVDD
2. CVDD1, VDDT1-2
3. DVDD18, AVDDA1, AVDDA2
4. DVDD15, VDDR1-4
PRODUCT PREVIEW
The second sequence provides compatibility with other TI processors with the IO voltage starting before the core
voltages as shown below.
1. DVDD18, AVDDA1, AVDDA2
2. CVDD
3. CVDD1, VDDT1-2
4. DVDD15, VDDR1-4
The clock input buffers for CORECLK, DDRCLK, SRIOSGMIICLK, and PCIECLK use only CVDD as a supply
voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid
voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD
is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either high and low or low
and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the clock inputs should
be removed from the high impedance state shortly after CVDD is present.
If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled to ground
through a 1K ohm resistor. The P leg should be tied to CVDD to ensure it won't have any voltage present until
CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be
driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could
cause damage to the device.
The device initialization is broken into two phases. The first phase consists of the time period from the activation of
the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the
sequencing scenarios described above can be implemented during this phase. The figures below show both the
core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire
power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL
will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must
always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to
the clock that is used by the CorePac, see Figure 7-7 for more details.
7.2.1.1 Core-Before-IO Power Sequencing
Figure 7-1 shows the power sequencing and reset control of TMS320C6654 for device initialization. POR may be
removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after
the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the
GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified.
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SYSCLK1 must always be active before POR can be removed. Core-before-IO power sequencing is defined in
Table 7-2.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp
Figure 7-1
Core Before IO Power Sequencing
Power Stabilization Phase
Device Initialization Phase
POR
PRODUCT PREVIEW
7
RESETFULL
8
GPIO Config
Bits
4b
9
10
RESET
2c
1
CVDD
6
2a
CVDD1
3
DVDD18
4a
DVDD15
5
SYSCLK1P&N
2b
DDRCLKP&N
RESETSTAT
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Table 7-2
www.ti.com
Core Before IO Power Sequencing
PRODUCT PREVIEW
Time
System State
1
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from
POR) is put into the reset state.
2a
• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is
permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will
ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core
constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
2b
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or be held in a static state with one leg high and one leg low.
2c
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t6.
3
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin
before DVDD18 is valid could cause damage to the device.
4a
• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the
voltage for DVDD15 must never exceed DVDD18.
4b
• RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven
high.
5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
6
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
7
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
8
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
9
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL
10
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL
End of Table 7-2
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7.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-2 and defined in Table 7-3.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp.
Figure 7-2
IO Before Core Power Sequencing
Power Stabilization Phase
Device Initialization Phase
POR
5
PRODUCT PREVIEW
7
RESETFULL
8
GPIO Config
Bits
2a
9
10
RESET
3c
2b
CVDD
6
3a
CVDD1
1
DVDD18
4
DVDD15
3b
SYSCLK1P&N
DDRCLKP&N
RESETSTAT
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Table 7-3
www.ti.com
IO Before Core Power Sequencing
PRODUCT PREVIEW
Time
System State
1
Begin Power Stabilization Phase
• Because POR is low, all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must
remain low through Power Stabilization Phase.
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before
DVDD18 could cause damage to the device.
2a
• RESET may be driven high anytime after DVDD18 is at a valid level.
2b
• CVDD (core AVS) ramps up.
3a
• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the
voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure
that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant)
ramps up before CVDD (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1.
3b
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or held in a static state with one leg high and one leg low.
3c
• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t6.
4
• DVDD15 (1.5 V) supply is ramped up following CVDD1.
5
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
6
Begin Device Initialization
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
• POR must remain low.
7
• RESETFULL is held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
8
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
9
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL
10
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL
End Device Initialization Phase
End of Table 7-3
7.2.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of
the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for
more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the
reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation
state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the
device.
7.2.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the
clocks is contingent on the state of the boot configuration pins. Table 7-4 describes the clock sequencing and the
conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until
CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the
other connected to CVDD.
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Table 7-4
Clock Sequencing
Clock
Condition
DDRCLK
None
Must be present 16 μsec before POR transitions high.
CORECLK
None
CORECLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.
SRIOSGMIICLK
PCIECLK
Sequencing
The SGMII port will be used.
SRIOSGMIICLK must be present 16 μsec before POR transitions high.
SGMII will not be used.
SRIOSGMIICLK is not used and should be tied to a static state.
PCIE will be used as a boot
device.
PCIECLK must be present 16 μsec before POR transitions high.
PCIE will be used after boot.
PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from
reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
7.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a
large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the
supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,
POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can also affect long term reliability.
7.2.3 Power Supply Decoupling and Bulk Capacitors
In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are
required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or
bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply
Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation
from Texas Instruments’’ on page 64.
7.2.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor structures
responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the
leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios.
This static power consumption is mainly determined by transistor type and process technology. Higher clock rates
also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a
specific usage scenario, clock rates, and I/O activity.
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the TMS320C6654 device is a feature that allows the core
voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each
TMS320C6654 device.
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required
to be implemented whenever the TMS320C6654 device is used. The voltage selection is done using 4 VCNTL pins
which are used to select the output voltage of the core voltage regulator.
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End of Table 7-4
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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For information on implementation of SmartReflex see the Power Management for KeyStone Devices application
report and the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’
on page 64.
Table 7-5
SmartReflex 4-Pin VID Interface Switching Characteristics
(see Figure 7-3)
No.
1
Parameter
td(VCNTL[2:0]-VCNTL[3])
Min
Delay Time - VCNTL[2:0] valid after VCNTL[3] low
2
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low
3
td(VCNTL[2:0]-VCNTL[3])
4
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high
Max
ns
(1)
ms
300.00
ns
172020C
ms
0.07 172020C
Delay Time - VCNTL[2:0] valid after VCNTL[3] high
0.07
Unit
300.00
End of Table 7-5
PRODUCT PREVIEW
1 C = 1/SYSCLK1 frequency (See Figure 7-9)in ms
Figure 7-3
SmartReflex 4-Pin VID Interface Timing
4
VCNTL[3]
1
3
VCNTL[2:0]
LSB VID[2:0]
MSB VID[5:3]
2
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7.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating
off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several
important power and clock operations.
For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
7.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power dissipation. The
global power/sleep controller (GPSC) is used to control the power gating of various power domains.
Table 7-6
PRODUCT PREVIEW
Table 7-6 shows the TMS320C6654 power domains.
Power Domains
Domain
Block(s)
Note
Power Connection
0
Most peripheral logic
Cannot be disabled
Always on
1
Per-core TETB and System TETB
RAMs can be powered down
Software control
2
Reserved
Reserved
Reserved
3
PCIe
Logic can be powered down
Software control
4
Reserved
Reserved
Reserved
5
Reserved
Reserved
Reserved
6
Reserved
Reserved
Reserved
7
Reserved
Reserved
Reserved
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
C66x Core 0, L1/L2 RAMs
L2 RAMs can sleep
Software control via C66x CorePac. For details, see
the C66x CorePac Reference Guide.
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
End of Table 7-6
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7.3.2 Clock Domains
Clock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating.
Table 7-7 shows the TMS320C6654 clock domains.
Table 7-7
Clock Domains
PRODUCT PREVIEW
LPSC Number
Module(s)
Notes
0
Shared LPSC for all peripherals other than those listed in this table
Always on
1
SmartReflex
Always on
2
DDR3 EMIF
Always on
3
EMAC
Software control
4
Reserved
Reserved
5
Debug Subsystem and Tracers
Software control
6
Per-core TETB and System TETB
Software control
7
Reserved
Reserved
8
Reserved
Reserved
9
Reserved
Reserved
10
PCIe
Software control
11
Reserved
Reserved
12
Reserved
Reserved
13
Reserved
Reserved
14
Reserved
Reserved
15
Reserved
Reserved
16
Reserved
Reserved
17
Reserved
Reserved
18
Reserved
Reserved
19
Reserved
Reserved
20
Reserved
Reserved
21
Reserved
Reserved
22
Reserved
Reserved
23
C66x CorePac 0 and Timer 0
Software control
24
Timer 1
Software control
No LPSC
Bootcfg, PSC, and PLL controller
These modules do not use LPSC
End of Table 7-7
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7.3.3 PSC Register Memory Map
Table 7-8 shows the PSC Register memory map.
PSC Register Memory Map (Part 1 of 3)
Offset
Register
Description
0x000
PID
Peripheral Identification Register
0x004 - 0x010
Reserved
Reserved
0x014
VCNTLID
Voltage Control Identification Register
0x018 - 0x11C
Reserved
Reserved
0x120
PTCMD
Power Domain Transition Command Register
0x124
Reserved
Reserved
0x128
PTSTAT
Power Domain Transition Status Register
0x12C - 0x1FC
Reserved
Reserved
0x200
PDSTAT0
Power Domain Status Register 0 (AlwaysOn)
0x204
PDSTAT1
Power Domain Status Register 1 (Per-core TETB and System TETB)
0x208
PDSTAT2
Power Domain Status Register 2 (Reserved)
0x20C
PDSTAT3
Power Domain Status Register 3 (PCIe)
0x210
PDSTAT4
Power Domain Status Register 4 (Reserved)
0x214
PDSTAT5
Power Domain Status Register 5(Reserved)
0x218
PDSTAT6
Power Domain Status Register 6 (Reserved)
0x21C
PDSTAT7
Power Domain Status Register 7(Reserved)
0x220
PDSTAT8
Power Domain Status Register 8 (Reserved)
0x224
PDSTAT9
Power Domain Status Register 9 (Reserved)
0x228
PDSTAT10
Power Domain Status Register 10 (Reserved)
0x22C
PDSTAT11
Power Domain Status Register 11(Reserved)
0x230
PDSTAT12
Power Domain Status Register 12 (Reserved)
0x234
PDSTAT13
Power Domain Status Register 13 (C66x CorePac 0)
0x238
PDSTAT14
Power Domain Status Register 14 (Reserved)
0x23C
Reserved
Reserved
0x240 - 0x2FC
Reserved
Reserved
0x300
PDCTL0
Power Domain Control Register 0 (AlwaysOn)
0x304
PDCTL1
Power Domain Control Register 1 (Per-core TETB and System TETB)
0x308
PDCTL2
Power Domain Control Register 2 (Reserved)
0x30C
PDCTL3
Power Domain Control Register 3 (PCIe)
0x310
PDCTL4
Power Domain Control Register 4 (Reserved)
0x314
PDCTL5
Power Domain Control Register 4 (Reserved)
0x318
PDCTL6
Power Domain Control Register 6 (Reserved)
0x31C
PDCTL7
Power Domain Control Register 7 (Reserved)
0x320
PDCTL8
Power Domain Control Register 8 (Reserved)
0x324
PDCTL9
Power Domain Control Register 9 (Reserved)
0x328
PDCTL10
Power Domain Control Register 10 (Reserved)
0x32C
PDCTL11
Power Domain Control Register 11(Reserved)
0x330
PDCTL12
Power Domain Control Register 12(Reserved)
0x334
PDCTL13
Power Domain Control Register 13 (C66x CorePac 0)
0x338
PDCTL14
Power Domain Control Register 14 (Reserved)
0x33C
Reserved
Reserved
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Table 7-8
117
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Table 7-8
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PSC Register Memory Map (Part 2 of 3)
Offset
Register
Description
0x340 - 0x7FC
Reserved
Reserved
PRODUCT PREVIEW
0x800
MDSTAT0
Module Status Register 0 (Never Gated)
0x804
MDSTAT1
Module Status Register 1 (SmartReflex)
0x808
MDSTAT2
Module Status Register 2 (DDR3 EMIF)
0x80C
MDSTAT3
Module Status Register 3 (EMAC)
0x810
MDSTAT4
Module Status Register 4 (Reserved)
0x814
MDSTAT5
Module Status Register 5 (Debug Subsystem and Tracers)
0x818
MDSTAT6
Module Status Register 6 (Per-core TETB and System TETB)
0x81C
MDSTAT7
Module Status Register 7 (Reserved)
0x820
MDSTAT8
Module Status Register 8 (Reserved)
0x824
MDSTAT9
Module Status Register 9 (Reserved)
0x828
MDSTAT10
Module Status Register 10 (PCIe)
0x82C
MDSTAT11
Module Status Register 11(Reserved)
0x830
MDSTAT12
Module Status Register 12(Reserved)
0x834
MDSTAT13
Module Status Register 13 (Reserved)
0x838
MDSTAT14
Module Status Register 14 (Reserved)
0x83C
MDSTAT15
Module Status Register 15 (Reserved)
0x840
MDSTAT16
Module Status Register 16 (Reserved)
0x844
MDSTAT17
Module Status Register 17 (Reserved)
0x848
MDSTAT18
Module Status Register 18 (Reserved)
0x84C
MDSTAT19
Module Status Register 19 (Reserved)
0x850
MDSTAT20
Module Status Register 20 (Reserved)
0x854
MDSTAT21
Module Status Register 11 (Reserved)
0x858
MDSTAT22
Module Status Register 22(Reserved)
0x85C
MDSTAT23
Module Status Register 23(C66x CorePac 0 and Timer 0)
0x860
MDSTAT24
Timer 1
0x864 - 0x9FC
Reserved
Reserved
0xA00
MDCTL0
Module Control Register 0 (Never Gated)
0xA04
MDCTL1
Module Control Register 1 (SmartReflex)
0xA08
MDCTL2
Module Control Register 2 (DDR3 EMIF)
0xA0C
MDCTL3
Module Control Register 3 (EMAC)
0xA10
MDCTL4
Module Control Register 4 (Reserved)
0xA14
MDCTL5
Module Control Register 5 (Debug Subsystem and Tracers)
0xA18
MDCTL6
Module Control Register 6 (Per-core TETB and System TETB)
0xA1C
MDCTL7
Module Control Register 7 (Reserved)
0xA20
MDCTL8
Module Control Register 8 (Reserved)
0xA24
MDCTL9
Module Control Register 9 (Reserved)
0xA28
MDCTL10
Module Control Register 10 (PCIe)
0xA2C
MDCTL11
Module Control Register 11(Reserved)
0xA30
MDCTL12
Module Control Register 12(Reserved)
0xA34
MDCTL13
Module Control Register 13 (Reserved)
0xA38
MDCTL14
Module Control Register 14 (Reserved)
0xA3C
MDCTL15
Module Control Register 15 (Reserved)
0xA40
MDCTL16
Module Control Register 16 (Reserved)
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PSC Register Memory Map (Part 3 of 3)
Offset
Register
Description
0xA44
MDCTL17
Module Control Register 17 (Reserved)
0xA48
MDCTL18
Module Control Register 18 (Reserved)
0xA4C
MDCTL19
Module Control Register 19 (Reserved)
0xA50
MDCTL20
Module Control Register 20 (Reserved)
0xA54
MDCTL21
Module Control Register 21(Reserved)
0xA58
MDCTL22
Module Control Register 22(Reserved)
0xA5C
MDCTL23
Module Control Register 23(C66x CorePac 0 and Timer 0)
0xA60
MDCTL24
Timer 1
0xA5C - 0xFFC
Reserved
Reserved
End of Table 7-8
7.4 Reset Controller
The reset controller detects the different type of resets supported on the TMS320C6654 device and manages the
distribution of those resets throughout the device.
The device has several types of resets:
• Power-on reset
• Hard reset
• Soft reset
• CPU local reset
Table 7-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data /
Timing’’ on page 123
Table 7-9
Reset Type
Reset Types
Initiator
POR (Power On Reset) POR pin active low
RESETFULL pin active low
Hard reset
RESET pin active low
Emulation
PLLCTL register (RSCTRL)
Watchdog timers
Soft reset
RESET pin active low
PLLCTL register (RSCTRL)
Watchdog timers
C66x CorePac
local reset
Software (through
LPSC MMR)
Watchdog timers
LRESET pin
Effect on Device When Reset Occurs
RESETSTAT Pin Status
Toggles RESETSTAT pin
Total reset of the chip. Everything on the device is reset to its default
state in response to this. Activates the POR signal on chip, which is used
to reset test/emu logic. Boot configurations are latched. ROM boot
process is initiated.
Resets everything except for test/emu logic and reset isolation
modules. Emulator and reset Isolation modules stay alive during this
reset. This reset is also different from POR in that the PLLCTL assumes
power and clocks are stable when device reset is asserted. Boot
configurations are not latched. ROM boot process is initiated.
Toggles RESETSTAT pin
Software can program these initiators to be hard or soft. Hard reset is
the default, but can be programmed to be soft reset. Soft reset will
behave like hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs,
sticky bits in PCIe MMRs, and external memory contents are retained.
Boot configurations are not latched. ROM boot process is initiated.
Toggles RESETSTAT pin
MMR bit in LPSC controls C66x CorePac local reset. Used by watchdog Does not toggle
RESETSTAT pin
timers (in the event of a timeout) to reset C66x CorePac. Can also be
initiated by LRESET device pin. C66x CorePac memory system and slave
DMA port are still alive when C66x CorePac is in local reset. Provides a
local reset of the C66x CorePac, without destroying clock alignment or
memory contents. Does not initiate ROM boot process.
End of Table 7-9
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Table 7-8
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following
1. POR pin
2. RESETFULL pin
PRODUCT PREVIEW
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device
including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR,
RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on
reset, the Main PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the
state of the PLL or the dividers in the PLL controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are
power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control
registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 66).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional time for the
Chip level PLLs to lock.
4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. The Chip level PLLs
is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, DDR3
PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL
controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system
reference clocks. After the pause, the system clocks are restarted at their default divide by settings.
6. The device is now out of reset and device execution begins as dictated by the selected boot mode.
Note—To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted
(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period
of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the
POR pin.
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7.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules.
POR should also remain de-asserted during this time.
Hard reset is initiated by the following
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog timer
• Emulation
The following sequence must be followed during a Hard reset:
1. The RESET pin is pulled active low for a minimum of 24 input clock cycles. During this time the RESET signal
is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules
affected by RESET, to prevent off-chip contention during the warm reset.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
together with the POR pin.
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PRODUCT PREVIEW
All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can
be configured as Soft resets in the RSCFG register in PLLCTL.
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SPRS841—March 2012
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7.4.3 Soft Reset
A soft reset will behave like a hard reset except that the PCIe MMR sticky bits and DDR3 EMIF MMRs contents are
retained. POR should also remain de-asserted during this time.
Soft reset is initiated by the following
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog timer
All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can
be configured as soft resets in the RSCFG register in PLLCTL.
PRODUCT PREVIEW
In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore,
the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers
are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in
self-refresh mode before invoking the soft reset.
During a soft reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate
through the system. Internal system clocks are not affected. PLLs also remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
controllers pause their system clocks for about 8 cycles.
At this point:
› The state of the peripherals before the soft reset is not changed.
› The I/O pins are controlled as dictated by the DEVSTAT register.
› The DDR3 MMRs and PCIe MMR sticky bits retain their previous values. Only the DDR3 Memory
Controller and PCIe state machines are reset by the soft reset.
› The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with
a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.
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7.4.4 Local Reset
Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) Controller for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64:
• LRESET pin
• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG
register in the PLL controller. See ‘‘Reset Configuration Register (RSTCFG)’’ on page 134 and ‘‘CIC Registers’’
on page 159:
– Local Reset
– NMI
– NMI followed by a time delay and then a local reset for the CorePac selected
– Hard Reset by requesting reset via PLLCTL
• LPSC MMRs (memory-mapped registers)
7.4.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.
The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/Soft reset
7.4.6 Reset Controller Register
The reset controller register are part of the PLLCTL MMRs. All C6654 device-specific MMRs are covered in Section
7.5.3 ‘‘Main PLL Control Register’’ on page 135. For more details on these registers and how to program them, see
the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 64.
7.4.7 Reset Electrical Data / Timing
Table 7-10
Reset Timing Requirements (1)
(see Figure 7-4 and Figure 7-5)
No.
Min
Max
Unit
RESETFULL Pin Reset
1
tw(RESETFULL)
Pulse width - Pulse width RESETFULL low
500C
ns
500C
ns
Soft/Hard-Reset
2
Pulse width - Pulse width RESET low
tw(RESET)
End of Table 7-10
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
Table 7-11
Reset Switching Characteristics Over Recommended Operating Conditions (1)
(see Figure 7-4 and Figure 7-5)
No.
Parameter
Min
Max
Unit
RESETFULL Pin Reset
3
td(RESETFULLH-RESETSTATH)
Delay time - RESETSTAT high after RESETFULL high
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The local reset can be used to reset a particular CorePac without resetting any other chip components.
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Reset Switching Characteristics Over Recommended Operating Conditions (1)
Table 7-11
(see Figure 7-4 and Figure 7-5)
No.
Parameter
Min
Max
Unit
Soft/Hard Reset
4
td(RESETH-RESETSTATH)
Delay time - RESETSTAT high after RESET high
50000C ns
End of Table 7-11
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
Figure 7-4
RESETFULL Reset Timing
POR
1
PRODUCT PREVIEW
RESETFULL
RESET
3
RESETSTAT
Figure 7-5
Soft/Hard-Reset Timing
POR
RESETFULL
2
RESET
4
RESETSTAT
Table 7-12
Boot Configuration Timing Requirements (1)
(See Figure 7-6)
No.
Min
Max
Unit
1
tsu(GPIOn-RESETFULL)
Setup time - GPIO valid before RESETFULL asserted
12C
ns
2
th(RESETFULL-GPIOn)
Hold time - GPIO valid after RESETFULL asserted
12C
ns
End of Table 7-12
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
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Figure 7-6
Boot Configuration Timing
POR
1
RESETFULL
GPIO[15:0]
PRODUCT PREVIEW
2
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7.5 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL
controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment,
and gating for the system clocks to the device. Figure 7-7 shows a block diagram of the main PLL and the PLL
controller.
Figure 7-7
Main PLL and PLL Controller
PLL
PLLD
xPLLM
/2
PRODUCT PREVIEW
CORECLK(N|P)
0
PLLOUT
OUTPUT
DIVIDE
1
BYPASS
PLL Controller
1
0
0
1
PLLEN
0
PLLENSRC
PLLDIV1
PLLDIV2
PLLDIV3
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
PLLDIV8
PLLDIV9
PLLDIV10
PLLDIV11
126
Peripheral Information and Electrical Specifications
/1
SYSCLK1
C66x
CorePac
/x
SYSCLK2
/2
SYSCLK3
/3
SYSCLK4
/y
SYSCLK5
/64
SYSCLK6
/6
SYSCLK7
To Switch Fabric,
Peripherals,
Accelerators
/z
SYSCLK8
/12
SYSCLK9
/3
SYSCLK10
/6
SYSCLK11
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Note—NOTE: PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL controller
and PLLM[12:6] bits are controlled by the chip level MAINPLLCTL0 register. The complete 13-bit value is
latched when the GO operation is initiated in the PLL controller. Only PLLDIV2, PLLDIV5, and PLLDIV8
are programmable on the C6654 device. See the Phase Locked Loop (PLL) Controller for KeyStone Devices
User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 for more details on how to
program the PLL controller.
Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 64 for detailed recommendations. For the best performance, TI
recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces
and the PLL external components (C1, C2, and the EMI Filter).
The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see
Section 7.5.5 ‘‘Main PLL Controller/PCIe Clock Input Electrical Data/Timing’’.
CAUTION—The PLL controller module as described in the see the Phase Locked Loop (PLL) Controller for
KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64 includes a
superset of features, some of which are not supported on the TMS320C6654 device. The following sections
describe the registers that are supported; it should be assumed that any registers not included in these
sections is not supported by the device. Furthermore, only the bits within the registers described here are
supported. Avoid writing to any reserved memory location or changing the value of reserved bits.
7.5.1 Main PLL Controller Device-Specific Information
7.5.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the
DDR3) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The Main
PLL’s PLL controller has several SYSCLK outputs that are listed below, along with the clock description. Each
SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not
programmable unless explicitly mentioned in the description below.
• SYSCLK1: Full-rate clock for the CorePac.
• SYSCLK2: 1/x-rate clock for CorePac emulation. Default rate for this will be 1/3. This is programmable from
/1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.
• SYSCLK3: 1/2-rate clock used to clock the MSMC and DDR EMIF.
• SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs will use this as
well.
• SYSCLK5: 1/y-rate clock for system trace module only. Default rate for this will be 1/5. It is configurable and
the max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turned
off by software.
• SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3
EMIF.
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The inputs, multiply and division factor within the PLL, post-division for each of the chip-level clocks is achieved
using the combination of this PLL and the PLL Controller. The PLL controller also controls reset propagation
through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an
output signal indicating when the PLL is locked.
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•
•
•
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SYSCLK7: 1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.
SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclk in the system. Default for this will be 1/64. This is
programmable from /24 to /80.
SYSCLK9: 1/12-rate clock for SmartReflex.
SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5 and SYSCLK8 are programmable on theTMS320C6654 device.
Note—In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8
(SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the
system.
PRODUCT PREVIEW
7.5.1.2 Main PLL Controller Operating Modes
The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by BYPASS bit of the PLL Secondary control register (SECCTL). In PLL mode, SYSCLK1 is generated
from the PLL output using the values set in PLLM and PLLD bit fields in the MAINPLLCTL0 register. In bypass
mode, PLL input is fed directly out as SYSCLK1.
All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must
be in place such that the DSP notifies the host when the PLL configuration has completed.
7.5.1.3 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become
stable after device powerup. The PLL should not be operated until this stabilization time has expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the
PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value,
see Table 7-13.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with
PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main PLL lock time
is given in Table 7-13.
Table 7-13
Main PLL Stabilization, Lock, and Reset Times
Min
PLL stabilization time
Max
100
PLL lock time
PLL reset time
Typ
μs
500 ×(PLLD
1000
Unit
(1)
+1) × C
(2)
ns
End of Table 7-13
1 PLLD is the value in PLLD bit fields of MAINPLLCTL0 register
2 C = SYSCLK1(N|P) cycle time in ns.
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7.5.2 PLL Controller Memory Map
The memory map of the PLL controller is shown in Table 7-14. TMS320C6654-specific PLL Controller register
definitions can be found in the sections following Table 7-14. For other registers in the table, see the Phase Locked
Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 64.
Table 7-14
PRODUCT PREVIEW
CAUTION—Note that only registers documented here are accessible on the TMS320C6654. Other addresses
in the PLL controller memory map including the reserved registers should not be modified. Furthermore,
only the bits within the registers described here are supported. Avoid writing to any reserved memory
location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to
make any changes to the valid bits in the register.
PLL Controller Registers (Including Reset Controller) (Part 1 of 2)
Hex Address Range
Field
Register Name
0231 0000 - 0231 00E3
-
Reserved
0231 00E4
RSTYPE
Reset Type Status Register (Reset Controller)
0231 00E8
RSTCTRL
Software Reset Control Register (Reset Controller)
0231 00EC
RSTCFG
Reset Configuration Register (Reset Controller)
0231 00F0
RSISO
Reset Isolation Register (Reset Controller)
0231 00F0 - 0231 00FF
-
Reserved
0231 0100
PLLCTL
PLL Control Register
0231 0104
-
Reserved
0231 0108
SECCTL
PLL Secondary Control Register
0231 010C
-
Reserved
0231 0110
PLLM
PLL Multiplier Control Register
0231 0114
-
Reserved
0231 0118
PLLDIV1
Reserved
0231 011C
PLLDIV2
PLL Controller Divider 2 Register
0231 0120
PLLDIV3
Reserved
0231 0124
-
Reserved
0231 0128
-
Reserved
0231 012C - 0231 0134
-
Reserved
0231 0138
PLLCMD
PLL Controller Command Register
0231 013C
PLLSTAT
PLL Controller Status Register
0231 0140
ALNCTL
PLL Controller Clock Align Control Register
0231 0144
DCHANGE
PLLDIV Ratio Change Status Register
0231 0148
CKEN
Reserved
0231 014C
CKSTAT
Reserved
0231 0150
SYSTAT
SYSCLK Status Register
0231 0154 - 0231 015C
-
Reserved
0231 0160
PLLDIV4
Reserved
0231 0164
PLLDIV5
PLL Controller Divider 5 Register
0231 0168
PLLDIV6
Reserved
0231 016C
PLLDIV7
Reserved
0231 0170
PLLDIV8
PLL Controller Divider 8 Register
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Table 7-14
www.ti.com
PLL Controller Registers (Including Reset Controller) (Part 2 of 2)
Hex Address Range
Field
Register Name
0231 0174 - 0231 0193
PLLDIV9 - PLLDIV16
Reserved
0231 0194 - 0231 01FF
-
Reserved
End of Table 7-14
7.5.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-8 and
described in Table 7-15.
Figure 7-8
PLL Secondary Control Register (SECCTL))
31
24
23
22
19
18
0
PRODUCT PREVIEW
Reserved
BYPASS
OUTPUT_DIVIDE
Reserved
R-0000 0000
RW-0
RW-0001
RW-001 0000 0000 0000 0000
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15
PLL Secondary Control Register (SECCTL) Field Descriptions
Bit
Field
Description
31-24
Reserved
Reserved
23
BYPASS
22-19
OUTPUT_DIVIDE
Output Divider ratio bits.
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h - Fh = Reserved.
18-0
Reserved
Reserved
Main PLL Bypass Enable
0 = Main PLL Bypass disabled
1 = Main PLL Bypass enabled
End of Table 7-15
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7.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
The PLL controller divider registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in Figure 7-9 and described in
Table 7-16. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different and
mentioned in the footnote of Figure 7-9.
Figure 7-9
PLL Controller Divider Register (PLLDIVn)
31
16
Reserved
15
Dn
R-0
(1)
14
8
EN
7
Reserved
R/W-1
0
RATIO
R-0
R/W-n
(2)
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16
PRODUCT PREVIEW
1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8
PLL Controller Divider Register (PLLDIVn) Field Descriptions
Bit
Field
Description
31-16
Reserved
Reserved.
15
DnEN
Divider Dn enable bit. (see footnote of Figure 7-9)
0 = Divider n is disabled.
1 = No clock output. Divider n is enabled.
14-8
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0
RATIO
Divider ratio bits. (see footnote of Figure 7-9)
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h = ÷3. Divide frequency by 3.
3h = ÷4. Divide frequency by 4.
4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.
End of Table 7-16
7.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-10 and described in Table 7-17.
Figure 7-10
PLL Controller Clock Align Control Register (ALNCTL)
31
8
7
6
5
4
3
2
1
0
Reserved
ALN8
Reserved
ALN5
Reserved
ALN2
Reserved
R-0
R/W-1
R-0
R/W-1
R-0
R/W-1
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-17
Bit
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Field
Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
ALN8
4
ALN5
1
ALN2
SYSCLKn alignment. Do not change the default values of these fields.
0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new
ratio immediately after the GOSET bit in PLLCMD is set.
1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.
The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
31-8
6-5
3-2
0
End of Table 7-17
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7.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
When a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE status
register. During the GO operation, the PLL controller will change only the divide ratio of the SYSCLKs with the bit
set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other clocks.
The PLLDIV divider ratio change status register is shown in Figure 7-11 and described in Table 7-18.
Figure 7-11
PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
8
7
6
5
4
3
2
1
0
Reserved
SYS8
Reserved
SYS5
Reserved
SYS2
Reserved
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
PRODUCT PREVIEW
Table 7-18
Bit
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Field
Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
SYS8
4
SYS5
1
SYS2
Identifies when the SYSCLKn divide ratio has been modified.
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
31-8
6-5
3-2
0
End of Table 7-18
7.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in Figure 7-12 and
described in Table 7-19.
SYSCLK Status Register (SYSTAT)
Figure 7-12
31
11
Reserved
10
9
SYS11ON SYS10ON
R-n
R-1
R-1
8
7
6
5
4
3
2
1
0
SYS9ON
SYS8ON
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-19
SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
Description
31-11
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
10-0
SYS[N (1)]ON
SYSCLK[N] on status.
0 = SYSCLK[N] is gated.
1 = SYSCLK[N] is on.
End of Table 7-19
1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)
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7.5.2.6 Reset Type Status Register (RSTYPE)
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in
Figure 7-13 and described in Table 7-20.
Figure 7-13
31
Reset Type Status Register (RSTYPE)
29
28
27
12
11
8
7
3
2
1
0
Reserved
EMU-RST
Reserved
WDRST[N]
Reserved
PLLCTRLRST
RESET
POR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Legend: R = Read only; -n = value after reset
Reset Type Status Register (RSTYPE) Field Descriptions
Bit
Field
Description
31-29
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
28
EMU-RST
Reset initiated by emulation.
0 = Not the last reset to occur.
1 = The last reset to occur.
27-12
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
11
WDRST3
10
WDRST2
9
WDRST1
Reset initiated by watchdog timer[N].
0 = Not the last reset to occur.
1 = The last reset to occur.
8
WDRST0
7-3
Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
2
PLLCTLRST
Reset initiated by PLLCTL.
0 = Not the last reset to occur.
1 = The last reset to occur.
1
RESET
RESET reset.
0 = RESET was not the last reset to occur.
1 = RESET was the last reset to occur.
0
POR
Power-on reset.
0 = Power-on reset was not the last reset to occur.
1 = Power-on reset was the last reset to occur.
PRODUCT PREVIEW
Table 7-20
End of Table 7-20
7.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value
is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register
(RSTCTRL) is shown in Figure 7-14 and described in Table 7-21.
Figure 7-14
Reset Control Register (RSTCTRL)
31
17
Reserved
R-0x0000
16
15
SWRST
R/W-0x
(1)
0
KEY
R/W-0x0003
Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
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Table 7-21
Bit
www.ti.com
Reset Control Register (RSTCTRL) Field Descriptions
Field
Description
31-17
Reserved
Reserved.
16
SWRST
Software reset
0 = Reset
1 = Not reset
15-0
KEY
Key used to enable writes to RSTCTRL and RSTCFG.
End of Table 7-21
7.5.2.8 Reset Configuration Register (RSTCFG)
PRODUCT PREVIEW
This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL controller’s
RSTCTRL Register; i.e., a Hard reset or a Soft reset. By default, these resets will be hard resets. The Reset
Configuration Register (RSTCFG) is shown in Figure 7-15 and described in Table 7-22.
Figure 7-15
Reset Configuration Register (RSTCFG)
31
14
Reserved
13
12
PLLCTLRSTTYPE
R-0
R/W-0
(2)
11
RESETTYPE
R/W-0
2
4
Reserved
R-0
3
0
WDTYPE[N
(1)
]
2
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)
2 Writes are conditional based on valid key. For details, see Section 7.5.2.7 ‘‘Reset Control Register (RSTCTRL)’’.
Table 7-22
Bit
Reset Configuration Register (RSTCFG) Field Descriptions
Field
Description
31-14
Reserved
Reserved.
13
PLLCTLRSTTYPE
PLL controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12
RESETTYPE
RESET initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
11-4
Reserved
Reserved.
3
WDTYPE3
2
WDTYPE2
1
WDTYPE1
Watchdog timer [N] initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
0
WDTYPE0
End of Table 7-22
7.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non
power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current
values of PLL multiplier, divide ratios and other settings. Along with setting module specific bit in RSISO, the
corresponding MDCTLx[12] bit also needs to be set in PSC to reset isolate a particular module. For more
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information on MDCTLx register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64. The Reset Isolation Register (RSTCTRL) is shown below.
Figure 7-16
Reset Isolation Register (RSISO)
31
10
9
8
7
0
Reserved
Reserved
SRISO
Reserved
R-0
R/W-0
R/W-0
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Bit
Reset Isolation Register (RSISO) Field Descriptions
Field
Description
31-10
Reserved
Reserved.
9
Reserved
Reserved.
8
SRISO
Isolate SmartReflex
0 = Not reset isolated
1 = Reset Isolated
7-0
Reserved
Reserved.
End of Table 7-23
7.5.3 Main PLL Control Register
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL controller
for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go
through an unlocking sequence using KICK0/KICK1 registers. For valid configurable values into the
MAINPLLCTL0 and MAINPLLCTL1 registers see Section 2.5.3 ‘‘PLL Boot Configuration Settings’’ on page 32. See
section 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 71 for the address location of the registers
and locking and unlocking sequences for accessing the registers. The registers are reset on POR only.
Figure 7-17
Main PLL Control Register 0 (MAINPLLCTL0)
31
24
23
19
18
12
11
6
5
0
BWADJ[7:0]
Reserved
PLLM[12:6]
Reserved
PLLD
RW-0000 0101
RW-0000 0
RW-0000000
RW-000000
RW-000000
Legend: RW = Read/Write; -n = value after reset
Table 7-24
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
Bit
Field
Description
31-24
BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
23-19
Reserved
Reserved
18-12
PLLM[12:6]
A 13-bit bus that selects the values for the multiplication factor (see Note below)
11-6
Reserved
Reserved
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-24
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Table 7-23
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 7-18
www.ti.com
Main PLL Control Register 1 (MAINPLLCTL1)
31
7
6
5
4
3
0
Reserved
ENSAT
Reserved
BWADJ[11:8]
RW-0000000000000000000000000
RW-0
RW-00
RW-0000
Legend: RW = Read/Write; -n = value after reset
Table 7-25
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
PRODUCT PREVIEW
Bit
Field
Description
31-7
Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper operation of PLL
5-4
Reserved
Reserved
3-0
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
End of Table 7-25
Note—PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL controller
and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The MAINPLLCTL0 register
PLLM[12:6] bits should be written just before writing to the PLLM register PLLM[5:0] bits in the controller
to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from
Texas Instruments’’ on page 64 for the recommended programming sequence. Output Divide ratio and
Bypass enable/disable of the Main PLL is controlled by the SECCTL register in the PLL Controller. See the
7.5.2.1 ‘‘PLL Secondary Control Register (SECCTL)’’ for more details.
7.5.4 Main PLL and PLL Controller Initialization Sequence
See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 64 for details on the initialization sequence for Main PLL and PLL Controller.
7.5.5 Main PLL Controller/PCIe Clock Input Electrical Data/Timing
Table 7-26
Main PLL Controller/PCIe Clock Input Timing Requirements (Part 1 of 2)
(see Figure 7-19 and Figure 7-20)
No.
Min
Max
3.2
25
Unit
CORECLK[P:N]
1
tc(CORCLKN)
1
tc(CORECLKP)
Cycle time _ CORECLKP cycle time
3.2
25
ns
3
tw(CORECLKN)
Pulse width _ CORECLKN high
0.45*tc(CORECLKN)
0.55*tc(CORECLKN)
ns
2
tw(CORECLKN)
Pulse width _ CORECLKN low
0.45*tc(CORECLKN)
0.55*tc(CORECLKN)
ns
2
tw(CORECLKP)
Pulse width _ CORECLKP high
0.45*tc(CORECLKP)
0.55*tc(CORECLKP)
ns
3
tw(CORECLKP)
Pulse width _ CORECLKP low
0.45*tc(CORECLKP)
0.55*tc(CORECLKP)
ns
4
tr(CORECLKN_250mv)
Transition time _ CORECLKN rise time (250 mV)
50
350
ps
136
Cycle time _ CORECLKN cycle time
Peripheral Information and Electrical Specifications
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Table 7-26
Main PLL Controller/PCIe Clock Input Timing Requirements (Part 2 of 2)
(see Figure 7-19 and Figure 7-20)
No.
Min
Max
Unit
4
tf(CORECLKN_250mv)
Transition time _ CORECLKN fall time (250 mV)
50
350
ps
4
tr(CORECLKP_250mv)
Transition time _ CORECLKP rise time (250 mV)
50
350
ps
50
4
tf(CORECLKP_250mv)
Transition time _ CORECLKP fall time (250 mV)
350
ps
5
tj(CORECLKN)
Jitter, peak_to_peak _ periodic CORECLKN
100
ps
5
tj(CORECLKP)
Jitter, peak_to_peak _ periodic CORECLKP
100
ps
1
tc(SRIOSMGMIICLKN)
Cycle time _ SRIOSMGMIICLKN cycle time
3.2
6.4
ns
1
tc(SRIOSMGMIICLKP)
Cycle time _ SRIOSMGMIICLKP cycle time
3.2
6.4
ns
3
tw(SRIOSMGMIICLKN)
Pulse width _ SRIOSMGMIICLKN high
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKN)
Pulse width _ SRIOSMGMIICLKN low
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
ns
2
tw(SRIOSMGMIICLKP)
Pulse width _ SRIOSMGMIICLKP high
0.45*tc(SRIOSGMIICLKP)
0.55*tc(SRIOSGMIICLKP)
ns
3
tw(SRIOSMGMIICLKP)
Pulse width _ SRIOSMGMIICLKP low
0.45*tc(SRIOSGMIICLKP)
0.55*tc(SRIOSGMIICLKP)
ns
4
tr(SRIOSMGMIICLKN_25 Transition time _ SRIOSMGMIICLKN rise time (250 mV)
0mv)
50
350
ps
4
tf(SRIOSMGMIICLKN_25 Transition time _ SRIOSMGMIICLKN fall time (250 mV)
0mv)
50
350
ps
4
tr(SRIOSMGMIICLKP_25 Transition time _ SRIOSMGMIICLKP rise time (250 mV)
0mv)
50
350
ps
4
tf(SRIOSMGMIICLKP_25 Transition time _ SRIOSMGMIICLKP fall time (250 mV)
0mv)
50
350
ps
5
tj(SRIOSMGMIICLKN)
Jitter, peak_to_peak _ periodic SRIOSMGMIICLKN
4 ps,RMS
5
tj(SRIOSMGMIICLKP)
Jitter, peak_to_peak _ periodic SRIOSMGMIICLKP
4 ps,RMS
5
tj(SRIOSMGMIICLKN)
Jitter, peak_to_peak _ periodic SRIOSMGMIICLKN (SRIO
not used)
8 ps,RMS
5
tj(SRIOSMGMIICLKP)
Jitter, peak_to_peak _ periodic SRIOSMGMIICLKP (SRIO
not used)
8 ps,RMS
PCIECLK[P:N]
1
tc(PCIECLKN)
Cycle time _ PCIECLKN cycle time
3.2
10
ns
1
tc(PCIECLKP)
Cycle time _ PCIECLKP cycle time
3.2
10
ns
3
tw(PCIECLKN)
Pulse width _ PCIECLKN high
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKN)
Pulse width _ PCIECLKN low
0.45*tc(PCIECLKN)
0.55*tc(PCIECLKN)
ns
2
tw(PCIECLKP)
Pulse width _ PCIECLKP high
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
3
tw(PCIECLKP)
Pulse width _ PCIECLKP low
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKP)
ns
4
tr(PCIECLKN_250mv)
Transition time _ PCIECLKN rise time (250 mV)
50
350
ps
4
tf(PCIECLKN_250mv)
Transition time _ PCIECLKN fall time (250 mV)
50
350
ps
4
tr(PCIECLKP_250mv)
Transition time _ PCIECLKP rise time (250 mV)
50
350
ps
4
tf(PCIECLKP_250mv)
Transition time _ PCIECLKP fall time (250 mV)
50
350
ps
5
tj(PCIECLKN)
Jitter, peak_to_peak _ periodic PCIECLKN
4 ps,RMS
5
tj(PCIECLKP)
Jitter, peak_to_peak _ periodic PCIECLKP
4 ps,RMS
End of Table 7-26
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SRIOSGMIICLK[P:N]
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 7-19
www.ti.com
Main PLL Controller/PCIe Clock Input Timing
1
2
3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
Figure 7-20
5
Main PLL Clock Input Transition Time
PRODUCT PREVIEW
peak-to-peak differential input
voltage (250 mV to 2 V)
0
250 mV peak-to-peak
TR = 50 ps min to 350 ps max (10% to 90 %)
for the 250 mV peak-to-peak centered at zero crossing
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7.6 DD3 PLL
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.
DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 64. For the best performance, TI recommends that all the PLL
external components be on a single side of the board without jumpers, switches, or components other than those
shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external
components (C1, C2, and the EMI Filter).
Figure 7-21
DDR3 PLL Block Diagram
DDR3 PLL
PLLD
xPLLM
/2
0
DDRCLK(N|P)
PLLOUT
DDR3
PHY
1
BYPASS
7.6.1 DDR3 PLL Control Register
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can
be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs
exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence using
KICK0/KICK1 registers. For suggested configurable values see section 3.3.4 ‘‘Kicker Mechanism (KICK0 and
KICK1) Register’’ on page 71 for the address location of the registers and locking and unlocking sequences for
accessing the registers. This register is reset on POR only
.
DDR3 PLL Control Register 0 (DDR3PLLCTL0) (1)
Figure 7-22
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
BYPASS
Reserved
PLLM
PLLD
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
RW,+000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
Table 7-27
DDR3 PLL Control Register 0 Field Descriptions (Part 1 of 2)
Bit
Field
Description
31-24
BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of
23
BYPASS
Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
22-19
Reserved
Reserved
PLLM[12:0] if PLLM has odd values. Example: PLLM=15, then BWADJ=7
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Figure 7-21 shows the DDR3 PLL.
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-27
www.ti.com
DDR3 PLL Control Register 0 Field Descriptions (Part 2 of 2)
Bit
Field
Description
18-6
PLLM
A 13-bit bus that selects the values for the multiplication factor
5-0
PLLD
A 6-bit bus that selects the values for the reference divider
End of Table 7-27
Figure 7-23
DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31
14
13
12
7
6
5
4
3
0
Reserved
PLLRST
Reserved
ENSAT
Reserved
BWADJ[11:8]
RW-000000000000000000
RW-0
RW-000000
RW-0
R-0
RW-0000
PRODUCT PREVIEW
Legend: RW = Read/Write; -n = value after reset
Table 7-28
Bit
DDR3 PLL Control Register 1 Field Descriptions
Field
Description
31-14
Reserved
Reserved
13
PLLRST
PLL reset bit.
0 = PLL reset is released.
1 = PLL reset is asserted.
12-7
Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper operation of PLL
5-4
Reserved
Reserved
3-0
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed
to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of PLLM[12:0] if PLLM has odd
values. Example: PLLM=15, then BWADJ=7
End of Table 7-28
7.6.2 DDR3 PLL Device-Specific Information
As shown in Figure 7-21, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory
controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3
PLL are affected as described in Section 7.4 ‘‘Reset Controller’’ on page 119. DDR3 PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
7.6.3 DDR3 PLL Initialization Sequence
The Main PLL and PLL Controller must always be initialized prior to the DDR3 PLL. The sequence shown below
must be followed to initialize the DDR3 PLL.
1. In DDR3PLLCTL1, write ENSAT = 1 (for optimal PLL operation)
2. In DDR3PLLCTL0, write BYPASS = 1 (set the PLL in Bypass)
3. In DDR3PLLCTL1, write PLLRST = 1 (PLL is reset)
4. Program PLLM and PLLD in DDR3PLLCTL0 register
5. Program BWADJ[7:0] in DDR3PLLCTL0 and BWADJ[11:8] in DDR3PLLCTL1 register. BWADJ value must
be set to ((PLLM + 1) >> 1) - 1)
6. Wait for at least 5 μs based on the reference clock (PLL reset time)
7. In DDR3PLLCTL1, write PLLRST = 0 (PLL reset is released)
8. Wait for at least 500 *REFCLK cycles * (PLLD + 1) (PLL lock time)
9. In DDR3PLLCTL0, write BYPASS = 0 (switch to PLL mode)
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7.6.4 DDR3 PLL Input Clock Electrical Data/Timing
Table 7-29
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
(see Figure 7-24 and Figure 7-20)
No.
Min
Max
3.2
25
Unit
DDRCLK[P:N]
tc(DDRCLKN)
Cycle time _ DDRCLKN cycle time
ns
1
tc(DDRCLKP)
Cycle time _ DDRCLKP cycle time
3.2
25
ns
3
tw(DDRCLKN)
Pulse width _ DDRCLKN high
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
ns
2
tw(DDRCLKN)
Pulse width _ DDRCLKN low
0.45*tc(DDRCLKN)
0.55*tc(DDRCLKN)
ns
2
tw(DDRCLKP)
Pulse width _ DDRCLKP high
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKP)
ns
3
tw(DDRCLKP)
Pulse width _ DDRCLKP low
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKP)
ns
4
tr(DDRCLKN_250mv) Transition time _ DDRCLKN rise time (250 mV)
50
350
ps
4
tf(DDRCLKN_250mv)
Transition time _ DDRCLKN fall time (250 mV)
50
350
ps
4
tr(DDRCLKP_250mv)
Transition time _ DDRCLKP rise time (250 mV)
50
350
ps
4
tf(DDRCLKP_250mv)
Transition time _ DDRCLKP fall time (250 mV)
50
350
ps
5
tj(DDRCLKN)
Jitter, peak_to_peak _ periodic DDRCLKN
0.025*tc(DDRCLKN)
ps
5
tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKP
0.025*tc(DDRCLKP)
ps
Peripheral Information and Electrical Specifications
141
End of Table 7-29
Figure 7-24
DDR3 PLL DDRCLK Timing
1
2
3
DDRCLKN
DDRCLKP
4
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1
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Fixed and Floating-Point Digital Signal Processor
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7.7 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There is one EDMA Channel Controller on the C6654 DSP, EDMA3_CC. It has four transfer controllers: TC0, TC1,
TC2, and TC3. In the context of this document, TCx associated with CC is referred to as EDMA3_CC_TCx. Each
of the transfer controllers has a direct connection to the switch fabric. Section 4.2 ‘‘Switch Fabric Connections
Matrix’’ lists the peripherals that can be accessed by the transfer controllers.
PRODUCT PREVIEW
The EDMA3 Channel Controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
› Array (multiple bytes)
› Frame (multiple arrays)
› Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 512 PaRAM entries
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 64 DMA channels
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• 4 transfer controllers and 4 event queues with programmable system-level priority
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
7.7.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode must be used.
On the C6654 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder
Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not
supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all
peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct
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Memory Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 64.
For the range of memory addresses that include EDMA3 channel controller (EDMA3_CC) control registers and
EDMA3 transfer controller (TC) control register see Section Table 2-2‘‘Memory Map Summary’’ on page 21. For
memory offsets and other details on EDMA3_CC and TC control registers entries, see the Enhanced Direct Memory
Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 64.
7.7.2 EDMA3 Channel Controller Configuration
Table 7-30 provides the configuration of the EDMA3 channel controller present on the device.
EDMA3 Channel Controller Configuration
Description
EDMA3 CC
Number of DMA channels in Channel Controller
64
Number of QDMA channels
8
Number of interrupt channels
64
Number of PaRAM set entries
512
Number of event queues
4
Number of Transfer Controllers
4
Memory Protection Existence
Yes
Number of Memory Protection and Shadow Regions
8
End of Table 7-30
7.7.3 EDMA3 Transfer Controller Configuration
Each transfer controller on a device is designed differently based on considerations like performance requirements,
system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the
transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the Data FIFO that is the temporary buffer for the in-flight data.
The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored
and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a
transfer controller.
• DSTREGDEPTH: This determines the number of Destination FIFO register set. The number of Destination
FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.
All four parameters listed above are specified by the design of the device.
Table 7-31 provides the configuration of the EDMA3 transfer controller present on the device.
Table 7-31
EDMA3 Transfer Controller Configuration (Part 1 of 2)
EDMA3 CC
Parameter
TC0
TC1
TC2
TC3
FIFOSIZE
BUSWIDTH
1024 bytes
512 bytes
512 bytes
1024 bytes
16 bytes
16 bytes
16 bytes
16 bytes
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Table 7-30
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-31
www.ti.com
EDMA3 Transfer Controller Configuration (Part 2 of 2)
EDMA3 CC
Parameter
TC0
TC1
TC2
TC3
DSTREGDEPTH
DBS
4 entries
4 entries
4 entries
4 entries
64 bytes
64 bytes
64 bytes
64 bytes
End of Table 7-31
7.7.4 EDMA3 Channel Synchronization Events
PRODUCT PREVIEW
The EDMA3 supports up to 64 DMA channels for EDMA3_CC that can be used to service system peripherals and
to move data between system memories. DMA channels can be triggered by synchronization events generated by
system peripherals. The following tables lists the source of the synchronization event associated with each of the
EDMA3_CC DMA channels. On the C6654, the association of each synchronization event and DMA channel is
fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed,
prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
Table 7-32
EDMA3_CC Events for C6654 (Part 1 of 2)
Event Number
Event
0
Reserved
1
Reserved
2
TINT2L
Timer2 interrupt low
3
TINT2H
Timer2 interrupt high
4
URXEVT
UART0 receive event
5
UTXEVT
UART0 transmit event
6
GPINT0
GPIO interrupt
7
GPINT1
GPIO interrupt
8
GPINT2
GPIO Interrupt
9
GPINT3
GPIO interrupt
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
URXEVT_B
UART1 receive event
15
UTXEVT_B
UART1 transmit event
16
SPIINT0
SPI interrupt
17
SPIINT1
SPI interrupt
18
SEMINT0
Semaphore interrupt
19
SEMINT1
Semaphore interrupt
20
SEMINT2
Semaphore interrupt
21
SEMINT3
Semaphore interrupt
22
TINT4L
Timer4 interrupt low
23
TINT4H
Timer4 interrupt high
24
TINT5L
Timer5 interrupt low
25
TINT5H
Timer5 interrupt high
26
TINT6L
Timer6 interrupt low
144
Event Description
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
EDMA3_CC Events for C6654 (Part 2 of 2)
Event Number
Event
Event Description
27
TINT6H
Timer6 interrupt high
28
TINT7L
Timer7 interrupt low
29
TINT7H
Timer7 interrupt high
30
SPIXEVT
SPI transmit event
31
SPIREVT
SPI receive event
32
I2CREVET
I2C receive event
33
I2CXEVT
I2C transmit event
34
TINT3L
Timer3 interrupt low
35
TINT3H
Timer3 interrupt high
36
MCBSP0_REVT
McBSP_0 receive event
37
MCBSP0_XEVT
McBSP_0 transmit event
38
MCBSP1_REVT
McBSP_1 receive event
39
MCBSP1_XEVT
McBSP_1 transmit event
40
TETBHFULLINT
TETB half full interrupt
41
TETBHFULLINT0
TETB half full interrupt
42
TETBHFULLINT1
TETB half full interrupt
43
CIC1_OUT0
Interrupt Controller output
44
CIC1_OUT1
Interrupt Controller output
45
CIC1_OUT2
Interrupt Controller output
46
CIC1_OUT3
Interrupt Controller output
47
CIC1_OUT4
Interrupt Controller output
48
CIC1_OUT5
Interrupt Controller output
49
CIC1_OUT6
Interrupt Controller output
50
CIC1_OUT7
Interrupt Controller output
51
CIC1_OUT8
Interrupt Controller output
52
CIC1_OUT9
Interrupt Controller output
53
CIC1_OUT10
Interrupt Controller output
54
CIC1_OUT11
Interrupt Controller output
55
CIC1_OUT12
Interrupt Controller output
56
CIC1_OUT13
Interrupt Controller output
57
CIC1_OUT14
Interrupt Controller output
58
CIC1_OUT15
Interrupt Controller output
59
CIC1_OUT16
Interrupt Controller output
60
CIC1_OUT17
Interrupt Controller output
61
TETBFULLINT
TETB full interrupt
62
TETBFULLINT0
TETB full interrupt
63
TETBFULLINT1
TETB full interrupt
PRODUCT PREVIEW
Table 7-32
End of Table 7-32
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Fixed and Floating-Point Digital Signal Processor
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7.8 Interrupts
7.8.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6654 device are configured through the C66x CorePac Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through CIC blocks, CIC[1:0]. This is clocked using CPU/6.
PRODUCT PREVIEW
The event controllers consist of simple combination logic to provide additional events to the C66x CorePacs, plus
the EDMA3_CC and CIC0 provide 12 additional events as well as 8 broadcast events to the C66x CorePacs, CIC1
provides 18 additional events to EDMA3_CC.
There are a large amount of events on the chip level. The chip level CIC provides a flexible way to combine and
remap those events. Multiple events can be combined to a single event through chip level CIC. However, an event
can only be mapped to a single event output from the chip level CIC. The chip level CIC also allows the software to
trigger system event through memory writes. The broadcast events to C66x CorePacs can be used for
synchronization among multiple cores, inter-processor communication purposes, etc. For more details on the CIC
features, please refer to the Chip Interrupt Controller (CIC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
Note—Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and EOI handshaking
interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.
Figure 7-25 shows the C6654 interrupt topology.
Figure 7-25
TMS320C6654 Interrupt Topology
16 Reserved Secondary Events
58 Reserved Secondary Events
102 Primary Events
92 Core-only Secondary Events
CIC0
12 Secondary Events
Core0
6 Reserved Primary Events
58 Common Events
8 Broadcast Events from CIC0
58 Common Events
56 Reserved Secondary Events
11 Reserved Secondary Events
CIC1
40 Primary Events
18 Secondary Events
46 EDMA3_CC-only
Secondary Events
146
Peripheral Information and Electrical Specifications
EDMA3
CC
6 Reserved Primary Events
Copyright 2012 Texas Instruments Incorporated
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 7-33 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
TMS320C6654 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
Event Number
Interrupt Event
Description
0
EVT0
Event combiner 0 output
1
EVT1
Event combiner 1 output
2
EVT2
Event combiner 2 output
3
EVT3
Event combiner 3 output
4
TETBHFULLINTn (1)
5
TETBFULLINTn
6
TETBACQINTn
TETB is half full
(1)
TETB is full
(1)
Acquisition has been completed
7
TETBOVFLINTn
(1)
8
TETBUNFLINTn
(1)
9
EMU_DTDMA
10
MSMC_mpf_errorn
11
EMU_RTDXRX
RTDX receive complete
12
EMU_RTDXTX
RTDX transmit complete
13
IDMA0
IDMA channel 0 interrupt
14
IDMA1
Overflow condition interrupt
Underflow condition interrupt
PRODUCT PREVIEW
Table 7-33
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
(2)
Memory protection fault indicators for local core
IDMA channel 1 interrupt
15
SEMERRn
16
SEMINTn
(3)
Semaphore error interrupt
(3)
Semaphore interrupt
17
PCIExpress_MSI_INTn
(4)
Message signaled interrupt mode
18
PCIExpress_MSI_INTn+4
Message signaled interrupt mode
19
MACINTn
20
Reserved
21
Reserved
22
CIC0_OUT(0+20*n)
Interrupt Controller Output
23
CIC0_OUT(1+20*n)
Interrupt Controller Output
24
CIC0_OUT(2+20*n)
Interrupt Controller Output
25
CIC0_OUT(3+20*n)
Interrupt Controller Output
26
CIC0_OUT(4+20*n)
Interrupt Controller Output
27
CIC0_OUT(5+20*n)
Interrupt Controller Output
28
CIC0_OUT(6+20*n)
Interrupt Controller Output
29
CIC0_OUT(7+20*n)
Interrupt Controller Output
30
CIC0_OUT(8+20*n)
Interrupt Controller Output
(5)
EMAC interrupt
31
CIC0_OUT(9+20*n)
Interrupt Controller Output
32
QM_INT_LOW_0
QM Interrupt for 0~31 Queues
33
QM_INT_LOW_1
QM Interrupt for 32~63 Queues
34
QM_INT_LOW_2
QM Interrupt for 64~95 Queues
35
QM_INT_LOW_3
QM Interrupt for 96~127 Queues
36
QM_INT_LOW_4
QM Interrupt for 128~159 Queues
37
QM_INT_LOW_5
QM Interrupt for 160~191 Queues
38
QM_INT_LOW_6
QM Interrupt for 192~223 Queues
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-33
www.ti.com
TMS320C6654 System Event Mapping — C66x CorePac Primary Interrupts (Part 2 of 4)
Event Number
Interrupt Event
Description
39
QM_INT_LOW_7
QM Interrupt for 224~255 Queues
40
QM_INT_LOW_8
QM Interrupt for 256~287 Queues
41
QM_INT_LOW_9
QM Interrupt for 288~319 Queues
42
QM_INT_LOW_10
QM Interrupt for 320~351 Queues
43
QM_INT_LOW_11
QM Interrupt for 352~383 Queues
44
QM_INT_LOW_12
QM Interrupt for 384~415 Queues
45
QM_INT_LOW_13
QM Interrupt for 416~447 Queues
46
QM_INT_LOW_14
QM Interrupt for 448~479 Queues
47
QM_INT_LOW_15
QM Interrupt for 480~511 Queues
PRODUCT PREVIEW
48
QM_INT_HIGH_n
(5)
(5)
49
QM_INT_HIGH_(n+4)
50
QM_INT_HIGH_(n+8) (5)
QM Interrupt for Queue 704+n
8
QM Interrupt for Queue 708+n
8
QM Interrupt for Queue 712+n8
51
QM_INT_HIGH_(n+12)
(5)
QM Interrupt for Queue 716+n
8
52
QM_INT_HIGH_(n+16)
(5)
QM Interrupt for Queue 720+n
53
QM_INT_HIGH_(n+20)
(5)
8
QM Interrupt for Queue 724+n8
54
QM_INT_HIGH_(n+24)
(5)
QM Interrupt for Queue 728+n
55
QM_INT_HIGH_(n+28)
(5)
QM Interrupt for Queue 732+n8
56
CIC0_OUT40
Interrupt Controller Output
57
CIC0_OUT41
Interrupt Controller Output
58
CIC0_OUT42
Interrupt Controller Output
59
CIC0_OUT43
Interrupt Controller Output
60
CIC0_OUT44
Interrupt Controller Output
61
CIC0_OUT45
Interrupt Controller Output
62
CIC0_OUT46
Interrupt Controller Output
63
CIC0_OUT47
Interrupt Controller Output
(6)
Local timer interrupt low
(6)
Local timer interrupt high
64
TINTLn
65
TINTHn
66
TINT2L
Timer2 interrupt low
67
TINT2H
Timer2 interrupt high
8
68
TINT3L
Timer3 interrupt low
69
TINT3H
Timer3 interrupt high
70
PCIExpress_MSI_INTn+2
Message signaled interrupt mode
71
PCIExpress_MSI_INTn+6
Message signaled interrupt mode
72
GPINT2
GPIO interrupt
73
GPINT3
GPIO interrupt
(5)
74
MACINTn+2
75
MACTXINTn+2
EMAC interrupt
(5)
EMAC interrupt
(5)
EMAC interrupt
(5)
EMAC interrupt
76
MACTRESHn+2
77
MACRXINTn+2
78
GPINT4
GPIO interrupt
79
GPINT5
GPIO interrupt
80
GPINT6
GPIO interrupt
81
GPINT7
GPIO interrupt
82
GPINT8
GPIO interrupt
148
Peripheral Information and Electrical Specifications
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
TMS320C6654 System Event Mapping — C66x CorePac Primary Interrupts (Part 3 of 4)
Event Number
Interrupt Event
Description
83
GPINT9
GPIO interrupt
84
GPINT10
GPIO interrupt
85
GPINT11
GPIO interrupt
86
GPINT12
GPIO interrupt
87
GPINT13
GPIO interrupt
88
GPINT14
GPIO interrupt
89
GPINT15
GPIO interrupt
90
IPC_LOCAL
Inter DSP interrupt from IPCGRn
91
GPINTn (7)
Local GPIO interrupt
92
CIC0_OUT(10+20*n)
Interrupt Controller Output
93
CIC0_OUT(11+20*n)
Interrupt Controller Output
(5)
EMAC interrupt
(5)
EMAC interrupt
94
MACTXINTn
95
MACTRESHn
96
INTERR
Dropped CPU interrupt event
97
EMC_IDMAERR
Invalid IDMA parameters
98
Reserved
99
MACRXINTn (5)
EMAC interrupt
100
EFIINTA
EFI Interrupt from side A
101
EFIINTB
EFI Interrupt from side B
QM_INT_HIGH_(n+2)
(8)
QM Interrupt for Queue 706+n8
103
QM_INT_HIGH_(n+6)
(5)
QM Interrupt for Queue 710+n
8
104
QM_INT_HIGH_(n+10)
(5)
QM Interrupt for Queue 714+n
8
105
QM_INT_HIGH_(n+14)
(5)
QM Interrupt for Queue 718+n8
106
QM_INT_HIGH_(n+18)
(5)
QM Interrupt for Queue 722+n
8
107
QM_INT_HIGH_(n+22)
(5)
QM Interrupt for Queue 726+n
8
108
QM_INT_HIGH_(n+26) (5)
109
QM_INT_HIGH_(n+30)
(5)
110
MDMAERREVT
111
Reserved
102
112
Reserved
113
PMC_ED
114
Reserved
115
EDMA3_CC_AETEVT
PRODUCT PREVIEW
Table 7-33
QM Interrupt for Queue 730+n8
QM Interrupt for Queue 734+n
8
VbusM error event
Single bit error detected during DMA read
EDMA3 CC AET Event
116
UMC_ED1
Corrected bit error detected
117
UMC_ED2
Uncorrected bit error detected
118
PDC_INT
Power down sleep interrupt
119
SYS_CMPA
SYS CPU memory protection fault event
120
PMC_CMPA
PMC CPU memory protection fault event
121
PMC_DMPA
PMC DMA memory protection fault event
122
DMC_CMPA
DMC CPU memory protection fault event
123
DMC_DMPA
DMC DMA memory protection fault event
124
UMC_CMPA
UMC CPU memory protection fault event
125
UMC_DMPA
UMC DMA memory protection fault event
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Peripheral Information and Electrical Specifications
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-33
www.ti.com
TMS320C6654 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)
Event Number
Interrupt Event
Description
126
EMC_CMPA
EMC CPU memory protection fault event
127
EMC_BUSERR
EMC bus error interrupt
End of Table 7-33
1
2
3
4
5
6
7
8
CorePac[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn
CorePac[n] will receive MSMC_mpf_errorn.
CorePac[n] will receive SEMINTn and SEMERRn.
CorePac[n] will receive PCIEXpress_MSI_INTn.
n is core number.
CorePac[n] will receive TINTLn and TINTHn.
CorePac[n] will receive GPINTn.
n is core number.
PRODUCT PREVIEW
Table 7-34
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 1 of 6)
Input Event# on CIC
System Interrupt
Description
0
GPINT16
GPIO interrupt
1
GPINT17
GPIO interrupt
2
GPINT18
GPIO interrupt
3
GPINT19
GPIO interrupt
4
GPINT20
GPIO interrupt
5
GPINT21
GPIO interrupt
6
GPINT22
GPIO interrupt
7
GPINT23
GPIO interrupt
8
GPINT24
GPIO interrupt
9
GPINT25
GPIO interrupt
10
GPINT26
GPIO interrupt
11
GPINT27
GPIO interrupt
12
GPINT28
GPIO interrupt
13
GPINT29
GPIO interrupt
14
GPINT30
GPIO interrupt
15
GPINT31
GPIO interrupt
16
EDMA3_CC_ERRINT
EDMA3_CC error interrupt
17
EDMA3_CC_MPINT
EDMA3_CC memory protection interrupt
18
EDMA3_TC_ERRINT0
EDMA3_CC TC0 error interrupt
19
EDMA3_TC_ERRINT1
EDMA3_CC TC1 error interrupt
20
EDMA3_TC_ERRINT2
EDMA3_CC TC2 error interrupt
21
EDMA3_TC_ERRINT3
EDMA3_CC TC3 error interrupt
22
EDMA3_CC_GINT
EDMA3_CC GINT
23
Reserved
24
EDMA3_CC_INT0
EDMA3_CC individual completion interrupt
25
EDMA3_CC_INT1
EDMA3_CC individual completion interrupt
26
EDMA3_CC_INT2
EDMA3_CC individual completion interrupt
27
EDMA3_CC_INT3
EDMA3_CC individual completion interrupt
28
EDMA3_CC_INT4
EDMA3_CC individual completion interrupt
29
EDMA3_CC_INT5
EDMA3_CC individual completion interrupt
30
EDMA3_CC_INT6
EDMA3_CC individual completion interrupt
31
EDMA3_CC_INT7
EDMA3_CC individual completion interrupt
150
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
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TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 6)
Input Event# on CIC
System Interrupt
Description
32
MCBSP0_RINT
McBSP0 interrupt
33
MCBSP0_XINT
McBSP0 interrupt
34
MCBSP0_REVT
McBSP0 interrupt
35
MCBSP0_XEVT
McBSP0 interrupt
36
MCBSP1_RINT
McBSP1 interrupt
37
MCBSP1_XINT
McBSP1 interrupt
38
MCBSP1_REVT
McBSP1 interrupt
39
MCBSP1_XEVT
McBSP1 interrupt
40
UARTINT_B
UART_1 interrupt
41
URXEVT_B
UART_1 interrupt
42
UTXEVT_B
UART_1 interrupt
43
Reserved
44
Reserved
45
Reserved
46
Reserved
47
Reserved
48
PCIEXpress_ERR_INT
Protocol error interrupt
49
PCIEXpress_PM_INT
Power management interrupt
50
PCIEXpress_Legacy_INTA
Legacy interrupt mode
51
PCIEXpress_Legacy_INTB
Legacy interrupt mode
52
PCIEXpress_Legacy_CIC
Legacy interrupt mode
53
PCIEXpress_Legacy_INTD
Legacy interrupt mode
54
SPIINT0
SPI interrupt0
55
SPIINT1
SPI interrupt1
56
SPIXEVT
Transmit event
57
SPIREVT
Receive event
58
I2CINT
I2C interrupt
59
I2CREVT
I C receive event
60
I2CXEVT
I C transmit event
61
Reserved
62
Reserved
63
TETBHFULLINT
TETB is half full
64
TETBFULLINT
TETB is full
2
2
65
TETBACQINT
Acquisition has been completed
66
TETBOVFLINT
Overflow condition occur
67
TETBUNFLINT
Underflow condition occur
68
SEMINT2
Semaphore interrupt
69
SEMINT3
Semaphore interrupt
70
SEMERR2
Semaphore interrupt
71
SEMERR3
Semaphore interrupt
72
Reserved
73
Tracer_core_0_INTD
74
Reserved
75
Reserved
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TI Confidential—NDA Restrictions
PRODUCT PREVIEW
Table 7-34
Tracer sliding time window interrupt for individual core
Peripheral Information and Electrical Specifications
151
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-34
www.ti.com
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 6)
PRODUCT PREVIEW
Input Event# on CIC
System Interrupt
76
Reserved
Description
77
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF1
78
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM bank0
79
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM bank1
80
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM bank2
81
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM bank3
81
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 TeraNet
82
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
84
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS slave
85
Tracer_SEM_INTD
Tracer sliding time window interrupt for semaphore
86
PSC_ALLINT
Power/sleep controller interrupt
87
Reserved
88
BOOTCFG_INTD
Chip-level MMR error register
89
po_vcon_smpserr_intr
SmartReflex VolCon error status
90
MPU0_INTD (MPU0_ADDR_ERR_INT and MPU0 addressing violation interrupt and protection violation interrupt.
MPU0_PROT_ERR_INT combined)
91
Reserved
92
MPU1_INTD (MPU1_ADDR_ERR_INT and MPU1 addressing violation interrupt and protection violation interrupt.
MPU1_PROT_ERR_INT combined)
93
Reserved
94
MPU2_INTD (MPU2_ADDR_ERR_INT and MPU2 addressing violation interrupt and protection violation interrupt.
MPU2_PROT_ERR_INT combined)
95
Reserved
96
MPU3_INTD (MPU3_ADDR_ERR_INT and MPU3 addressing violation interrupt and protection violation interrupt.
MPU3_PROT_ERR_INT combined)
97
Reserved
98
Reserved
99
Reserved
100
Reserved
101
Reserved
102
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
103
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
104
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
105
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
105
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
107
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
108
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
109
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
110
DDR3_ERR
DDR3 EMIF error interrupt
111
Reserved
112
Reserved
113
Reserved
114
Reserved
115
Reserved
116
Reserved
152
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 6)
Input Event# on CIC
System Interrupt
117
Reserved
118
Reserved
119
Reserved
120
Reserved
121
Reserved
122
Reserved
123
Reserved
124
Reserved
125
Reserved
126
Reserved
127
Reserved
128
Reserved
129
Reserved
130
po_vp_smpsack_intr
131
Reserved
132
Reserved
Description
Indicating that Volt_Proc receives the r-edge at its smpsack input
133
Reserved
134
QM_INT_PASS_TXQ_PEND_662
Queue manager pend event
135
QM_INT_PASS_TXQ_PEND_663
Queue manager pend event
136
QM_INT_PASS_TXQ_PEND_664
Queue manager pend event
137
QM_INT_PASS_TXQ_PEND_665
Queue manager pend event
138
QM_INT_PASS_TXQ_PEND_666
Queue manager pend event
139
QM_INT_PASS_TXQ_PEND_667
Queue manager pend event
140
QM_INT_PASS_TXQ_PEND_668
Queue manager pend event
141
QM_INT_PASS_TXQ_PEND_669
Queue manager pend event
142
QM_INT_PASS_TXQ_PEND_670
Queue manager pend event
143
Reserved
144
Reserved
145
TINT4L
Timer4 interrupt low
146
TINT4H
Timer4 interrupt high
147
Reserved
148
Reserved
149
Reserved
150
Reserved
151
TINT5L
Timer5 interrupt low
152
TINT5H
Timer5 interrupt high
153
TINT6L
Timer6 interrupt low
154
TINT6H
Timer6 interrupt high
155
Reserved
156
UPPINT
157
Reserved
158
Reserved
159
Reserved
160
MSMC_mpf_error2
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Table 7-34
UPP interrupt
Memory protection fault indicators for each system master PrivID
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Fixed and Floating-Point Digital Signal Processor
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Table 7-34
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CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 5 of 6)
Input Event# on CIC
System Interrupt
Description
161
MSMC_mpf_error3
Memory protection fault indicators for each system master PrivID
PRODUCT PREVIEW
162
TINT7L
Timer7 interrupt low
163
TINT7H
Timer7interrupt high
164
UARTINT_A
UART_0 interrupt
165
URXEVT_A
UART_0 interrupt
166
UTXEVT_A
UART_0 interrupt
167
EASYNCERR
EMIF16 error interrupt
168
Tracer_SCR_EMIF
Tracer sliding time window interrupt for EMIF16
169
Reserved
170
MSMC_mpf_error4
Memory protection fault indicators for each system master PrivID
171
MSMC_mpf_error5
Memory protection fault indicators for each system master PrivID
172
MSMC_mpf_error6
Memory protection fault indicators for each system master PrivID
173
MSMC_mpf_error7
Memory protection fault indicators for each system master PrivID
174
MPU4_INTD (MPU4_ADDR_ERR_INT and MPU4 addressing violation interrupt and protection violation interrupt.
MPU4_PROT_ERR_INT combined)
175
QM_INT_PASS_TXQ_PEND_671
Queue manager pend event
176
QM_INT_PKTDMA_0
QM interrupt for CDMA starvation
177
QM_INT_PKTDMA_1
QM interrupt for CDMA starvation
178
Reserved
179
Reserved
180
Reserved
181
SmartReflex_intrreq0
SmartReflex sensor interrupt
182
SmartReflex_intrreq1
SmartReflex sensor interrupt
183
SmartReflex_intrreq2
SmartReflex sensor interrupt
184
SmartReflex_intrreq3
SmartReflex sensor interrupt
185
VPNoSMPSAck
VPVOLTUPDATE has been asserted but SMPS has not been responded to in a
defined time interval
186
VPEqValue
SRSINTERUPT is asserted, but the new voltage is not different from the current
SMPS voltage
187
VPMaxVdd
The new voltage required is equal to or greater than MaxVdd.
188
VPMinVdd
The new voltage required is equal to or less than MinVdd.
189
VPINIDLE
Indicating that the FSM of voltage processor is in idle.
190
VPOPPChangeDone
Indicating that the average frequency error is within the desired limit.
191
Reserved
192
MACINT4
EMAC interrupt
193
MACRXINT4
EMAC interrupt
194
MACTXINT4
EMAC interrupt
195
MACTRESH4
EMAC interrupt
196
MACINT5
EMAC interrupt
197
MACRXINT5
EMAC interrupt
198
MACTXINT5
EMAC interrupt
199
MACTRESH5
EMAC interrupt
200
MACINT6
EMAC interrupt
201
MACRXINT6
EMAC interrupt
202
MACTXINT6
EMAC interrupt
154
Peripheral Information and Electrical Specifications
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Fixed and Floating-Point Digital Signal Processor
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Table 7-34
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 6 of 6)
Input Event# on CIC
System Interrupt
Description
203
MACTRESH6
EMAC interrupt
204
MACINT7
EMAC interrupt
205
MACRXINT7
EMAC interrupt
206
MACTXINT7
EMAC interrupt
207
MACTRESH7
EMAC interrupt
End of Table 7-34
CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 1 of 4)
Input Event # on CIC
System Interrupt
Description
0
GPINT8
GPIO interrupt
1
GPINT9
GPIO interrupt
2
GPINT10
GPIO interrupt
3
GPINT11
GPIO interrupt
4
GPINT12
GPIO interrupt
5
GPINT13
GPIO interrupt
6
GPINT14
GPIO interrupt
7
GPINT15
GPIO interrupt
8
Reserved
9
Reserved
10
TETBACQINT
11
Reserved
12
Reserved
13
TETBACQINT0
14
Reserved
15
Reserved
System TETB acquisition has been completed
TETB0 acquisition has been completed
16
Reserved
17
GPINT16
GPIO interrupt
18
GPINT17
GPIO interrupt
19
GPINT18
GPIO interrupt
20
GPINT19
GPIO interrupt
21
GPINT20
GPIO interrupt
22
GPINT21
GPIO interrupt
23
Reserved
24
QM_INT_HIGH_16
QM interrupt
25
QM_INT_HIGH_17
QM interrupt
26
QM_INT_HIGH_18
QM interrupt
27
QM_INT_HIGH_19
QM interrupt
28
QM_INT_HIGH_20
QM interrupt
29
QM_INT_HIGH_21
QM interrupt
30
QM_INT_HIGH_22
QM interrupt
31
QM_INT_HIGH_23
QM interrupt
32
QM_INT_HIGH_24
QM interrupt
33
QM_INT_HIGH_25
QM interrupt
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Table 7-35
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CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 2 of 4)
PRODUCT PREVIEW
Input Event # on CIC
System Interrupt
Description
34
QM_INT_HIGH_26
QM interrupt
35
QM_INT_HIGH_27
QM interrupt
36
QM_INT_HIGH_28
QM interrupt
37
QM_INT_HIGH_29
QM interrupt
38
QM_INT_HIGH_30
QM interrupt
39
QM_INT_HIGH_31
QM interrupt
40
Reserved
41
Reserved
42
Reserved
43
Reserved
44
Reserved
45
Tracer_core_0_INTD
46
Reserved
Tracer sliding time window interrupt for individual core
47
GPINT22
GPIO interrupt
48
GPINT23
GPIO interrupt
49
Tracer_DDR_INTD
Tracer sliding time window interrupt for DDR3 EMIF
50
Tracer_MSMC_0_INTD
Tracer sliding time window interrupt for MSMC SRAM bank0
51
Tracer_MSMC_1_INTD
Tracer sliding time window interrupt for MSMC SRAM bank1
52
Tracer_MSMC_2_INTD
Tracer sliding time window interrupt for MSMC SRAM bank2
53
Tracer_MSMC_3_INTD
Tracer sliding time window interrupt for MSMC SRAM bank3
54
Tracer_CFG_INTD
Tracer sliding time window interrupt for CFG0 TeraNet
55
Tracer_QM_SS_CFG_INTD
Tracer sliding time window interrupt for QM_SS CFG
56
Tracer_QM_SS_DMA_INTD
Tracer sliding time window interrupt for QM_SS slave port
57
Tracer_SEM_INTD
Tracer sliding time window interrupt for semaphore
58
SEMERR0
Semaphore interrupt
59
SEMERR1
Semaphore interrupt
60
SEMERR2
Semaphore interrupt
61
SEMERR3
Semaphore interrupt
62
BOOTCFG_INTD
BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT
63
UPPINT
UPP interrupt
64
MPU0_INTD (MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
MPU0 addressing violation interrupt and protection violation interrupt.
65
Reserved
66
MPU1_INTD (MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
67
Reserved
68
MPU2_INTD (MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
MPU2 addressing violation interrupt and protection violation interrupt.
69
QM_INT_PKTDMA_0
QM interrupt for packet DMA starvation
70
MPU3_INTD (MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
MPU3 addressing violation interrupt and protection violation interrupt.
71
QM_INT_PKTDMA_1
QM interrupt for packet DMA starvation
72
Reserved
73
Reserved
74
Reserved
156
Peripheral Information and Electrical Specifications
MPU1 addressing violation interrupt and protection violation interrupt.
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CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 3 of 4)
Input Event # on CIC
System Interrupt
75
Reserved
Description
76
MSMC_mpf_error0
Memory protection fault indicators for each system master PrivID
77
MSMC_mpf_error1
Memory protection fault indicators for each system master PrivID
78
MSMC_mpf_error2
Memory protection fault indicators for each system master PrivID
79
MSMC_mpf_error3
Memory protection fault indicators for each system master PrivID
80
MSMC_mpf_error4
Memory protection fault indicators for each system master PrivID
81
MSMC_mpf_error5
Memory protection fault indicators for each system master PrivID
82
MSMC_mpf_error6
Memory protection fault indicators for each system master PrivID
83
MSMC_mpf_error7
Memory protection fault indicators for each system master PrivID
84
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
85
MSMC_mpf_error9
Memory protection fault indicators for each system master PrivID
86
MSMC_mpf_error10
Memory protection fault indicators for each system master PrivID
87
MSMC_mpf_error11
Memory protection fault indicators for each system master PrivID
88
MSMC_mpf_error12
Memory protection fault indicators for each system master PrivID
89
MSMC_mpf_error13
Memory protection fault indicators for each system master PrivID
90
MSMC_mpf_error14
Memory protection fault indicators for each system master PrivID
91
MSMC_mpf_error15
Memory protection fault indicators for each system master PrivID
92
Reserved
93
Reserved
94
Reserved
95
Reserved
96
Reserved
97
Reserved
98
Reserved
99
Reserved
100
Reserved
101
Reserved
102
Reserved
103
Reserved
104
Reserved
105
Reserved
106
Reserved
107
Reserved
108
Reserved
109
Reserved
110
Reserved
111
Reserved
112
Reserved
113
Reserved
114
Reserved
115
Reserved
116
Reserved
117
GPINT24
GPIO interrupt
118
GPINT25
GPIO interrupt
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Fixed and Floating-Point Digital Signal Processor
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Table 7-35
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CIC1 Event Inputs (Secondary Events for EDMA3_CC) (Part 4 of 4)
Input Event # on CIC
System Interrupt
119
Reserved
Description
PRODUCT PREVIEW
120
Reserved
121
GPINT26
GPIO interrupt
122
GPINT27
GPIO interrupt
123
Reserved
124
GPINT28
GPIO interrupt
125
GPINT29
GPIO interrupt
126
GPINT30
GPIO interrupt
127
GPINT31
GPIO interrupt
128
GPINT4
GPIO interrupt
129
GPINT5
GPIO interrupt
130
GPINT6
GPIO interrupt
131
GPINT7
GPIO interrupt
132
Reserved
133
Tracer_SCR_EMIF
Tracer sliding time window interrupt for EMIF16
134
EASYNCERR
EMIF16 error interrupt
135
MPU4_INTD (MPU4_ADDR_ERR_INT and
MPU4_PROT_ERR_INT combined)
MPU4 addressing violation interrupt and protection violation interrupt.
136
Reserved
137
QM_INT_HIGH_0
QM interrupt
138
QM_INT_HIGH_1
QM interrupt
139
QM_INT_HIGH_2
QM interrupt
140
QM_INT_HIGH_3
QM interrupt
141
QM_INT_HIGH_4
QM interrupt
142
QM_INT_HIGH_5
QM interrupt
143
QM_INT_HIGH_6
QM interrupt
144
QM_INT_HIGH_7
QM interrupt
145
QM_INT_HIGH_8
QM interrupt
146
QM_INT_HIGH_9
QM interrupt
147
QM_INT_HIGH_10
QM interrupt
148
QM_INT_HIGH_11
QM interrupt
149
QM_INT_HIGH_12
QM interrupt
150
QM_INT_HIGH_13
QM interrupt
151
QM_INT_HIGH_14
QM interrupt
152
QM_INT_HIGH_15
QM interrupt
153
Reserved
154
Reserved
155
Reserved
156
Reserved
157
Reserved
158
Reserved
159
DDR3_ERR
DDR3 error interrupt
End of Table 7-35
158
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Fixed and Floating-Point Digital Signal Processor
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7.8.2 CIC Registers
This section includes the offsets for CIC registers. The base addresses for interrupt control registers are CIC0 0x0260 0000 and CIC1 - 0x0260 4000.
7.8.2.1 CIC0 Register Map
CIC0 Register (Part 1 of 3)
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x4
CONTROL_REG
Control Register
0xc
HOST_CONTROL_REG
Host Control Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x208
RAW_STATUS_REG2
Raw Status Register 2
0x20c
RAW_STATUS_REG3
Raw Status Register 3
0x210
RAW_STATUS_REG4
Raw Status Register 4
0x214
RAW_STATUS_REG5
Raw Status Register 5
0x218
RAW_STATUS_REG6
Raw Status Register 6
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x288
ENA_STATUS_REG2
Enabled Status Register 2
0x28c
ENA_STATUS_REG3
Enabled Status Register 3
0x290
ENA_STATUS_REG4
Enabled Status Register 4
0x294
ENA_STATUS_REG5
Enabled Status Register 5
0x298
ENA_STATUS_REG6
Enabled Status Register 6
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x308
ENABLE_REG2
Enable Register 2
0x30c
ENABLE_REG3
Enable Register 3
0x310
ENABLE_REG4
Enable Register 4
0x314
ENABLE_REG5
Enable Register 5
0x318
ENABLE_REG6
Enable Register 6
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x388
ENABLE_CLR_REG2
Enable Clear Register 2
0x38c
ENABLE_CLR_REG3
Enable Clear Register 3
0x390
ENABLE_CLR_REG4
Enable Clear Register 4
0x394
ENABLE_CLR_REG5
Enable Clear Register 5
0x398
ENABLE_CLR_REG6
Enable Clear Register 6
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
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Table 7-36
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Table 7-36
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CIC0 Register (Part 2 of 3)
PRODUCT PREVIEW
Address Offset
Register Mnemonic
Register Name
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x440
CH_MAP_REG16
Interrupt Channel Map Register for 64 to 64+3
0x444
CH_MAP_REG17
Interrupt Channel Map Register for 68 to 68+3
0x448
CH_MAP_REG18
Interrupt Channel Map Register for 72 to 72+3
0x44c
CH_MAP_REG19
Interrupt Channel Map Register for 76 to 76+3
0x450
CH_MAP_REG20
Interrupt Channel Map Register for 80 to 80+3
0x454
CH_MAP_REG21
Interrupt Channel Map Register for 84 to 84+3
0x458
CH_MAP_REG22
Interrupt Channel Map Register for 88 to 88+3
0x45c
CH_MAP_REG23
Interrupt Channel Map Register for 92 to 92+3
0x460
CH_MAP_REG24
Interrupt Channel Map Register for 96 to 96+3
0x464
CH_MAP_REG25
Interrupt Channel Map Register for 100 to 100+3
0x468
CH_MAP_REG26
Interrupt Channel Map Register for 104 to 104+3
0x46c
CH_MAP_REG27
Interrupt Channel Map Register for 108 to 108+3
0x470
CH_MAP_REG28
Interrupt Channel Map Register for 112 to 112+3
0x474
CH_MAP_REG29
Interrupt Channel Map Register for 116 to 116+3
0x478
CH_MAP_REG30
Interrupt Channel Map Register for 120 to 120+3
0x47c
CH_MAP_REG31
Interrupt Channel Map Register for 124 to 124+3
0x480
CH_MAP_REG32
Interrupt Channel Map Register for 128 to 128+3
0x484
CH_MAP_REG33
Interrupt Channel Map Register for 132 to 132+3
0x488
CH_MAP_REG34
Interrupt Channel Map Register for 136 to 136+3
0x48c
CH_MAP_REG35
Interrupt Channel Map Register for 140 to 140+3
0x490
CH_MAP_REG36
Interrupt Channel Map Register for 144 to 144+3
0x494
CH_MAP_REG37
Interrupt Channel Map Register for 148 to 148+3
0x498
CH_MAP_REG38
Interrupt Channel Map Register for 152 to 152+3
0x49c
CH_MAP_REG39
Interrupt Channel Map Register for 156 to 156+3
0x4a0
CH_MAP_REG40
Interrupt Channel Map Register for 160 to 160+3
0x4a4
CH_MAP_REG41
Interrupt Channel Map Register for 164 to 164+3
0x4a8
CH_MAP_REG42
Interrupt Channel Map Register for 168 to 168+3
0x4ac
CH_MAP_REG43
Interrupt Channel Map Register for 172 to 172+3
0x4b0
CH_MAP_REG44
Interrupt Channel Map Register for 176 to 176+3
160
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CIC0 Register (Part 3 of 3)
Address Offset
Register Mnemonic
Register Name
0x4b4
CH_MAP_REG45
Interrupt Channel Map Register for 180 to 180+3
0x4b8
CH_MAP_REG46
Interrupt Channel Map Register for 184 to 184+3
0x4bc
CH_MAP_REG47
Interrupt Channel Map Register for 188 to 188+3
0x4c0
CH_MAP_REG48
Interrupt Channel Map Register for 192 to 192+3
0x4c4
CH_MAP_REG49
Interrupt Channel Map Register for 196 to 196+3
0x4c8
CH_MAP_REG50
Interrupt Channel Map Register for 200 to 200+3
0x4cc
CH_MAP_REG51
Interrupt Channel Map Register for 204 to 204+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x82c
HINT_MAP_REG11
Host Interrupt Map Register for 44 to 44+3
0x830
HINT_MAP_REG12
Host Interrupt Map Register for 48 to 48+3
0x834
HINT_MAP_REG13
Host Interrupt Map Register for 52 to 52+3
0x838
HINT_MAP_REG14
Host Interrupt Map Register for 56 to 56+3
0x83c
HINT_MAP_REG15
Host Interrupt Map Register for 60 to 60+3
0x840
HINT_MAP_REG16
Host Interrupt Map Register for 64 to 64+3
0x844
HINT_MAP_REG17
Host Interrupt Map Register for 68 to 68+3
0x848
HINT_MAP_REG18
Host Interrupt Map Register for 72 to 72+3
0x84c
HINT_MAP_REG19
Host Interrupt Map Register for 76 to 76+3
0x850
HINT_MAP_REG20
Host Interrupt Map Register for 80 to 80+3
0x854
HINT_MAP_REG21
Host Interrupt Map Register for 84 to 84+3
0x858
HINT_MAP_REG22
Host Interrupt Map Register for 88 to 88+3
0x860
HINT_MAP_REG23
Host Interrupt Map Register for 92 to 92+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
0x1508
ENABLE_HINT_REG2
Host Int Enable Register 2
PRODUCT PREVIEW
Table 7-36
End of Table 7-36
7.8.2.2 CIC1 Register Map
Table 7-37
CIC1 Register (Part 1 of 3)
Address Offset
Register Mnemonic
Register Name
0x0
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
Global Host Int Enable Register
0x20
STATUS_SET_INDEX_REG
Status Set Index Register
0x24
STATUS_CLR_INDEX_REG
Status Clear Index Register
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Table 7-37
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CIC1 Register (Part 2 of 3)
PRODUCT PREVIEW
Address Offset
Register Mnemonic
Register Name
0x28
ENABLE_SET_INDEX_REG
Enable Set Index Register
0x2c
ENABLE_CLR_INDEX_REG
Enable Clear Index Register
0x34
HINT_ENABLE_SET_INDEX_REG
Host Int Enable Set Index Register
0x38
HINT_ENABLE_CLR_INDEX_REG
Host Int Enable Clear Index Register
0x200
RAW_STATUS_REG0
Raw Status Register 0
0x204
RAW_STATUS_REG1
Raw Status Register 1
0x208
RAW_STATUS_REG2
Raw Status Register 2
0x20c
RAW_STATUS_REG3
Raw Status Register 3
0x210
RAW_STATUS_REG4
Raw Status Register 4
0x280
ENA_STATUS_REG0
Enabled Status Register 0
0x284
ENA_STATUS_REG1
Enabled Status Register 1
0x288
ENA_STATUS_REG2
Enabled Status Register 2
0x28c
ENA_STATUS_REG3
Enabled Status Register 3
0x290
ENA_STATUS_REG4
Enabled Status Register 4
0x300
ENABLE_REG0
Enable Register 0
0x304
ENABLE_REG1
Enable Register 1
0x308
ENABLE_REG2
Enable Register 2
0x30c
ENABLE_REG3
Enable Register 3
0x310
ENABLE_REG4
Enable Register 4
0x380
ENABLE_CLR_REG0
Enable Clear Register 0
0x384
ENABLE_CLR_REG1
Enable Clear Register 1
0x388
ENABLE_CLR_REG2
Enable Clear Register 2
0x38c
ENABLE_CLR_REG3
Enable Clear Register 3
0x390
ENABLE_CLR_REG4
Enable Clear Register 4
0x400
CH_MAP_REG0
Interrupt Channel Map Register for 0 to 0+3
0x404
CH_MAP_REG1
Interrupt Channel Map Register for 4 to 4+3
0x408
CH_MAP_REG2
Interrupt Channel Map Register for 8 to 8+3
0x40c
CH_MAP_REG3
Interrupt Channel Map Register for 12 to 12+3
0x410
CH_MAP_REG4
Interrupt Channel Map Register for 16 to 16+3
0x414
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
0x418
CH_MAP_REG6
Interrupt Channel Map Register for 24 to 24+3
0x41c
CH_MAP_REG7
Interrupt Channel Map Register for 28 to 28+3
0x420
CH_MAP_REG8
Interrupt Channel Map Register for 32 to 32+3
0x424
CH_MAP_REG9
Interrupt Channel Map Register for 36 to 36+3
0x428
CH_MAP_REG10
Interrupt Channel Map Register for 40 to 40+3
0x42c
CH_MAP_REG11
Interrupt Channel Map Register for 44 to 44+3
0x430
CH_MAP_REG12
Interrupt Channel Map Register for 48 to 48+3
0x434
CH_MAP_REG13
Interrupt Channel Map Register for 52 to 52+3
0x438
CH_MAP_REG14
Interrupt Channel Map Register for 56 to 56+3
0x43c
CH_MAP_REG15
Interrupt Channel Map Register for 60 to 60+3
0x440
CH_MAP_REG16
Interrupt Channel Map Register for 64 to 64+3
0x444
CH_MAP_REG17
Interrupt Channel Map Register for 68 to 68+3
0x448
CH_MAP_REG18
Interrupt Channel Map Register for 72 to 72+3
0x44c
CH_MAP_REG19
Interrupt Channel Map Register for 76 to 76+3
162
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CIC1 Register (Part 3 of 3)
Address Offset
Register Mnemonic
Register Name
0x450
CH_MAP_REG20
Interrupt Channel Map Register for 80 to 80+3
0x454
CH_MAP_REG21
Interrupt Channel Map Register for 84 to 84+3
0x458
CH_MAP_REG22
Interrupt Channel Map Register for 88 to 88+3
0x45c
CH_MAP_REG23
Interrupt Channel Map Register for 92 to 92+3
0x460
CH_MAP_REG24
Interrupt Channel Map Register for 96 to 96+3
0x464
CH_MAP_REG25
Interrupt Channel Map Register for 100 to 100+3
0x468
CH_MAP_REG26
Interrupt Channel Map Register for 104 to 104+3
0x46c
CH_MAP_REG27
Interrupt Channel Map Register for 108 to 108+3
0x470
CH_MAP_REG28
Interrupt Channel Map Register for 112 to 112+3
0x474
CH_MAP_REG29
Interrupt Channel Map Register for 116 to 116+3
0x478
CH_MAP_REG30
Interrupt Channel Map Register for 120 to 120+3
0x47c
CH_MAP_REG31
Interrupt Channel Map Register for 124 to 124+3
0x480
CH_MAP_REG32
Interrupt Channel Map Register for 128 to 128+3
0x484
CH_MAP_REG33
Interrupt Channel Map Register for 132 to 132+3
0x488
CH_MAP_REG34
Interrupt Channel Map Register for 136 to 136+3
0x48c
CH_MAP_REG35
Interrupt Channel Map Register for 140 to 140+3
0x490
CH_MAP_REG36
Interrupt Channel Map Register for 144 to 144+3
0x494
CH_MAP_REG37
Interrupt Channel Map Register for 148 to 148+3
0x498
CH_MAP_REG38
Interrupt Channel Map Register for 152 to 152+3
0x49c
CH_MAP_REG39
Interrupt Channel Map Register for 156 to 156+3
0x800
HINT_MAP_REG0
Host Interrupt Map Register for 0 to 0+3
0x804
HINT_MAP_REG1
Host Interrupt Map Register for 4 to 4+3
0x808
HINT_MAP_REG2
Host Interrupt Map Register for 8 to 8+3
0x80c
HINT_MAP_REG3
Host Interrupt Map Register for 12 to 12+3
0x810
HINT_MAP_REG4
Host Interrupt Map Register for 16 to 16+3
0x814
HINT_MAP_REG5
Host Interrupt Map Register for 20 to 20+3
0x818
HINT_MAP_REG6
Host Interrupt Map Register for 24 to 24+3
0x81c
HINT_MAP_REG7
Host Interrupt Map Register for 28 to 28+3
0x820
HINT_MAP_REG8
Host Interrupt Map Register for 32 to 32+3
0x824
HINT_MAP_REG9
Host Interrupt Map Register for 36 to 36+3
0x828
HINT_MAP_REG10
Host Interrupt Map Register for 40 to 40+3
0x82c
HINT_MAP_REG11
Host Interrupt Map Register for 44 to 44+3
0x830
HINT_MAP_REG12
Host Interrupt Map Register for 48 to 48+3
0x834
HINT_MAP_REG13
Host Interrupt Map Register for 52 to 52+3
0x838
HINT_MAP_REG14
Host Interrupt Map Register for 56 to 56+3
0x83c
HINT_MAP_REG15
Host Interrupt Map Register for 60 to 60+3
0x1500
ENABLE_HINT_REG0
Host Int Enable Register 0
0x1504
ENABLE_HINT_REG1
Host Int Enable Register 1
PRODUCT PREVIEW
Table 7-37
End of Table 7-37
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7.8.3 Inter-Processor Register Map
Table 7-38
IPC Generation Registers (IPCGRx)
PRODUCT PREVIEW
Address Start
Address End
Size
Register Name
Description
0x02620200
0x02620203
4B
NMIGR0
NMI Event Generation Register for CorePac0
0x02620204
0x02620207
4B
Reserved
0x02620208
0x0262020B
4B
Reserved
Reserved
0x0262020C
0x0262020F
4B
Reserved
Reserved
0x02620210
0x02620213
4B
Reserved
Reserved
0x02620214
0x02620217
4B
Reserved
Reserved
0x02620218
0x0262021B
4B
Reserved
Reserved
0x0262021C
0x0262021F
4B
Reserved
Reserved
0x02620220
0x0262023F
32B
Reserved
Reserved
IPC Generation Register for CorePac 0
0x02620240
0x02620243
4B
IPCGR0
0x02620244
0x02620247
4B
Reserved
0x02620248
0x0262024B
4B
Reserved
Reserved
0x0262024C
0x0262024F
4B
Reserved
Reserved
0x02620250
0x02620253
4B
Reserved
Reserved
0x02620254
0x02620257
4B
Reserved
Reserved
0x02620258
0x0262025B
4B
Reserved
Reserved
0x0262025C
0x0262025F
4B
Reserved
Reserved
0x02620260
0x0262027B
28B
Reserved
Reserved
0x0262027C
0x0262027F
4B
IPCGRH
IPC Generation Register for Host
IPC Acknowledgement Register for CorePac 0
0x02620280
0x02620283
4B
IPCAR0
0x02620284
0x02620287
4B
Reserved
0x02620288
0x0262028B
4B
Reserved
Reserved
0x0262028C
0x0262028F
4B
Reserved
Reserved
0x02620290
0x02620293
4B
Reserved
Reserved
0x02620294
0x02620297
4B
Reserved
Reserved
0x02620298
0x0262029B
4B
Reserved
Reserved
0x0262029C
0x0262029F
4B
Reserved
Reserved
0x026202A0
0x026202BB
28B
Reserved
Reserved
0x026202BC
0x026202BF
4B
IPCARH
IPC Acknowledgement Register for Host
End of Table 7-38
7.8.4 NMI and LRESET
Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured
to select between the CorePacs available as shown in Table 7-39.
Table 7-39
LRESET and NMI Decoding (Part 1 of 2)
CORESEL[1:0] Pin Input LRESET Pin Input NMI Pin Input
XX
X
X
LRESETNMIEN Pin Input
1
Reset Mux Block Output
No local reset or NMI assertion.
00
0
X
0
Assert local reset to CorePac 0
01
0
X
0
Reserved
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Table 7-39
LRESET and NMI Decoding (Part 2 of 2)
CORESEL[1:0] Pin Input LRESET Pin Input NMI Pin Input
LRESETNMIEN Pin Input
Reset Mux Block Output
1x
0
X
0
Assert local reset to all CorePacs
00
1
1
0
De-assert local reset & NMI to CorePac 0
01
1
1
0
Reserved
1x
1
1
0
De-assert local reset & NMI to all CorePacs
00
1
0
0
Assert NMI to CorePac 0
01
1
0
0
Reserved
1x
1
0
0
Assert NMI to all CorePacs
7.8.5 External Interrupts Electrical Data/Timing
Table 7-40
NMI and Local Reset Timing Requirements (1)
(see Figure 7-26)
No.
Min
1
tsu(LRESET-LRESETNMIENL)
Setup Time - LRESET valid before LRESETNMIEN low
Max
Unit
12*P
ns
1
tsu(NMI-LRESETNMIENL)
Setup Time - NMI valid before LRESETNMIEN low
12*P
ns
1
tsu(CORESELn-LRESETNMIENL)
Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
12*P
ns
2
th(LRESETNMIENL-LRESET)
Hold Time - LRESET valid after LRESETNMIEN high
12*P
ns
2
th(LRESETNMIENL-NMI)
Hold Time - NMI valid after LRESETNMIEN high
12*P
ns
2
th(LRESETNMIENL-CORESELn)
Hold Time - CORESEL[2:0] valid after LRESETNMIEN high
12*P
ns
3
tw(LRESETNMIEN)
Pulse Width - LRESETNMIEN low width
12*P
ns
End of Table 7-40
1 P = 1/SYSCLK1 clock frequency in ns.
Figure 7-26
NMI and Local Reset Timing
1
2
CORESEL[3:0]/
LRESET/
NMI
3
LRESETNMIEN
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End of Table 7-39
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SPRS841—March 2012
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7.9 Memory Protection Unit (MPU)
The C6654 supports five MPUs:
• One MPU is used to protect main CORE/3 CFG TeraNet (CFG space of all slave devices on the TeraNet is
protected by the MPU).
• Two MPUs are used for QM_SS (one for DATA PORT port and another is for CFG PORT port).
• One MPU is used for Semaphore.
• One MPU is used for EMIF16
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and
details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
PRODUCT PREVIEW
The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 7-41
MPU Default Configuration
Setting
MPU0
Main CFG
TeraNet
MPU1
(QM_SS DATA PORT)
MPU2
(QM_SS CFG PORT)
MPU3
Semaphore
MPU4
EMIF16
Default permission
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Number of allowed IDs supported
16
16
16
16
16
Number of programmable ranges
supported
16
5
16
1
16
Compare width
1KB granularity
1KB granularity
1KB granularity
1KB granularity
1KB granularity
End of Table 7-41
Table 7-42
MPU Memory Regions
Memory Protection
Start Address
End Address
MPU0
Main CFG TeraNet
0x01D00000
0x026203FF
MPU1
QM_SS DATA PORT
0x34000000
0x340BFFFF
MPU2
QM_SS CFG PORT
0x02A00000
0x02ABFFFF
MPU3
Semaphore
0x02640000
0x026407FF
MPU4
EMIF16
0x70000000
0x7FFFFFFF
Table 7-43 shows the privilege ID of each CORE and every mastering peripheral. Table 7-43 also shows the privilege
level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read
or write) of each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 7-43
Privilege ID
Privilege ID Settings (Part 1 of 2)
Master
Privilege Level
Security Level
Access Type
0
CorePac0
SW dependant, driven by MSMC
SW dependant
DMA
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
UPP
User
Non-secure
DMA
7
EMAC
User
Non-secure
DMA
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Table 7-43
Privilege ID Settings (Part 2 of 2)
Privilege ID
Master
Privilege Level
Security Level
Access Type
8
QM_PKTDMA
User
Non-secure
DMA
User
Non-secure
DMA
9
Reserved
10
QM_second
11
PCIe
Supervisor
Non-secure
DMA
12
DAP
Driven by debug_SS
Driven by debug_SS
DMA
13
Reserved
14
Reserved
15
Reserved
Table 7-44 shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine
allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters,
master IDs are unique to each master.
Table 7-44
Master ID Settings (Part 1 of 3) (1)
Master ID
Master
0
CorePac0
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
CorePac0_CFG
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16
Reserved
17
Reserved
18
Reserved
19
Reserved
20
Reserved
21
Reserved
22
Reserved
23
Reserved
24
Reserved
25
Reserved
26
Reserved
27
Reserved
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End of Table 7-43
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-44
www.ti.com
Master ID Settings (Part 2 of 3) (1)
PRODUCT PREVIEW
Master ID
Master
28
EDMA_TC0 read
29
EDMA_TC0 write
30
EDMA_TC1 read
31
EDMA_TC1 write
32
EDMA_TC2 read
33
EDMA_TC2 write
34
EDMA_TC3 read
35
EDMA_TC3 write
36 - 37
Reserved
38 - 39
Reserved
40 - 47
Reserved
48
DAP
49
Reserved
50
EDMA3_CC
51
Reserved
52
MSMC (2)
53
PCIe
54
Reserved
55
Reserved
56
EMAC
57 - 87
Reserved
88 - 91
QM_PKTDMA
92 - 93
QM_second
94
Reserved
95
UPP
96 - 127
Reserved
128
Tracer_core_0 (3)
129
Reserved
130
Reserved
131
Reserved
132
Reserved
133
Reserved
134
Reserved
135
Reserved
136
Tracer_MSMC0
137
Tracer_MSMC1
138
Tracer_MSMC2
139
Tracer_MSMC3
140
Tracer_DDR
141
Tracer_SEM
142
Tracer_QM_CFG
143
Tracer_QM_Data
144
Tracer_CFG
145
Reserved
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Table 7-44
Master ID Settings (Part 3 of 3)
(1)
Master ID
Master
146
Reserved
147
Reserved
148
Tracer_EMIF16
End of Table 7-44
1 Some of the PKTDMA-based peripherals require multiple master IDs. QMS_PKTDMA is assigned with 88,89,90,91, but only 88-89 are actually used. There are two master ID
values are assigned for the QM_second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses.
2 The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.
3 All Tracers are set to the same master ID and bit 7 of the master ID needs to be 1.
7.9.1 MPU Registers
PRODUCT PREVIEW
This section includes the offsets for MPU registers and definitions for device specific MPU registers.
7.9.1.1 MPU Register Map
Table 7-45
MPU0 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
210h
PROG1_MPSAR
Programmable range 1, start address
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
250h
PROG5_MPSAR
Programmable range 5, start address
254h
PROG5_MPEAR
Programmable range 5, end address
258h
PROG5_MPPA
Programmable range 5, memory page protection attributes
260h
PROG6_MPSAR
Programmable range 6, start address
264h
PROG6_MPEAR
Programmable range 6, end address
268h
PROG6_MPPA
Programmable range 6, memory page protection attributes
270h
PROG7_MPSAR
Programmable range 7, start address
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Table 7-45
www.ti.com
MPU0 Registers (Part 2 of 2)
PRODUCT PREVIEW
Offset
Name
Description
274h
PROG7_MPEAR
Programmable range 7, end address
278h
PROG7_MPPA
Programmable range 7, memory page protection attributes
280h
PROG8_MPSAR
Programmable range 8, start address
284h
PROG8_MPEAR
Programmable range 8, end address
288h
PROG8_MPPA
Programmable range 8, memory page protection attributes
290h
PROG9_MPSAR
Programmable range 9, start address
294h
PROG9_MPEAR
Programmable range 9, end address
298h
PROG9_MPPA
Programmable range 9, memory page protection attributes
2A0h
PROG10_MPSAR
Programmable range 10, start address
2A4h
PROG10_MPEAR
Programmable range 10, end address
2A8h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2B0h
PROG11_MPSAR
Programmable range 11, start address
2B4h
PROG11_MPEAR
Programmable range 11, end address
2B8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2C0h
PROG12_MPSAR
Programmable range 12, start address
2C4h
PROG12_MPEAR
Programmable range 12, end address
2C8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2D0h
PROG13_MPSAR
Programmable range 13, start address
2D4h
PROG13_MPEAR
Programmable range 13, end address
2Dh
PROG13_MPPA
Programmable range 13, memory page protection attributes
2E0h
PROG14_MPSAR
Programmable range 14, start address
2E4h
PROG14_MPEAR
Programmable range 14, end address
2E8h
PROG14_MPPA
Programmable range 14, memory page protection attributes
2F0h
PROG15_MPSAR
Programmable range 15, start address
2F4h
PROG15_MPEAR
Programmable range 15, end address
2F8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-45
Table 7-46
MPU1 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
170
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MPU1 Registers (Part 2 of 2)
Offset
Name
Description
210h
PROG1_MPSAR
Programmable range 1, start address
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
PRODUCT PREVIEW
Table 7-46
End of Table 7-46
Table 7-47
MPU2 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
210h
PROG1_MPSAR
Programmable range 1, start address
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
250h
PROG5_MPSAR
Programmable range 5, start address
254h
PROG5_MPEAR
Programmable range 5, end address
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Table 7-47
www.ti.com
MPU2 Registers (Part 2 of 2)
Offset
Name
Description
258h
PROG5_MPPA
Programmable range 5, memory page protection attributes
260h
PROG6_MPSAR
Programmable range 6, start address
264h
PROG6_MPEAR
Programmable range 6, end address
268h
PROG6_MPPA
Programmable range 6, memory page protection attributes
270h
PROG7_MPSAR
Programmable range 7, start address
PRODUCT PREVIEW
274h
PROG7_MPEAR
Programmable range 7, end address
278h
PROG7_MPPA
Programmable range 7, memory page protection attributes
280h
PROG8_MPSAR
Programmable range 8, start address
284h
PROG8_MPEAR
Programmable range 8, end address
288h
PROG8_MPPA
Programmable range 8, memory page protection attributes
290h
PROG9_MPSAR
Programmable range 9, start address
294h
PROG9_MPEAR
Programmable range 9, end address
298h
PROG9_MPPA
Programmable range 9, memory page protection attributes
2A0h
PROG10_MPSAR
Programmable range 10, start address
2A4h
PROG10_MPEAR
Programmable range 10, end address
2A8h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2B0h
PROG11_MPSAR
Programmable range 11, start address
2B4h
PROG11_MPEAR
Programmable range 11, end address
2B8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2C0h
PROG12_MPSAR
Programmable range 12, start address
2C4h
PROG12_MPEAR
Programmable range 12, end address
2C8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2D0h
PROG13_MPSAR
Programmable range 13, start address
2D4h
PROG13_MPEAR
Programmable range 13, end address
2Dh
PROG13_MPPA
Programmable range 13, memory page protection attributes
2E0h
PROG14_MPSAR
Programmable range 14, start address
2E4h
PROG14_MPEAR
Programmable range 14, end address
2E8h
PROG14_MPPA
Programmable range 14, memory page protection attributes
2F0h
PROG15_MPSAR
Programmable range 15, start address
2F4h
PROG15_MPEAR
Programmable range 15, end address
2F8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-47
Table 7-48
Offset
MPU3 Registers (Part 1 of 2)
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
172
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Table 7-48
MPU3 Registers (Part 2 of 2)
Offset
Name
Description
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
Table 7-49
PRODUCT PREVIEW
End of Table 7-48
MPU4 Registers (Part 1 of 2)
Offset
Name
Description
0h
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
PROG0_MPSAR
Programmable range 0, start address
204h
PROG0_MPEAR
Programmable range 0, end address
208h
PROG0_MPPA
Programmable range 0, memory page protection attributes
210h
PROG1_MPSAR
Programmable range 1, start address
214h
PROG1_MPEAR
Programmable range 1, end address
218h
PROG1_MPPA
Programmable range 1, memory page protection attributes
220h
PROG2_MPSAR
Programmable range 2, start address
224h
PROG2_MPEAR
Programmable range 2, end address
228h
PROG2_MPPA
Programmable range 2, memory page protection attributes
230h
PROG3_MPSAR
Programmable range 3, start address
234h
PROG3_MPEAR
Programmable range 3, end address
238h
PROG3_MPPA
Programmable range 3, memory page protection attributes
240h
PROG4_MPSAR
Programmable range 4, start address
244h
PROG4_MPEAR
Programmable range 4, end address
248h
PROG4_MPPA
Programmable range 4, memory page protection attributes
250h
PROG5_MPSAR
Programmable range 5, start address
254h
PROG5_MPEAR
Programmable range 5, end address
258h
PROG5_MPPA
Programmable range 5, memory page protection attributes
260h
PROG6_MPSAR
Programmable range 6, start address
264h
PROG6_MPEAR
Programmable range 6, end address
268h
PROG6_MPPA
Programmable range 6, memory page protection attributes
270h
PROG7_MPSAR
Programmable range 7, start address
274h
PROG7_MPEAR
Programmable range 7, end address
278h
PROG7_MPPA
Programmable range 7, memory page protection attributes
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Table 7-49
www.ti.com
MPU4 Registers (Part 2 of 2)
Offset
Name
Description
280h
PROG8_MPSAR
Programmable range 8, start address
PRODUCT PREVIEW
284h
PROG8_MPEAR
Programmable range 8, end address
288h
PROG8_MPPA
Programmable range 8, memory page protection attributes
290h
PROG9_MPSAR
Programmable range 9, start address
294h
PROG9_MPEAR
Programmable range 9, end address
298h
PROG9_MPPA
Programmable range 9, memory page protection attributes
2A0h
PROG10_MPSAR
Programmable range 10, start address
2A4h
PROG10_MPEAR
Programmable range 10, end address
2A8h
PROG10_MPPA
Programmable range 10, memory page protection attributes
2B0h
PROG11_MPSAR
Programmable range 11, start address
2B4h
PROG11_MPEAR
Programmable range 11, end address
2B8h
PROG11_MPPA
Programmable range 11, memory page protection attributes
2C0h
PROG12_MPSAR
Programmable range 12, start address
2C4h
PROG12_MPEAR
Programmable range 12, end address
2C8h
PROG12_MPPA
Programmable range 12, memory page protection attributes
2D0h
PROG13_MPSAR
Programmable range 13, start address
2D4h
PROG13_MPEAR
Programmable range 13, end address
2Dh
PROG13_MPPA
Programmable range 13, memory page protection attributes
2E0h
PROG14_MPSAR
Programmable range 14, start address
2E4h
PROG14_MPEAR
Programmable range 14, end address
2E8h
PROG14_MPPA
Programmable range 14, memory page protection attributes
2F0h
PROG15_MPSAR
Programmable range 15, start address
2F4h
PROG15_MPEAR
Programmable range 15, end address
2F8h
PROG15_MPPA
Programmable range 15, memory page protection attributes
300h
FLTADDRR
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
End of Table 7-49
174
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Fixed and Floating-Point Digital Signal Processor
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7.9.1.2 Device-Specific MPU Registers
7.9.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Configuration Register (CONFIG)
31
Reset Values
24
23
20
19
16
15
12
11
1
0
ADDR_WIDTH
NUM_FIXED
NUM_PROG
NUM_AIDS
Reserved
ASSUME_ALLOWED
MPU0
R-0
R-0
R-16
R-16
R-0
R-1
MPU1
R-0
R-0
R-5
R-16
R-0
R-1
MPU2
R-0
R-0
R-16
R-16
R-0
R-1
MPU3
R-0
R-0
R-1
R-16
R-0
R-1
MPU4
R-0
R-0
R-16
R-16
R-0
R-1
Legend: R = Read only; -n = value after reset
Table 7-50
Configuration Register (CONFIG) Field Descriptions
Bit
Field
Description
31 – 24
ADDR_WIDTH
Address alignment for range checking
0 = 1KB alignment
6 = 64KB alignment
23 – 20
NUM_FIXED
Number of fixed address ranges
19 – 16
NUM_PROG
Number of programmable address ranges
15 – 12
NUM_AIDS
Number of supported AIDs
11 – 1
Reserved
Reserved. These bits will always reads as 0.
0
ASSUME_ALLOWED
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the
transfer is assumed to be allowed or not.
0 = Assume disallowed
1 = Assume allowed
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PRODUCT PREVIEW
Figure 7-27
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.9.2 MPU Programmable Range Registers
7.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The programmable address start register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also
writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines
the width of the address field in MPSAR and MPEAR.
Figure 7-28
Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
PRODUCT PREVIEW
START_ADDR
Reserved
R/W
R
Legend: R = Read only; R/W = Read/Write
Table 7-51
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
Bit
Field
Description
31 – 10
START_ADDR
Start address for range n.
9–0
Reserved
Reserved and these bits always read as 0.
End of Table 7-51
Table 7-52
Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
Register
MPU0
MPU1
MPU2
MPU3
MPU4
PROG0_MPSAR
0x01D0_0000
0x3400_0000
0x02A0_0000
0x0264_0000
0x7000_0000
PROG1_MPSAR
0x01F0_0000
0x3402_0000
0x02A2_0000
N/A
0x7100_0000
PROG2_MPSAR
0x0200_0000
0x3406_0000
0x02A4_0000
N/A
0x7200_0000
PROG3_MPSAR
0x01E0_0000
0x3406_8000
0x02A6_0000
N/A
0x7300_0000
PROG4_MPSAR
0x021C_0000
0x340B_8000
0x02A6_8000
N/A
0x7400_0000
PROG5_MPSAR
0x021F_0000
N/A
0x02A6_9000
N/A
0x7500_0000
PROG6_MPSAR
0x0220_0000
N/A
0x02A6_A000
N/A
0x7600_0000
PROG7_MPSAR
0x0231_0000
N/A
0x02A6_B000
N/A
0x7700_0000
PROG8_MPSAR
0x0232_0000
N/A
0x02A6_C000
N/A
0x7800_0000
PROG9_MPSAR
0x0233_0000
N/A
0x02A6_E000
N/A
0x7900_0000
PROG10_MPSAR
0x0235_0000
N/A
0x02A8_0000
N/A
0x7A00_0000
PROG11_MPSAR
0x0240_0000
N/A
0x02A9_0000
N/A
0x7B00_0000
PROG12_MPSAR
0x0250_0000
N/A
0x02AA_0000
N/A
0x7C00_0000
PROG13_MPSAR
0x0253_0000
N/A
0x02AA_8000
N/A
0x7D00_0000
PROG14_MPSAR
0x0260_0000
N/A
0x02AB_0000
N/A
0x7E00_0000
PROG15_MPSAR
0x0262_0000
N/A
0x02AB_8000
N/A
0x7F00_0000
End of Table 7-52
176
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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7.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also writeable only by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
Reserved
R/W
R
PRODUCT PREVIEW
Figure 7-29
Legend: R = Read only; R/W = Read/Write
Table 7-53
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
Bit
Field
Description
31 – 10
END_ADDR
End address for range n.
9–0
Reserved
Reserved and these bits always read as 3FFh.
End of Table 7-53
Table 7-54
Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
Register
MPU0
MPU1
MPU2
MPU3
MPU4
PROG0_MPEAR
0x01D8_007F
0x3401_FFFF
0x02A1_FFFF
0x0264_07FF
0x70FF_FFFF
PROG1_MPEAR
0x01F7_FFFF
0x3405_FFFF
0x02A3_FFFF
N/A
0x71FF_FFFF
PROG2_MPEAR
0x0209_FFFF
0x3406_7FFF
0x02A5_FFFF
N/A
0x72FF_FFFF
PROG3_MPEAR
0x01EB_FFFF
0x340B_7FFF
0x02A6_7FFF
N/A
0x73FF_FFFF
PROG4_MPEAR
0x021E_0C3F
0x340B_FFFF
0x02A6_8FFF
N/A
0x74FF_FFFF
PROG5_MPEAR
0x021F_7FFF
N/A
0x02A6_9FFF
N/A
0x75FF_FFFF
PROG6_MPEAR
0x0227_007F
N/A
0x02A6_AFFF
N/A
0x76FF_FFFF
PROG7_MPEAR
0x0231_03FF
N/A
0x02A6_BFFF
N/A
0x77FF_FFFF
PROG8_MPEAR
0x0232_03FF
N/A
0x02A6_DFFF
N/A
0x78FF_FFFF
PROG9_MPEAR
0x0233_03FF
N/A
0x02A6_FFFF
N/A
0x79FF_FFFF
PROG10_MPEAR
0x0235_0FFF
N/A
0x02A8_FFFF
N/A
0x7AFF_FFFF
PROG11_MPEAR
0x0245_3FFF
N/A
0x02A9_FFFF
N/A
0x7BFF_FFFF
PROG12_MPEAR
0x0252_03FF
N/A
0x02AA_7FFF
N/A
0x7CFF_FFFF
PROG13_MPEAR
0x0255_03FF
N/A
0x02AA_FFFF
N/A
0x7DFF_FFFF
PROG14_MPEAR
0x0260_BFFF
N/A
0x02AB_7FFF
N/A
0x7EFF_FFFF
PROG15_MPEAR
0x0262_07FF
N/A
0x02AB_FFFF
N/A
0x7FFF_FFFF
End of Table 7-54
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7.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
The programmable address memory protection page attribute register holds the permissions for the region. This
register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also only
writeable by a non-debug secure entity. The NS bit is writeable only by a non-debug secure entity. For debug accesses
the register is writeable only when NS = 1 or EMU = 1.
Figure 7-30
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
31
26
25
24
23
22
21
20
19
18
17
16
15
Reserved
AID15
AID14
AID13
AID12
AID11
AID10
AID9
AID8
AID7
AID6
AID5
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PRODUCT PREVIEW
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID4
AID3
AID2
AID1
AID0
AIDX
Reserved
NS
EMU
SR
SW
SX
UR
UW
UX
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Legend: R = Read only; R/W = Read/Write
Table 7-55
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 1 of 2)
Bit
Field
Description
31 – 26
Reserved
Reserved. These bits will always reads as 0.
25
AID15
Controls access from ID = 15
0 = Access denied.
1 = Access granted.
24
AID14
Controls access from ID = 14
0 = Access denied.
1 = Access granted.
23
AID13
Controls access from ID = 13
0 = Access denied.
1 = Access granted.
22
AID12
Controls access from ID = 12
0 = Access denied.
1 = Access granted.
21
AID11
Controls access from ID = 11
0 = Access denied.
1 = Access granted.
20
AID10
Controls access from ID = 10
0 = Access denied.
1 = Access granted.
19
AID9
Controls access from ID = 9
0 = Access denied.
1 = Access granted.
18
AID8
Controls access from ID = 8
0 = Access denied.
1 = Access granted.
17
AID7
Controls access from ID = 7
0 = Access denied.
1 = Access granted.
16
AID6
Controls access from ID = 6
0 = Access denied.
1 = Access granted.
178
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Table 7-55
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 2 of 2)
Field
Description
15
AID5
Controls access from ID = 5
0 = Access denied.
1 = Access granted.
14
AID4
Controls access from ID = 4
0 = Access denied.
1 = Access granted.
13
AID3
Controls access from ID = 3
0 = Access denied.
1 = Access granted.
12
AID2
Controls access from ID = 2
0 = Access denied.
1 = Access granted.
11
AID1
Controls access from ID = 1
0 = Access denied.
1 = Access granted.
10
AID0
Controls access from ID = 0
0 = Access denied.
1 = Access granted.
9
AIDX
Controls access from ID > 15
0 = Access denied.
1 = Access granted.
8
Reserved
Always reads as 0.
7
NS
Non-secure access permission
0 = Only secure access allowed.
1 = Non-secure access allowed.
6
EMU
Emulation (debug) access permission. This bit is ignored if NS = 1
0 = Debug access not allowed.
1 = Debug access allowed.
5
SR
Supervisor Read permission
0 = Access not allowed.
1 = Access allowed.
4
SW
Supervisor Write permission
0 = Access not allowed.
1 = Access allowed.
3
SX
Supervisor Execute permission
0 = Access not allowed.
1 = Access allowed.
2
UR
User Read permission
0 = Access not allowed.
1 = Access allowed
1
UW
User Write permission
0 = Access not allowed.
1 = Access allowed.
0
UX
User Execute permission
0 = Access not allowed.
1 = Access allowed.
PRODUCT PREVIEW
Bit
End of Table 7-551
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-56
www.ti.com
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values
Register
MPU0
MPU1
MPU2
MPU3
MPU3
PROG0_MPPA
0x03FF_FCB6
0x03FF_FC80
0x03FF_FCA4
0x0003_FCB6
0x03FF_FCB6
PROG1_MPPA
0x03FF_FC80
0x000F_FCB6
0x000F_FCB6
N/A
0x03FF_FCB6
PROG2_MPPA
0x03FF_FCB6
0x03FF_FCB4
0x000F_FCB6
N/A
0x03FF_FCB6
PROG3_MPPA
0x03FF_FCB6
0x03FF_FC80
0x03FF_FCB4
N/A
0x03FF_FCB6
PRODUCT PREVIEW
PROG4_MPPA
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG5_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG6_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG7_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG8_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG9_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG10_MPPA
0x03FF_FCB4
N/A
0x03FF_FCA4
N/A
0x03FF_FCB6
PROG11_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG12_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG13_MPPA
0x03FF_FCB6
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG14_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB4
N/A
0x03FF_FCB6
PROG15_MPPA
0x03FF_FCB4
N/A
0x03FF_FCB6
N/A
0x03FF_FCB6
End of Table 7-56
180
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7.10 DDR3 Memory Controller
The 32-bit DDR3 Memory Controller bus of the TMS320C6654 is used to interface to JEDEC standard-compliant
DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus
with any other types of peripherals.
7.10.1 DDR3 Memory Controller Device-Specific Information
The TMS320C6654 includes one 32-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate
at 800 Mega Transfers per Second (MTS) and 1033 MTS.
The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3
SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the
interface:
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)
• 32-bit: Two 16-bit SDRAMs
• 32-bit: Four 8-bit SDRAMs
• 16-bit: One 16-bit SDRAM
• 16-bit: Two 8-bit SDRAM
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as
I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O
buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible
DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if
master A passes a software message via a buffer in external memory and does not wait for an indication that the write
completes, before signaling to master B that the message is ready, when master B attempts to read the software
message, then the master B read may bypass the master A write and, thus, master B may read stale data and,
therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to
complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of
the read in step 3 ensures that the previous write was done.
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PRODUCT PREVIEW
Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit
or 32-bit interface.
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.10.2 DDR3 Memory Controller Electrical Data/Timing
The KeyStone DSP DDR3 Implementation Guidelines in ‘‘Related Documentation from Texas Instruments’’ on
page 64 specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3
electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the
simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no
electrical data/timing information is supplied here for this interface.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
7.11 I2C Peripheral
2
PRODUCT PREVIEW
The inter-integrated circuit (I C) module provides an interface between DSP and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by way of an I2C bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
2
through the I C module.
2
7.11.1 I C Device-Specific Information
2
The TMS320C6654 device includes an I C peripheral module.
2
Note—When using the I
C module, ensure there are external pullup resistors on the SDA and SCL pins.
2
The I C modules on the C6654 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may
be used to communicate with other controllers in a system or to implement a user interface.
2
2
The I C port is compatible with Philips I C specification revision 2.1 (January 2000) and supports:
• Fast mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2
Figure 7-31 shows a block diagram of the I C module.
Figure 7-31
I2C Module Block Diagram
2
I C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
2
I CPSC
Bit Clock
Generator
SCL
Noise
Filter
2
I C Clock
I COAR
Own
Address
I2CSAR
Slave
Address
I2CMDR
Mode
2
2
I CCLKH
PRODUCT PREVIEW
Control
I2CCLKL
2
I CCNT
Transmit
I2CXSR
2
I CDXR
Transmit
Shift
I2CEMDR
Extended
Mode
Transmit
Buffer
SDA
Interrupt/DMA
Noise
Filter
I2C Data
Data
Count
I2CDRR
2
I CRSR
2
Interrupt
Mask/Status
2
Interrupt
Status
I CIMR
Receive
Receive
Buffer
I CSTR
Receive
Shift
I CIVR
2
Interrupt
Vector
Shading denotes control/status registers.
2
7.11.2 I C Peripheral Register Description(s)
Table 7-57
I2C Registers (Part 1 of 2)
Hex Address Range
Register
Register Name
0253 0000
ICOAR
I2C Own Address Register
0253 0004
ICIMR
I C Interrupt Mask/Status Register
0253 0008
ICSTR
I C Interrupt Status Register
0253 000C
ICCLKL
I2C Clock Low-Time Divider Register
0253 0010
ICCLKH
I C Clock High-Time Divider Register
0253 0014
ICCNT
I C Data Count Register
0253 0018
ICDRR
I2C Data Receive Register
0253 001C
ICSAR
I C Slave Address Register
0253 0020
ICDXR
I C Data Transmit Register
0253 0024
ICMDR
I2C Mode Register
0253 0028
ICIVR
I C Interrupt Vector Register
0253 002C
ICEMDR
I C Extended Mode Register
0253 0030
ICPSC
I2C Prescaler Register
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2
2
2
2
2
2
2
Peripheral Information and Electrical Specifications
183
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-57
www.ti.com
I2C Registers (Part 2 of 2)
Hex Address Range
Register
Register Name
0253 0034
ICPID1
I2C Peripheral Identification Register 1 [Value: 0x0000 0105]
0253 0038
ICPID2
I C Peripheral Identification Register 2 [Value: 0x0000 0005]
0253 003C - 0253 007F
-
Reserved
2
End of Table 7-57
2
7.11.3 I C Electrical Data/Timing
2
7.11.3.1 Inter-Integrated Circuits (I C) Timing
Table 7-58
I2C Timing Requirements (1)
(see Figure 7-32)
PRODUCT PREVIEW
Standard Mode
No.
Min
1
2
3
Max
Fast Mode
Min
Max Units
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
μs
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μs
4
tw(SCLL)
Pulse duration, SCL low
5
tw(SCLH)
Pulse duration, SCL high
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
4.7
1.3
μs
4
0.6
μs
250
2
(3)
100
0 (3)
μs
(5)
300
ns
20 + 0.1Cb (5)
300
ns
20 + 0.1Cb
(5)
300
ns
20 + 0.1Cb
(5)
300
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (For I C bus devices)
0
8
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
10
tr(SCL)
Rise time, SCL
1000
11
tf(SDA)
Fall time, SDA
300
tf(SCL)
Fall time, SCL
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
14
tw(SP)
15
Cb
(5)
1.3
300
4
μs
0.6
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
ns
0.9 (4)
7
12
3.45
(2)
0
400
ns
μs
50
ns
400
pF
End of Table 7-58
2
1 The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down
2
2
2 A Fast-mode I C-bus™ device can be used in a Standard-mode I C-bus™ system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
4 The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
2
I C Receive Timings
Figure 7-32
11
9
SDA
8
6
4
14
13
5
10
SCL
1
3
12
7
Stop
Table 7-59
Start
Repeated
Start
2
I C Switching Characteristics
Stop
(1)
(see Figure 7-33)
Standard Mode
No.
Parameter
Min
Fast Mode
Max
Min
Max Unit
tc(SCL)
Cycle time, SCL
10
2.5
ms
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low (for a repeated START
condition)
4.7
0.6
ms
th(SDAL-SCLL)
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
4
0.6
ms
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
ms
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
ms
21
td(SDAV-SDLH)
Delay time, SDA valid to SCL high
250
100
ns
16
17
18
2
22
tv(SDLL-SDAV)
Valid time, SDA valid after SCL low (For I C bus devices)
23
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
0
0
4.7
1.3
0.9
ms
ms
24
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
(1)
300
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
(1)
300
ns
(1)
300
ns
300
ns
10
pF
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
27
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb (1)
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
29
Cp
Capacitance for each I C pin
4
2
0.6
10
ms
End of Table 7-59
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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PRODUCT PREVIEW
2
3
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 7-33
www.ti.com
2
I C Transmit Timings
26
24
SDA
23
21
19
28
20
25
SCL
16
18
27
22
17
18
PRODUCT PREVIEW
Stop
186
Start
Peripheral Information and Electrical Specifications
Repeated
Start
Stop
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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7.12 SPI Peripheral
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot. The SPI module on
C6654 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
7.12.1 SPI Electrical Data/Timing
7.12.1.1 SPI Timing
Table 7-60
SPI Timing Requirements
See Figure 7-34)
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 1
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 1
2
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 0
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 1
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 0
5
ns
8
th(SPC-SOMI)
Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 1
5
ns
End of Table 7-60
Table 7-61
SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-34 and Figure 7-35)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
(1)
ns
1
tc(SPC)
Cycle Time, SPIx_CLK, All Master Modes
3*P2
2
tw(SPCH)
Pulse Width High, SPIx_CLK, All Master Modes
0.5*tc - 1
3
tw(SPCL)
Pulse Width Low, SPIx_CLK, All Master Modes
0.5*tc - 1
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 0.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 1.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 0
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 1
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK. Polarity = 0 Phase = 0
2
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 0 Phase = 1
2
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 0
2
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 1
2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 1
0.5*tc - 2
ns
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ns
ns
Peripheral Information and Electrical Specifications
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PRODUCT PREVIEW
No.
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-61
www.ti.com
SPI Switching Characteristics (Part 2 of 2)
(See Figure 7-34 and Figure 7-35)
No.
Parameter
Min
Max
Unit
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 1
0.5*tc - 2
ns
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
PRODUCT PREVIEW
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 0
2*P2 - 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
2*P2 + 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 0
2*P2 - 5
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 0
1*P2 - 5
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 0
1*P2 - 5
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
tw(SCSH)
Minimum inactive time on SPIx_SCS\ pin between two transfers when
SPIx_SCS\ is not held using the CSHOLD feature.
2*P2 - 5
2*P2 + 5
1*P2 + 5
1*P2 + 5
ns
ns
ns
ns
ns
End of Table 7-61
1 P2 = 1/SYSCLK7
188
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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Figure 7-34
SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
2
MASTER MODE
POLARITY = 0 PHASE = 0
3
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
6
MO(1)
MO(n-1)
MO(n)
8
MI(0)
MI(1)
MI(n-1)
MI(n)
PRODUCT PREVIEW
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
6
5
SPIx_SIMO
MO(0)
7
SPIx_SOMI
MO(1)
MO(n-1)
MI(1)
MI(n-1)
MO(n)
8
MI(0)
4
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
5
SPIx_SIMO
6
MO(0)
7
SPIx_SOMI
MO(1)
MO(n-1)
MO(n)
8
MI(0)
MI(1)
MI(n-1)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
Figure 7-35
6
MO(1)
MO(n-1)
MI(1)
MI(n-1)
MO(n)
8
MI(0)
MI(n)
SPI Additional Timings for 4 Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MI(0)
MO(1)
MO(n-1)
MO(n)
MI(1)
MI(n-1)
MI(n)
SPIx_SCS
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Fixed and Floating-Point Digital Signal Processor
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7.13 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and
UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550
asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per
byte for the receiver FIFO.
PRODUCT PREVIEW
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes
control capability and a processor interrupt system that can be tailored to minimize software management of the
communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter
(UART) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
Table 7-62
UART Timing Requirements
(see Figure 7-36 and Figure 7-37)
No.
Min
Max
Unit
Receive Timing
Pulse width, receive start bit
0.96U
(1)
1.05U
ns
4
tw(RXSTART)
5
tw(RXH)
Pulse width, receive data/parity bit high
0.96U
1.05U
ns
5
tw(RXL)
Pulse width, receive data/parity bit low
0.96U
1.05U
ns
6
tw(RXSTOP1)
Pulse width, receive stop bit 1
0.96U
1.05U
ns
6
tw(RXSTOP15)
Pulse width, receive stop bit 1.5
0.96U
1.05U
ns
6
tw(RXSTOP2)
Pulse width, receive stop bit 2
0.96U
1.05U
ns
(2)
5P
ns
Autoflow Timing Requirements
8
td(CTSL-TX)
Delay time, CTS asserted to START bit transmit
P
End of Table 7-62
1 U = UART baud time = 1/programmed baud rate
2 P = 1/SYSCLK7
Figure 7-36
UART Receive Timing Waveform
5
4
RXD
Stop/Idle
Figure 7-37
Start
5
Bit 0
Bit 1
Bit N-1
Bit N
6
Parity
Stop
Idle
Start
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
8
TXD
Bit N-1
Bit N
Stop
Start
Bit 0
CTS
190
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
Table 7-63
UART Switching Characteristics
(See Figure 7-38 and Figure 7-39)
No.
Parameter
Min
Max
Unit
Transmit Timing
(1)
1
tw(TXSTART)
Pulse width, transmit start bit
-2
U+2
ns
2
tw(TXH)
Pulse width, transmit data/parity bit high
U-2
U+2
ns
2
tw(TXL)
Pulse width, transmit data/parity bit low
U-2
U+2
ns
3
tw(TXSTOP1)
Pulse width, transmit stop bit 1
U-2
U+2
ns
3
tw(TXSTOP15)
Pulse width, transmit stop bit 1.5
1.5 * (U - 2) 1.5 * ('U + 2)
ns
3
tw(TXSTOP2)
Pulse width, transmit stop bit 2
U
2 * (U - 2)
2 * ('U + 2)
ns
P (2)
5P
ns
7
Delay time, STOP bit received to RTS deasserted
td(RX-RTSH)
End of Table 7-63
1 U = UART baud time = 1/programmed baud rate
2 P = 1/SYSCLK7
Figure 7-38
UART Transmit Timing Waveform
1
TXD
Figure 7-39
Start
Stop/Idle
2
Bit 0
2
Bit 1
Bit N-1
Bit N
Parity
3
Stop
Idle
Start
UART RTS (Request-to-Send Output) — Autoflow Timing Waveform
7
RXD
Bit N-1
Bit N
Stop
Start
CTS
7.14 PCIe Peripheral
The two-lane PCI express (PCIe) module on the device provides an interface between the DSP and other
PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed data
transfer at rates of 5.0 GBaud per lane on the serial links. For more information, see the Peripheral Component
Interconnect Express (PCIe) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 64. The PCIe electrical requirements are fully specified in the PCI Express Base Specification Revision 2.0
of PCI-SIG. TI has performed the simulation and system characterization to ensure all PCIe interface timings in this
solution are met; therefore, no electrical data/timing information is supplied here for this interface.
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Autoflow Timing Requirements
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7.15 EMIF16 Peripheral
The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For
more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
7.15.1 EMIF16 Electrical Data/Timing
Table 7-64
EMIF16 Asynchronous Memory Timing Requirements (1) (Part 1 of 2)
(see Figure 7-40 and Figure 7-41)
No.
Min
Max
Unit
General Timing
PRODUCT PREVIEW
2
tw(WAIT)
Pulse duration, WAIT assertion and deassertion minimum time
2E
ns
28
td(WAIT-WEH)
Setup time, WAIT asserted before WE high
4E + 3
ns
14
td(WAIT-OEH)
Setup time, WAIT asserted before OE high
4E + 3
ns
Read Timing
3
3
4
tC(CSL)
tC(CSL)
EMIF read cycle time when ew = 0, meaning not in extended wait mode
(RS+RST+RH+3)
*E-3
(RS+RST+RH+3)
*E+3
ns
EMIF read cycle time when ew =1, meaning extended wait mode enabled
(RS+RST+RH+3)
*E-3
(RS+RST+RH+3)
*E+3
ns
ns
tosu(CSL-OEL)
Output setup time from CS low to OE low. SS = 0, not in select strobe mode
(RS+1) * E - 3
(RS+1) * E + 3
5
toh(OEH-CSH)
Output hold time from OE high to CS high. SS = 0, not in select strobe mode
(RH+1) * E - 3
(RH+1) * E + 3
ns
4
tosu(CSL-OEL)
Output setup time from CS low to OE low in select strobe mode, SS = 1
(RS+1) * E - 3
(RS+1) * E + 3
ns
5
toh(OEH-CSH)
Output hold time from OE high to CS high in select strobe mode, SS = 1
(RH+1) * E - 3
(RH+1) * E + 3
ns
6
tosu(BAV-OEL)
Output setup time from BA valid to OE low
(RS+1) * E - 3
(RS+1) * E + 3
ns
7
toh(OEH-BAIV)
Output hold time from OE high to BA invalid
(RH+1) * E - 3
(RH+1) * E + 3
ns
8
tosu(AV-OEL)
Output setup time from A valid to OE low
(RS+1) * E - 3
(RS+1) * E + 3
ns
9
toh(OEH-AIV)
Output hold time from OE high to A invalid
(RH+1) * E - 3
(RH+1) * E + 3
ns
10
tw(OEL)
OE active time low, when ew = 0. Extended wait mode is disabled.
(RST+1) * E - 3
(RST+1) * E + 3
ns
10
tw(OEL)
OE active time low, when ew = 1. Extended wait mode is enabled.
(RST+1) * E - 3
(RST+1) * E + 3
ns
11
td(WAITH-OEH)
Delay time from WAIT deasserted to OE# high
4E + 3
ns
12
tsu(D-OEH)
Input setup time from D valid to OE high
13
th(OEH-D)
Input hold time from OE high to D invalid
3
ns
0.5
ns
Write Timing
15
15
16
(WS+WST+WH+ (WS+WST+WH+
TA+4)*E-3
TA+4)*E+3
ns
tc(CSL)
EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WH+ (WS+WST+WH+
TA+4)*E-3
TA+4)*E+3
ns
tosuCSL-WEL)
Output setup time from CS low to WE low. SS = 0, not in select strobe mode
(WS+1) * E - 3
ns
tc(CSL)
EMIF write cycle time when ew = 0, meaning not in extended wait mode
17
toh(WEH-CSH)
Output hold time from WE high to CS high. SS = 0, not in select strobe mode
(WH+1) * E - 3
ns
16
tosuCSL-WEL)
Output setup time from CS low to WE low in select strobe mode, SS = 1
(WS+1) * E - 3
ns
17
toh(WEH-CSH)
Output hold time from WE high to CS high in select strobe mode, SS = 1
(WH+1) * E - 3
ns
18
tosu(RNW-WEL)
Output setup time from RNW valid to WE low
(WS+1) * E - 3
ns
19
toh(WEH-RNW)
Output hold time from WE high to RNW invalid
(WH+1) * E - 3
ns
20
tosu(BAV-WEL)
Output setup time from BA valid to WE low
(WS+1) * E - 3
ns
21
toh(WEH-BAIV)
Output hold time from WE high to BA invalid
(WH+1) * E - 3
ns
22
tosu(AV-WEL)
Output setup time from A valid to WE low
(WS+1) * E - 3
ns
23
toh(WEH-AIV)
Output hold time from WE high to A invalid
(WH+1) * E - 3
ns
24
tw(WEL)
WE active time low, when ew = 0. Extended wait mode is disabled.
(WST+1) * E - 3
ns
192
Peripheral Information and Electrical Specifications
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Table 7-64
EMIF16 Asynchronous Memory Timing Requirements
(1)
(Part 2 of 2)
(see Figure 7-40 and Figure 7-41)
No.
Min
Max
Unit
24
tw(WEL)
WE active time low, when ew = 1. Extended wait mode is enabled.
(WST+1) * E - 3
ns
26
tosu(DV-WEL)
Output setup time from D valid to WE low
(WS+1) * E - 3
ns
27
toh(WEH-DIV)
Output hold time from WE high to D invalid
(WH+1) * E - 3
25
td(WAITH-WEH)
Delay time from WAIT deasserted to WE# high
ns
4E + 3
ns
End of Table 7-64
1 E = 1/SYSCLK7
Figure 7-40
EMIF16 Asynchronous Memory Read Timing Diagram
PRODUCT PREVIEW
3
EM_CS[5:2]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
5
7
9
4
6
8
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 7-41
EMIF16 Asynchronous Memory Write Timing Diagram
15
EM_CS[5:2]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
17
19
21
23
16
18
20
22
24
EM_WE
26
27
EM_D[15:0]
EM_OE
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Figure 7-42
www.ti.com
EMIF16 EM_WAIT Read Timing Diagram
Setup
Extended Due to EM_WAIT
Strobe
Strobe
Hold
Strobe
Hold
EM_CS[5:2]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_OE
14
11
PRODUCT PREVIEW
EM_WAIT
Figure 7-43
2
2
Asserted
Deasserted
EMIF16 EM_WAIT Write Timing Diagram
Setup
Extended Due to EM_WAIT
Strobe
EM_CS[5:2]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
28
25
EM_WAIT
194
2
2
Asserted
Deasserted
Peripheral Information and Electrical Specifications
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7.16 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the TMS320C6654
DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and
100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with
hardware flow control and quality-of-service (QOS) support.
Deviating from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER. Instead
of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally
generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an
error by the network.
The EMAC control module is the main interface between the device core processor, the MDIO module, and the
EMAC module. The relationship between these three components is shown in Figure 7-44. The EMAC control
module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it
controls device interrupts. The EMAC control module incorporates 8K-bytes of internal RAM to hold EMAC buffer
descriptors.
Figure 7-44
EMAC, MDIO, and EMAC Control Modules
Interrupt
Controller
Configuration Bus
DMA Memory
Transfer Controller
Peripheral Bus
EMAC Control Module
EMAC/MDIO
Interrupt
EMAC Module
MDIO Module
Ethernet Bus
MDIO Bus
For more detailed information on the EMAC/MDIO, see Gigabit Ethernet (GbE) Subsystem for KeyStone Devices
User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
7.16.1 EMAC Device-Specific Information
The EMAC module on the device supports Serial Gigabit Media Independent Interface (SGMII). The SGMII
interface conforms to version 1.8 of the industry standard specification.
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The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple Access with
Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also
been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.16.2 EMAC Peripheral Register Description(s)
The memory maps of the EMAC are shown in Table 7-65 through Table 7-70.
Table 7-65
Ethernet MAC (EMAC) Control Registers (Part 1 of 3)
Hex Address
PRODUCT PREVIEW
196
Acronym
02C0 8000
TXIDVER
02C0 8004
TXCONTROL
02C0 8008
TXTEARDOWN
02C0 800F
-
Register Name
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown register
Reserved
02C0 8010
RXIDVER
02C0 8014
RXCONTROL
Receive Identification and Version Register
02C0 8018
RXTEARDOWN
02C0 801C
-
Reserved
02C0 8020 - 02C0 807C
-
Reserved
02C0 8080
TXINTSTATRAW
Receive Control Register
Receive Teardown Register
Transmit Interrupt Status (Unmasked) Register
02C0 8084
TXINTSTATMASKED
02C0 8088
TXINTMASKSET
02C0 808C
TXINTMASKCLEAR
02C0 8090
MACINVECTOR
MAC Input Vector Register
02C0 8094
MACEOIVECTOR
MAC End of Interrupt Vector Register
02C0 8098 - 02C0 819C
-
02C0 80A0
RXINTSTATRAW
02C0 80A4
RXINTSTATMASKED
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
Reserved
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
02C0 80A8
RXINTMASKSET
02C0 80AC
RXINTMASKCLEAR
Receive Interrupt Mask Clear Register
02C0 80B0
MACINTSTATRAW
MAC Interrupt Status (Unmasked) Register
02C0 80B4
MACINTSTATMASKED
02C0 80B8
MACINTMASKSET
02C0 80BC
MACINTMASKCLEAR
Receive Interrupt Mask Set Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
02C0 80C0 - 02C0 80FC
-
02C0 8100
RXMBPENABLE
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
02C0 8104
RXUNICASTSET
Receive Unicast Enable Set Register
02C0 8108
RXUNICASTCLEAR
02C0 810C
RXMAXLEN
02C0 8110
RXBUFFEROFFSET
Reserved
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
02C0 8114
RXFILTERLOWTHRESH
02C0 8118 - 02C0 811C
-
Receive Filter Low Priority Frame Threshold Register
02C0 8120
RX0FLOWTHRESH
Receive Channel 0 Flow Control Threshold Register
02C0 8124
RX1FLOWTHRESH
Receive Channel 1 Flow Control Threshold Register
Reserved
02C0 8128
RX2FLOWTHRESH
Receive Channel 2 Flow Control Threshold Register
02C0 812C
RX3FLOWTHRESH
Receive Channel 3 Flow Control Threshold Register
02C0 8130
RX4FLOWTHRESH
Receive Channel 4 Flow Control Threshold Register
02C0 8134
RX5FLOWTHRESH
Receive Channel 5 Flow Control Threshold Register
02C0 8138
RX6FLOWTHRESH
Receive Channel 6 Flow Control Threshold Register
02C0 813C
RX7FLOWTHRESH
Receive Channel 7 Flow Control Threshold Register
02C0 8140
RX0FREEBUFFER
Peripheral Information and Electrical Specifications
Receive Channel 0 Free Buffer Count Register
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Ethernet MAC (EMAC) Control Registers (Part 2 of 3)
Hex Address
Acronym
02C0 8144
RX1FREEBUFFER
Register Name
Receive Channel 1 Free Buffer Count Register
02C0 8148
RX2FREEBUFFER
Receive Channel 2 Free Buffer Count Register
02C0 814C
RX3FREEBUFFER
Receive Channel 3 Free Buffer Count Register
02C0 8150
RX4FREEBUFFER
Receive Channel 4 Free Buffer Count Register
02C0 8154
RX5FREEBUFFER
Receive Channel 5 Free Buffer Count Register
02C0 8158
RX6FREEBUFFER
Receive Channel 6 Free Buffer Count Register
02C0 815C
RX7FREEBUFFER
Receive Channel 7 Free Buffer Count Register
02C0 8160
MACCONTROL
MAC Control Register
02C0 8164
MACSTATUS
MAC Status Register
02C0 8168
EMCONTROL
02C0 816C
FIFOCONTROL
Emulation Control Register
02C0 8170
MACCONFIG
02C0 8174
SOFTRESET
02C0 81D0
MACSRCADDRLO
MAC Source Address Low Bytes Register
02C0 81D4
MACSRCADDRHI
MAC Source Address High Bytes Register
02C0 81D8
MACHASH1
MAC Hash Address Register 1
02C0 81DC
MACHASH2
MAC Hash Address Register 2
FIFO Control Register
MAC Configuration Register
Soft Reset Register
02C0 81E0
BOFFTEST
Back Off Test Register
02C0 81E4
TPACETEST
Transmit Pacing Algorithm Test Register
02C0 81E8
RXPAUSE
Receive Pause Timer Register
02C0 81EC
TXPAUSE
Transmit Pause Timer Register
02C0 8200 - 02C0 82FC
-
See Table 7-66 ‘‘EMAC Statistics Registers’’
02C0 8300 - 02C0 84FC
-
Reserved
02C0 8500
MACADDRLO
MAC Address Low Bytes Register (used in Receive Address Matching)
02C0 8504
MACADDRHI
MAC Address High Bytes Register (used in Receive Address Matching)
02C0 8508
MACINDEX
02C0 850C - 02C0 85FC
-
02C0 8600
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
02C0 8604
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer Register
MAC Index Register
Reserved
02C0 8608
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer Register
02C0 860C
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer Register
02C0 8610
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer Register
02C0 8614
TX5HDP
Transmit Channel 5 DMA Head Descriptor Pointer Register
02C0 8618
TX6HDP
Transmit Channel 6 DMA Head Descriptor Pointer Register
02C0 861C
TX7HDP
Transmit Channel 7 DMA Head Descriptor Pointer Register
02C0 8620
RX0HDP
Receive Channel 0 DMA Head Descriptor Pointer Register
02C0 8624
RX1HDP
Receive t Channel 1 DMA Head Descriptor Pointer Register
02C0 8628
RX2HDP
Receive Channel 2 DMA Head Descriptor Pointer Register
02C0 862C
RX3HDP
Receive t Channel 3 DMA Head Descriptor Pointer Register
02C0 8630
RX4HDP
Receive Channel 4 DMA Head Descriptor Pointer Register
02C0 8634
RX5HDP
Receive t Channel 5 DMA Head Descriptor Pointer Register
02C0 8638
RX6HDP
Receive Channel 6 DMA Head Descriptor Pointer Register
02C0 863C
RX7HDP
Receive t Channel 7 DMA Head Descriptor Pointer Register
02C0 8640
TX0CP
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PRODUCT PREVIEW
Table 7-65
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register
Peripheral Information and Electrical Specifications
197
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-65
www.ti.com
Ethernet MAC (EMAC) Control Registers (Part 3 of 3)
Hex Address
Acronym
02C0 8644
TX1CP
Register Name
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register
02C0 8648
TX2CP
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register
02C0 864C
TX3CP
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register
02C0 8650
TX4CP
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register
02C0 8654
TX5CP
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register
02C0 8658
TX6CP
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register
02C0 865C
TX7CP
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register
02C0 8660
RX0CP
Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register
02C0 8664
RX1CP
Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register
PRODUCT PREVIEW
02C0 8668
RX2CP
Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register
02C0 866C
RX3CP
Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register
02C0 8670
RX4CP
Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register
02C0 8674
RX5CP
Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register
02C0 8678
RX6CP
Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register
02C0 867C
RX7CP
Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register
02C0 8680 - 02C0 86FC
-
Reserved
02C0 8700 - 02C0 877C
-
Reserved
02C0 8780 - 02C0 8FFF
-
Reserved
End of Table 7-65
Table 7-66
EMAC Statistics Registers (Part 1 of 2)
Hex Address
198
Acronym
Register Name
02C0 8200
RXGOODFRAMES
Good Receive Frames Register
02C0 8204
RXBCASTFRAMES
Broadcast Receive Frames Register (Total number of Good Broadcast Frames Receive)
02C0 8208
RXMCASTFRAMES
Multicast Receive Frames Register (Total number of Good Multicast Frames Received)
02C0 820C
RXPAUSEFRAMES
Pause Receive Frames Register
02C0 8210
RXCRCERRORS
Receive CRC Errors Register (Total number of Frames Received with CRC Errors)
02C0 8214
RXALIGNCODEERRORS
Receive Alignment/Code Errors register (Total number of frames received with
alignment/code errors)
02C0 8218
RXOVERSIZED
02C0 821C
RXJABBER
02C0 8220
RXUNDERSIZED
Receive Undersized Frames Register (Total number of Undersized Frames Received)
02C0 8224
RXFRAGMENTS
Receive Frame Fragments Register
02C0 8228
RXFILTERED
02C0 822C
RXQOSFILTERERED
Receive Oversized Frames Register (Total number of Oversized Frames Received)
Receive Jabber Frames Register (Total number of Jabber Frames Received)
Filtered Receive Frames Register
Received QOS Filtered Frames Register
02C0 8230
RXOCTETS
02C0 8234
TXGOODFRAMES
Good Transmit Frames Register (Total number of Good Frames Transmitted)
Receive Octet Frames Register (Total number of Received Bytes in Good Frames)
02C0 8238
TXBCASTFRAMES
Broadcast Transmit Frames Register
02C0 823C
TXMCASTFRAMES
Multicast Transmit Frames Register
02C0 8240
TXPAUSEFRAMES
Pause Transmit Frames Register
02C0 8244
TXDEFERED
Deferred Transmit Frames Register
Transmit Collision Frames Register
02C0 8248
TXCOLLISION
02C0 824C
TXSINGLECOLL
Transmit Single Collision Frames Register
02C0 8250
TXMULTICOLL
Transmit Multiple Collision Frames Register
Peripheral Information and Electrical Specifications
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Fixed and Floating-Point Digital Signal Processor
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EMAC Statistics Registers (Part 2 of 2)
Hex Address
Acronym
02C0 8254
TXEXCESSIVECOLL
Register Name
Transmit Excessive Collision Frames Register
02C0 8258
TXLATECOLL
Transmit Late Collision Frames Register
02C0 825C
TXUNDERRUN
Transmit Under Run Error Register
02C0 8260
TXCARRIERSENSE
02C0 8264
TXOCTETS
Transmit Octet Frames Register
Transmit and Receive 64 Octet Frames Register
Transmit Carrier Sense Errors Register
02C0 8268
FRAME64
02C0 826C
FRAME65T127
Transmit and Receive 65 to 127 Octet Frames Register
02C0 8270
FRAME128T255
Transmit and Receive 128 to 255 Octet Frames Register
02C0 8274
FRAME256T511
Transmit and Receive 256 to 511 Octet Frames Register
02C0 8278
FRAME512T1023
Transmit and Receive 512 to 1023 Octet Frames Register
02C0 827C
FRAME1024TUP
Transmit and Receive 1024 to 1518 Octet Frames Register
02C0 8280
NETOCTETS
02C0 8284
RXSOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
PRODUCT PREVIEW
Table 7-66
Network Octet Frames Register
02C0 8288
RXMOFOVERRUNS
Receive FIFO or DMA Middle of Frame Overruns Register
02C0 828C
RXDMAOVERRUNS
Receive DMA Start of Frame and Middle of Frame Overruns Register
02C0 8290 - 02C0 82FC
-
Reserved
End of Table 7-66
Table 7-67
EMAC Descriptor Memory
Hex Address
Acronym
02C0 A000 - 02C0 BFFF
-
Register Name
EMAC Descriptor Memory
End of Table 7-67
Table 7-68
SGMII Control Registers
Hex Address
Acronym
02C0 8900
IDVER
02C0 8904
SOFT_RESET
02C0 8910
CONTROL
Control Register
02C0 8914
STATUS
Status Register
02C0 8918
MR_ADV_ABILITY
02C0 891C
-
02C0 8920
MR_LP_ADV_ABILITY
02C0 8924 - 02C0 8948
-
Register Name
Identification and Version register
Software Reset Register
Advertised Ability Register
Reserved
Link Partner Advertised Ability Register
Reserved
End of Table 7-68
Table 7-69
EMIC Control Registers (Part 1 of 2)
Hex Address
Acronym
02C0 8A00
IDVER
02C0 8A04
SOFT_RESET
Register Name
Identification and Version register
Software Reset Register
02C0 8A08
EM_CONTROL
Emulation Control Register
02C0 8A0C
INT_CONTROL
Interrupt Control Register
02C0 8A10
C0_RX_THRESH_EN
02C0 8A14
C0_RX_EN
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Receive Threshold Interrupt Enable Register for CorePac0
Receive Interrupt Enable Register for CorePac0
Peripheral Information and Electrical Specifications
199
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-69
www.ti.com
EMIC Control Registers (Part 2 of 2)
Hex Address
Acronym
Register Name
02C0 8A18
C0_TX_EN
Transmit Interrupt Enable Register for CorePac0
02C0 8A1C
C0_MISC_EN
02C0 8A10
Reserved
02C0 8A14
Reserved
02C0 8A18
Reserved
Misc Interrupt Enable Register for CorePac0
02C0 8A1C
Reserved
02C0 8A90
C0_RX_THRESH_STAT
Receive Threshold Masked Interrupt Status Register for CorePac0
02C0 8A94
C0_RX_STAT
Receive Interrupt Masked Interrupt Status Register for CorePac0
02C0 8A98
C0_TX_STAT
Transmit Interrupt Masked Interrupt Status Register for CorePac0
PRODUCT PREVIEW
02C0 8A9C
C0_MISC_STAT
02C0 8AA0
Reserved
02C0 8AA4
Reserved
02C0 8AA8
Reserved
Misc Interrupt Masked Interrupt Status Register for CorePac0
02C0 8AAC
Reserved
02C0 8B10
C0_RX_IMAX
Receive Interrupts Per Millisecond for CorePac0
Transmit Interrupts Per Millisecond for CorePac0
02C0 8B14
C0_TX_IMAX
02C0 8B18
Reserved
02C0 8B1C
Reserved
End of Table 7-69
7.16.3 EMAC Electrical Data/Timing (SGMII)
The Hardware Design Guide for KeyStone Devices application report specifies a complete EMAC and SGMII
interface solution for the C6654 as well as a list of compatible EMAC and SGMII devices. TI has performed the
simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution are met;
therefore, no electrical data/timing information is supplied here for this interface.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
7.17 Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application
software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the GbE
switch subsystem, retrieve the negotiation results, and configure required parameters in the GbE switch subsystem
module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface,
with very little maintenance from the core processor. For more information, see the Gigabit Ethernet (GbE)
Subsystem for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
The EMAC control module is the main interface between the device core processor, the MDIO module, and the
EMAC module. The relationship between these three components is shown in Figure 7-44.
For more detailed information on the EMAC/MDIO, see Gigabit Ethernet (GbE) Subsystem for KeyStone Devices
User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
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Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
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7.17.1 MDIO Peripheral Registers
The memory map of the MDIO is shown in Table 7-70.
MDIO Registers
Hex Address
Acronym
Register Name
02C0 8800
VERSION
MDIO Version Register
02C0 8804
CONTROL
MDIO Control Register
02C0 8808
ALIVE
MDIO PHY Alive Status Register
02C0 880C
LINK
MDIO PHY Link Status Register
02C0 8810
LINKINTRAW
02C0 8814
LINKINTMASKED
02C0 8818 - 02C0 881C
-
02C0 8820
USERINTRAW
MDIO link Status Change Interrupt (unmasked) Register
MDIO link Status Change Interrupt (masked) Register
Reserved
PRODUCT PREVIEW
Table 7-70
MDIO User Command Complete Interrupt (Unmasked) Register
02C0 8824
USERINTMASKED
MDIO User Command Complete Interrupt (Masked) Register
02C0 8828
USERINTMASKSET
MDIO User Command Complete Interrupt Mask Set Register
02C0 882C
USERINTMASKCLEAR
02C0 8830 - 02C0 887C
-
MDIO User Command Complete Interrupt Mask Clear Register
02C0 8880
USERACCESS0
MDIO User Access Register 0
02C0 8884
USERPHYSEL0
MDIO User PHY Select Register 0
Reserved
02C0 8888
USERACCESS1
MDIO User Access Register 1
02C0 888C
USERPHYSEL1
MDIO User PHY Select Register 1
02C0 8890 - 02C0 8FFF
-
Reserved
End of Table 7-70
7.17.2 MDIO Timing
Table 7-71
MDIO Timing Requirements
See Figure 7-45
No.
Min
Max
Unit
1
tc(MDCLK)
Cycle time, MDCLK
400
ns
2
tw(MDCLKH)
Pulse duration, MDCLK high
180
ns
3
tw(MDCLKL)
Pulse duration, MDCLK low
180
ns
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
10
ns
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
tt(MDCLK)
Transition time, MDCLK
5
ns
5
ns
End of Table 7-71
Figure 7-45
MDIO Input Timing
MDCLK
2
3
4
5
MDIO
(Input)
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Table 7-72
www.ti.com
MDIO Switching Characteristics
See Figure 7-46
No.
6
Parameter
td(MDCLKL-MDIO)
Min
Delay time, MDCLK low to MDIO data output valid
Max
Unit
100
ns
End of Table 7-72
Figure 7-46
MDIO Output Timing
1
MDCLK
6
PRODUCT PREVIEW
MDIO
(Ouput)
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7.18 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU and send synchronization
events to the EDMA3 channel controller.
7.18.1 Timers Device-Specific Information
The TMS320C6654 device has eight 64-bit timers in total. Timer0 is dedicated to the CorePac as a watchdog timer
and can also be used as a general-purpose timer. Each of the other seven timers can also be configured as a
general-purpose timer only, programmed as a 64-bit timer or as two separate 32-bit timers.
When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two
32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low
counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement
that software writes to the timer before the count expires, after which the count begins again. If the count ever
reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming ‘‘Reset
Type Status Register (RSTYPE)’’ on page 133 and the type of reset initiated can set by programming ‘‘Reset
Configuration Register (RSTCFG)’’ on page 134. For more information, see the 64-bit Timer (Timer 64) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
7.18.2 Timers Electrical Data/Timing
The tables and figure below describe the timing requirements and switching characteristics of Timer0 through
Timer7 peripherals.
Table 7-73
Timer Input Timing Requirements (1)
(see Figure 7-47)
No.
Min
Max
Unit
1
tw(TINPH)
Pulse duration, high
12C
ns
2
tw(TINPL)
Pulse duration, low
12C
ns
End of Table 7-73
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
Table 7-74
Timer Output Switching Characteristics (1)
(see Figure 7-47)
No.
Parameter
Min
Max
Unit
3
tw(TOUTH)
Pulse duration, high
12C - 3
ns
4
tw(TOUTL)
Pulse duration, low
12C - 3
ns
End of Table 7-74
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
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PRODUCT PREVIEW
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge)
and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable
period.
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 7-47
www.ti.com
Timer Timing
1
2
TIMIx
3
4
TIMOx
PRODUCT PREVIEW
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7.19 General-Purpose Input/Output (GPIO)
7.19.1 GPIO Device-Specific Information
On the TMS320C6654, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more
detailed information on device/peripheral configuration and the C6654 device pin muxing, see ‘‘Device
Configuration’’ on page 65. For more information on GPIO, see the General Purpose Input/Output (GPIO) for
KeyStone Devices User Guide ‘‘Related Documentation from Texas Instruments’’ on page 64.
7.19.2 GPIO Electrical Data/Timing
GPIO Input Timing Requirements
No.
Min
1
tw(GPOH)
Pulse duration, GPOx high
2
tw(GPOL)
Pulse duration, GPOx low
Max
Unit
(1)
ns
12C
ns
12C
End of Table 7-75
1 C = 1 ÷ CORECLK(N|P) frequency in ns.
Table 7-76
GPIO Output Switching Characteristics
No.
(1)
Parameter
3
tw(GPOH)
Pulse duration, GPOx high
4
tw(GPOL)
Pulse duration, GPOx low
Min
36C
(2)
Max
Unit
-8
ns
36C - 8
ns
End of Table 7-76
1 Over recommended operating conditions.
2 C = 1 ÷ CORECLK(N|P) frequency in ns.
Figure 7-48
GPIO Timing
1
2
GPIx
3
4
GPOx
7.20 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the DSP C66x
CorePacs. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write
sequence is not broken. The semaphore block has unique interrupts to each of the cores to identify when that core
has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to
allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports 8 masters and contains 32 semaphores to be used within the system.
There are two methods of accessing a semaphore resource:
• Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the
semaphore is not granted.
• Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt
notifies the CPU that it is available.
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Table 7-75
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.21 Emulation Features and Capability
7.21.1 Advanced Event Triggering (AET)
PRODUCT PREVIEW
The TMS320C6654 device supports Advanced Event Triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting
the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events
such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely
generate events for complex sequences.
For more information on AET, see the following documents in ‘‘Related Documentation from Texas Instruments’’
on page 64:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor
Systems application report
7.21.2 Trace
The C6654 device supports Trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information
for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the 60-Pin Emulation Header
Technical Reference in ‘‘Related Documentation from Texas Instruments’’ on page 64.
7.21.2.1 Trace Electrical Data/Timing
Table 7-77
Trace Switching Characteristics
(1)
(see Figure 7-49)
No.
Parameter
1
tw(DPnH)
1
2
Min Max Unit
Pulse duration, DPn/EMUn high
2.4
ns
tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
1.5
ns
tw(DPnL)
Pulse duration, DPn/EMUn low
2.4
ns
2
tw(DPnL)10%
Pulse duration, DPn/EMUn low detected at 10% Voh
1.5
3
tsko(DPn)
Output skew time, time delay difference between DPn/EMUn pins configured as trace
tskp(DPn)
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays.
tσλδπ_ο(DPn)
Output slew rate DPn/EMUn
-1
ns
1
600
3.3
ns
ps
V/ns
End of Table 7-77
1 Over recommended operating conditions.
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Figure 7-49
Trace Timing
A
TPLH
TPHL
1
2
B
3
C
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported
allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary
scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes
(SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.21.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6654 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
7.21.3.2 JTAG Electrical Data/Timing
Table 7-78
JTAG Test Port Timing Requirements
(see Figure 7-50)
No.
Min
Max
Unit
1
tc(TCK)
Cycle time, TCK
34
ns
1a
tw(TCKH)
1b
tw(TCKL)
Pulse duration, TCK high (40% of tc)
13.6
ns
Pulse duration, TCK low(40% of tc)
13.6
ns
3
tsu(TDI-TCK)
input setup time, TDI valid to TCK high
3.4
ns
3
tsu(TMS-TCK)
input setup time, TMS valid to TCK high
3.4
ns
4
th(TCK-TDI)
input hold time, TDI valid from TCK high
17
ns
4
th(TCK-TMS)
input hold time, TMS valid from TCK high
17
ns
End of Table 7-78
Table 7-79
JTAG Test Port Switching Characteristics (1)
(see Figure 7-50)
No.
2
Parameter
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
Min
Max
Unit
13.6
ns
End of Table 7-79
1 Over recommended operating conditions.
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7.21.3 IEEE 1149.1 JTAG
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Figure 7-50
www.ti.com
JTAG Test-Port Timing
1
1b
1a
TCK
2
TDO
4
3
TDI / TMS
PRODUCT PREVIEW
7.22 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected
analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
• Transmit & receive FIFO buffers allow the McBSP to operate at a higher sample rate by making it more
tolerant to DMA latency
If an internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always
be set to a value of 1 or greater.
For more information, see the Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User Guide in
‘‘Related Documentation from Texas Instruments’’ on page 64.
7.22.1 McBSP Peripheral Register
Table 7-80
McBSP0
Byte Address
McBSP/FIFO Registers (Part 1 of 2)
McBSP1
Byte Address
Acronym
Register Description
McBSP Registers
0x021B 4000
0x021B 8000
DRR
McBSP Data Receive Register (read-only)
0x021B 4004
0x021B 8004
DXR
McBSP Data Transmit Register
0x021B 4008
0x021B 8008
SPCR
McBSP Serial Port Control Register
0x021B 400C
0x021B 800C
RCR
McBSP Receive Control Register
0x021B 4010
0x021B 8010
XCR
McBSP Transmit Control Register
0x021B 4014
0x021B 8014
SRGR
McBSP Sample Rate Generator register
0x021B 4018
0x021B 8018
MCR
McBSP Multichannel Control Register
0x021B 401C
0x021B 801C
RCERE0
McBSP Enhanced Receive Channel Enable Register 0 Partition A/B
0x021B 4020
0x021B 8020
XCERE0
McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B
0x021B 4024
0x021B 8024
PCR
McBSP Pin Control Register
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Table 7-80
McBSP/FIFO Registers (Part 2 of 2)
McBSP0
Byte Address
McBSP1
Byte Address
Acronym
Register Description
0x021B 4028
0x021B 8028
RCERE1
McBSP Enhanced Receive Channel Enable Register 1 Partition C/D
0x021B 402C
0x021B 802C
XCERE1
McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D
0x021B 4030
0x021B 8030
RCERE2
McBSP Enhanced Receive Channel Enable Register 2 Partition E/F
0x021B 4034
0x021B 8034
XCERE2
McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F
0x021B 4038
0x021B 8038
RCERE3
McBSP Enhanced Receive Channel Enable Register 3 Partition G/H
0x021B 403C
0x021B 803C
XCERE3
McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H
0x021B 6800
0x021B A800
BFIFOREV
0x021B 6810
0x021B A810
WFIFOCTL
Write FIFO Control Register
0x021B 6814
0x021B A814
WFIFOSTS
Write FIFO Status Register
0x021B 6818
0x021B A818
RFIFOCTL
Read FIFO Control Register
0x021B 681C
0x021B A81C
RFIFOSTS
Read FIFO Status Register
0x2200 0000
0x2240 1000
RBUF
McBSP FIFO Receive Buffer
0x2200 0000
0x2240 1000
XBUF
McBSP FIFO Transmit Buffer
McBSP FIFO Control and Status Registers
PRODUCT PREVIEW
BFIFO Revision Identification Register
McBSP FIFO Data Registers
End of Table 7-80
7.22.2 McBSP Electrical Data/Timing
The following tables assume testing over recommended operating conditions.
7.22.2.1 McBSP Timing
Table 7-81
McBSP Timing Requirements
(see Figure 7-51)
No.
Min
Max
Unit
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
TBD
TBD
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
TBD
TBD
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
TBD
TBD
CLKR ext
TBD
TBD
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
TBD
TBD
CLKR ext
TBD
TBD
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
TBD
TBD
CLKR ext
TBD
TBD
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
TBD
TBD
CLKR ext
TBD
TBD
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKR int
TBD
TBD
CLKR ext
TBD
TBD
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKR int
TBD
TBD
CLKR ext
TBD
TBD
ns
ns
ns
ns
ns
ns
End of Table 7-81
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are
based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
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(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
Table 7-82
McBSP Switching Characteristics
(see Figure 7-51)
No.
Parameter
Min
Max Unit
TBD
TBD
PRODUCT PREVIEW
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input.
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
TBD
TBD
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
TBD
TBD
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
TBD
TBD
ns
CLKX int
TBD
TBD
CLKX ext
TBD
TBD
CLKX int
TBD
TBD
CLKX ext
TBD
TBD
CLKX int
TBD
TBD
CLKX ext
TBD
TBD
FSX int
TBD
TBD
FSX ext
TBD
TBD
Delay time, CLKX high to internal FSX valid
9
td(CKXH-FXV)
12
tdis(CKXH-DXHZ) Disable time, DX Hi-Z following last data bit from CLKX high
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
14
td(FXH-DXV)
Delay time, FSX high to DX valid applies ONLY when in data delay 0
(XDATDLY = 00b) mode
ns
ns
ns
ns
ns
End of Table 7-82
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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Figure 7-51
McBSP Timing
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
8
Bit(n-1)
DR
(n-2)
(n-3)
3
PRODUCT PREVIEW
2
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
14
(B)
13
Bit(n-1)
12
DX
Table 7-83
Bit 0
13
(n-2)
(n-3)
McBSP Timing Requirements for FSR When GSYNC = 1
(see Figure 7-52)
No.
Min
Max
Unit
1
tsu(FRH-CKSH)
Setup time, FSR high before CLKS high
TBD
TBD
ns
2
th(CKSH-FRH)
Hold time, FSR high after CLKS high
TBD
TBD
ns
End of Table 7-83
Figure 7-52
FSR Timing When GSYNC = 1
CLKS
1
2
FSR external
CLKR/X
(no need to resync)
CLKR/X
(needs resync)
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7.23 Universal Parallel Port (UPP)
The Universal Parallel Port (UPP) peripheral is a multichannel, high-speed parallel interface with dedicated data
lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters
(ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be
interconnected with field-programmable gate arrays (FPGAs) or other UPP devices to achieve high-speed digital
data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels
operate in opposite directions.
PRODUCT PREVIEW
The UPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead
during high-speed data transmission. All UPP transactions use the internal DMA to provide data to or retrieve data
from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O
channels. The UPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O
channel. In this mode, only one I/O channel may be used.
The features of the UPP include:
• Programmable data width per channel (from 8 bits to 16 bits inclusive)
• Programmable data justification
– Right-justify with 0 extend
– Right-justify with sign extend
– Left-justify with 0 fill
• Supports multiplexing of interleaved data during SDR transmit
• Optional frame START signal with programmable polarity
• Optional data ENABLE signal with programmable polarity
• Optional synchronization WAIT signal with programmable polarity
• Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface
– Supports multiplexing of interleaved data during SDR transmit
– Supports demultiplexing and multiplexing of interleaved data during DDR transfers
For more information, see the Universal Parallel Port (UPP) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
7.23.1 UPP Register Descriptions
Table 7-84
Universal Parallel Port (UPP) Registers (Part 1 of 2)
Byte Address
Acronym
Register Description
0x0258 0000
UPPID
UPP Peripheral Identification Register
0x0258 0004
UPPCR
UPP Peripheral Control Register
0x0258 0008
UPDLB
UPP Digital Loopback Register
0x0258 0010
UPCTL
UPP Channel Control Register
0x0258 0014
UPICR
UPP Interface Configuration Register
0x0258 0018
UPIVR
UPP Interface Idle Value Register
0x0258 001C
UPTCR
UPP Threshold Configuration Register
0x0258 0020
UPISR
UPP Interrupt Raw Status Register
0x0258 0024
UPIER
UPP Interrupt Enabled Status Register
0x0258 0028
UPIES
UPP Interrupt Enable Set Register
0x0258 002C
UPIEC
UPP Interrupt Enable Clear Register
0x0258 0030
UPEOI
UPP End-of-Interrupt Register
0x0258 0040
UPID0
UPP DMA Channel I Descriptor 0 Register
212
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Universal Parallel Port (UPP) Registers (Part 2 of 2)
Byte Address
Acronym
Register Description
0x0258 0044
UPID1
UPP DMA Channel I Descriptor 1 Register
0x0258 0048
UPID2
UPP DMA Channel I Descriptor 2 Register
0x0258 0050
UPIS0
UPP DMA Channel I Status 0 Register
0x0258 0054
UPIS1
UPP DMA Channel I Status 1 Register
0x0258 0058
UPIS2
UPP DMA Channel I Status 2 Register
0x0258 0060
UPQD0
UPP DMA Channel Q Descriptor 0 Register
0x0258 0064
UPQD1
UPP DMA Channel Q Descriptor 1 Register
0x0258 0068
UPQD2
UPP DMA Channel Q Descriptor 2 Register
0x0258 0070
UPQS0
UPP DMA Channel Q Status 0 Register
0x0258 0074
UPQS1
UPP DMA Channel Q Status 1 Register
0x0258 0078
UPQS2
UPP DMA Channel Q Status 2 Register
End of Table 7-84
Table 7-85
UPP Timing Requirements
(see Figure 7-53, Figure 7-54, Figure 7-55, Figure 7-56)
No.
Min
1
tc(INCLK)
Cycle time, CHn_CLK
2
tw(INCLKH)
Pulse width, CHn_CLK high
3
tw(INCLKL)
Pulse width, CHn_CLK low
4
tsu(STV-INCLKH)
Setup time, CHn_START valid before CHn_CLK high
5
th(INCLKH-STV)
Hold time, CHn_START valid after CHn_CLK high
6
tsu(ENV-INCLKH)
Setup time, CHn_ENABLE valid before CHn_CLK high
7
th(INCLKH-ENV)
Hold time, CHn_ENABLE valid after CHn_CLK high
8
tsu(DV-INCLKH)
Setup time, CHn_DATA/XDATA valid before CHn_CLK high
9
th(INCLKH-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
10
tsu(DV-INCLKL)
Setup time, CHn_DATA/XDATA valid before CHn_CLK low
11
th(INCLKL-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
SDR mode
13.33
DDR mode
26.66
SDR mode
5
DDR mode
10
SDR mode
5
DDR mode
10
Max Unit
ns
ns
ns
4
ns
0.8
ns
4
ns
0.8
ns
4
ns
0.8
ns
4
ns
0.8
ns
19
su(WTV-INCLKL)
Setup time, CHn_WAIT valid before CHn_CLK high
10
ns
20
th(INCLKL-WTV)
Hold time, CHn_WAIT valid after CHn_CLK high
0.8
ns
21
tc(2xTXCLK)
Cycle time, 2xTXCLK input clock (1)
6.66
ns
End of Table 7-85
1 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required UPP transmit clock rate (as it is divided down by 2 inside the UPP). 2xTXCLK has no
specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
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PRODUCT PREVIEW
Table 7-84
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
Table 7-86
www.ti.com
UPP Switching Characteristics
(see Figure 7-55, Figure 7-56)
No.
Parameter
Min
SDR mode
13.33
DDR mode
26.66
SDR mode
5
DDR mode
10
SDR mode
5
DDR mode
10
Max Unit
PRODUCT PREVIEW
12
tc(OUTCLK)
Cycle time, CHn_CLK
ns
13
tw(OUTCLKH)
Pulse width, CHn_CLK high
14
tw(OUTCLKL)
Pulse width, CHn_CLK low
15
td(OUTCLKH-STV)
Delay time, CHn_START valid after CHn_CLK high
16
td(OUTCLKH-ENV) Delay time, CHn_ENABLE valid after CHn_CLK high
1
11
ns
17
td(OUTCLKH-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK high
1
11
ns
18
td(OUTCLKL-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK low
1
11
ns
ns
ns
1
11
ns
End of Table 7-86
Figure 7-53
UPP Single Data Rate (SDR) Receive Timing
2
1
3
CHx_CLK
5
4
CHx_START
7
6
CHx_ENABLE
CHx_WAIT
8
CHx_DATA[n:0]
CHx_XDATA[n:0]
Data1
Data3
Data2
Data5
Data4
Data6
Data7
Data8
Data9
9
Figure 7-54
UPP Double Data Rate (DDR) Receive Timing
2
1
3
CHx_CLK
5
4
CHx_START
7
6
CHx_ENABLE
CHx_WAIT
10
8
CHx_DATA[n:0]
CHx_XDATA[n:0]
I1
Q1
I2
Q2
I3
Q3
I4
Q4
I5
9
214
Peripheral Information and Electrical Specifications
Q5
I6
Q6
I7
Q7
I8
Q8
I9
Q9
11
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Figure 7-55
UPP Single Data Rate (SDR) Transmit Timing
12
14
13
CHx_CLK
15
CHx_START
16
CHx_ENABLE
20
19
CHx_WAIT
17
Figure 7-56
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
I8
I9
PRODUCT PREVIEW
CHx_DATA[n:0]
CHx_XDATA[n:0]
UPP Double Data Rate (DDR) Transmit Timing
12
14
13
CHx_CLK
15
CHx_START
16
CHx_ENABLE
20
19
CHx_WAIT
17
CHx_DATA[n:0]
CHx_XDATA[n:0]
I1
18
Q1
I2
Q2
I3
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Q3
I4
Q4
I5
Q5
I6
Q6
I7
Q7
Q8
Q9
Peripheral Information and Electrical Specifications
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PRODUCT PREVIEW
216
Peripheral Information and Electrical Specifications
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PRODUCT PREVIEW
A Revision History
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Revision History
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B Mechanical Data
B.1 Thermal Data
Table B-1 shows the thermal resistance characteristics for the PBGA - CZH/GZH mechanical package.
Table B-1
Thermal Resistance Characteristics (PBGA Package) [CZH/GZH]
No.
°C/W
1
RθJC
Junction-to-case
TBD
2
RθJB
Junction-to-board
TBD
End of Table B-1
PRODUCT PREVIEW
B.2 Packaging Information
The following packaging information reflects the most current released data available for the designated device(s).
This data is subject to change without notice and without revision of this document.
218
Mechanical Data
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PACKAGE OPTION ADDENDUM
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24-Mar-2012
PACKAGING INFORMATION
Orderable Device
TMS320C6654CZH8
Status
(1)
PREVIEW
Package Type Package
Drawing
FCBGA
CZH
Pins
Package Qty
Eco Plan
625
TBD
(2)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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