Single-chip Type with Built-in FET Switching Regulators Output 1.5A or Less High-efficiency Step-down Switching Regulator with Built-in Power MOSFET BD9123MUV No.11027EAT38 ●Description ROHM’s high efficiency step-down switching regulator BD9123MUV is a power supply designed to produce a low voltage including 0.85 to 1.2 volts from 5.5/3.3 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. ●Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) and SLLM (Simple Light Load Mode) 3) Incorporates output voltage inside control function.(3 bit) 4) Incorporates PGOOD function. 5) Incorporates soft-start function. 6) Incorporates thermal protection and ULVO functions. 7) Incorporates short-current protection circuit with time delay function. 8) Incorporates shutdown function Icc=0µA(Typ.) 9) Employs small surface mount package: VQFN016V3030 ●Applications Power supply for LSI including DSP, Micro computer and ASIC ●Absolute maximum ratings (Ta=25℃) Parameter Symbol Ratings Unit Vcc -0.3～+7 *1 V PVcc -0.3～+7 *1 V EN,SW,ITH Voltage EN, SW, ITH -0.3～+7 V Logic input voltage VID<2:0> -0.3～+7 V Power Dissipation 1 Pd1 0.27 *2 W Pd2 3 W 4 W 5 VCC Voltage PVCC Voltage Power Dissipation 2 Power Dissipation 3 0.62 * Pd3 1.77 * Power Dissipation 4 Pd4 2.66 * W Operating temperature range Topr -40～+95 ℃ Storage temperature range Tstg -55～+150 ℃ Tj +150 ℃ Maximum junction temperature *1 *2 *3 *4 *5 Pd should not be exceeded. IC only 1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, 1st and 4th copper foil area : 10.29mm2 , 2nd and 3rd copper foil area : 5505mm2 4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/17 2011.01 - Rev.A Technical Note BD9123MUV ●Operating Conditions (Ta=-40～+95℃) Parameter Power Supply Voltage EN Voltage Logic input voltage Output voltage Setting Range SW average output current *6 Symbol Ratings Unit Min. Typ. Max. VCC 2.7 3.3 5.5 V PVCC 2.7 3.3 5.5 V VEN 0 - Vcc V VID<2:0> 0 - 5.5 V VOUT 0.85 - 1.2 V ISW - - *6 1.2 A Pd should not be exceeded. ●Electrical Characteristics (Ta=25℃ VCC=PVCC=5V, EN=VCC, VID<2>=VID<1>=VID<0>= 0V), unless otherwise specified.) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Standby current ISTB - 0 10 µA Active current ICC - 300 500 µA EN Low voltage VENL - GND 0.8 V Standby mode EN High voltage VENH 2.0 VCC - V Active mode EN input current IEN - 5 10 µA VEN=5V VID Low voltage VVIDL - GND 0.8 V VID High voltage VVIDH 2.0 VCC - V VID input current IVID - 5 10 µA Oscillation frequency FOSC 0.8 1 1.2 MHz Pch FET ON resistance RONP - 0.35 0.60 Ω PVCC=5V Nch FET ON resistance RONN - 0.25 0.50 Ω PVCC=5V Output voltage VOUT 0.98 1.0 1.02 V VID<2:0>=(0,0,0) ITH SInk current ITHSI 25 50 - µA VOUT =1.2V ITH Source Current ITHSO 25 50 - µA VOUT =0.8V UVLO threshold voltage VUVLO1 2.4 2.5 2.6 V VCC=5V→0V UVLO release voltage VUVLO2 2.425 2.55 2.7 V VCC=0V→5V Power Good Threshold VPGOOD1 70 75 80 % VOUT→0V Power Good Release VPGOOD2 85 90 95 % 0V→VOUT TPG 2.5 5 10 ms RONPG - 140 280 Ω TSS 0.4 0.8 1.6 ms TLATCH 1 2 4 ms VSCP - Power Good Delay PGOOD ON Resistance Soft start time Timer latch time Output Short circuit threshold Voltage www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 2/17 VOUT×0.5 VOUT×0.7 V EN=GND VVID=5V VOUT→0V 2011.01 - Rev.A Technical Note BD9123MUV ●Package outline, SYMBOLS 【BD9123MUV】 ●Block Diagram, Application Circuit VCC EN 13 D 9 2 VCC VREF 1 3 Current Comp VID<0> 12 VID<1> 11 Lot No. R Q S SELECTOR VID<2> 10 Gm Amp CLK OSC VOUT 9 VCC PGOOD SLOPE Vcc Soft Start Current Sense/ Protect 1 8 SW 4.7µH 3 Driver Logic 4 Input 10µF 2 + Output 22µF PGND 5 TSD PGOOD 100Ω 16 UVLO 7 0.1µF 14 PVCC 15 6 GND ITH RITH CITH VQFN016V3030 (Unit:mm) Fig.1 BD9123MUV Package outline Fig.2 BD9123MUV Block Diagram ●Pin No. & function table Pin No. VID<0> VID<1> VID<2> VOUT 12 11 10 Pin name Function 1 2 9 SW Pch/Nch FET drain output pin 3 EN 8 13 ITH 4 5 VCC 7 14 PGOOD PVCC 15 6 GND PVCC 16 5 PGND 1 2 3 4 SW SW SW PGND Fig 3 Top View Ground GND 7 PGOOD 8 ITH 9 VOUT 10 VID<2> Output voltage control pin<2> 11 VID<1> Output voltage control pin<1> 12 VID<0> Output voltage control pin<0> Power Good pin Gm Amp output pin/Connected phase compensation capacitor Output voltage pin Enable pin(High Active） 13 EN 14 VCC VCC power supply input pin PVCC Pch FET source pin 16 www.rohm.com Nch FET source pin 6 15 © 2011 ROHM Co., Ltd. All rights reserved. PGND 3/17 2011.01 - Rev.A Technical Note BD9123MUV ●Characteristics data 2.0 2.0 2.0 【VOUT=1.0V】 1.6 1.2 0.8 Io=1.2A Ta=25℃ 0.4 0.0 1.6 1.2 0.8 VCC=5V Io=0A Ta=25℃ 0.4 0.0 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 0 1 0 0.98 70 60 50 40 30 Vcc=5.0V Ta=25℃ 10 10 1.0 0.5 100 Io [A] 1000 2.7 10000 1200 200 600 400 VCC=5V 200 0 1.9 1.8 150 125 EN VOLTAGE:VEN[V] ON RESISTANCE:RON[O] 800 Low side (NMOS FET) 100 75 50 VCC=5.0V 25 1.7 1.6 1.5 1.4 1.3 1.2 1.0 -40 -20 0 20 40 60 80 TEMPERATURE:Ta[℃] 100 -40 Fig.11 Ta-RONN,RONP Fig.10 Ta-Fosc ON RESISTANCE:RON[O] -20 0 20 40 60 80 TEMPERATURE:Ta[℃] 100 Fig.12 Ta-VEN 400 【SLLM control 【VOUT=1.0V】 350 VCC=5V 1.1 0 100 5.5 2.0 High side (PMOS FET) 175 1000 3.4 4.1 4.8 INPUT VOLTAGE:VCC[V] Fig.9 Power supply voltageOperating frequency Fig.8 Efficiency Fig. 7 Ta-VOUT 0 20 40 60 80 TEMPERATURE:Ta[℃] 1.5 0.0 1 100 5 Ta=25℃ 0 0.96 2 3 4 EN VOLTAGE:VEN[V] 2.0 20 VCC=5V Io=0A -20 1 Fig.6 IOUT-VOUT FREQUENCY:FOSC[MHz] 1.00 -40 VCC=5V Ta=25℃ 0.4 5 80 1.02 0 20 40 60 80 INPUT VOLTAGE:VCC[V] 0.8 【VOUT=1.0】 90 EFFICIENCY:?[%] OUTPUT VOLTAGE:VOUT[V] 2 3 4 EN VOLTAGE:VEN[V] 100 【VOUT=1.0V】 -20 1.2 Fig.5 VEN - VOUT 1.04 -40 1.6 0.0 5 Fig.4 Vcc-VouT FREQUENCY:FOSC[kHz] 【VOUT=1.0V】 OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V] 【VOUT=1.0V】 VOUT=1.0V】 VCC=5V Io=0A Ta=25℃ 300 SW 250 SW 200 150 VO 100 VCC=5V VCC=5V Io=1.2A Ta=25℃ VO 50 0 -40 -20 0 20 40 60 80 TEMPERATURE:Ta[℃] 100 Fig.13 Ta-Icc www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. Fig.14 Soft start waveform 4/17 Fig.15 SW waveform Io=0mA 2011.01 - Rev.A Technical Note BD9123MUV SW Vo VO VO VCC=5V Io=1.2A Ta=25℃ Io IO Ta=25℃ Fig.16 SW waveform Io=1.2A Ta=25℃ Fig.17 Transient Response Io=125mA→850mA(2µA) Fig.18 Transient Response Io=850mA→125mA(2µA) VID[2:0]= (1,1,1)→0,0,1) VID[2:0]=(0,0,1)→(1,1,1) VID PGOOD VID 1.2V 1.2V 0.9V VOUT VO 0.85V Fig.19 BIT CHANCE RESPONSE www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. VO 0.85V Fig.20 BIT CHANCE RESPONSE 5/17 0.75V TPG VCC=5V Vo=1V Ta=25℃ Fig.21 PGOOD Delay 2011.01 - Rev.A Technical Note BD9123MUV ●Information on advantages Advantage 1: Offers fast transient response with current mode control system. Conventional product (Load response IO=0.1A→0.6A) BD9123MUV (Load response IO=0.6A→0.1A) VOUT 37mV VOUT 27mV IOUT IOUT Fig.22 Comparison of transient response Advantage 2: Offers high efficiency for all load range. ・For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load. Achieves efficiency improvement for lighter load. ・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. 100 Efficiency η[%] ON resistance of Pch side MOS FET : 0.35mΩ(Typ.) ON resistance of Nch side MOS FET : 0.25mΩ(Typ.) Achieves efficiency improvement for heavier load. SLLM ② 50 ① PWM ①inprovement by SLLM system ②improvement by synchronous rectifier 0 0.001 0.01 0.1 Output current Io[A] Offers high efficiency for all load range with the improvements mentioned above. 1 Fig.23 Efficiency Advantage 3: ・Supplied in smaller package due to small-sized power MOS FET incorporated. ・Output capacitor Co required for current mode control: 10µF ceramic capacitor ・Inductance L required for the operating frequency of 1 MHz: 4.7µH inductor Reduces a mounting area required. VCC VCC 20mm R PGOOD L Cin DC/DC Convertor RITH Co L VOUT Rf CIN Cf RPGOOD 15mm Co RITH CITH CITH Fig.24 Example application www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 6/17 2011.01 - Rev.A Technical Note BD9123MUV ●Operation BD9123MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a Pch MOS FET (while a Nch MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. ・SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency. SENSE Current Comp RESET VOUT R Q Level Shift FB SET S Driver Logic Gm Amp. ITH IL VOUT SW Load OSC Fig.25 Diagram of current mode PWM control PVCC Current Comp SENSE PVCC SENSE Current Comp FB SET FB GND SET GND RESET GND RESET GND SW GND SW IL GND IL(AVE) IL 0A VOUT VOUT(AVE) VOUT VOUT(AVE) Not switching Fig.26 PWM switching timing chart www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. Fig.27 SLLM 7/17 TM switching timing chart 2011.01 - Rev.A Technical Note BD9123MUV ●Description of operations ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. The inclination of standing up is different and the soft start time is different because of constancy depending on the value offset output voltage. When 1V settiing it, it is Tss=1msec(Typ.) VCC,EN 1.2V 0.85V VOUT Tss [ms] Tss’ Fig.28 Soft start action ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µA(Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50mV (Typ.) is provided to prevent output chattering. Hysteresis 50mV Vcc EN VOUT Tss Soft start Standby mode Tss Tss Operating mode UVLO Standby mode Operating mode UVLO Standby mode EN Standby mode Operating mode UVLO Fig.29 Soft start, Shutdown, UVLO timing chart ・PGOOD function When the output voltage falls below 75% (Typ.) of a set value, the PGOOD pin of Open-Drain is turned off. And the hysteresis width of 15% (Typ.) is provided to prevent output chattering. VOUT 90% The hysteresis width 75% TGP PGOOD Fig.30 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. PGOOD timing chart 8/17 2011.01 - Rev.A Technical Note BD9123MUV ●About setting the output voltage Output voltage shifts step by step as often as bit setting to control the overshoot/undershoot that happen when changing the setting value of output voltage. From the bit switching until output voltage reach to setting value, 8 steps (max) delay will occur. (0,0,1) VID<2:0> (1,1,1) 1.2V 0.85V VOUT tVID (max)=0.06ms ⅰ) Switching 3 bit synchronously ⅲ) Switching the bit during counting VID<2> V2D〈2〉 VID<1> 〈1〉 VID<0> 〈0〉 Count STOP Count STOP VOUT VOUT 5µs(max) About 10µs from bit switching About 10µs from bit switching ⅱ) Switching 3 bit with the time lag VID<2> VID<1> VID<0> Count STOP VOUT About 10µs from switching the last bit Fig.31 Timing chart of setting the output voltage It is possible to set output voltage, shown the diagram 1 below, by setting VID<0>～<2> 0 or 1. VID<2:0> terminal is set to VID<2:0>=(0,0,0) originally by the pull down resistor with high impedance inside IC. By pulling up/ pulling down about 10kΩ, the original value is changeable optionally. Table of output voltage setting VID<2> VID<1> VID<0> VOUT 0 0 0 1.0V 0 0 1 0.85V 0 1 0 0.9V 0 1 1 0.95V 1 0 0 1.05V 1 0 1 1.1V 1 1 0 1.15V 1 1 1 1.2V *After 10µs(max) from the bit change, VOUT change starts. *Requiring time for one step (50 mV shift) of VOUT is 5µs(max). *From the bit switching until output voltage reach to setting value, tVID(max)=0.06ms delay will occur. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 9/17 2011.01 - Rev.A Technical Note BD9123MUV ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time (TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO. VCC Output voltage OFF Latch Output Short circuit Threshold Voltage VOUT IL Limit IL t1<TLATCH Output voltage OFF t2=TLATCH Operated mode Output voltage OFF Timer Latch UVLO Operated mode UVLO Fig.32 Short-current protection circuit with time delay timing chart ●Switching regulator efficiency Efficiency ŋ may be expressed by the equation shown below: η= VOUT×IOUT Vin×Iin ×100[%]= POUT Pin ×100[%]= POUT POUT+PDα ×100[%] Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows: Dissipation factors: 1) ON resistance dissipation of inductor and FET: PD(I2R) 2) Gate charge/discharge dissipation: PD(Gate) 3) Switching dissipation: PD (SW) 4) ESR dissipation of capacitor: PD (ESR) 5) Operating current dissipation of IC: PD(IC) 1) 2 2 PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]: DC resistance of inductor, RON[Ω]: ON resistance of FET, IOUT[A]: Output current.) 2) PD(Gate)=Cgs×f×V (Cgs[F]: Gate capacitance of FET、f[H]: Switching frequency、V[V]: Gate driving voltage of FET) 3) PD(SW)= 4) PD(ESR)=IRMS ×ESR (IRMS[A]: Ripple current of capacitor, ESR[Ω]: Equivalent series resistance.) 5) PD(IC)=Vin×ICC (ICC[A]: Circuit current.) Vin2×CRSS×IOUT×f IDRIVE (CRSS[F]: Reverse transfer capacitance of FET, IDRIVE[A]: Peak current of gate.) 2 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 10/17 2011.01 - Rev.A Technical Note BD9123MUV ●Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. Power dissipation:Pd [W] 3.0 ①2.66W 2.0 1.0 2 4 layers (Copper foil area : 5505mm ) copper foil in each layers. θj-a=47.0℃/W st th 2 ② 4 layers (1 and 4 copper foil area : 6.28m ) nd rd 2 (2 and 3 copper foil area: 5505m ) (copper foil in each layers) θj-a=70.62℃/W 2 ③ 1 layer (Copper foil area : 6.28m ) θj-a=201.6℃/W ④ IC only. θj-a=462.9℃/W ① 4.0 ②1.77W P=IOUT2×RON RON=D×RONP+(1-D)RONN D：ON duty (=VOUT/VCC) RONP：ON resistance of Highside MOS FET RONN：ON resistance of Lowside MOS FET IOUT：Output curren ③0.62W ④0.27W 0 0 25 50 75 100 105 125 150 Ambient temperature:Ta [℃] Fig.33 Thermal derating curve (VQFN016V3030) If VCC=3.3V, VOUT=1.2V, RONP=0.35mΩ, RONN=0.25mΩ IOUT=1.2A, for example, D=VOUT/VCC=1.2/5=0.24 RON=0.24×0.35+(1-0.24)×0.25 =0.084+0.19 =0.274[Ω] P=1.22×0.247=0.394[W] As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/17 2011.01 - Rev.A Technical Note BD9123MUV ●Selection of components externally connected 1. Selection of inductor (L) The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. IL ΔIL ΔIL= (VCC-VOUT)×VOUT [A]・・・(1) L×VCC×f VCC Appropriate ripple current at output should be 20% more or less of the maximum output current. IL ΔIL=0.3×IOUTmax. [A]・・・(2) VOUT L L= Co (VCC-VOUT)×VOUT ΔIL×VCC×f [H]・・・(3) (ΔIL: Output ripple current, and f: Switching frequency) Fig.34 Output ripple current ※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=5.0V, VOUT=1.2V, f=1MHz, ΔIL=0.3×1.2A=0.36A, for example, L= (5-1.2)×1.2 0.6×5×1M =2.53µ → 4.7 [µH] ※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. VCC Output ripple voltage is determined by the equation (4): ΔVOUT=ΔIL×ESR [V]・・・(4) (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) VOUT L ESR Co ※ Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 10µF to 100µF ceramic capacitor is recommended. Fig.35 Output capacitor Less ESR allows reduction in output ripple voltage. 3. Selection of input capacitor (Cin) Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5): VCC Cin IRMS=IOUT× VOUT L √VOUT(VCC-VOUT) VCC < Worst case > IRMS(max.) Co When Vcc=2×VOUT, IRMS= Fig.36 Input capacitor [A]・・・(5) IOUT 2 If VCC=5V, VOUT=1.2V, and IOUTmax.=1.2A, √1.2(5-1.2) IRMS=1.2× =0.51 [ARMS] 5 A low ESR 10µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 12/17 2011.01 - Rev.A Technical Note BD9123MUV 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. fp(Min.) fp= A fp(Max.) Gain [dB] 1 fz(ESR)= 2π×ESR×CO 0 fz(ESR) IOUTMin. Phase [deg] 1 2π×RO×CO IOUTMax. Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. 0 -90 fp(Min.)= 1 [Hz]←with lighter load 2π×ROMax.×CO fp(Max.)= 1 2π×ROMin.×CO Fig.37 Open loop gain characteristics A [Hz]←with heavier load Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) fz(Amp.) Gain [dB] 0 fz(Amp.)= 0 Phase [deg] -90 1 2π×RITH.×CITH Fig.38 Error amp phase compensation characteristics VCC RPG Cin VCC EN VOUT VID<2:0> VCC,PVCC PGOOD VOUT L VID<2:0) ITH GND,PGND VOUT SW RITH ESR CITH CO RO Fig.39 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2π×RITH×CITH www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. = 1 2π×ROMax.×CO 13/17 2011.01 - Rev.A Technical Note BD9123MUV ●Cautions on PC Board layout Fig.40 Layout diagram ① ② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. ※VQFN016V3030 has thermal PAD on the reverse of the package. The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB. ●Recommended components Lists on above application Recommended components Lists Symbol Value Manufacturer Coil 4.7uH TDK VLF5014S-4R7M1R7 CIN Ceramic capacitor 10uF KYOCERA CM316X5R106M10A CO Ceramic capacitor 22uF KYOCERA CM316B226M06A CITH Ceramic capacitor 1500pF murata GRM18 Series RITH Resistance 9.1kΩ ROHM MCR03 Series Cf Ceramic capacitor 0.1uF murata GRM18 Series Rf Resistance 100Ω ROHM MCR03 Series L Part Series ※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 14/17 2011.01 - Rev.A Technical Note BD9123MUV ●I/O equivalence circuit 【BD9123MUV】 ・EN pin ・SW pin PVCC EN PVCC PVCC SW ・VOUT pin ・ITH pin VCC PGOOD ・PGOOD VOUT ITH ・VID〈2:0〉 pin VID〈2:0〉 Fig.41 I/O equivalence circuit www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 15/17 2011.01 - Rev.A Technical Note BD9123MUV ●Notes for use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 5. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 6. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic elements are formed. If a resistor is joined to a transistor terminal as shown in Fig 42. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Transistor (NPN) Pin A Pin B C Pin B B Pin A N P+ N P+ P N E Parasitic element N P+ Parasitic element P P+ B N C E Parasitic element P substrate P substrate GND N Parasitic element GND GND GND Other adjacent elements Fig.42 Simplified structure of monorisic IC 7. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 8. Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 50mΩ or less. Especially, in case output voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 50mΩ, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 16/17 2011.01 - Rev.A Technical Note BD9123MUV ●Ordering part number B D 9 Part No. 1 2 3 Part No. M U V - Package MUV : VQFN016V3030 E 2 Packaging and forming specification E2: Embossed tape and reel VQFN016V3030 <Tape and Reel information> 3.0±0.1 3.0±0.1 0.5 5 13 8 12 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 4 16 0.75 E2 9 1.4±0.1 0.4±0.1 1 3000pcs (0.22) 1.4±0.1 +0.03 0.02 −0.02 1.0MAX S C0.2 Embossed carrier tape Quantity Direction of feed 1PIN MARK 0.08 S Tape +0.05 0.25 −0.04 1pin (Unit : mm) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. Reel 17/17 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2011.01 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. R1120A