ROHM BD8966FVM

Single-chip Type with Built-in FET Switching Regulators
Low Noise High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD8966FVM
No.10027EBT24
●Description
ROHM’s high efficiency step-down switching regulator BD8966FVM is a power supply designed to produce a low voltage
including 1 volts from 5/3.3 volts power supply line. Offers high efficiency with synchronous rectifier. Employs a current mode
control system to provide faster transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET)
3) Incorporates soft-start function.
4) Incorporates thermal protection and ULVO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function
7) Employs small surface mount package : MSOP8
●Applications
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute maximum ratings
Parameter
VCC Voltage
Symbol
Ratings
VCC
PVCC Voltage
EN Voltage
V
-0.3~+7 *1
V
-0.3~+7
PVCC
Unit
*1
VEN
-0.3~+7
V
VSW,VITH
-0.3~+7
V
Pd1
387.5*2
mW
Power Dissipation 2
Pd2
*3
mW
Operating temperature range
Topr
-25~+85
℃
Tstg
-55~+150
℃
Tjmax
+150
℃
SW,ITH Voltage
Power Dissipation 1
Storage temperature range
Maximum junction temperature
*1
*2
*3
587.4
Pd should not be exceeded.
Derating in done 3.1mW/℃ for temperatures above Ta=25℃.
Derating in done 4.7mW/℃ for temperatures above Ta=25℃, Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB.
●Operating Conditions (Ta=25℃)
Parameter
Symbol
Limits
Min.
Typ.
Max.
Unit
VCC Voltage
VCC *4
4.0
5.0
5.5
V
PVCC Voltage
PVCC *4
4.0
5.0
5.5
V
-
VCC
V
0.8
A
2.5
V
VEN
0
SW average output current
Isw *4
-
Output voltage Setting Range
VOUT
1.0
EN Voltage
*4
-
Pd should not be exceeded.
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1/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Electrical characteristics
◎(Ta=25℃, VCC=5V, EN=VCC, R1=20kΩ, R2=10kΩ unless otherwise specified.)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Standby current
ISTB
0
10
Bias current
ICC
250
450
EN Low voltage
VENL
GND
0.8
EN High voltage
VENH
2.0
VCC
EN input current
IEN
1
10
Oscillation frequency
FOSC
0.8
1
1.2
Pch FET ON resistance
RONP
350
600
Nch FET ON resistance
RONN
250
500
ADJ voltage
VADJ
0.78
0.80
0.82
ITH SInk current
ITHSI
10
20
ITH Source Current
ITHSO
10
20
UVLO threshold voltage
VUVLO1
3.20
3.40
3.6
UVLO release voltage
VUVLO2
3.25
3.50
3.80
Soft start time
TSS
1.5
3
6
Timer latch time
TLATCH
0.5
2
3
●Block diagram, Application circuit
4
2.8±0.1
4.0±0.2
+6
-4
5
D 8 9
6
6
0.9Max.
0.75±0.05
0.08±0.05
0.475
Standby mode
Active mode
VEN=5V
PVCC=5V
PVCC=5V
VADJ=H
VADJ=L
VCC=4→0V
VCC=0→4V
VADJ=H
SCP/TSD operated
3
8
Current
Comp.
R Q
Gm Amp.
VCC
+0.05
0.145 -0.03
TSD
+0.05
0.22 -0.04
1
Pin name
ADJ
ITH
EN
GND
PGND
SW
PVCC
VCC
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ADJ
2
VCC
Input
PVCC
Current
Sense/
Protect
+
Output
6
SW
Driver
Logic
5
4
PGND
GND
ITH
Fig.2 BD8966FVM Block Diagram
Fig.1 BD8966FVM View
●Pin No. & function table
Pin No.
1
2
3
4
5
6
7
8
OSC
UVLO
Soft
Start
S
0.08 S
S
CLK
SLOPE
Lot No.
1PIN MARK
0.65
EN=GND
7
0.29±0.15
0.6±0.2
2.9±0.1
4
µA
µA
V
V
µA
MHz
mΩ
mΩ
V
µA
µA
V
V
ms
ms
VREF
Max3.25(include.BURR)
1
Conditions
VCC
EN
8
Unit
PIN function
Output voltage detect pin
GmAmp output pin/Connected phase compensation capacitor
Enable pin(Active High)
Ground
Nch FET source pin
Pch/Nch FET drain output pin
Pch FET source pin
VCC power supply input pin
2/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Characteristics data (Reference data)
2.0
1.0
0.5
0.0
1.5
1.0
VCC=5V
Ta=25℃
Io=0A
0.5
1
2
3
4
INPUT VOLTAGE:VCC[V]
5
0
1
Fig.3 Vcc-Vout
1.85
1.79
1.78
1.15
30
10
0
35
45
55 65
75
VCC=5V
Ta=25℃
10
100
OUTPUT CURRENT:IOUT[mA]
Fig.6 Ta-VOUT
EN VOLTAGE:VEN[V]
0.25
NMOS
0.15
0.10
VCC=5V
15
25 35
45
55
65
75
85
TEMPERATURE:Ta[℃]
Fig.9 Ta-RONN, RONP
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5
15
25 35
45 55
65 75
85
65
85
350
VCC=5V
1.4
1.2
1.0
0.8
0.6
300
250
200
150
100
50
0
0.0
5
0.90
-25 -15 -5
VCC=5V
0.2
0.00
-5
0.95
Fig.8 Ta-FOSC
0.4
-25 -15
1.00
TEMPERATURE:Ta[℃]
1.6
PMOS
0.05
1.05
1000
CIRCUIT CURRENT:I CC [μA]
0.35
0.20
1.10
0.85
2.0
1.8
3
VCC=5V
Fig.7 Efficiency
0.40
2
0.80
1
85
1
1.20
TEMPERATURE:Ta[℃]
ON [Ω]
0
Fig.5 Iout-Vout
40
1.75
25
VCC=5V
Ta=25℃
Fig.4 Ven-Vout
50
1.76
15
0.5
OUTPUT CURRENT:IOUT [A]
60
20
5
1.0
EN VOLTAGE:VEN[V]
70
1.77
-5
1.5
5
80
1.80
-25 -15
ON RESISTANCE:R
4
【VOUT=1.8V】
90
1.81
0.30
3
FREQUENCY:FOSC[MHz]
1.82
2
100
【VOUT=1.8V】
VCC=5V
Io=0A
EFFICIENCY:η[%]
OUTPUT VOLTAGE:VOUT[V]
1.83
【VOUT=1.8V】
0.0
0.0
0
1.84
OUTPUT VOLTAGE:VOUT[V]
1.5
2.0
【VOUT=1.8V】
【VOUT=1.8V】
Ta=25℃
Io=0A
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
2.0
-25 -15
-5
5
15
25
35
45
55 65
75
85
-25 -15
-5
5
15
25 35
45
55
TEMPERATURE:Ta[℃]
TEMPERATURE:Ta[℃]
Fig.10 Ta-VEN
Fig.11 Ta-ICC
3/14
75
2010.04 - Rev.B
Technical Note
BD8966FVM
1.2
FREQUENCY:FOSC[MHz]
【VOUT=1.8V】
VCC=PVCC
=EN
1.1
【PWM
VOUT=1.8V】
SW
1
VOUT
VOUT
0.9
VCC=5V
Ta=25℃
Io=0A
0.8
4
4.5
5
INPUT VOLTAGE:VCC[V]
VCC=5V
Ta=25℃
5.5
Fig.12 Vcc-Fosc
Fig.13 Soft start waveform
【VOUT=1.8V】
VOUT
Fig.14 SW waveform
【VOUT=1.8V】
VOUT
98mV
90mV
IOUT
IOUT
VCC=5V
Ta=25℃
Fig. 15 Transient response
Io=100→600mA(10µs)
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VCC=5V
Ta=25℃
Fig.16 Transient response
Io=600→100mA(10µs)
4/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Information on advantages
Advantage 1:Offers fast transient response with current mode control system.
Conventional product (Load response IO=0.1A→0.6A)
VOUT
BD8966FVM (Load response IO=0.1A→0.6A)
VOUT
110mV
IOUT
90mV
IOUT
Voltage drop due to sudden change in load was reduced .
Fig.17 Comparison of transient response
Advantage 2: Offers high efficiency with synchronous rectifier
100
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs
incorporated as power transistor.
90 【VOUT=1.5V】
EFFICIENCY:η[%]
80
ON resistance of P-channel MOS FET : 350mΩ(Typ.)
ON resistance of N-channel MOS FET : 250mΩ(Typ.)
70
60
50
40
30
VCC=5V
Ta=25℃
20
10
0
1
10
100
1000
OUTPUT CURRENT:IOUT[mA]
10000
Fig.18
Advantage 3:・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control:10μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 4.7μH inductor
Reduces a mounting area required.
VCC
15mm
Cin
CIN
RITH
DC/DC
Convertor
Controller
RITH
L
VOUT
L
10mm
CITH
Co
CO
CITH
Fig.19 Example application
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5/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Operation
BD8966FVM is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeats this operation.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
ITH
IL
Driver
Logic
S
VOUT
SW
Load
OSC
Fig.20 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
FB
SET
GND
RESET
GND
SW
GND
IL
IL(AVE)
VOUT
VOUT(AVE)
Fig.21 PWM switching timing chart
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6/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
300mV (Typ.) is provided to prevent output chattering.
Hysteresis 100mV
VCC
EN
VOUT
Tss
Tss
Tss
Soft start
Standby mode
Operating mode
Standby
mode
Operating mode
Standby
mode
UVLO
UVLO
Operating mode
EN
Standby mode
UVLO
Fig.22 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
at least 1 ms. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
EN
Output OFF
latch
VOUT
Limit
IL
1msec
Standby
mode
Standby
mode
Operating mode
Timer latch
EN
Operating mode
EN
Fig.23 Short-current protection circuit with time delay timing chart
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7/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET:PD(I R)
2) Gate charge/discharge dissipation:PD(Gate)
3) Switching dissipation:PD(SW)
4) ESR dissipation of capacitor:PD(ESR)
5) Operating current dissipation of IC:PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]:DC resistance of inductor, RON[Ω]:ON resistance of FET, IOUT[A]:Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]:Gate capacitance of FET, f[Hz]:Switching frequency, V[V]:Gate driving voltage of FET)
2
Vin ×CRSS×IOUT×f
3)PD(SW)=
(CRSS[F]:Reverse transfer capacitance of FET, IDRIVE[A]:Peak current of gate.)
IDRIVE
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]:Ripple current of capacitor、ESR[Ω]:Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]:Circuit current.)
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8/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
2
P=IOUT ×(RCOIL+RON)
RON=D×RONP+(1-D)RONN
1000
①using an IC alone
D:ON duty (=VOUT/VCC)
RCOIL:DC resistance of coil
RONP:ON resistance of P-channel MOS FET
RONN:ON resistance of N-channel MOS FET
IOUT:Output current
If VCC=5V, VOUT=1.5V, RCOIL=0.15Ω, RONP=0.35Ω, RONN=0.25Ω
IOUT=0.8A, for example,
D=VOUT/VCC=1.5/5=0.3
RON=0.3×0.35+(1-0.3)×0.25
=0.105+0.175
=0.28[Ω]
Power dissipation:Pd [mW]
θj-a=322.6℃/W
800
②mounted on glass epoxy PCB
θj-a=212.8℃/W
600
400
①587.4mW
②387.5mW
200
0
0
P =0.82×(0.15+0.28)
≒275.2[mW]
25
50
75 85 100
125
150
Fig. 24
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration
on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
●Selection of components externally connected
1. Selection of inductor (L)
IL
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
ΔIL
VCC
ΔIL=
(VCC-VOUT)×VOUT
[A]・・・(1)
L×VCC×f
Appropriate ripple current at output should be 30% more or less of
the maximum output current.
ΔIL=0.3×IOUTmax. [A]・・・(2)
IL
VOUT
L
Co
L=
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
Fig.25 Output ripple current
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases
efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5V, VOUT=1.5V, f=1MHz, ΔIL=0.3×0.8A=0.24A, for example,
L=
(5-1.5)×1.5
0.24×5×1M
=4.375μ → 4.7[μH]
* Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for
better efficiency.
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9/14
2010.04 - Rev.B
Technical Note
BD8966FVM
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
Output ripple voltage is determined by the equation (4):
VOUT
L
ΔVOUT=ΔIL×ESR [V]・・・(4)
ESR
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
Co
*Rating of the capacitor should be determined allowing sufficient margin
against output voltage. Less ESR allows reduction in output ripple voltage.
Fig.26 Output capacitor
As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be
determined with consideration on the requirements of equation (5):
Co≦
TSS×(Ilimit-IOUT)
・・・(5)
VOUT
Tss: Soft-start time
Ilimit: Over current detection level, 2A(Typ)
In case of BD8966FVM, for instance, and if VOUT=1.5V, IOUT=0.8A, and TSS=1ms,
Co≦
1m×(2-0.8)
1.5
≒800[μF]
Inappropriate capacitance may cause problem in startup. A 10 μF to 100 μF ceramic capacitor is recommended.
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage.
The ripple current IRMS is given by the equation (5):
Cin
VOUT
L
Co
IRMS=IOUT×
√VOUT(VCC-VOUT)
VCC
[A]・・・(5)
< Worst case > IRMS(max.)
When Vcc is twice the VOUT, IRMS=
Fig.27 Input capacitor
IOUT
2
If VCC=5.0V, VOUT=1.5V, and IOUTmax.=0.8A
IRMS=0.8×
√5(5-1.5)
5
=0.67[ARMS]
A low ESR 10µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
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10/14
2010.04 - Rev.B
Technical Note
BD8966FVM
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
A
Gain
[dB]
fp(Max.)
0
fz(ESR)
IOUTMin.
Phase
[deg]
IOUTMax.
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
0
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.28 Open loop gain characteristics
A
fz(Amp.)
Zero at power amplifier
Gain
[dB]
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
0
Phase
[deg]
[Hz] ←with heavier load
0
fz(Amp.)=
-90
1
2π×RITH×CITH
Fig.29 Error amp phase compensation characteristics
Cin
VCC
EN
VOUT
L
VCC,PVCC
SW
ESR
VOUT
ITH
VOUT
RO
CO
GND,PGND
RITH
CITH
Fig.30 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
=
1
2π×ROMax.×CO
5. Determination of output voltage
The output voltage VOUT is determined by the equation (7):
VOUT=(R2/R1+1)×VADJ・・・(7) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
(Adjustable output voltage range: 1.0V~2.5V)
Use 1 kΩ~100 kΩ resistor for R1. If a resistor of the resistance higher than
100 kΩ is used, check the assembled set carefully for ripple voltage etc.
4.7µH
Output
6
SW
10µF
R2
1
ADJ
R1
Fig.31 Determination of output voltage
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11/14
2010.04 - Rev.B
Technical Note
BD8966FVM
Cautions on PC Board layout
●BD8966FVM
VCC
1
2
3
RITH
③
CITH
4
ADJ
EN
VCC
PVCC
ITH
SW
GND
PGND
8
EN
7
L
6
①
VOUT
CIN
②
5
Co
GND
Fig.32 Layout diagram
For the sections drawn with heavy line, use thick conductor pattern as short as possible.
Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the
pin PGND.
③ Lay out CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring.
①
②
●Recommended Components Lists on Above Application
Symbol
Part
Value
L
Coil
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
CIN
CO
CITH
RITH
*
4.7µH
10µF
10µF
750pF
VOUT=1.0V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
VOUT=2.5V
Resistance
18kΩ
22kΩ
22kΩ
27kΩ
36kΩ
Manufacturer
Sumida
TDK
Kyocera
Kyocera
murata
ROHM
ROHM
ROHM
ROHM
ROHM
Series
CMD6D11B
VLF5014AT-4R7M1R1
CM316X5R106K10A
CM316X5R106K10A
GRM18series
MCR10 1802
MCR10 2202
MCR10 2202
MCR10 2702
MCR10 3602
The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on
your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when
employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these
margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a
schottky barrier diode established between the SW and PGND pins.
●I/O equivalence circuit
・EN pin
PVCC
・SW pin
PVCC
PVCC
EN
SW
・ADJ pin
・ITH pin
VCC
VCC
10kΩ
ITH
ADJ
Fig.33 I/O equivalence circuit
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12/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4.Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 34.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or
malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage
lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
P+
N
P+
P
N
Parasitic
element
N
P
+
P substrate
Parasitic element
GND
B
N
P+
P
N
C
E
Parasitic
element
P substrate
Parasitic element
GND
GND
GND
Other adjacent elements
Fig.34 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
9 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Note that use of a high DCR
inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified
period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF.
When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this
IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output
with EN after supply voltage is within operation range.
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© 2010 ROHM Co., Ltd. All rights reserved.
13/14
2010.04 - Rev.B
Technical Note
BD8966FVM
●Ordering part number
B
D
8
Part No.
9
6
6
Part No.
F
V
M
Package
FVM : MSOP8
-
T
R
Packaging and forming specification
TR: Embossed tape and reel
(MSOP8)
MSOP8
<Tape and Reel information>
2.8±0.1
4.0±0.2
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 −0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 −0.04
0.08 S
Direction of feed
0.65
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
14/14
∗ Order quantity needs to be multiple of the minimum quantity.
2010.04 - Rev.B
Notice
Notes
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The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
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While ROHM always makes efforts to enhance the quality and reliability of its Products, a
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Please be sure to implement in your equipment using the Products safety measures to guard
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R1010A