ROHM BD9111NV

Single-chip built-in FET type Switching Regulator Series
Output 2A or More High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9111NV
No.09027EAT32
●Description
ROHM’s high efficiency step-down switching regulator BD9111NV is a power supply designed to produce a low voltage
including 3.3 volts from 5 volts power supply line. Offers high efficiency with our original pulse skip control technology and
synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET)
TM
and SLLM (Simple Light Load Mode)
3) Incorporates soft-start function.
4) Incorporates thermal protection and ULVO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function
7) Employs small surface mount package : SON008V5060
●Use
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute Maximum Ratings (Ta=25℃)
Parameter
VCC Voltage
Symbol
Limits
VCC
PVCC Voltage
EN Voltage
SW,ITH Voltage
PVCC
Unit
-0.3～+7
*1
-0.3～+7
*1
VEN
-0.3～+7
V
V
V
VSW,VITH
-0.3～+7
V
Power Dissipation 1
Pd1
900*2
mW
Power Dissipation 2
Pd2
3900*3
mW
Operating temperature range
Topr
-25～+105
℃
Storage temperature range
Tstg
-55～+150
℃
Tjmax
+150
℃
Maximum junction temperature
*1
*2
*3
Pd should not be exceeded.
Derating in done 7.2mW/℃ for temperatures above Ta=25℃, Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB (the density of copper:3%)
Derating in done 31.2mW/℃ for temperatures above Ta=25℃, Mounted on JESD51-7.
●Operating Conditions (Ta=25℃)
Parameter
VCC Voltage
PVCC Voltage
EN Voltage
SW average output current
*4
Symbol
VCC *4
PVCC
*4
Limits
Typ.
Max.
4.5
5.0
5.5
V
4.5
5.0
5.5
V
0
-
VCC
V
-
-
2.0
A
VEN
Isw
Unit
Min.
*4
Pd should not be exceeded.
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1/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Electrical Characteristics
◎BD9111NV (Ta=25℃, VCC=PVCC=3.3V, EN=VCC.)
Parameter
Symbol
Standby current
ISTB
Bias current
ICC
EN Low voltage
VENL
EN High voltage
VENH
EN input current
IEN
Oscillation frequency
FOSC
Pch FET ON resistance
RONP
Nch FET ON resistance
RONN
Output voltage
VOUT
ITH SInk current
ITHSI
ITH Source Current
ITHSO
UVLO threshold voltage
VUVLO1
UVLO release voltage
VUVLO2
Soft start time
TSS
Timer latch time
TLATCH
Output Short circuit Threshold Voltage
VSCP
Min.
2.0
0.8
3.250
10
10
3.6
3.65
0.5
1
-
Typ.
0
250
GND
VCC
1
1
200
150
3.300
20
20
3.8
3.90
1
2
1.65
Max.
10
450
0.8
10
1.2
320
270
3.350
4.0
4.2
2
3
2.31
Unit
μA
μA
V
V
μA
MHz
mΩ
mΩ
V
μA
μA
V
V
ms
ms
VOUT
Conditions
EN=GND
Standby mode
Active mode
VEN=5V
PVCC=5V
PVCC=5V
VOUT=3.6V
VOUT=3.0V
VCC=5→0V
VCC=0→5V
SCP/TSD operated
VOUT=3.3→0V
●Block Diagram, Application Circuit
VCC
EN
8
2
VREF
Current
Comp
R Q
SLOPE
Gm Amp.
S
+
CLK
Driver
Logic
OSC
VOUT1
8
7
ITH 3
6 SW
GND 4
1
SW
5
PGND
4
GND
ITH
VOUT
RITH
Fig.1 BD9111NV TOP View
●Pin number and function
Pin No.
TSD
3
TOP View
CITH
Fig.2 BD9111NV Block Diagram
Pin name
PIN function
1
VOUT
2
VCC
VCC power supply input pin
3
ITH
GmAmp output pin/Connected phase compensation capacitor
4
GND
5
PGND
6
SW
7
PVCC
8
EN
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Output
22µF
SCP
5 PGND
2.2µH
6
22µF
UVLO
Soft
Start
PVCC
5V
Input
7
PVCC
VCC
EN
VCC 2
Current
Sense/
Protect
VCC
Output voltage pin
Ground
Nch FET source pin
Pch/Nch FET drain output pin
Pch FET source pin
Enable pin(Active High)
2/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Characteristics data
5.0
3.5
3.0
2.5
2.0
1.5
1.0
1.5
1.0
0.5
VCC=5V
Ta=25℃
Io=0A
0.5
0.0
0.0
0
1
2
3
4
INPUT VOLTAGE:VCC[V]
0
5
1
3.34
90
4
3.30
3.29
3.28
0.0
0
40
30
10
VCC=5V
Ta=25℃
50
75
1
100
10
100
1000
OUTPUT CURRENT:IOUT[mA]
TEMPERATURE:Ta[℃]
1.10
1.05
1.00
0.95
0.90
0.85
0
25
10000
0.80
-25
0.40
NMOS
0.10
1.4
1.2
1.0
0.8
0.6
0.4
0.05
-25
0
25
50
75
TEMPERATURE:Ta[℃]
100
Fig.9 Ta-RONN, RONP
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75
100
300
250
200
150
100
50
0.2
0.00
100
VCC=5V
CIRCUIT CURRENT:I CC [μA]
EN VOLTAGE:VEN[V]
PMOS
75
350
1.6
0.25
50
400
VCC=5V
1.8
0.30
25
Fig.8 Ta-FOSC
2.0
VCC=5V
0
TEMPERATURE:Ta[℃]
Fig.7 Efficiency
Fig. 6 Ta-VOUT
0.15
5
VCC=5V
1.15
50
3.26
0.20
2
3
4
OUTPUT CURRENT:IOUT [A]
1.20
60
20
0.35
1
Fig.5 Iout-Vout
70
3.27
0
VCC=5V
Ta=25℃
1.0
5
FREQUENCY:FOSC[MHz]
3.31
-25
2.0
80
VCC=5V
Io=0A
EFFICIENCY:η[%]
OUTPUT VOLTAGE:VOUT[V]
100
3.25
ON RESISTANCE:R ON [Ω]
3
3.0
Fig.4 Ven-Vout
3.35
3.32
2
4.0
EN VOLTAGE:VEN[V]
Fig.3 Vcc-Vout
3.33
OUTPUT VOLTAGE:VOUT[V]
4.0
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
5.0
2.0
Ta=25℃
Io=2A
4.5
0.0
0
-25
0
25
50
TEMPERATURE:Ta[℃]
Fig.10 Ta-VEN
3/13
75
100
-25
0
25
50
TEMPERATURE:Ta[℃]
Fig.11 Ta-ICC
2009.05 - Rev.A
Technical Note
BD9111NV
1.2
【SLLM control】
FREQUENCY:FOSC[MHz]
Ta=25℃
1.1
VCC=PVCC
=EN
SW
1msec
1
VOUT
VCC=5V
Ta=25℃
Io=0A
0.9
0.8
2.7
3.1
3.5
3.9
4.3
4.7
INPUT VOLTAGE:VCC [V]
5.1
VOUT
VCC=5V
Ta=25℃
5.5
Fig.12 Vcc-Fosc
Fig.13 Soft start waveform
Fig.14 SW waveform Io=10mA
【PWM control】
110mV
100mV
VOUT
VOUT
IOUT
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
Fig.15 SW waveform Io=200mAs
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Fig. 16 Transient response
Io=1A→2A(10μs)
4/13
IOUT
VCC=5V
Ta=25℃
Fig.17 Transient response
Io=2A→1A(10μs)
2009.05 - Rev.A
Technical Note
BD9111NV
●Information on advantages
Advantage 1：Offers fast transient response with current mode control system.
BD9111NV (Load response IO=1A→2A)
Conventional product (Load response IO=0.1A→0.6A)
VOUT
VOUT
100mV
160mV
IOUT
IOUT
Voltage drop due to sudden change in load was reduced by about 50%.
Fig.18 Comparison of transient response
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
100
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance
MOS FETs incorporated as power transistor.
Efficiency η[%]
SLLM
ON resistance of P-channel MOS FET : 200mΩ(Typ.)
ON resistance of N-channel MOS FET : 160mΩ(Typ.)
②
50
①
PWM
①inprovement by SLLM system
②improvement by synchronous rectifier
0
0.001
0.01
0.1
Output current Io[A]
1
Fig.19 Efficiency
Achieves efficiency improvement for heavier load.
Offers high efficiency for all load range with the improvements mentioned above.
Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 22μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor
(BD9111NV:Co=22μF, L=2.2μH)
Reduces a mounting area required.
VCC
15mm
Cin
CIN
RITH
DC/DC
Convertor
Controller
RITH
L
VOUT
L
10mm
CITH
Co
CO
CITH
Fig.20 Example application
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5/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Operation
BD9111NV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeat this operation.
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse
is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current
Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is
tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the
switching dissipation and improves the efficiency.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
ITH
IL
Driver
Logic
S
VOUT
SW
Load
OSC
Fig.21 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
PVCC
SENSE
Current
Comp
FB
SET
FB
GND
SET
GND
RESET
GND
RESET
GND
SW
GND
SW
IL
GND
IL(AVE)
IL
0A
VOUT
VOUT
VOUT(AVE)
VOUT(AVE)
Not switching
Fig.22 PWM switching timing chart
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Fig.23 SLLM
6/13
TM
switching timing chart
2009.05 - Rev.A
Technical Note
BD9111NV
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
100mV (Typ.) is provided to prevent output chattering.
Hysteresis 100mV
VCC
EN
VOUT
Tss
Tss
Tss
Soft start
Standby mode
Operating mode
Standby
mode
Standby
mode
Operating mode
UVLO
UVLO
Operating mode
Standby mode
EN
UVLO
Fig.24 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN
Output OFF
latch
Output Short circuit
Threshold Voltage
VOUT
IL Limit
IL
t1<TLATCH
Standby
mode
t2=TLATCH
Operating mode
Standby
mode
Timer latch
EN
Operating mode
EN
Fig.25 Short-current protection circuit with time delay timing chart
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7/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET：PD(I R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET,f[Hz]：Switching frequency,V[V]：Gate driving voltage of FET)
Vin2×CRSS×IOUT×f
3)PD(SW)=
(CRSS[F]：Reverse transfer capacitance of FET,IDRIVE[A]：Peak current of gate.)
IDRIVE
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor,ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
①3.9W
Power dissipation:Pd [W]
4.0
①for SON008V5060
JEDEC 4 layer board 76.2×114.3×1.6mm
θj-a=32.1℃/W
②for SON008V5060
ROHM standard 1 layer board 70×70×1.6mm
θj-a=138.9℃/W
③ IC only
θj-a=195.3℃/W
3.0
2
P=IOUT ×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
2.0
1.0
②0.90W
③0.64W
0
0
25
50
75
100105 125
150
Ambient temperature:Ta [℃]
Fig.26 Thermal derating curve
(SON008V5060)
If VCC=5V, VOUT=3.3V, RONP=0.2Ω, RONN=0.16Ω
IOUT=2A, for example,
D=VOUT/VCC=3.3/5.0=0.66
RON=0.66×0.20+(1-0.66)×0.16
=0.132+0.0544
=0.1864[Ω]
P=22×0.1864＝0.7456W]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater.
With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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8/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Selection of components externally connected
1. Selection of inductor (L)
IL
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
(VCC-VOUT)×VOUT
ΔIL=
[A]・・・(1)
L×VCC×f
ΔIL
VCC
IL
Appropriate ripple current at output should be 20% more or less of the
maximum output current.
VOUT
L
ΔIL=0.3×IOUTmax. [A]・・・(2)
Co
L=
Fig.27 Output ripple current
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5V, VOUT=3.3V, f=1MHz, ΔIL=0.3×2A=0.6A, for example,(BD9111NV)
L=
(5.0-3.3)×3.3
0.6×5.0×1M
=1.87μ → 2.2[μH]
* Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency.
2. Selection of output capacitor (CO)
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
VCC
Output ripple voltage is determined by the equation (4)：
VOUT
L
ESR
ΔVOUT=ΔIL×ESR [V]・・・(4)
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
Co
*Rating of the capacitor should be determined allowing sufficient margin
against output voltage. Less ESR allows reduction in output ripple voltage.
22μF to 100μF ceramic capacitor is recommended.
Fig.28 Output capacitor
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage.
The ripple current IRMS is given by the equation (5):
Cin
VOUT
L
Co
IRMS=IOUT×
√VOUT(VCC-VOUT)
VCC
[A]・・・(5)
< Worst case > IRMS(max.)
When Vcc is twice the VOUT, IRMS=
Fig.29 Input capacitor
IOUT
2
If VCC=5.0V, VOUT=3.3V, and IOUTmax.=2A, (BD9111NV)
IRMS=2×
√3.3(5.0-3.3)
5.0
=0.947[ARMS]
A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
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9/13
2009.05 - Rev.A
Technical Note
BD9111NV
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
A
Gain
[dB]
0
fz(ESR)
IOUTMin.
Phase
[deg]
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
fp(Max.)
IOUTMax.
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
0
-90
fp(Min.)=
1
2π×ROMax.×CO
[Hz]←with lighter load
fp(Max.)=
1
2π×ROMin.×CO
[Hz] ←with heavier load
Fig.30 Open loop gain characteristics
A
fz(Amp.)
Zero at power amplifier
Gain
[dB]
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
0
Phase
[deg]
0
-90
fz(Amp.)=
1
2π×RITH×CITH
Fig.31 Error amp phase compensation characteristics
VCC
Cin
EN
VOUT
VCC,PVCC
L
SW
VOUT
ESR
VOUT
ITH
GND,PGND
RO
CO
RITH
CITH
Fig.32 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
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=
1
2π×ROMax.×CO
10/13
2009.05 - Rev.A
Technical Note
BD9111NV
●BD9111NV
Cautions on PC Board layout
VCC
1
2
3
RITH
③
CITH
4
VOUT
EN
VCC
PVCC
ITH
SW
GND
PGND
8
EN
7
L
6
①
VOUT
CIN
②
5
Co
GND
Fig.33 Layout diagram
①For the sections drawn with heavy line, use thick conductor pattern as short as possible.
②Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to
the pin PGND.
③Lay out CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring.
※SON008V5060 (BD9111NV) has thermal FIN on the reverse of the package.
The package thermal performance may be enhanced by bonding the FIN to GND plane which take a large area of PCB.
●Recommended components Lists on above application
Symbol
Part
Value
L
Coil
2.2uH
CIN
Ceramic capacitor
22uF
CO
Ceramic capacitor
22uF
CITH
Ceramic capacitor
680pF
RITH
Resistance
12kΩ
Manufacturer
TDK
Kyocera
Kyocera
murata
Rohm
Series
LTF5022-2R2N3R2
CM32X5R226M10A
CM316B226M06A
MCH03Serise
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your
application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the
depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode
established between the SW and PGND pins.
●I/O equivalence circuit
・EN pin
PVCC
・SW pin
PVCC
PVCC
EN
SW
・ITH pin
・VOUT pin
VCC
VCC
10kΩ
ITH
VOUT
Fig.34 I/O equivalence circuit
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© 2009 ROHM Co., Ltd. All rights reserved.
11/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4.Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below.
This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 35.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side),
or GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
P
+
N
P+
P
N
Parasitic
element
N
P+
P substrate
Parasitic element
GND
B
N
P+
P
N
C
E
Parasitic
element
P substrate
Parasitic element
GND
GND
GND
Other adjacent elements
Fig.35 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
9 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Note that use of a high DCR
inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified
period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF.
When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this
IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output
with EN after supply voltage is within operation range.
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© 2009 ROHM Co., Ltd. All rights reserved.
12/13
2009.05 - Rev.A
Technical Note
BD9111NV
●Ordering part number
B
D
9
Part No.
1
1
1
N
Part No.
9111
V
-
Package
E
2
Packaging and forming specification
NV : SON008V5060
E2: Embossed tape and reel
(SON008V5060)
SON008V5060
<Tape and Reel information>
6.0 ± 0.15
5.0±0.15
4.2±0.1
1.27
2 3
4
0.59
8
7
5
2000pcs
Direction
of feed
S
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
3.6 ± 0.1
1
0.8 ± 0.1
C0.25
Embossed carrier tape
Quantity
(0.22)
0.08 S
+0.03
0.02 -0.02
1.0MAX
1PIN MARK
Tape
6
+0.05
0.4 -0.04
1pin
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
13/13
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
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use of such technical information.
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While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
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R0039A