TOSHIBA TC9496AF

TC9496AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9496AF
1 Chip Audio Digital Signal Processor
TC9496AF is the 1 chip audio DSP which built in 24-bits, a
22.5 MIPS DSP core, 3 ch AD converter, 5 ch DA converter, and
electronic volume for trims, and corresponds to a Multi-speaker
system.
It is possible to realize many application, such as sound field
control-hall simulation, for example-, digital filter for equalizers,
dynamic range control, KARAOKE and something.
Features
·
Incorporates 3 ch AD converter, 2 ch is 1 bit Σ-∆ type AD
converter for HiFi-Audio and 1 ch is 16 bit Multi-bit type AD
converter for Microphone.
Weight: 1.57 g (typ.)
2 ch HiFi-ADC (1 bitΣ-∆ type) S/N: 96dB (typ.)
1 ch Mic. ADC (16 bit Multi-bit type) S/N: 80dB (typ.)
·
Incorporates 1 bitΣ-∆ type DA converter, and the attenuator for trims is built in each DAC output. In case of the
use which does not use a trim, It is possible to output the analog signal of DAC directly.
5 ch DAC (1 bitΣ-∆ type) S/N: 96dB (typ.)
Attenuator for trim 0dB to −24dB (1dB step)
·
Each port has a digital input/output.
·
A built-in self-boot function automatically sets the coefficients and register values at initialization.
Moreover, four kinds of boot data can be chosen by pin setup.
Boot ROM: 1024 word × 18 bit
·
The DSP block specification are as follows:
Data bus: 24 bit
Multiplier/adder: 24 bit × 16 bit + 43 bit → 43 bit
Accumulator: 43 bit (sign extension: 4 bit)
Program ROM: 2048 word × 32 bit
Coefficient RAM: 448 word × 16 bit
Coefficient ROM: 256 word × 16 bit
Offset RAM: 64 word × 16 bit
Data RAM: 256 word × 24 bit
Operation speed: 44 ns (510-step (approx.) operation per cycle at fs = 44.1 kHz)
Interface buffer RAM: 32 word × 16 bit
·
Incorporates data delay RAM of 64 kbit.
·
The microcontroller interface can be selected between TOSHIBA original 3 line type and I2C bus format.
·
CMOS silicon structure supports high speed.
·
The package is a 100-pin flat package.
Delay RAM: 4096 word × 16 bit (64 kbit)
1
2002-01-11
Rch-IN
GNDX
VSAR
RIN
AVRR
VDR
VDL
AVRL
LIN
100
99
98
97
96
95
94
93
BOOT
1
ADC
(Rch)
ADC
(Lch)
ADC
(MIC)
Self
Boot
2
+5 V
3
4
256 fs
Timing
Gen.
XI
VSAL
BA0
XO
Lch-IN
BA1
VDX
92
I2CS
6
7
8
+5 V
9
ATT
DAC
(Lch)
SD
SD
DAC
(Rch)
SD
ATT
DAC
(Cch)
Decimation
Filter
ASP
(audio signal processor)
D-IN/OUT
ATT
DAC
(SLch)
SD
Interpolation
Filter
ATT
DAC
(SRch)
SD
Delay
RAM
4 k word ´ 16 bit
Timing
Gen.
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ATT
Moving average
filter
Unfolding
MCU
I/F
Lch-OUT
5
256 fs
GNDAL
GNDM
ERR
AOL
91
IFOK
AOLT
VRM2
IFDO
VRLR
90
IFDI
AILT
MOUT
CS
Rch-OUT
AIRT
89
IFCK
VDALR
MIN
GND
AORT
88
DOUT
AOR
VRM1
DIN
GNDAR
MIC-IN
EBCI
2
GNDAC
87
EBCO
Cch-OUT
AOC
VDM
ELRI
AOCT
86
ELRO
VRCS
TST3
SYNC
AICT
85
VDD
VRO
TST2
RESET
+5 V
VRI
84
STEP0
SLch-OUT
VDACS
TST1
STEP1
AISLT
83
EM1
AOSLT
TST0
EM0
AOSL
82
TP15
GNDASL
81
SRch-OUT
GNDASR
NC
TP14
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD
AOSR
(QFP 100 pin)
Top View
MCK
AOSRT
Block Diagram/Pin Connection
TP13
+5 V
AISRT
GND
VDASR
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
TP0
TP1
TP2
TP3
TP4
NC
VDDR
GNDR
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
FS
CKO0
CKO1
2002-01-11
TC9496AF
TC9496AF
Pin Function
Pin No.
Symbol
I/O
Function
1
XI
I
Crystal oscillator connecting or external clock input pin
2
XO
O
Crystal oscillator connecting pin
3
VDX
¾
Power pin for oscillator circuit
4
GNDAL
¾
Ground pin for DAC Left channel
5
AOL
O
DAC Left channel signal output pin
6
AOLT
O
DAC Left channel attenuator output pin
7
VRLR
¾
Reference voltage pin for DAC L/R channel
8
AILT
I
9
VDALR
¾
10
AIRT
I
DAC Right channel attenuator input pin
11
AORT
O
DAC Right channel attenuator output pin
12
AOR
O
DAC Right channel signal output pin
13
GNDAR
¾
Ground pin for DAC Right channel
14
GNDAC
¾
Ground pin for DAC Center channel
15
AOC
O
DAC Center channel signal output pin
16
AOCT
O
DAC Center channel attenuator output pin
17
VRCS
¾
Reference power pin for DAC C/SL/SR channel
18
AICT
I
DAC Center channel attenuator input pin
19
VRO
O
Reference voltage pin for attenuator (buffer output)
Reference voltage pin for attenuator (buffer input)
Remarks
DAC Left channel attenuator input pin
Power pin for DAC L/R channel
20
VRI
I
21
VDACS
¾
22
AISLT
I
DAC SL channel attenuator input pin
23
AOSLT
O
DAC SL channel attenuator output pin
24
AOSL
O
DAC SL channel signal output pin
25
GNDASL
¾
Ground pin for DAC SL channel
26
GNDASR
¾
Ground pin for DAC SR channel
27
AOSR
O
DAC SR channel signal output pin
28
AOSRT
O
DAC SR channel attenuator output pin
29
AISRT
I
DAC SR channel attenuator input pin
30
VDASR
¾
Power pin for DAC SR channel
31
NC
¾
Non-Connecting
32
TP0
O
Test pin 0
33
TP1
O
Test pin 1
34
TP2
O
Test pin 2
35
TP3
O
Test pin 3
36
TP4
O
Test pin 4
37
NC
¾
Non-Connecting
38
VDDR
¾
Power pin for delay RAM
39
GNDR
¾
Ground pin for delay RAM
40
TP5
O
Test pin 5
Power pin for DAC C/SL channel
Select the open state, VDD
connecting or GND
connecting
Select the open state, VDD
connecting or GND
connecting
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2002-01-11
TC9496AF
Pin No.
Symbol
I/O
Function
41
TP6
O
Test pin 6
42
TP7
O
Test pin 7
43
TP8
O
Test pin 8
44
TP9
O
Test pin 9
45
TP10
O
Test pin 10
46
TP11
O
Test pin 11
47
TP12
O
Test pin 12
48
FS
O
Clock out pin (sampling frequency)
49
CKO0
O
Clock output pin 0
50
CKO1
O
Clock output pin 1
51
GND
¾
Ground pin
52
TP13
O
Test pin 13
53
MCK
O
MCK clock output pin
54
VDD
¾
Power pin
55
TP14
O
Test pin 14
56
TP15
O
Test pin 15
57
EM0
I
De-emphasis setting pin 0
Schmitt input
58
EM1
I
De-emphasis setting pin 1
Schmitt input
59
STEP1
I
ASP execution step switching pin 1
Schmitt input
60
STEP0
I
ASP execution step switching pin 0
Schmitt input
61
RESET
I
Reset pin
Schmitt input
62
VDD
¾
Power pin
63
SYNC
I
Program synchronous signal input pin
Schmitt input
64
ELRO
I
LR clock input pin for serial data output (DOUT)
Schmitt input
65
ELRI
I
LR clock input pin for serial data input (DIN)
Schmitt input
66
EBCO
I
Bit clock input pin for serial data output (DOUT)
Schmitt input
67
EBCI
I
Bit clock input pin for serial data input (DIN)
Schmitt input
68
DIN
I
Serial data input pin
Schmitt input
69
DOUT
O
Serial data output pin
70
GND
¾
Ground pin
71
CS
I
Microcontroller interface chip select signal input pin
Schmitt input
72
IFCK
I
Microcontroller interface data shift clock signal input pin
Schmitt input
I
3 line bus mode: Microcontroller interface data input pin
73
IFDI
Schmitt input/
Open drain output
2
I/O
I C bus mode: Microcontroller interface data input/output pin
Remarks
74
IFDO
O
Microcontroller interface data output pin
75
IFOK
O
Microcontroller interface operation flag pin
Open drain output
76
ERR
O
Error flag output pin
Open drain output
2
77
I2CS
I
Microcontroller interface I C bus/3 line bus switching pin
78
BA1
I
Boot address setting pin 1
Schmitt input
79
BA0
I
Boot address setting pin 0
Schmitt input
80
BOOT
I
Self boot control pin
Schmitt input
81
NC
¾
Non-connecting
Select the open state, VDD
connecting or GND
connecting
82
TST0
I
Test pin T0
Schmitt input
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2002-01-11
TC9496AF
Pin No.
Symbol
I/O
Function
83
TST1
I
Test pin T1
Schmitt input
84
TST2
I
Test pin T2
Schmitt input
85
TST3
I
Test pin T3
Schmitt input
86
VDM
¾
Power pin for microphone ADC
87
VRM1
¾
Reference voltage pin 1 for microphone ADC
88
MIN
I
Microphone ADC amplifier input pin
89
MOUT
O
Microphone ADC amplifier output pin
90
VRM2
¾
Reference voltage pin 2 microphone ADC
91
GNDM
¾
Ground pin for microphone ADC
92
VSAL
¾
Ground pin for ADC L channel
93
LIN
I
ADC L channel signal input pin
94
AVRL
¾
Reference voltage pin for ADC L channel
95
VDL
¾
Power pin for ADC L channel
96
VDR
¾
Power pin for ADC R channel
97
AVRR
¾
Reference voltage pin for ADC R channel
98
RIN
I
99
VSAR
¾
Ground pin for ADC R channel
100
GNDX
¾
Ground pin for oscillator circuit
Remarks
ADC R ch signal input pin
5
2002-01-11
TC9496AF
Operation
1. Pin Operation
Pin No.
Symbol
1
XI
2
XO
3 to 30
Omitted
31
NC
32 to 36
Function
Connect the crystal oscillator.
¾
Non-connecting. Select the open state, VDD connecting or GND connecting.
TP0 to TP4 Test pin. (leave open)
37
NC
Non-connecting. Select the open state, VDD connecting or GND connecting.
38
VDDR
Power pin for delay RAM
39
GNDR
Ground pin for delay RAM
40 to 47
TP5 to
TP12
Test pin (leave open)
48
FS
Clock out pin (sampling frequency)
Timing output pins. The output frequency is set from the microcontroller (command-40h)
Command
(set the command-40h)
49
CKO0
50
CKO1
CKO0
Output
Frequency
Command
(set the command-40h)
CKO1
Output
Frequency
CKOS12
CKOS11
CKOS10
Fixed to L
0
0
0
Fixed to L
1
fs ´ 2
0
0
1
fs ´ 2
1
0
fs ´ 4
0
1
0
fs ´ 4
0
1
1
fs ´ 8
0
1
1
fs ´ 8
1
0
0
fs ´ 16
1
0
0
fs ´ 16
1
0
1
fs ´ 32
1
0
1
fs ´ 32
1
1
0
fs ´ 64
1
1
0
fs ´ 64
1
1
1
fs ´ 128
1
1
1
XI ´ 1/2
CKOS02
CKOS01
CKOS00
0
0
0
0
0
0
51
GND
Ground pin
52
TP13
Test pin (leave open)
Master clock output pin. Validated/Invalidated of an output, and the frequency is switched from in the of
microcontroller command (command-4Dh) and STEP1 pin (59 pin).
Command
(set the command-4Dh)
MCKE
53
MCK
Pin
MCKS
0
MCK Output
STEP1
(Note 1) (Note 1)
Fixed to L
1
0
(Note 1)
fs ´ 256
1
1
0
Source
oscillation (XI)
1
1
1
Prohibited
Note 1: Don’t care
54
VDD
55
TP14
56
TP15
Power pin
Test pin (leave open)
6
2002-01-11
TC9496AF
Pin No.
Symbol
Function
De-emphasis control pins
EM1
EM0
De-Emphasis Setting
57
EM0
0
0
De-emphasis off
58
EM1
0
1
fs = 48 kHz
1
0
fs = 44.1 kHz
1
1
fs = 32 kHz
Source oscillation frequency/ASP operation speed switching pins
59
STEP1
60
STEP0
61
RESET
62
VDD
63
SYNC
64
ELRO
STEP1
STEP0
Source
Oscillation
Frequency
No. of ASP Operation
Steps
0
0
fs ´ 512
340/fs
0
1
fs ´ 768
1
*
510/fs
Prohibited
Reset pin. L at initialization.
Power pin
Program operation SYNC signal input pin.
LR clock signal input pin for serial output data.
Valid when serial data are output in a slave operation (set the command-4Dh).
LR clock signal input pin for serial input data.
65
ELRI
Valid when serial data are input in a slave operation (set the command-4Dh).
Bit clock signal input pin for serial output data.
66
EBCO
Valid when serial data are output in a slave operation (set the command-4Dh).
Bit clock signal input pin for serial input data.
67
EBCI
Valid when serial data are input in a slave operation (set the command-4Dh).
Serial input data signal input pin. Connected to internal register in ASP block.
68
DIN
The internal register connected is set up by the microcomputer command (command-43h).
Serial input data signal input pin. Connected to internal register in ASP block.
69
DOUT
70
GND
The internal register connected is set up by the microcomputer command (command-43h).
Ground pin
7
2002-01-11
TC9496AF
Pin No.
Symbol
Function
Microcontroller interface pins.
I2CS
71
CS
72
IFCK
73
IFDI
74
IFDO
75
IFOK
76
ERR
77
I2CS
Transmission Mode
0
Standard Transmission mode
1
I C mode
2
2
Standard Transmission Mode
I C Mode
Chip select
Chip select (can be fixed to L)
IFCK
Transmit/receive clock
Transmit/receive clock
IFDI
Data or command input
Data input/output
IFDO
Data output (monitor mode)
Fixed to L output
ERR
Error flag signal output
Error flag signal output
IFOK
Internal operation confirmation
flag signal output
Internal operation confirmation flag
signal output
CS
Self-boot start address setting pins (at reset)
BA1
BA0
Start Address
78
BA1
0
0
000h
79
BA0
0
1
001h
1
0
002h
1
1
003h
Self-boot control pin
BOOT
80
Operation
BOOT
81
NC
82 to 85
TST0 to
TST3
86 to 100
Omitted
0
Does not Self-boot at reset
1
Self-boot at reset
Non-connecting. Select the open state, VDD connecting or GND connecting.
Test pin. Use fixed to L.
¾
8
2002-01-11
TC9496AF
2. Microcontroller interface
2.1
Standard Transmission Mode
When I2CS = L, data can be transmitted or received in Standard Transmission mode.
When the CS signal is Low, control from the microcontroller is enabled.
The IFCK signal is the transmit/receive clock, the IFDI signal is the data.
The TC9496AF loads the IFDI data on the IFCK signal rising edge.
When CS = H, the IFCK and IFDI signals are don’t care.
2.1.1 Setting Registers
CS
IFCK
IFDI
C7
Don’t care
IFOK
C5
C6
C3
C4
C1
C2
C0
D15 D13 D11 D9
D14 D12 D10 D8
D7
D5
D6
D3
D4
D1
D2
D0
Don’t care
Cn: COMMAND
Dn: Data
The registers are set by command data using IFDI signal.
The first byte is a command, which differs for each register. The data sent after that are fixed to
two bytes. Both command and data are sent starting from the MSB.
Data are loaded the rising edge of the IFCK signal. Note that commands or data that must be
switched, such as the RUN-MUTE command (command-44h) or the IFF flag, must be synchronized
with the SYNC signal and loaded on that signal.
9
2002-01-11
C0
C1
C2
C3
C4
C5
C6
C7
A14 A12 A10 A8
A15 A13 A11 A9
A0
A1
A2
A3
A4
A5
A6
A7
D14 D12 D10 D8
D15 D13 D11 D9
D0
D1
Cn: COMMAND
An: ADDRESS
Dn: Data
Don’t care
10
2002-01-11
The RAMs are set by command data using the IFDI signal.
The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written.
The length of the data field following the RAM address bytes is 2 ´ n bytes. The address is automatically incremented by 1.
During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal.
Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [s] per 1 word and it sets up, taking in of data is not
performed correctly.
At the time of program STOP, it is written in asynchronous.
Don’t care
IFOK
IFDI
IFCK
CS
2.1.2 Setting RAM (sequential)
TC9496AF
C0
C1
C2
C3
C4
C5
C6
C7
A14 A12 A10 A8
A15 A13 A11 A9
A0
A1
A2
A3
A4
A5
A6
A7
D14 D12 D10 D8
D15 D13 D11 D9
D0
D1
Cn: COMMAND
An: ADDRESS
Dn: Data
D0
D1
D2
D3
D4
D5
D6
D7
(1)
Don’t care
(2)
K4
K5
K3
+
K2
K1
K8
K7
K6
+
K10
K9
11
Write one by one･･
MCU-I/F
IFB-RAM
Update for 1 fs
CRAM
2002-01-11
In ACMP mode, the TC9496AF does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the
interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs.
For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same
applies to the K6 to K10 data.
Using ACMP mode can reduce the noise caused by updating coefficients while the TC9496AF is operating.
IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words.
< 32.
The length of the data field is 2 ´ n bytes, where n =
In ACMP mode, the IFOK pin outputs an ACMP operation end flag.
When ACMP operations complete, the flag is set to LOW ((1)) and is initialized at the next low chip select signal ((2)).
Operation at the time of transmitting other commands, before IFOK terminal was set to “L” level cannot be guaranteed.
Please set up again after initializing by RESET terminal or the initialization command.
Don’t care
IFOK
IFDI
IFCK
CS
2.1.3 Setting RAM (ACMP mode)
TC9496AF
C0
C1
C2
C3
C4
C5
C6
C7
(1)
D23
D21 D19 D17
D13 D11
D14 D12 D10
D15
D22 D20 D18 D16
D9
D0
Don’t care
Cn: COMMAND
Dn: DATA
D1
D2
D3
D4
D5
D6
D7
D8
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2002-01-11
Monitor mode is used to monitor the data bus or pointers.
There are two further modes: a mode where the data bus or pointer (s) is monitored at a present program counter (PC) and a mode where a loop counter (LC) is
added to monitor conditions in addition to PC. After the command is issued, when the TC9496AF loads data to the IFDO register (IFDOR), the IFOK pin signal
is set to LOW (see (1) above).
Next, when the IFCK signal is sent, the data are output on the IFCK signal falling edge starting from the MSB.
The data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. In cases where transfer must be interrupted, such as where only
eight or 16 bits of the MSB side are required, monitoring can be interrupted at any time by setting the CS signal to High, the IFOK signal also goes High.
IFOK
IFDO
Don’t care
IFDI
IFCK
CS
2.1.4 Monitor Mode
TC9496AF
TC9496AF
2.2
2
I C Bus Mode
When I2CS = H, data can be transmitted or received in I2C bus mode.
When the CS signal is Low, control from the microcontroller is enabled.
In I2C mode, the CS signal can be used fixed to L. The IFCK signal is the transmit/receive clock.
The IFDI signal is the data.
The TC9496AF loads the IFDI data on the IFCK signal rising edge.
When CS = H, IFCK and IFD signal are don’t care.
2.2.1 Setting Registers
start
32h
HZ
HZ
HZ
HZ
end
CS
IFCK
IFDI
(MCU ®)
A7
A5
A6
A3
A4
A1
A2 A0
C7
C5
C6
C3
C4
C1
C2
D15 D13 D11 D9
C0
D14 D12 D10 D8
D7
D5
D6
D3
D4
D1
D2
D0
IFCK
2
An: I C ADDRESS
Cn: COMMAND
Dn: Data
The register are set by command data using the IFDI signal.
The first byte after the I2C address (= 32h) is a command, which differs for each register. The data
sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C
format.
The data loaded internally every two bytes. Note that commands or data that must be switched on
the SYNC signal, such as the RUN command or the IFF flag, must be synchronized with the SYNC
signal and loaded on that signal.
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2002-01-11
A1
HZ
A2 A0
A3
32h
A4
A5
A6
A7
start
C0
C1
C2
C3
C4
C5
C6
C7
HZ
RA14 RA12 RA10 RA8
RA15 RA13 RA11 RA9
HZ
RA6 RA4 RA2 RA0
RA7 RA5 RA3 RA1
HZ
HZ
end
Cn: COMMAND
2
An: I C ADDRESS
RAn: RAM-ADDRESS
Dn: Data
D14 D12 D10 D8
D15 D13 D11 D9
HZ
14
2002-01-11
The RAMs are set by command data using the IFDI signal.
The first byte after the I2C address (= 32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM.
The length of the data field following the RAM address bytes is 2 ´ n bytes. The address is automatically incremented by 1.
During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal.
Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [s] per 1 word and it sets up, taking in of data is not
performed correctly.
At the time of program STOP, it is written in asynchronous.
IFCK
IFDI
(MCU ®)
IFCK
CS
2.2.2 Setting RAM (sequential)
TC9496AF
A1
A2 A0
A3
32h
A4
A5
A6
A7
start
HZ
C0
C1
C2
C3
C4
C5
C6
C7
HZ
RA14 RA12 RA10 RA8
RA15 RA13 RA11 RA9
HZ
RA6 RA4 RA2 RA0
RA7 RA5 RA3 RA1
HZ
2
HZ end
An: I C ADDRESS
Cn: COMMAND
RAn: RAM-ADDRESS
Dn: Data
D14 D12 D10 D8
D15 D13 D11 D9
HZ
(1)
A4
A1
HZ
(2)
A2 A0
A3
32h
K4
K5
K3
+
K2
K1
K8
K7
K6
+
K10
K9
15
Write one by one･･
MCU-I/F
IFB-RAM
Update for 1 fs
CRAM
2002-01-11
In ACMP mode, the TC9496AF does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the
interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs.
For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same
applies to the K6 to K10 data.
Using ACMP mode can reduce the noise caused by updating coefficients while the TC9496AF is operating.
IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words.
< 32.
The length of the data field is 2 ´ n bytes, where n =
In ACMP mode, the IFOK pin outputs an ACMP operation end flag.
When ACMP operations complete, the flag is set to LOW ((1)) and is initialized at the next low chip select signal ((2)).
Operation at the time of transmitting other commands, before IFOK terminal was set to “L” level cannot be guaranteed.
Please set up again after initializing by RESET terminal or the initialization command.
IFOK
IFDI
(MCU ®)
IFCK
CS
2.2.3 Setting RAM (ACMP mode)
TC9496AF
start
ID = 32h
COMMAND
(50h to 57h)
end
(1)
start
ID = 33h
end
16
2002-01-11
Monitor mode is used to monitor the data bus or pointers.
There are two further modes: a mode where the data bus or pointer (s) monitored at a preset program counter (PC) and a mode where a loop counter (LC) is
added to monitor conditions in addition to the PC. First, issue the monitoring command, which has no data.
When the TC9496AF loads data to the IFDO register (IFDOR), the IFOK pin signal is set to LOW (see (1) above).
Next, the I2C read command (ID = 33h) is issued, then when the IFCK signal is sent, the data are output on the IFCK signal falling edge from the MSB. The
data length is at its maximum (24 bits or three byte) during monitoring of the data bus.
Although it is possible per byte to read only 8 or 16 bits by the side of MSB, MCU has to make it the number of bytes which specified I2COS of command 4Bh
at that time.
After issuing a monitor command (50h to 56h), be sure to perform a continuous read operation by issuing the I2C read comman (ID = 33h).
IFDI
(TC9496AF ®)
IFOK
IFDI
(MCU ®)
IFCK
CS
2.2.4 Monitor Mode
TC9496AF
The IFOK signal has the following three functions.
IFOK Pin Description
Don’t care
8 clock
CRAM-ACMP
16 clock
16 clock
Update complete
Next Command
any command
IFOK
IFDO
IFDI
IFCK
CS
Example:
Don’t care
MON-DB
Internal register
loading end
17
data
16 clock
16 clock
any command
2002-01-11
When monitoring using the bus monitor command (command-50h), for example, after data are loaded to the internal register under the specified conditions,
the IFOK signal goes Low. In this mode, if CS signal is made into “H” level, IFOK signal will also be set to “H” level.
2.3.2 Loading End Flag Output in Monitor Mode
IFOK
IFDI
IFCK
CS
Example:
After the completion of a RAM data update with CRAM-ACMP (command-47h) or OFRAM-ACMP (command- 49h), the IFOK pin goes Low. Setting the CS
signal to Low changes the IFOK signal from Low to High.
2.3.1 ACMP Mode End Flag Output
2.3
TC9496AF
0%
100%
8 clock
Don’t care MUTE ON
MUTE
1 fs ´ 1024
(23 ms @ fs = 44.1 kHz)
16 clock
ATT
= 100%
16 clock
Next Command
MUTE OFF
MUTE
18
Note
At power on, the IFOK pin output is undefined. When the CS signal goes Low, the IFOK signal goes High.
ATT
IFOK
IFDI
IFCK
CS
1 fs ´ 1024
ATT
= 0%
2002-01-11
Next Command
any command
When using a command to control the DF block mute ON/OFF (command-44h, bit5), the mute end flag is output from the IFOK pin after the mute operation
completes.
Moreover, when the amount of attenuators by DF attenuator command (command-58h) is changed, IFOK terminal is set to “L” level as a flag which attenuator
operation completed.
2.3.3 Attenuator Operation End Flag Output of the Digital-Filter Section
TC9496AF
TC9496AF
3. Control Commands
The following table lists the control commands that can be used from the microcontroller.
3.1
Control Commands
Table 1
Command
Code
R/W
Control Commands
Description
RAM Sequential
Transfer Sync/
Async to SYNC Signal
TIMING
40h
Timing
¾
Async
BOOT
41h
Self Boot ROM start address
¾
Async
DAC-LR
42h
DAC output trim level (L, R)
¾
Async
SIO
43h
SIO setting
¾
Async
RUN-MUTE
44h
Program execution, mute
¾
Sync
MSEQ
45h
Sequential RAM
CRAM
46h
CRAM
CRAM-ACMP
47h
ORAM
48h
ORAM
ORAM-ACMP
49h
ORAM (ACMP mode)
IFF
4Ah
IFF setting
¾
Sync
MONI-PC
4Bh
Monitor: PC condition
¾
Async
MONI-LC
4Ch
Monitor: LC condition
¾
Async
MISC
4Dh
Others
¾
Async
4Eh
Prohibited
¾
¾
M-RST
4Fh
Initialization
¾
Async
MONI-DB
50h
DBUS monitor
¾
Async
MONI-CP
51h
CP monitor
¾
Async
MONI-OFP
52h
OFP monitor
¾
Async
MONI-DP
53h
DP monitor
¾
Async
MONI-AR
54h
AR monitor
¾
Async
MONI-CRP
55h
CRP monitor
¾
Async
MONI-SR
56h
SR monitor
¾
Async
DF-ATT
58h
DF attenuator level (all channel)
¾
Async
DAC-S
59h
DAC output trim level (SL, SR-ch)
¾
Async
DAC-C
5Ah
DAC output trim level (C-ch)
¾
Async
Sync: RUN/Async: STOP
¾
W
R
W
Enable
CRAM (ACMP mode)
Async
Sync: RUN/Async: STOP
Async
Note 2: The command which is “Sync” in the transfer Sync with Sync signal needs to set the CS = H section to a
minimum of 1 fs more until it transmits the follwing command. (It need more than 22.68 ms at fs = 44.1 KHz.)
19
2002-01-11
TC9496AF
3.2
Commands Description
Each command explanation is shown below. * mark in each command explanation table shows the
initial value at the time of reset.
Command-40h (0100 0000): TIMING
D15
D14
D13
SYPD SYD1
D12
SYD0 SYPA
D11
D10
D9
D8
D7
D6
SYA1
SYA0
SYPS
SYS1
SYS0
0
D5
D4
D3
Name
Description
Value
D15
SYPD
ASP digital block sync polarity
switching
0*
ASP program starts on falling edge
1
ASP program starts on rising edge
0*
Signal after SYNC output
1
SYNC pin
2
ELRI pin
3
ELRO pin
0*
DF-processing starts in a falling
1
DF-processing starts in a rising
0*
Signal after SYNC output
SYD
D13
[1:0]
D12
SYPA
D11
SYA
D10
[1:0]
D9
SYPS
D8
SYS
D7
[1:0]
D6
¾
ASP digital block SYNC signal
input switching
DF block sync polarity
switching
DF block SYNC signal input
switching
Overall system sync polarity
switching
SYNC circuit input signal
switching selection
Fixed to 0 (zero)
CKOS1
[2:0]
CKO1 (50 pin) pin output
selection
D3
SYNC pin
2
ELRI pin
3
ELRO pin
0*
Operates at polarity for SYPD, SYPA settings above.
1
Reverses all polarities for SYPD, SYPA settings above.
0*
Internal SYNC signal
1
SYNC pin
2
ELRI pin
3
ELRO pin
¾
CKOS0
D1
[2:0]
D0
CKO0 (49 pin) pin output
selection
¾
0*
Fixed to L output
1
fs2 (internal fs ´ 2)
2
fs4 (internal fs ´ 4)
3
fs8 (internal fs ´ 8)
4
fs16 (internal fs ´ 16)
5
fs32 (internal fs ´ 32)
6
fs64 (internal fs ´ 64)
7
Output XI divided by 2
0*
Fixed to L output
1
fs2 (internal fs ´ 2)
2
fs4 (internal fs ´ 4)
3
fs8 (internal fs ´ 8)
4
fs16 (internal fs ´ 16)
5
fs32 (internal fs ´ 32)
6
fs64 (internal fs ´ 64)
7
fs128 (internal fs ´ 128)
D2
D0
Operation
1
D5
D4
D1
CKOS CKOS CKOS CKOS CKOS CKOS
12
11
10
02
01
00
Bit
D14
D2
20
2002-01-11
TC9496AF
Command-41h (0100 0001): BOOT
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
BTA9
BTA8
BTA7
BTA6
BTA5
BTA4
BTA3
BTA2
BTA1
BTA0
D1
D0
ATTR
1
ATTR
0
Bit
Name
D9
to
D0
BTA
Description
Value
Self-boot ROM start address
[9:0]
Operation
000h
to
Starts self-boot operation from specified address
3FEh
Command-42h (0100 0010): DAC-LR
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
ATTL
4
ATTL
3
ATTL
2
ATTL
1
ATTL
0
0
0
0
ATTR
4
Bit
Name
D12
to
D8
ATTL
D4
to
D0
ATTR
[4:0]
[4:0]
Description
DAC L channel attenuator
value
DAC R channel attenuator
value
Value
00h
to
1Fh*
00h
to
1Fh*
D3
D2
ATTR ATTR
3
2
Operation
Code:
00h
01h
02h ･･･
18h 19h ･･･ 1Fh
ATT (dB):
0
-1
-2
-24 ca.-60
Initial value:
1Fh
Code:
00h
01h
02h ･･･
18h 19h ･･･ 1Fh
ATT (dB):
0
-1
-2
-24 ca.-60
Initial value:
1Fh
21
ca.-60
1Fh
ca.-60
2002-01-11
TC9496AF
Command-43h (0100 0011): SIO
D15
D14
CHSI
0
D13
D11
D10
D9
D8
Name
D15
CHSI
D14
¾
Description
Serial input (SI) switching
Fixed to 0 (zero)
ISLT
D11
[1:0]
IBCS
D6
D5
CHSO CHSO OSLT
1
0
1
Value
D4
D3
D2
D1
D0
OSLT OBCS OBCS OFMT OFMT
0
1
0
1
0
Operation
0*
SI0 register ¬ ADC, SI1 register ¬ DIN pin
1
SI1 register ¬ ADC, SI0 register ¬ DIN pin
¾
¾
0*
16 slots (bit clock = 32 fs)
1
20 slots (bit clock = 40 fs)
2
24 slots (bit clock = 48 fs)
3
32 slots (bit clock = 64 fs)
0*
16 bits
1
18 bits
2
20 bits
3
24 bits
0*
Pads from the beginning
1
Pads from the end
Number of serial input slots
D12
D7
ISLT1 ISLT0 IBCS1 IBCS0 IFMT1 IFMT0
Bit
D13
D12
Serial input bit length
D10
D9
[1:0]
IFMT
Serial input format
D8
[1:0]
2
I2S format
3
D7
CHSO
D6
[1:0]
0
DOUT pin ¬ SO0 register
1
DOUT pin ¬ SO1 register
Serial output (SO) switching
2*
3
D5
OSLT
0*
16 slots (bit clock = 32 fs)
1
20 slots (bit clock = 40 fs)
2
24 slots (bit clock = 48 fs)
3
32 slots (bit clock = 64 fs)
0*
16 bits
1
18 bits
2
20 bits
3
24 bits
0*
Pads from the beginning
1
Pads from the end
Number of serial output slots
D4
D3
[1:0]
OBCS
DOUT pin ¬ SO2 register
Serial output bit length
D2
D1
[1:0]
OFMT
Serial output format
D0
[1:0]
2
I2S format
3
22
2002-01-11
TC9496AF
Command-44h (0100 0100): RUN-MUTE
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
0
0
0
0
0
0
0
RUN
MADOFF
DFMUTE
0
IMUTE
Bit
Name
D15
to
D8
¾
D7
RUN
D6
D5
MADOFF
DFMUTE
D4
¾
D3
IMUTE
D2
D1
D0
Description
Fixed to 0 (zero)
Value
Operation
¾
¾
0*
Stops program
1
Runs program
0*
Microphone ADC ON
1
Microphone ADC OFF
0
Mute OFF
1*
Mute ON
D2
D1
D0
OMUTE OMUTE OMUTE
2
1
0
ASP program execution
Microphone ADC OFF
DF block mute
Fixed to 0 (zero)
¾
¾
ASP block input mute
0
Mute OFF
(SI0, SI1 register mute)
1*
Mute ON
ASP block output mute
0
Mute OFF
(SO2 register mute)
1*
Mute ON
ASP block output mute
0
Mute OFF
(SO1 register mute)
1*
Mute ON
ASP block output mute
0
Mute OFF
(SO0 register mute)
1*
Mute ON
OMUTE2
OMUTE1
OMUTE0
23
2002-01-11
TC9496AF
Command-45h (0100 0101): MSEQ
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
D3
to
D0
MSA
Description
Value
Module sequential RAM first
address
[3:0]
D15
D14
D13
D12
D11
0
0
0
0
0
Bit
Name
D10
to
D0
MSEQ
D10
D9
D2
D1
D0
MSA3 MSA2 MSA1 MSA0
Operation
The address of the head to write in is set up.
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ
10
9
8
7
6
5
4
3
2
1
0
Description
Module sequential RAM data
[10:0]
0h
to
Fh
D3
Value
Operation
000h
The data written in module sequence RAM are set up. (PC value
to
at the time of SQRET)
7FFh
Data are sent continuously after transmitting the module sequence RAM head address (2 bytes).
Enable a sequential write to RAM.
45h-MSEQ RAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
(module sequential RAM: 16 words)
24
2002-01-11
TC9496AF
Command-46h (0100 0110): CRAM
D15
D14
D13
D12
D11
D10
0
0
0
0
0
0
D9
Name
Description
D9
to
D0
CRAMA
CRAM (coefficient RAM) head
address
D15
D14
D13
D12
D11
D10
D7
D6
D5
D4
D3
D2
D1
CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA
9
8
7
6
5
4
3
2
1
Bit
[9:0]
D8
Value
D9
D0
CRAMA
0
Operation
000h
CRAM address of the head at the time of writing in by 46h
to
command is set up.
1BFh
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
D15
to
D0
CRAMD
Value
Operation
7FFFh
to
Set CRAM data (two-complement-form formula)
8000h
CRAM data
[15:0]
The data written in continuously are sent after transmitting CRAM head address (2 bytes).
Enable a sequential write to RAM.
46h-CRAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
Command-47h (0100 0111): CRAM-ACMP
D15
D14
D13
D12
D11
D10
0
0
0
0
0
0
Bit
Name
D9
to
D0
CRAMA
D15
D13
Description
D12
D11
D10
D8
D7
D6
D5
D4
D3
D2
D1
CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA
9
8
7
6
5
4
3
2
1
Value
D0
CRAMA
0
Operation
000h
CRAM address of the head at the time of writing in by 47h
to
command is set up.
1BFh
CRAM first address
[9:0]
D14
D9
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
D15
to
D0
CRAMD
Description
CRAM data
[15:0]
Value
Operation
7FFFh
to
Set CRAM data (two-complement-form formula)
8000h
It is CRAM write-in command which used the address compare mode. A maximum of 32 words is
written at once.
The data written in continuously are sent after transmitting CRAM head address (2 bytes).
Enable a sequential write to RAM.
47h-CRAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
25
2002-01-11
TC9496AF
Command-48h (0100 1000): ORAM
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
0
0
0
0
0
0
0
0
0
0
Bit
Name
D5
to
D0
ORAMA
D15
Description
00h
to
3Fh
[5:0]
D13
D12
D11
D10
D9
D4
D3
D2
D1
D0
ORAMA ORAMA ORAMA ORAMA ORAMA ORAMA
5
4
3
2
1
0
Value
ORAM first address
D14
D5
Operation
ORAM address of the head at the time of writing in by 48h
command is set up.
D8
D7
D6
D5
D4
D3
D2
D1
D0
ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
D15
to
D0
ORAMD
Value
Operation
7FFFh
to
0000h
ORAM data
[15:0]
Set ORAM data
The data written in continuously are sent after transmitting ORAM head address (2 bytes).
Enable a sequential write to RAM.
48h-ORAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
(ORAM: 64 word)
Command-49h (0100 1001): ORAM-ACMP
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
0
0
0
0
0
0
0
0
0
0
Bit
Name
D5
to
D0
ORAMA
D15
00h
to
3Fh
D13
D12
D11
D10
D9
D4
D3
D2
D1
D0
ORAMA ORAMA ORAMA ORAMA ORAMA ORAMA
5
4
3
2
1
0
Value
ORAM first address
[5:0]
D14
Description
D5
Operation
ORAM address of the head at the time of writing in by 49h
command is set up.
D8
D7
D6
D5
D4
D3
D2
D1
D0
ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
D15
to
D0
ORAMD
Description
ORAM Data
[15:0]
Value
7FFFh
to
0000h
Operation
Set ORAM data (two-complement-form formula)
It is ORAM write-in command which used the address compare mode. A maximum of 32 words is
written at once.
The data written in continuously are sent after transmitting ORAM head address (2 bytes)
Enable a sequential write to RAM.
49h-ORAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
(ORAM: 64 word)
26
2002-01-11
TC9496AF
Command-4Ah (0100 1010): IFF
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
IFF2
IFF1
IFF0
D2
D1
D0
Bit
Name
Description
Value
Operation
D2
to
D1
IFF
Set IFFn
0*
IFFn = 0
[2:0]
n = 2, 1, 0
1
IFFn = 1
Command-4Bh (0100 1011): MONI-PC
D15
D14
D13
D12
D11
D10
0
0
0
MPC
10
I2COS I2COS
1
0
Bit
Name
D15
to
D14
I2COS
D9
D8
D7
D6
D5
D4
D3
MPC9 MPC8 MPC7 MPC6 MPC5 MPC4 MPC3 MPC2 MPC1 MPC0
Description
Value
Operation
2
Monitor data length in I C
mode
[2:0]
D13
to
D11
¾
D10
to
D0
2h
1h, 0h
Byte: 3 byte
2 byte
1 byte
¾
000h
Set the Program Counter (PC) conditions (PC value) when
to
carrying out a monitor by command-50h to 56h.
7FFh
Monitor condition
(command-50h to 56h)
[10:0]
Code: 3h
¾
Fixed to 0 (zero)
MPC
Set the data byte length when monitoring in I C mode.
0h
to
3h
2
Command-4Ch (0100 1100): MONI-LC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
LCE
LCS
LCDE
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
Bit
Name
D15
to
D11
¾
D10
LCE
D9
D8
D7
to
D0
LCS
LCDE
LCD
[7:0]
Description
Value
Operation
Fixed to 0 (zero)
¾
¾
Whether LC (loop counter)
value applied to monitor
conditions or not.
0*
Does not add LC value to the conditions.
1
Adds LC value to the condition.
0
Compares with LC0 value.
1
Compares with LC1 value.
0
After a match, does not change the value to be compared with
the LC.
1
After a match, automatically decrements by -1 the value to be
compared with the LC.
00h
to
FFh
Set the LC conditions (loop counter value) when carrying out a
monitor by command-50h to 56h.
LC selection
Automatic LC decrement
Value in comparison with the
loop counter when carrying out
a monitor
27
2002-01-11
TC9496AF
Command-4Dh (0100 1101): MISC
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
0
0
0
0
SIS
SOS
ERDET
ZST
Bit
Name
D15
to
D11
¾
D10
SIS
D9
D8
D3
D2
D1
D4
D3
D2
D1
DP7F SYRC SYRO MCKE MCKS DLSEP
Value
Operation
¾
¾
0*
Master (synchronized with the internal clock)
1
Slave (synchronized with the external clock (ELRI, EBCI))
0*
Master (synchronized with the internal clock)
1
Slave (synchronized with the external clock (ELRO, EBCO))
D0
0
Serial output
0
Invalid
1*
Valid
0
2-cycle access
1*
1-cycle access
0*
256 word
1
128 word
0
Does not reset
1*
Reset
0
Does not reset
1*
Reset
0
Disable (fixed to L)
1*
Enable (output )
0
256 fs
1*
Source oscillation
Error detection
Switches to access CROM
using Log-Linear adjustment
ZST
128/256 word of DRAM (DATA
RAM) switching
DP7F
SYRC
Set CP at each SYNC
SYRO
Set OFP at each SYNC
MCKE
MCK pin output enable
MCKS
MCK pin output switching
DLSEP
¾
D0
D5
Serial Input
ERDET
D6
D4
Fixed to 0 (zero)
SOS
D7
D5
Description
D6
Delay RAM table area
switching
0
Does not use table
1*
Use 2-k word area as the table
Fixed to 0 (zero)
¾
¾
Command-4Fh (0100 1111): M-RST
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MRST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
D15
MRST
D14
to
D0
¾
Description
Value
Operation
Initialization from the micro
controller command
0*
Does not initialize
1
Initializes (set to initial value.)
Fixed to 0 (zero)
¾
¾
28
2002-01-11
TC9496AF
Command-50h (0101 0000): MON-DB
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
DB
23
DB
22
DB
21
DB
20
DB
19
DB
18
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Bit
Name
O23
to
O0
DB
Description
Value
Operation
000000h
to
Reads data bus on the condition: Command-4Bh, 4Ch
FFFFFFh
Data bus monitor
[23:0]
Command-51h (0101 0001): MON-CP
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CP
7
CP
6
CP
5
CP
4
CP
3
CP
2
CP
1
CP
0
O1
O0
Bit
Name
O23
to
O9
¾
Fixed to 0 (zero)
CP
CP monitor
(coefficient RAM pointer)
O8
to
O0
[8:0]
Description
Value
Operation
¾
¾
000000h
to
Reads CP on the condition: Command-4Bh, 4Ch
0001BFh
Command-52h (0101 0010): MON-OFP
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O9
O8
O7
O6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
O23
to
O6
¾
O5
to
O0
OFP
[5:0]
Description
Fixed to 0 (zero)
OFP monitor
(offset RAM pointer)
O5
O4
O3
O2
QFP QFP QFP QFP QFP QFP
5
4
3
2
1
0
Value
Operation
¾
¾
000000h
to
Reads OFP on the condition: Command-4Bh, 4Ch
00003Fh
29
2002-01-11
TC9496AF
Command-53h (0101 0011): MON-DP
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP
7
DP
6
DP
5
DP
4
DP
3
DP
2
DP
1
DP
0
Bit
Name
O23
to
O8
¾
Fixed to 0 (zero)
DP
DP monitor
(data RAM pointer)
O7
to
O0
[7:0]
Description
Value
Operation
¾
¾
000000h
to
Reads DP on the condition: Command-4Bh, 4Ch
0000FFh
Selection (DP0/DP1/DP2/DP3) of DP is DP chosen by command executed at the time of PC set up as
conditions.
Command-54h (0101 0100): MON-AR
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
0
0
0
0
0
0
0
0
0
0
0
0
AR
11
AR
10
AR
9
AR
8
AR
7
AR
6
AR
5
AR
4
AR
3
AR
2
AR
1
AR
0
Bit
Name
O23
to
O12
¾
Fixed to 0 (zero)
AR
AR monitor
(delay RAM address)
O11
to
O0
[11:0]
Description
Value
Operation
¾
¾
000000h
Reads delay RAM address on the condition: Command-4Bh,
to
4Ch
000FFFh
Command-55h (0101 0101): MON-CRP
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
O23
to
O9
¾
Fixed to 0 (zero)
CRP
CRP monitor
(CROM pointer)
O8
to
O0
[8:0]
Description
O8
O7
O6
O5
O4
O3
O2
O1
O0
CRP CRP CRP CRP CRP CRP CRP CRP CRP
8
7
6
5
4
3
2
1
0
Value
Operation
¾
¾
000000h
to
Reads CRP on the condition: Command-4Bh, 4Ch
0001FFh
30
2002-01-11
TC9496AF
Command-56h (0101 0110): MON-SR
O
23
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O2
O1
O0
0
0
0
0
0
0
0
0
0
LRF
GF
3
GF
2
GF
1
GF LI LG OV OV RD RD
V1F V0F
0 -LG -LI -1E -0E -23 -16
ZF
SF
Bit
Name
O23
to
O15
¾
O14
to
O0
SR
Description
Fixed to 0 (zero)
SR monitor
O8
O7
O6
O5
Value
Operation
¾
¾
¾
(status register)
O9
O4
O3
Reads SR on the condition: Command-4Bh, 4Ch
Command-58h (0101 1000): DF-ATT
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Bit
Name
Description
Value
Operation
Initial value: 7Fh (level = 0dB)
LEVEL = 20 ´ log (ATL/128)
D6
to
D0
ATL
DF attenuator value
[6:0]
00h
to
7Fh*
31
Code
Level
7Fh
0.00dB
7Eh
-0.14dB
7Dh
-0.21dB
~
~
72h
-1.01dB
65h
-2.06dB
5Ah
-3.06dB
~
~
40h
-6.02dB
~
~
02h
-36.12dB
01h
-42.14dB
00h
-¥dB
2002-01-11
TC9496AF
Command-59h (0101 1001): DAC-S
D15
D14
D13
0
0
0
Bit
Name
D12
to
D8
ATTSL
D4
to
D0
ATTSR
D12
D11
D10
D9
D8
ATTSL ATTSL ATTSL ATTSL ATTSL
4
3
2
1
0
Description
D7
D6
D5
0
0
0
D4
00h
to
1Fh*
[4:0]
DAC SR-ch attenuator value
[4:0]
00h
to
1Fh*
D2
D1
D0
ATTSR ATTSR ATTSR ATTSR ATTSR
4
3
2
1
0
Value
DAC SL-ch attenuator value
D3
Operation
Code:
00h
01h
02h ･･･
18h 19h ･･･ 1Fh
ATT (dB):
0
-1
-2
-24 ca.-60
Initial value:
1Fh
Code:
00h
01h
02h ･･･
18h 19h ･･･ 1Fh
ATT (dB):
0
-1
-2
-24 ca.-60
Initial value:
1Fh
ca.-60
ca.-60
Command-5Ah (0101 1010): DAC-C
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
0
0
0
0
0
0
0
ATTC
4
Bit
Name
D4
to
D0
ATTC
Description
DAC C-ch attenuator value
[4:0]
Value
00h
to
1Fh*
D3
D2
ATTC ATTC
3
2
D1
D0
ATTC
1
ATTC
0
Operation
Code:
00h
01h
02h ･･･
18h 19h ･･･ 1Fh
ATT (dB):
0
-1
-2
-24 ca.-60
Initial value:
1Fh
32
ca.-60
2002-01-11
TC9496AF
4. Self-Boot Function Description
4.1
Self-Boot Function
The TC9496AF supports a self-boot function for setting coefficients and offsets.
As Figure 1 shows, the data are set via the microcontroller interface circuit.
First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various
modes to be set later. The microcontroller interface circuit supports two format: I2C and the original
mode. However, the boot must be executed in Standard Transmission.
All the command inputs from the exterior are disregarded during a boot term.
RESET
BOOT
BA1
Self-boot circuit
Microcontroller interface circuit
SBROM
Timing
(1024 word
´ 18 bit)
gener
-ator
BTCSN
BTIFCK
BTIFDI
CS
IFCK
IFDI
BTMODE
1
0
Internal
CSN
BA0
Figure 1
1
0
Internal
IFCK
1
0
Internal
IFDI
Internal
I2CS
I2CS
Self-Boot System
33
2002-01-11
TC9496AF
4.2
Boot ROM Format
The following shows the brake down of the 18 bits.
00
Data that are being sent
01
Command
10
Final data (after the data are sent, the CS signal is set to "H").
11
Jump address (jump to any address in the self-boot ROM).
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
(MSB)
(LSB)
000h
11
Address
JMP
001h
11
Address
JMP
002h
11
Address
JMP
003h
11
Address
JMP
004h
01
005h
10
006h
01
007h
00
Data
Data (cont)
008h
00
Data
Data (cont)
009h
00
Data
Data (cont)
00Ah
00
Data
Data (cont)
00Bh
10
Data
Data (last)
00Ch
11
Address
JMP 3FFh
3FFh
11
Address
JMP 3FFh
CMD
Data
Data (last)
CMD
Figure 2
CMD
CMD
Boot ROM Format and Example
Note 3: Boot mode completes when the address reaches 3FFh, the maximum value.
Therefore, for the final address, write JMP 3FFh (data = 303FFh).
34
2002-01-11
TC9496AF
4.3
Self-Boot Operation
Self-boot operations support two modes: one for use at reset and for setting the microcontroller. The
modes can be used in combination.
Table 1
4.3.1 Self-Boot Operation
To enter this mode, set the Boot pin to
High, then set the RESET pin to Low
or send initialized command.
The 2048 fs period (46.4 ms when fs =
44.1 kHz) after a reset release is wait
period. The boot operation starts at the
end of this period.
When switching the setting according
to application, specify the start address
using the BA [1:0] pin. At addresses
000h to 002h, set jump addresses.
fs
Wait Period
Boot Time (max.)
32 kHz
64.0 ms
32.0 ms
44.1 kHz
46.4 ms
23.2 ms
48 kHz
42.7 ms
21.3 ms
Table 2
The data setting speed is one of
SBROM per 1 fs. As up to 1024 words
can be set in the SBROM, the maximum
time required for setting the data is the
1024 fs period.
35
Relationship between fs and
Wait Period
Relationship between BA [1:0]
Pin Value and Start Address
BA1
BA2
Start Address
0
0
000h
0
1
001h
1
0
002h
1
1
003h
2002-01-11
TC9496AF
4.3.2 Self-Boot Operation when Setting Microcontroller
In this mode, the microcontoroller can specify any address and the boot operation starts from that
address.
The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the
BOOT command (command: 41h) from the microcontroller starts the boot operation with no wait. The
boot operation when set from the microcontroler is the same as the self-boot operation at reset except
that the boot operation can start from any address.
Boot wait period
2048 fs
Boot time
1024 fs (max)
/RST
FS
Fixed to “H”
BOOT
BTMODE
(internal signal)
BA [1:0]
2
BootRom Adrs
2
Rom Dt [17:16]
JMP
10 11 12 13 14 15 16
CMD
DT DT DE
CMD
DE
CMD
D
C
D
3FF
JMP
JMP
BTCSN
BTIFCK
BTIFDI
C
D
D
C
DT: Data
DE: DataEnd
8 clock
C
Figure 3
Table 3
Boot Timing Chart (at reset)
Differences Depending on Operation Mode
Parameter
RESET Pin or Initialized Command
BOOT Command
Boot Wait Period
Yes
No
Boot Start Address
Select from 000h to 003h with BA0 and BA1
terminal
Any address specified from microcontroller
BOOT pin
“H” Level
Any (don’t care)
36
2002-01-11
TC9496AF
4.4
Programming Examples
The following shows the programming example in Self-boot mode.
000: 30040h
jmp 040h
; Jump to 040h
001: 30100h
jmp 100h
; Jump to 100h
002: 30200h
jmp 200h
; Jump to 200h
003: 30004h
jmp 004h
; Jump to 004h
004: 10040h
cmd 40h
; Command 40h (TIMING)
005: 28007h
data 8007h
; CKOS0 = 7 (fs128 output)
006: 10043h
cmd 43h
; Command 43h (SIO)
007: 20039h
date 0039h
; CHSO = 0 (SO0), OSLT = 3 (32 bit), OBCS = 2 (20 bit),
OFMT = 1 (padded from the end)
008: 10045h
cmd 45h
; Command 45h (MSEQ)
009: 00000h
data 0000h
; Start address = 0h
00A: 00001h
data 0001h
; MSEQ [0] = 001h
00B: 00123h
data 0123h
; MSEQ [1] = 123h
00C: 20320h
data 0320h
; MSEQ [2] = 320h
00D: 30300h
jmp 300h
; Jump to 300h
:
100: 10046h
cmd 46h
; Command 46h (CRAM)
101: 00000h
data 0000h
; Start address = 0h
102: 00000h
data 0000h
; CRAM [0] = 0000h
103: 00000h
data 0000h
; CRAM [1] = 0000h
104: 00000h
data 0000h
; CRAM [2] = 0000h
105: 20000h
data 0000h
; CRAM [3] = 0000h
106: 30380h
jmp 380h
; Jump to 380h
:
300: 10046h
cmd 46h
; Command 46h (CRAM)
301: 00000h
date 0000h
; Start address = 0h
302: 07FFFh
data 7FFFh
; CRAM [0] = 7FFFh
303: 08000h
data 8000h
; CRAM [1] = 8000h
304: 03FFFh
data 3FFFh
; CRAM [2] = 3FFFh
305: 24000h
data 4000h
; CRAM [3] = 4000h
306: 30380h
jmp 380h
; Jump to 380h
:
380: 10046h
cmd 46h
; Command 46h (CRAM)
381: 00080h
data 0080h
; Start address = 80h
382: 0FFFEh
data FFFEh
; CRAM [80h] = FFFEh
383: 2FFFFh
data FFFFh
; CRAM [81h] = FFFFh
384: 303FFh
jmp 3FFh
; Jump to 3FFh
:
3FF: 303FFh
jmp 3FFh
; Jump to 3FFh
37
2002-01-11
TC9496AF
5. Cautions on Use
5.1
Initial Reset
After a power-supply injection, once at least, please set up a required register after applying reset
which makes RESET terminal “L” level and making the value of an internal register data.
5.2
The Cautions at the Time of Using IFOK Terminal
The timing which outputs IFOK signal is the signal which shows whether the command received
from the microcomputer was performed normally.
Since the initial value of IFOK signal is unfixed when a control microcomputer is checking IFOK
signal, before sending a command, it may stop performing control from a microcomputer.
5.3
The Cautions at the Time of Using ACMP (address compare mode)
In rewriting coefficient data and offset data using ACMP mode, please do not use it the following
condition.
5.3.1 Please do not Transmit the Following Command before Completing Rewriting of Data.
Please do not send the following command before completing rewriting of data of CRAM or ORAM.
Please check that waiting the term after rewriting has been completed until it transmits the
following command was carried out, or rewriting has been completing using IFOK signal.
5.3.2 Please do not Include Data of an Intact Address.
Please do not include coefficient data of offset data of address which are not used by the program
under execution, into transmitting data. When data of an intact address is contained, operation in
ACMP mode cannot de ended. If the following command is transmitted in this state, RAM data will
become unfixed also by the command with the command unrelated to CRAM or ORAM.
It needs to reset and all data needs to be reset up to interrupt before completing rewriting of data in
the rewriting processing.
th
5.3.3 Please do not Perform Continuation Transmission Over the 0 Address.
The transmission over the 0th address may incorrect-operate.
The same of this restriction is said not only of ACMP mode but continuation transmission of usual
RAM data.
For example, when writing in 1B8h from 1BFh and 007h from 000h or CRAM, it must transmit in
two steps.
5.4
The Handling of NC Terminal
Please use NC terminal by either of the following.
31 pin and 37 pin
· Open (non-connection)
·
Connect to VDD
·
Connect to GND
81 pin
· Open (non-connection)
·
Connect to VDD
38
2002-01-11
TC9496AF
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
VDD
-0.3 to 6.0
V
Input voltage
Vin
-0.3 to VDD + 0.3
V
Power dissipation
PD
1500
mW
Operating temperature
Topr
-40 to 75
°C
Storage temperature
Tstg
-55 to 150
°C
Power supply voltage
Electrical Characteristics
(unless otherwise noted, Ta = 25°C, VDD = VDX = VDDR = VDM = VDL = VDR = VDX = VDAL =
VDAR = VDAC = VDAS = VDASR = 5.0 V)
DC Characteristics
Symbol
Test
Circuit
Operating power supply voltage
VDD
¾
Operating frequency range
fopr
¾
IDD
¾
Symbol
Test
Circuit
Characteristics
Operating power supply current
Test Condition
Ta = -40 to 75°C
Min
Typ.
Max
Unit
4.75
5.0
5.25
V
340 step mode
8
15
25
511 step mode
12
33.8
37
fopr = 36.864 MHz,
511-step mode
¾
150
165
mA
Min
Typ.
Max
Unit
VDD
´ 0.7
¾
VDD
+ 0.3
¾
¾
VDD
´ 0.3
VDD
- 0.5
¾
¾
¾
¾
0.5
Min
Typ.
Max
VDD
´ 0.8
¾
¾
¾
¾
VDD
´ 0.2
¾
¾
10
-10
¾
¾
MHz
Clock pins (XI, XO)
Characteristics
“H” level
VIH1
“L” level
VIL1
“H” level
VOH1
¾
Input voltage (1)
Output voltage (1)
“L” level
¾
Test Condition
XI pin
IOH = -3.0 mA
XO pin
IOL = 5.0 mA
VOL1
V
V
Input Pins
Characteristics
“H” level
Symbol
Test Condition
VIH2
¾
Input voltage (2)
Input leakage
current
Test
Circuit
“L” level
VIL2
“H” level
IIH2
“L” level
IIL2
¾
(Note 4)
VIN = VDD
VIN = 0 V
(Note 4)
(Note 5)
Unit
V
mA
Note 4: STEP0 to 1, RESET , SYNC, ELRO, ELRI, EBCO, EBCI, DIN, EM0 to 1, I2CS, CS , IFCK, IFDI, BOOT,
BA0 to BA1, TST0 to 3 (normally input pins and schmitt input pins)
Note 5: XI
39
2002-01-11
TC9496AF
Output Pins
Characteristics
Symbol
Test
Circuit
Test Condition
IOH = -2.0 mA
Min
Typ.
Max
VDD
- 0.5
¾
¾
¾
¾
0.5
Unit
“H” level
VOH2
“L” level
VOL2
Output voltage (3) “L” level
VOL3
¾
IOL = 4.0 mA
(Note 7)
¾
¾
0.5
V
Output open leakage current
IOZ4
¾
VOH = VDD
(Note 7)
¾
¾
±10
mA
Output voltage (2)
¾
(Note 6)
IOL = 2.0 mA
V
Note 6: FS, CKO0 to 1, MCK, DOUT, IFDO (normally output)
2
Note 7: IFDI (when I C mode output), IFOK, ERR (open drain output)
40
2002-01-11
TC9496AF
AC Characteristic
AD Converter (1): LIN, RIN pins
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Maximum input signal level
Vi
¾
Input level that ADC output at
full-scale digital output
(Note 8)
1.18
1.27
¾
Vrms
Input impedance
Zin
¾
LIN, RIN pins
¾
27
¾
kW
S/Na1
¾
A-Weight,
X’tal: 36.864 MHz
88
96
¾
dB
85
93
¾
dB
¾
-80
-72
dB
¾
-90
-83
dB
85
92
¾
dB
Characteristics
(Note 8)
(Note 8)
S/(N + D) ratio
S/Na2
¾
CCIR-ARM,
X’tal: 36.864 MHz
(Note 8)
THD + N
THDa
¾
20 kHz LPF,
X’tal: 36.864 MHz
(Note 8)
Cross-talk
CTa
¾
20 kHz LPF,
X’tal: 36.864 MHz
(Note 8)
Dynamic range
DRa
¾
A-Weight,
X’tal: 36.864 MHz
(Note 8)
Note 8: Input channels: LIN, RIN
AD Converter (2): MIN pin
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Maximum input signal level
ViM
¾
Input level that ADC output at
full-scale digital output
(Note 9)
¾
1.1
1.15
Vrms
Input impedance
ZinM
¾
MIN pin
¾
1
¾
kW
S/NaM
¾
A-Weight,
X’tal: 36.864 MHz
70
80
¾
dB
¾
-62
-53
dB
¾
-76
-60
dB
¾
-90
-83
dB
70
80
¾
dB
Characteristics
S/(N + D) ratio
(Note 9)
(Note 9)
THD + N
THDaM
¾
20 kHz LPF,
X’tal: 36.864 MHz
(Note 9)
CTaM1
¾
X’tal: 36.864 MHz
LIN, RIN ® MIN
(Note 10)
Cross-talk
CTaM2
¾
X’tal: 36.864 MHz
MIN ® LIN, RIN
(Note 10)
Dynamic range
DRaM
¾
A-Weight,
X’tal: 36.864 MHz
(Note 9)
Note 9: Input channels: MIN
Note 10: Input channels: LIN, RIN, MIN
41
2002-01-11
TC9496AF
DA Converter
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Ao
¾
Output voltage at full-scale
(Note 10)
digital input
1.23
1.33
1.43
Vrms
S/Nratio
S/Nd
¾
A-Weight,
X’tal: 36.864 MHz
90
98
¾
dB
THD + N
THDd
¾
20 kHz LPF,
X’tal: 36.864 MHz
¾
-84
-75
dB
Cross-talk
CTd
¾
20 kHz LPF,
X’tal: 36.864 MHz
¾
-90
-83
dB
Dynamic range
DRd
¾
A-Weight,
X’tal: 36.864 MHz
87
95
¾
dB
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
tXI
¾
¾
29
¾
¾
ns
Clock “H” cycle width
tXIH
¾
¾
¾
14.5
¾
ns
Clock “L” cycle width
tXIL
¾
¾
¾
14.5
¾
ns
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Standby time
tRRS
¾
¾
10
¾
¾
ms
Reset pulse width
tWRS
¾
¾
1.0
¾
¾
ms
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
tDFC
¾
¾
-150
¾
150
ns
Characteristics
Output signal level
Timing
Clock Input Pins (XI)
Characteristics
Clock cycle
Reset Pin ( RESET )
Characteristics
Timing Output
Characteristics
CKO output delay time
Audio Serial Interface (EBCI, DIN, EBCO, DOUT)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
ELRI hold time
tLIH
¾
¾
-75
¾
75
ns
DIN setup time
tSDI
¾
¾
50
¾
¾
ns
DIN hold time
tHDI
¾
¾
50
¾
¾
ns
EBCI clock cycle
tEBCI
¾
¾
300
¾
¾
ns
EBCI clock “H” cycle width
tEBIH
¾
¾
150
¾
¾
ns
EBCI clock “L” cycle width
tEBIL
¾
¾
150
¾
¾
ns
ELRO hold time
tLOH
¾
¾
-75
¾
75
ns
DOUT output delay time (1)
tDO1
¾
¾
¾
¾
60
ns
Characteristics
tDO2
¾
¾
¾
¾
60
ns
EBCO clock cycle
tEBCO
¾
¾
300
¾
¾
ns
EBCO clock “H” cycle width
tEBOH
¾
¾
150
¾
¾
ns
EBCO clock “L” cycle width
tEBOL
¾
¾
150
¾
¾
ns
DOUT output delay time (2)
42
2002-01-11
TC9496AF
Microcontroller Interface
(1)
Standard transmission mode ( CS , IFCK, IFDI, IFDO)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Standby time
tSTB
¾
¾
1.0
¾
¾
ms
CS (fall)-IFCK (fall)
setup time
tCCD
¾
¾
0.2
¾
¾
ms
IFCK “L” cycle width
tWLC
¾
¾
0.25
¾
¾
ms
IFCK “H” cycle width
tWHC
¾
¾
0.25
¾
¾
ms
IFCK (rise)- CS (rise)
setup time
tCKC
¾
¾
0.2
¾
¾
ms
CS “H” cycle time
tWCS
¾
0.5
¾
¾
ms
IFDI-IFCK (rise)
setup time
tSCD
¾
¾
0.2
¾
¾
ms
IFCK (rise)-IFDI
hold time
tHCD
¾
¾
0.2
¾
¾
ms
IFCK (fall)-IFDO
propagation delay time
tDDO
¾
¾
¾
0.2
ms
Characteristics
(Note 11)
CL = 30 pF
Note 11: The command which is “Sync” in the transfer Sync with Sync signal of a 19 page table 1 control command
table needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command.
(It needs more than 22.68 ms at fs = 44.1 KHz.)
(2)
I2C mode ( CS , IFCK, IFDI)
Symbol
Test
Circuit
IFCK clock frequency
tIFCK
¾
IFCK "H" cycle width
tH
IFCK "L" cycle width
Characteristics
Min
Typ.
Max
Unit
CL = 400 pF
0
¾
400
kHz
¾
CL = 400 pF
0.6
¾
¾
ms
tL
¾
CL = 400 pF
1.3
¾
¾
ms
Data setup time
tDS
¾
CL = 400 pF
0.1
¾
¾
ms
Data hold time
tDH
¾
CL = 400 pF
0
¾
¾
ms
Transmission start condition hold time
tSCH
¾
CL = 400 pF
0.6
¾
¾
ms
Repeat transmission start setup time
tSCS
¾
CL = 400 pF
0.6
¾
¾
ms
Transmission end condition setup
time
tECS
¾
CL = 400 pF
0.6
¾
¾
ms
Data transmission interval
tBUF
¾
CL = 400 pF
1.3
¾
¾
ms
tR
¾
CL = 400 pF
¾
¾
0.3
ms
tF
¾
CL = 400 pF
¾
¾
0.3
ms
2
I C rising time
2
I C falling time
Test Condition
43
2002-01-11
TC9496AF
AC Characteristic Measurement Point
(1)
Clock Pin (XI)
XI
50%
tXIH
tXIL
tXI
(2)
Reset
100%
90%
VDD
0%
50%
RESET
tRRS
(3)
tWRS
Timing output
100%
FS
50%
0%
CKO0 to 1
50%
tDFC
(4)
Audio serial interface (ELRI, EBCI, DIN, ELRO, EBCO, DOUT)
tEBCI
tEBIH
tEBIL
ELRI
EBCI
DIN
tLIH
tSDI
tLIH
tHDI
tEBCO
tEBOL
tEBOH
ELRO
EBCO
DOUT
tLOH
tDO2
tDO1
44
tLOH
2002-01-11
TC9496AF
(5)
Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO)
RESET
CS
tSTB
tCCD
tWHC
tWLC
tCKC
tWCS
CS
IFCK
IFDI
tSCD
tHCD
IFDO
tDDO
(6)
Microcontroller interface in I2C mode (IFCK, IFDI)
tBUF
IFDI
IFCK
tSCH
tR
tL
tH
tDS
tDH
tSCS
tF
tECS
Purchase of Toshiba I2C components conveys a license under the Philips I2C Patent Right to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
45
2002-01-11
Rch Input
Lch Input
MIC Input
1 kW
1 kW
4.7 mF
4.7 mF
560 pF
4.7 mF 10 kW
2200 pF
2200 pF
0.1 mF
0.1 mF
1200 pF
47 mF
47 mF
18 kW
39 kW
50 W
10 kW
10 kW
47 mF
0.1 mF
47 mF
47 mF
BOOT
1
XI
36.8 MHz
0.1 mF
47 mF
100 GNDX
99 VSAR
98 RIN
97 AVRR
96 VDR
95 VDL
94 AVRL
93 LIN
92 VSAL
91 GNDM
90 VRM2
89 MOUT
88 MIN
87 VRM1
86 VDM
85 TST3
84 TST2
83 TST1
82 TST0
0.1 mF
47 mF
0.1 mF
47 mF
BA0
XO
2
BA1
4
0.1 mF
47 mF
AOLTch Output
10 kW
2200 pF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
9
8
7
5
I2CS
GNDAL
6
ERR
AOL
2.2 MW
3
IFOK
AOLT
IFCK
0.1 mF
47 mF
DOUT
AOR
46
AORTch Output
10 kW
2200 pF
AOCTch Output
10 kW
2200 pF
0.1 mF
47 mF
TC9496AF
(top view)
IFDO
VRLR
AOC
2200 pF
47 mF
4.7 kW
IFDI
AOCT
81 NC
DIN
GNDAR
27 pF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CS
270 W
47 mF
4.7 kW
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
GND
AORT
10 mF
10 pF
EBCI
GNDAC
AILT
47 mF
VDX
3.3 mF
EBCO
VDALR
3.3 mF
ELRO
VRCS
0.1 mF
47 mF
10 kW
MCK
AOSRT
VDD
AOSR
0.1 mF
47 mF
AOSRTch Output
10 kW
2200 pF
TP15
GNDASL
2200 pF
TP14
GNDASR
AOSLTch Output
270 W
50 W
1000 pF
ELRI
AIRT
RESET
VRI
10 mF
3.3 mF
270 W
10 mF
SYNC
AICT
47 mF
VDD
VRO
3.3 mF
STEP0
VDACS
47 mF
STEP1
AISLT
47 mF
EM1
AOSLT
3.3 mF
EM0
270 W
TP13
AISRT
270 W
10 mF
AOSL
10 mF
GND
VDASR
3.3 mF
Peripheral Circuit Example
NC 31
TP0 32
TP1 33
TP2 34
TP3 35
TP4 36
NC 37
VDDR 38
GNDR 39
TP5 40
TP6 41
TP7 42
TP8 43
TP9 44
TP10 45
TP11 46
TP12 47
FS 48
CKO0 49
CKO1 50
MCU I/F
Audio I/F
47 mF
0.1 mF
2002-01-11
TC9496AF
TC9496AF
Package Dimensions
Weight: 1.57 g (typ.)
47
2002-01-11
TC9496AF
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
48
2002-01-11