TC94A04AFG/AFDG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A04AFG,TC94A04AFDG 1 chip Audio Digital Processor TC94A04AFG/AFDG is a single-chip audio Digital Signal Processor, incorporating 4 way stereo analog switch, 2 ch AD converter, 4 ch DA converter, and electronic volume for trimming. It is possible to realize many applications, such as sound field control -hall simulation, for example-, digital filter for equalizers, surround, base boost and something. TC94A04AFG Features • Incorporates a 4 ch-stereo analog switch for AD converter input. • Incorporates a 1 ch stereo line-out. • Incorporates a 1 bit Σ ∆-type AD converter (two channels). • Incorporates a 1 bit Σ ∆-type DA converter (four channels). P-QFP60-1414-0.80N TC94A04AFDG THD: −82dB (typ.) S/N: 95dB (typ.) THD: −86dB (typ.) S/N: 98dB (typ.) • Incorporates a trimming analog volume for each output of DA converter. 0dB to −24dB (1dB step) • As digital input/output port, this has 3 input port (6 ch) and 1 output port (2 ch), enabling input/output of sampling of 96 kHz/24 bit. • Incorporates a built-in digital de-emphasis filter. • Incorporates a digital attenuator. • Incorporates a boot ROM to set a coefficient automatically, which enables to transfer an initial data from built-in ROM/RAM to registers at the time of resetting P-QFP80-1420-0.80M Weight P-QFP60-1414-0.80N : 1.08 g (typ.) P-QFP80-1420-0.80M: 1.57 g (typ.) Boot ROM: 512 words • The DSP block specifications are as follows: Data bus: 24 bits Multiplier/adder: 24 bits × 16 bits + 43 bits → 43 bits Accumulator: 43 bits (sign extension: 4 bits) Program ROM: 1024 words × 32 bits Coefficient RAM: 384 words × 16 bits Coefficient ROM: 256 words × 16 bits Offset RAM: 16 words × 11 bits Data RAM: 256 words × 24 bits Interface buffer RAM: 32 words × 16 bits Operation speed: 22.5 MIPS (510 step/fs: master clock = 768 fs, fs = 44.1 kHz) • Note 1: At the time of an analog input, approximately 170 steps (85 step/ch) in 510 step are used for the operation of the decimation filter for AD converters. Incorporates data delay RAM (32 kbits). Delay RAM: 2048 words × 16 bits (32 kbits) • The microcontroller interface can be selected between Toshiba original 3 line mode and I2C mode. • CMOS silicon structure supports high speed. • Power supply is a single 5 V. • The package are 60-pin and 80 pin flat package. 1 2005-09-28 TC94A04AFG/AFDG Block Diagram/Pin Connection 45 LIN4 46 19 kΩ LIN3 47 19 kΩ LIN2 48 19 kΩ 44 43 42 39 38 37 36 35 34 33 DIN2 DIN1 DIN0 DOUT VDD RST CS IFCK IFDI IFDO 40 32 C1 C2 C2 Mute SW C3 20 kΩ MCU Interface SYNC 28 500 Ω GNDR 27 C4 Delay RAM VRAL Rch input 500 Ω Ch4 DAC circuit RIN1 53 Same as Ch1 DAC circuit GNDAL 54 Ch3 DAC circuit Σ∆ ADC AO4 23 BP AOT4 22 8 kΩ 41.5 kΩ BP 11 12 13 14 VRI 10 VRO1 9 GNDA2 8 AO2 7 4 kΩ 7.8 kΩ 6 BP VRO2 16 AOT2 5 AO3 19 GNDA3 17 Same as Ch1 DAC circuit VDA12 4 20 kΩ AOT1 3 Same as Ch1 DAC circuit Ch2 DAC Circuit AOT3 20 AI3 18 AO1 2 XO GNDX 1 XI VDX Oscillator circuit AI1 27 kΩ 15 kΩ 15 kΩ 15 kΩ 41.5 kΩ 15 kΩ 15 kΩ 15 kΩ Same as Lch circuit GNDA1 VRAR 58 Ch1 DAC circuit AI2 Σ∆ DAC VRAL Lch circuit GNDAR 60 AI4 24 VDA34 21 27 kΩ VRAL 56 OUTR 59 VDDR 26 GNDA4 25 DSP (I/O Interface) Same as Lch input circuit VDALR 57 EBCI/O 30 ELRI/O 29 C4 19 kΩ RIN3 51 OUTL 55 31 Audio serial interface RIN4 50 RIN2 52 41 C1 Lch input C3 LIN1 49 ERR I2CS GND TST0 TST1 TC94A04AFG 15 BP 2 2005-09-28 TC94A04AFG/AFDG 64 LIN4 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 EBCI/O NC DIN2 NC DIN1 DIN0 NC DOUT VDD RST NC CS IFCK IFDI IFDO NC ERR I2CS GND TST0 TST1 NC NC NC TC94A04AFDG 44 42 41 ELRI/O 40 C1 Lch input 19 kΩ 65 C1 LIN3 66 19 kΩ LIN2 67 19 kΩ C2 C2 Mute SW C3 20 kΩ 19 kΩ 500 Ω VDDR 37 C4 Delay RAM C4 RIN4 69 NC 36 VRAL RIN3 70 RIN2 71 SYNC 39 GNDR 38 C3 LIN1 68 Audio serial interface MCU Interface GNDA4 35 Rch input 500 Ω NC 34 DSP (I/O Interface) Same as Lch input circuit Ch4 DAC circuit RIN1 72 NC 73 AI4 33 AO4 32 Same as Ch1 DAC circuit BP NC 31 GNDAL 74 OUTL 75 AOT4 30 27 kΩ Ch3 DAC circuit VRAL 76 Σ∆ ADC Σ∆ DAC 8 kΩ 41.5 kΩ BP 20 21 22 23 GNDA3 19 VRO2 18 NC 17 VRI 16 VRO1 15 NC 14 GNDA2 13 AI2 12 NC 11 AO2 10 AOT2 9 BP 4 kΩ 7.8 kΩ 8 VDA12 7 AI3 25 NC 6 AO3 26 Same as Ch1 DAC circuit AOT1 5 VDA34 28 Same as Ch1 DAC circuit 20 kΩ NC 4 NC 3 XO GNDX 2 XI 1 VDX GNDAR Oscillator circuit Ch2 DAC circuit AOT3 27 AO1 OUTR 80 15 kΩ 15 kΩ 15 kΩ 27 kΩ Ch1 DAC circuit 41.5 kΩ VRAR 79 Same as Lch circuit GNDA1 VDALR 78 15 kΩ 15 kΩ 15 kΩ VRAL Lch circuit AI1 NC 77 NC 29 24 BP 3 2005-09-28 TC94A04AFG/AFDG Pin Functions Pin No. TC94A 04AFG TC94A 04AFDG (Note 3) Symbol I/O 1 2 VDX ⎯ 2 3 XI I Crystal oscillator connecting or clock input pin 3 4 XO O Crystal oscillator connecting pin 4 5 GNDX ⎯ Ground pin for crystal oscillator circuit. 5 7 GNDA1 ⎯ Analog ground pin for DAC-Lch 6 8 AI1 I DAC-Lch attenuator input pin 7 9 AO1 O DAC-Lch signal output terminal 8 11 AOT1 O DAC-Lch attenuator output pin Function Remarks Power pin for oscillator circuit 9 13 VDA12 ⎯ Analog power pin for DAC-L/Rch 10 14 AOT2 O DAC-Rch attenuator output pin 11 15 AO2 O DAC-Rch signal output pin 12 17 AI2 I DAC-Rch attenuator input pin 13 18 GNDA2 ⎯ Analog ground terminal for DAC-Rch 14 20 VRO1 O Reference voltage output pin-1 for DAC 15 21 VRI I Reference voltage pin for DAC 16 23 VRO2 O Reference voltage output pin-2 for DAC 17 24 GNDA3 ⎯ Analog ground pin for DAC-Cch 18 25 AI3 I 19 26 AO3 O DAC-Cch signal input pin 20 27 AOT3 O DAC-Cch attenuator output pin 21 28 VDA34 ⎯ Analog power pin for DAC-C/Sch 22 30 AOT4 O DAC-Sch signal output pin 23 32 AO4 O DAC-Sch signal output pin 24 33 AI4 I DAC-Sch attenuator input pin 25 35 GNDA4 ⎯ 26 37 VDDR ⎯ Power pin for delay RAM 27 38 GNDR ⎯ Ground pin for delay RAM 28 39 SYNC I 29 40 ELRI/O 30 41 31 43 DAC-Cch attenuator input pin Analog ground pin for DAC-Sch Program SYNC signal input pin Schmitt input, TTL/CMOS (Note 2) I/O LR clock input/output pin for serial data (DIN/DOUT) Schmitt input, TTL/CMOS (Note 2) EBCI/O I/O Bit clock input/output pin for serial data (DIN/DOUT) Schmitt input, TTL/CMOS (Note 2) DIN2 I Serial data input pin 2 Schmitt input, TTL/CMOS (Note 2) Note 2: 28 to 33 pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are 39 to 41 pins and 43 to 46 pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins. 4 2005-09-28 TC94A04AFG/AFDG Pin No. TC94A 04AF TC94A 04AFD (Note 3) Symbol I/O Function Remarks 32 45 DIN1 I Serial data input pin 1 Schmitt input, TTL/CMOS (Note 2) 33 46 DIN0 I Serial data input pin 0 Schmitt input, TTL/CMOS (Note 2) 34 48 DOUT O Serial data output pin 35 49 VDD ⎯ Power pin 36 50 RST I Reset pin Schmidt input 37 52 CS I Microcontroller interface chip select signal input pin Schmidt input 38 53 IFCK I Microcontroller interface data shift clock input pin Schmidt input 2 39 54 IFDI I/O Microcontroller interface data input/output pin (I C bus) 40 55 IFDO O Microcontroller interface data output pin 41 57 ERR O Error flag output pin Open drain output 42 58 I2CS I Microcontroller interface switching pin (I2C bus/Toshiba bus) Schmitt input 43 59 GND ⎯ GND pin 44 60 TST0 I Test pin 0 45 61 TST1 I Test pin 1 46 65 LIN4 I ADC-Lch signal input pin 4 47 66 LIN3 I ADC-Lch signal input pin 3 48 67 LIN2 I ADC-Lch signal input pin 2 49 68 LIN1 I ADC-Lch signal input pin 1 50 69 RIN4 I ADC-Rch signal input pin 4 51 70 RIN3 I ADC-Rch signal input pin 3 52 71 RIN2 I ADC-Rch signal input pin 2 53 72 RIN1 I ADC-Rch signal input pin 1 54 74 GNDAL ⎯ Analog ground pin for ADC-Lch 55 75 OUTL O Lch analog line-out pin 56 76 VRAL I Reference voltage pin for ADC-Lch 57 78 VDALR ⎯ 58 79 VRAR I Reference voltage pin for ADC-Rch 59 80 OUTR O Rch analgo lline-out pin 60 1 GNDAR ⎯ Analog ground pin for ADC-Rch Schmidt input Analog power pin for ADC-L/Rch Note 2: 28 to 33 pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are 39 to 41 pins and 43 to 46 pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins. 5 2005-09-28 TC94A04AFG/AFDG Explanation of Block Operations 1. Explanation Pin Operations Pin No. TC94A 04AFG TC94A 04AFDG (Note 3) Symbol 2 3 XI Master mode: Connect the crystal oscillator 3 4 XO Slave mode: Supplies an external master clock to XI. Function Master clock is 768 fs. Each master-clock frequency to fs is as follows. fs 768 fs 32 kHz 24.576 MHz 44.1 kHz 33.868 MHz 48 kHz 36.864 MHz 96 kHz 36.864 MHz ⎯ 1, 4 to 25 2, 5 to 35 Omitted 26 37 VDDR Power pin for delay RAM 27 38 GNDR Ground pin for delay RAM 28 39 SYNC Program SYNC signal input pin 29 40 ELRI/O LR clock pin for serial data input (DIN)/serial data output (DOUT). When you carry out a slave operation to a serial input/output data, please set it as an input. And when you carry out a master operation, please set it as an output (command 43h: SIOS). Output frequency can perform selection of 1 fs/2 fs by ELRQS (command: 40h). 30 41 EBCI/O Bit clock pin for serial data input (DIN)/serial data output (DOUT). When you carry out a slave operation to a serial input/output data, please set it as an input. And when you carry out a master operation, please set it as an output (command 43h: SIOS). Output frequency can be select as follows by EBCQS (command: 40h). EBCQS [1:0] Output Frequency 0 32 fs 1 64 fs 2 128 fs 3 for test 31 43 DIN2 32 45 DIN1 33 46 DIN0 34 48 DOUT 35 49 VDD Power pin 36 50 RST Reset pin. “L” at initialization. Serial data input pin. The serial data of a total of 6-channels can be inputted. Switching of the number of channel is set by CHSI (command: 42h). Moreover, switching of master/slave function is set by SIS (command: 42h) Serial data output pin. Connected to internal register for output in DSP block. The internal register connected is set up by CHSO (command: 43h). Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins. 6 2005-09-28 TC94A04AFG/AFDG Pin No. TC94A 04AFG TC94A 04AFDG Symbol Function (Note 3) 37 52 CS 38 53 IFCK 39 54 IFDI 40 55 41 42 Microcontroller interface pin I2CS Transmission Mode IFDO 0 Toshiba original bus mode 57 ERR 1 I2C bus mode 58 I2CS 43 59 GND 44 60 TST0 45 61 TST1 46 65 LIN4 47 66 LIN3 48 67 LIN2 49 68 LIN1 50 69 RIN4 51 70 RIN3 52 71 RIN2 53 72 RIN1 54 to 60 74 to 80, 1 Omitted 2 Toshiba Original Bus Mode I C Bus Mode CS Chip select Chip select (can be fixed to “L”) IFCK Transmit/receive clock Transmit/receive clock IFDI Data/command input Data input/output IFDO Data output (monitor data) Fixed to “L” level output ERR Error flag signal output (for runaway detector) Error flag signal output (for runaway detector) Ground pin Test pin. Fixed to “L” Four channel analog L-ch input pin. Incorporates an analog selector. And an input switching is selected by Command AIS (command: 42h) (MIX is also possible). The selected signal is outputted from OUTL (55 pin). Four channel analog R-ch input pin. Incorporates an analog selector. And an input switching is selected by Command AIS (command: 42h) (MIX is also possible). The selected signal is outputted from OUTR (59 pin). ⎯ Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins. 7 2005-09-28 TC94A04AFG/AFDG 2. Microcontroller Interface 2.1 Standard Transmission Mode When I2CS = “L”, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI signal on the IFCK signal rising edge. When CS = “H”, the IFCK and IFDI signals are don’t care. 2.1.1 Setting Resisters CS IFCK IFDI C7 Don’t care C5 C6 C3 C4 C1 C2 C0 D15 D13 D11 D9 D14 D12 D10 D8 D7 D5 D6 D3 D4 D1 D2 D0 Don’t care Cn: COMMAND Dn: Data The registers are set by command using the IFDI signals. The first byte is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB. Data are loaded the rising edge of the IFCK signal. Note that commands or data that must be switched, such as the RUN-MUTE command (command-44h) or the IFF flag (command-4Ah), must be synchronized with the SYNC signal and loaded on that signal. 8 2005-09-28 TC94A04AFG/AFDG 2.1.2 Setting RAM (sequential) CS IFCK IFDI C7 Don’t care C5 C6 C3 C4 C1 C2 C0 A15 A13 A11 A9 A14 A12 A10 A8 A7 A5 A6 A3 A4 A1 A2 A0 D15 D13 D11 D9 D14 D12 D10 D8 D1 D0 Don’t care Cn: COMMAND An: ADDRESS Dn: Data The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field following the RAM address bytes is 2 × n bytes. The address is automatically incremented by 1. During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal. Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP, it is written in asynchronous. 9 2005-09-28 TC94A04AFG/AFDG 2.1.3 Setting RAM (ACMP mode) CS IFCK IFDI C7 Don’t care C5 C6 C3 C4 C1 C2 C0 A15 A13 A11 A9 A14 A12 A10 A8 A7 A5 A6 A3 A4 A1 A2 A0 D15 D13 D11 D9 D14 D12 D10 D8 D7 D5 D6 D3 D4 D1 D2 D1 D0 D0 Don’t care Cn: COMMAND An: ADDRESS Dn: Data In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC94A04AFG/AFDG is operating. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words. The length of the data field is 2 × n bytes, where n < = 32. In addition, operation at the time of transmitting other commands, before package rewriting of the data by ACMP mode was completed cannot be guaranteed. Please set up again after initializing by RST terminal or the initialization command. K1 K6 + + K2 K4 K7 K9 K3 K5 K8 K10 MCU-I/F Write one by one･･･ 10 IFB-RAM CRAM Update for 1 fs 2005-09-28 TC94A04AFG/AFDG 2.2 2 I C Bus Mode When I2CS = “H”, data can be transmitted or received in I2C bus mode. When the CS signal is Low, control from the microcontroller is enabled. In I2C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI data on the IFCK signal rising edge. When CS = “H”, IFCK and IFD signal are don't care. 2.2.1 Setting Registers 32h start HZ HZ HZ HZ end CS IFCK IFDI (MCU →) A7 A5 A6 A3 A4 A1 A2 A0 C7 C5 C6 C3 C4 C1 C2 D15 D13 D11 D9 C0 D14 D12 D10 D8 D7 D5 D6 D3 D4 D2 2 An: I C address Cn: COMMAND Dn: Data The registers are set by command data using the IFDI signal. The first byte after the I2C address (= 32h) is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C format. The data loaded internally every two bytes. Note that commands or data that must be switched on the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be synchronized with the SYNC signal and loaded on that signal. 11 2005-09-28 TC94A04AFG/AFDG 2.2.2 Setting RAM (sequential) 32h start HZ HZ HZ HZ HZ end CS IFCK IFDI (MCU →) A7 A5 A6 A3 A4 A1 A2 A0 C7 C5 C6 C3 C4 C1 C2 C0 RA7 RA5 RA3 RA1 RA15 RA13 RA11 RA9 RA14 RA12 RA10 RA8 RA6 RA4 RA2 RA0 D15 D13 D11 D9 D14 D12 D10 D8 Cn: COMMAND 2 An: I C address RAn: RAM-ADDRESS Dn: Data The RAMs are set by command data using the IFDI signal. The first byte after the I2C address (32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM. The length of the data field following the RAM address bytes is 2 × n bytes. The address is automatically incremented by 1. During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal. Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP, it is written in asynchronous. 12 2005-09-28 TC94A04AFG/AFDG 2.2.3 Setting RAM (ACMP mode) 32h start HZ HZ HZ HZ HZ HZ end CS IFCK IFDI (MCU →) A7 A5 A6 A3 A4 A1 A2 C7 C5 C3 A0 C6 C1 C4 C2 C0 RA7 RA5 RA3 RA1 RA15 RA13 RA11 RA9 RA14 RA12 RA10 RA8 D15 D13 D11 D9 RA6 RA4 RA2 RA0 D14 D12 D10 D8 Cn: COMMAND 2 An: I C address RAn: RAM-ADDRESS Dn: Data In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC94A04AFG/AFDG is operating. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words. The length of the data field is 2 × n bytes, where n < = 32. In addition, operation at the time of transmitting other commands, before package rewriting of the data by ACMP mode was completed cannot be guaranteed. Please set up again after initializing by RST terminal or the initialization command. K1 K6 + + K2 K4 K7 K9 K3 K5 K8 K10 MCU-I/F Write one by one･･･ 13 IFB-RAM CRAM Update for 1 fs 2005-09-28 TC94A04AFG/AFDG 3. Control Commands The following table lists the control commands that can be used from the microcontroller. 3.1 Control-Command Table Table 1 Command Code R/W Control commands Description RAM Sequential Transfer Sync/Async to SYNC Signal TIMING 40h Timing ⎯ Async BOOT 41h Self boot ROM start address ⎯ Async DIN/AIN 42h Setting digital/analog input ⎯ Async DOUT/AOUT 43h Setting digital/analog output ⎯ Async RUN-MUTE 44h Program execution, mute ⎯ Sync MSEQ 45h Sequential RAM ⎯ CRAM 46h CRAM CRAM-ACMP 47h W CRAM (ACMP mode) Enable Sync: RUN, Async: STOP Async ORAM 48h ORAM ORAM-ACMP 49h ORAM (ACMP mode) Sync: RUN, Async: STOP IFF 4Ah IFF setting ⎯ Sync Async DE-EMPH 4Bh De-emphasis ⎯ Sync DAC-LR 4Ch DAC output trim level (L/R-ch) ⎯ Sync DAC-CS 4Dh DAC output trim level (C/S-ch) ⎯ Sync DF-ATT 4Eh DF attenuator level (all ch) ⎯ Async M-RST 4Fh Initialization ⎯ Async Note 4: The command which is “Sync” in the transfer Sync with Sync signal needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command. (It need more than 22.68 µs at fs = 44.1 KHz.) 14 2005-09-28 TC94A04AFG/AFDG 3.2 Control Commands Description Each command explanation is shown below. *mark in each command explanation table shows the initial value at the time of reset. Command-40h (0100 0000): TIMING (4400h*) D15 D14 D13 0 SYPD SYD1 Bit Name D15 ⎯ D14 SYPD D13 SYD D12 [1:0] D11 D10 ⎯ SYPA D9 SYA D8 [1:0] D7 D6 ⎯ SYPS D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SYD0 0 SYPA SYA1 SYA0 0 SYPS SYS1 SYS0 0 ELROS EBCOS1 EBCOS0 Description ⎯ ASP digital block sync polarity switching 0 ASP program starts on falling edge 1* ASP program starts on rising edge 0* Signal after SYNC 1 fs output ASP digital block SYNC signal input switching EBCOS [1:0] 3 ELRI/O pin DF block sync polarity switching 1* DF-processing starts in a rising ⎯ 0* SYNC 1 fs output 1 SYNC 2 fs output 2 Reserved 3 Reserved DF block sync input switching Fixed to 0 (zero) ⎯ SYNC circuit input polarity switching (SYNC reference signal) 0* Reference input = L Lch 1 Reference input = H Lch 0* Internal divided results 1 SYNC pin 2 ELRI/O pin 3 Output ELRI/O pin input divided by 2 (for 96 kHz sampling) (SYNC reference signal) D0 SYNC pin DF-processing starts in a falling SYNC circuit input switching D1 Signal after SYNC 2 fs output 2 fs (for 96 kHz sampling) 2 0 [1:0] ELROS 1 ⎯ SYS D2 ⎯ Fixed to 0 (zero) D4 ⎯ Operation Fixed to 0 (zero) D5 D3 Value ⎯ Fixed to 0 (zero) ⎯ Select the clock at the time of ELRI/O output 0* 1 fs (Internal fs) 1 2 fs (Internal fs × 2) 0* 32 fs (Internal fs × 32) 1 64 fs (Internal fs × 64) 2 128 fs (Internal fs × 128) 3 Reserved Select the clock at the time of EBCI/O output ⎯ 15 2005-09-28 TC94A04AFG/AFDG Command-41h (0100 0001): BOOT (0000h*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 BTA8 BTA7 BTA6 BTA5 BTA4 BTA3 BTA2 BTA1 BTA0 D1 D0 Bit Name D15 to D7 ⎯ D8 to D0 Description Fixed to 0 (zero) BTA Self-boot ROM start address [8:0] Value Operation ⎯ ⎯ 000h to Starts self-boot operation from specified address 1FEh Command-42h (0100 0010): DIN/AIN (0100h*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 CHSI 1 CHSI 0 VS AUTO AIS4 AIS3 AIS2 AIS1 ZDE SIS Bit Name D15 CHSI D14 [1:0] D13 VS D12 AUTO Description Serial input (SI) switching AIS D9 [4:1] Analog 2 ch input 1 Digital 4 ch input (2 ch input by the program is possible) 2 Digital 6 ch input Analog and Digital MIX mode Switching threshold of input pin 0* CMOS level [SYNC，ELRI/O，EBCI/O， DIN2，DIN1，DIN0] 1 TTL level Switching analog input D6 ZDE 0* Mute OFF 1 Mute ON SIS D5 ISLT D4 [1:0] D3 IBCS D2 [1:0] D1 IFMT D0 [1:0] AIS4: LIN4/RIN4 pin, AIS3: LIN3/RIN3 pin, AIS2: LIN2/RIN2 pin, AIS1: LIN1/RIN1 pin 0 to Fh (1*) Digital-input zero-level detection mute function Serial input bit length Serial input format Select channel, it was set as “1”. (output from OUTL/OUTR) MIX between channels is also possible. 0* Mute OFF 1 Mute ON 0* Master (synchronizes with internal clock (output from ELRI/O， EBCI/O pin)) 1 Slave (synchronizes with external clock (input from ELRI/O， EBCI/O pin)) Serial input Number of serial input slots D2 Operation 3 Auto mute (analog input) D3 0* D8 D7 D4 ISLT1 ISLT0 IBCS1 IBCS0 IFMT1 IFMT0 Value D11 D10 D5 0* 16 slots (bit clock = 32 fs) 1 20 slots (bit clock = 40 fs) 2 24 slots (bit clock = 48 fs) 3 32 slots (bit clock = 64 fs) 0* 16 bits 1 18 bits 2 20 bits 3 24 bits 0* Pads from the beginning 1 Pads from the end 2 3 I2S format 16 2005-09-28 TC94A04AFG/AFDG Command-43h (0100 0011): DOUT/AOUT (0080h*) D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 HSMP 0 0 SIOS SOS Bit Name D15 to D13 ⎯ D12 HSMP D11 ⎯ Description D7 D6 D5 CHSO CHSO OSLT 1 0 1 D4 D3 D2 D1 D0 OSLT OBCS OBCS OFMT OFMT 0 1 0 1 0 Value Operation Fixed to 0 (zero) ⎯ ⎯ Switching high sampling of analog output 0* Normal rate 1 High sampling rate Fixed to 0 (zero) ⎯ Switching input/output of ELRI/O, EBCI/O pin 0* Input 1 Output 0* Master (synchronizes with internal clock (output from EBLRI/O, EBCI/O pin)) 1 Slave (synchronizes with external clock (input from EBLR/O, EBCI/O pin)) 0 DOUT pin ← SIR0 1 DOUT pin ← SIR1 2* DOUT pin ← SIR2 ⎯ D10 D9 D8 D7 D6 D5 SIOS SOS Serial output CHSO [1:0] Serial output switching OSLT 3 Reserved 0* 16 slots 1 20 slots 2 24 slots Number of serial input slots D4 [1:0] D3 OBCS D2 [1:0] D1 OFMT D0 [1:0] 3 32 slots 0* 16 bits 1 18 bits Serial output bit length 2 20 bits 3 24 bits 0* Pads from the beginning 1 Pads from the end Serial output format 2 I2S format 3 17 2005-09-28 TC94A04AFG/AFDG Command-44h (0100 0100): RUN-MUTE (1F0Fh*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 RUN 0 0 AD MUT IMUTE OMU TE2 OMU TE1 OMU TE0 0 0 0 0 Bit Name D15 RUN D14 ⎯ Description ASP program execution Fixed to 0 (zero) Value D3 D2 ERDET ZST D1 D0 SYRC SYRO Operation 0* Stops program 1 Runs program ⎯ ⎯ D13 D12 D11 D10 D9 D8 ADMUT IMUTE OMUTE1 OMUTE0 0 D3 ERDET D1 D0 ASP block input mute 0 Mute OFF 1* Mute ON 0 Mute OFF 1* Mute ON ASP block output mote 0 Mute OFF (SIR2 register mute) 1* Mute ON ASP block output mute 0 Mute OFF (SIR1 register mute) 1* Mute ON ASP block output mute 0 Mute OFF (SIR0 register mute) 1* Mute ON Fixed to 0 (zero) ⎯ OMUTE2 D7 to D4 D2 ADC mute ZST SYRC SYRO ⎯ 0 Disable 1* Enable 0 2-cycle access Error detection Switches to access CROM using Log-Linear adjustment Set CP at each SYNC Set OFP at each SYNC 1* 1-cycle access 0 Does not reset 1* Reset 0 Does not reset 1* Reset 18 2005-09-28 TC94A04AFG/AFDG Command-45h (0100 0101): MSEQ D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name D15 to D3 ⎯ D2 to D0 Description MSA [2:0] Value Operation Fixed to 0 (zero) ⎯ ⎯ Module sequential RAM first address 0h to 7h D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 Bit Name D15 to D10 ⎯ D9 to D0 D9 D1 D0 MSA2 MSA1 MSA0 The address of the head to write in is set up. D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ 9 8 7 6 5 4 3 2 1 0 Description Fixed to 0 (zero) MSEQ Module sequential RAM data [9:0] D2 Value Operation ⎯ ⎯ 000h to The data written in module sequence RAM are set up. 3FFh Data are sent continuously after transmitting the module sequence RAM head address (2 bytes). Enable a sequential write to RAM. 45h-MSEQ RAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････- data (2 bytes) (module sequential RAM: 8 words) 19 2005-09-28 TC94A04AFG/AFDG Command-46h (0100 0110): CRAM D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 Bit Name D15 to D9 ⎯ D8 to D0 D15 Fixed to 0 (zero) CRAMA [8:0] D14 Description D13 CRAM (coefficient RAM) head address D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM A8 A7 A6 A5 A4 A3 A2 A1 A0 Value Operation ⎯ ⎯ 000h CRAM address of the head at the time of writing in by 46h to command is set up. 17Fh D8 D7 D6 D5 D4 D3 D2 D1 D0 CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name D15 to D0 CRAMD [15:0] Description CRAM data Value Operation 7FFFh to Set CRAM data (two-complement-form formula) 8000h The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 46h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････-data (2 bytes) (CRAM: 384 words) 20 2005-09-28 TC94A04AFG/AFDG Command-47h (0100 0111): CRAM-ACMP D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 Bit Name D15 to D9 ⎯ D8 to D0 D15 Fixed to 0 (zero) CRAMA [8:0] D14 Description D13 CRAM (coefficient RAM) head address D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM A8 A7 A6 A5 A4 A3 A2 A1 A0 Value Operation ⎯ ⎯ 000h CRAM address of the head at the time of writing in by 47h to command is set up. 17Fh D8 D7 D6 D5 D4 D3 D2 D1 D0 CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name D15 to D0 CRAMD [15:0] Description CRAM data Value Operation 7FFFh to Set CRAM data (two-complement-form formula) 8000h It is CRAM write-in command which used the address compare mode. A maximum of 32 words is written at once. The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 47h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････-data (2 bytes) (CRAM: 384 word) 21 2005-09-28 TC94A04AFG/AFDG Command-48h (0100 1000): ORAM D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name D15 to D4 ⎯ D3 to D0 Description ORAMA [3:0] Operation Fixed to 0 (zero) ⎯ ⎯ ORAM (offset RAM) head address 0h to Fh D14 D13 D12 D11 0 0 0 0 0 Name D15 to D11 ⎯ D10 to D0 Fixed to 0 (zero) ORAM data D9 D1 D0 ORAM address of the head at the time of writing in by 48h command is set up. D8 D7 D6 D5 D4 D3 D2 D1 D0 ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Description ORAMD [10:0] D10 D2 ORAM ORAM ORAM ORAM A3 A2 A1 A0 Value D15 Bit D3 Value Operation ⎯ ⎯ 000 to Set ORAM data 7FFh It is ORAM write-in command which used the address compare mode. The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 48h-ORAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････-data (2 bytes) (ORAM: 16 words) 22 2005-09-28 TC94A04AFG/AFDG Command-49h (0100 1001): ORAM-ACMP D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name D15 to D4 ⎯ D3 to D0 Description ORAMA [3:0] Operation Fixed to 0 (zero) ⎯ ⎯ ORAM (offset RAM) head address 0h to Fh D14 D13 D12 D11 0 0 0 0 0 Name D15 to D11 ⎯ D10 to D0 Fixed to 0 (zero) ORAM data D9 D1 D0 ORAM address of the head at the time of writing in by 48h command is set up. D8 D7 D6 D5 D4 D3 D2 D1 D0 ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Description ORAMD [10:0] D10 D2 ORAM ORAM ORAM ORAM A3 A2 A1 A0 Value D15 Bit D3 Value Operation ⎯ ⎯ 000 to Set ORAM data 7FFh The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 49h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････-data (2 bytes) (ORAM: 16 words) 23 2005-09-28 TC94A04AFG/AFDG Command-4Ah (0100 1010): IFF (0000h*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFF2 IFF1 IFF0 D1 D0 Bit Name D15 to D4 ⎯ D3 IFF2 Description Fixed to 0 (zero) Set IFFn (n = 2, 1, 0) Value Operation ⎯ ⎯ 0* IFFn = 0 1 IFFn = 1 Command-4Bh (0100 1011): DE-EMPH (0000h*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name D15 to D2 ⎯ Description Fixed to 0 (zero) D1 DEMP [1:0] Value Operation ⎯ ⎯ 0* De-emphasis Off 1 fs = 32 kHz 2 fs = 44.1 kHz 3 fs = 48 kHz Set de-emphasis D0 DEMP DEMP 1 0 Command-4Ch (0100 1100): DAC-LR (1F1Fh*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 ATTL 4 ATTL 3 ATTL 2 ATTL 1 ATTL 0 0 0 0 ATTR 4 ATTR 3 ATTR 2 ATTR 1 ATTR 0 Bit Name D15 to D13 ⎯ D12 to D8 D7 to D5 D4 to D0 Description Fixed to 0 (zero) ATTL [4:0] ⎯ DAC L-ch attenuator value Fixed to 0 (zero) ATTR [4:0] DAC R-ch attenuator value Value Operation ⎯ ⎯ 00h to 1Fh* Code : 00h 01h ATT (dB) : 0 −1 02h ･･･ −2 18h 19h ･･･ 1Fh −24 ca.−60 ca.−60 Initial value: 1Fh ⎯ ⎯ 00h to 1Fh* Code : 00h 01h ATT (dB) : 0 −1 02h −2 ･･･ 18h 19h ･･･ 1Fh −24 ca.−60 ca.−60 Initial value: 1Fh 24 2005-09-28 TC94A04AFG/AFDG Command-4Dh (0100 1101): DAC-CS (1F1Fh*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 ATTC 4 ATTC 3 ATTC 2 ATTC 1 ATTC 0 0 0 0 ATTS 4 ATTS 3 ATTS 2 ATTS 1 ATTS 0 Bit Name D15 to D13 ⎯ D12 to D8 Description Fixed to 0 (zero) D7 to D5 DAC C-ch attenuator value ⎯ D4 to D0 ⎯ ⎯ Code : 00h 01h −1 ATT (dB) : 0 ･･･ 02h −2 DAC-Sch attenuator value 1Fh ca.−60 ⎯ 00h to 1Fh* ATTS 18h 19h ･･･ −24 ca.−60 Initial value: 1Fh ⎯ Fixed to 0 (zero) [4:0] Operation 00h to 1Fh* ATTC [4:0] Value Code : 00h 01h −1 ATT (dB) : 0 ･･･ 02h −2 18h 19h ･･･ 1Fh −24 ca.−60 ca.−60 Initial value: 1Fh Command-4Eh (0100 1110): DF-ATT (007Fh*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 Bit Name D15 to D7 ⎯ Description Fixed to 0 (zero) Value Operation ⎯ ⎯ Initial value: 7Fh (level = −∞) LEVEL = 20 × log (ATL/128) Code D6 to D0 ATL [6:0] DF attenuator value 00h to 7Fh* 25 ATL Level 00h 7Fh 0.00dB 01h 7Eh −0.14dB 02h 7Dh −0.21dB to to to 0Dh 72h −1.01dB 1Ah 65h −2.06dB 25h 5Ah −3.06dB to to to 3Fh 40h −6.02dB to to to 7Dh 02h −36.12dB 7Eh 01h −42.14dB 7Fh 00h −∞ 2005-09-28 TC94A04AFG/AFDG Command-4Fh (0100 1111): M-RST (0000h*) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MRST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name D15 MRST D14 to D0 ⎯ Description Value Operation Initialization from the micro controller command 0* Does not initialize 1 Initializes (set to initial value (0*)) Fixed to 0 (zero) ⎯ ⎯ 26 2005-09-28 TC94A04AFG/AFDG 4. Self-Boot Function Description 4.1 Self-Boot Function The TC94A04AFG/AFDG supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later. The microcontroller interface circuit supports two format: I2C and the original mode. However, the boot must be executed in Standard Transmission. RST Self-boot Circuit SBROM (512 word × 18 bit) Microcontroller Interface Circuit Timing generat or BTCSN BTIFCK BTIFDI CS IFCK IFDI BTMODE 1 0 Internal IFDI 1 0 Internal IFCK 1 0 Internal CSN Internal I2CS I2CS Figure 1 Self-Boot System All the command inputs from the exterior are disregarded during a boot term. 27 2005-09-28 TC94A04AFG/AFDG 4.2 Boot ROM Format The following shows the breakdown of the 18 bits. 00 Data that are being sent 01 Command 10 Final data (after the data are sent, the CS signal set to “H”). 11 Jump address (jump to any address in the boot-ROM) 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (MSB) 000h 0 0 (LSB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All ‘0’ 001h 11 Address JMP 002h 11 Address JMP 003h 01 004h 10 005h 01 006h 00 Data Data (cont) 007h 00 Data Data (cont) 008h 00 Data Data (cont) 009h 00 Data Data (cont) 00Ah 10 Data Data (last) 00Bh 11 Address JMP 1FFh 1FFh 11 Address JMP 1FFh CMD Data CMD Data (last) CMD CMD Figure 2 Boot ROM Format and Example Note 5: Boot mode completes when the address reaches 1FFh, the maximum value. Therefore, for the final address (1FFh), write JMP 1FFh (data = 301FFh). Note 6: For the head address (000h), write (00000). Note 7: Please do not set a command of fs synchronous taking in to the address: 1FEh (RUN-MUTE/IFF/DE-EMPH/DAC-LR/DAC-CS etc.). 28 2005-09-28 TC94A04AFG/AFDG 4.3 Self-Boot Operation Self-boot operation supports two modes: one for use at reset and for setting the microcontroller. 4.3.1 Self-Boot Operation at Reset To enter this mode, set the RST pin to High or send initialized command. The 2048 fs period (46.4 ms when fs = 44.1 kHz) after a reset release is wait period. The boot operation starts at the end of this period. Relationship between fs and Wait Period fs Wait Period Boot Time (maximum) 32 kHz 64.0 ms 16.0 ms 44.1 kHz 46.4 ms 11.6 ms 42.7 ms 10.7 ms 48 kHz 96 kHz Starting address is fixed to 001h. If the jump address to application to execute at the time of a boot is specified to be 0001h, at the time of a reset, the initial value of application will be set up automatically. When you do not boot at the time of a reset, please set JMP (1FFh: data = 301FFh) as 001h. 4.3.2 Self-Boot Operation When Setting Microcontroller In this mode, the microcontroller can specify any address and the boot operation starts from that address. The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the BOOT command (command: 41h) from the microcontroller starts the boot operation with no wait. The boot operation when set from the microcontroller is the same as the self-boot operation at reset except that the boot operation can start from any address. Boot wait period 2048 fs Boot period 512 fs (max) RST FS BTMODE (internal signal) BootRom Adrs 2 Rom Dt [17:16] JMP 10 11 12 13 14 15 16 CMD DT DT DE CMD DE CMD D C D 3FF JMP JMP BTCSN BTIFCK BTIFDI C D D C 8 clock DT: Data DE: DataEnd C Figure 3 Boot Timing Chart (at reset) 29 2005-09-28 TC94A04AFG/AFDG 5. Cautions on Use 5.1 Initial Reset After a power-supply injection, once at least, please set up a required register after applying reset which makes RST terminal “L” level and making the value of an internal register decide. 5.2 The Cautions at the Time of Using ACMP (address compare mode) In rewriting coefficient data and offset data using ACMP mode, please do not use it the following condition. 5.2.1 Please Do Not Transmit the Following Command before Completing Rewriting of Data. Please do not send the following command before completing rewriting of data of CRAM or ORAM. Please check that waiting the term after rewriting has been completed until it transmits the following was carried out. 5.2.2 Please Do Not Include Data of an Intact Address. Please do not include coefficient data of offset data of address which are not used by the program under execution, into transmitting data. When data of an intact address is contained, operation in ACMP mode cannot de ended. If the following command is transmitted in this state, RAM data will become unfixed also by the command with the command unrelated to CRAM or ORAM. It needs to reset and all data needs to be re-set up to interrupt before completing rewriting of data in the rewriting processing. 5.2.3 Please Do Not Use the 0th Street of CRAM Address. 5.3 Please Do Not Perform Continuation Transmission over the 0th Address. The transmission over the 0th address may incorrect-operate. For example, when writing in 17Fh from 178h and 000h from 007h of CRAM, it must transmit in two steps. 5.4 Please Do Not Set-Up a Soft Reset Command as the Data of Boot ROM. 30 2005-09-28 TC94A04AFG/AFDG Maximum Ratings (Ta = 25°C) Characteristics Power supply voltage Input voltage Power dissipation TC94A04AFG TC94A04AFDG Symbol Rating Unit VDD −0.3 to 6.0 V Vin −0.3 to VDD + 0.3 V 1538 PD (Note 8) mW 1538 Operating temperature Topr −40 to 75 °C Storage temperature Tstg −55 to 150 °C Note 8: Power dissipation of TC94A04AFG is reference value when assembled chip on PCB. (normally, PD is 1250 mW.) Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = VDX = VDR = VDA12 = VDA23 = VDALR = 5.0 V) DC Characteristics Symbol Test Circuit Operating power supply voltage VDD ⎯ Ta = −40 to 75°C Operating frequency range fopr ⎯ 511 step mode Operating power supply current IDD ⎯ Symbol Test Circuit Characteristics Test Condition Min Typ. Max Unit 4.75 5.0 5.25 V 12 33.8 37 MHz ⎯ 135 146 mA Min Typ. Max Unit VDD × 0.7 ⎯ VDD + 0.3 ⎯ ⎯ VDD × 0.7 VDD − 0.5 ⎯ ⎯ fopr = 36.864 MHz 511 Step mode Clock Pins (XI, XO) Characteristics “H” level VIH1 “L” level VIL1 “H” level VOH1 ⎯ Input voltage (1) Output voltage (1) “L” level VOL1 ⎯ Test Condition XI pin IOH = −3.0 mA IOL = 5.0 mA 31 XO pin ⎯ V V ⎯ 0.5 2005-09-28 TC94A04AFG/AFDG Input Pins Characteristics “H” level Symbol Test Circuit Test Condition VIH2 (Note 9) (CMOS input), (Note 10) ⎯ Input voltage (2) Typ. Max VDD × 0.8 ⎯ ⎯ VIL2 ⎯ ⎯ VDD × 0.2 “H” level VIH3 VDD × 0.5 ⎯ ⎯ ⎯ ⎯ VDD × 0.2 ⎯ ⎯ 10 −10 ⎯ ⎯ Min Typ. Max ⎯ “L” level VIL3 “H” level IIH2 “L” level IIL2 ⎯ (Note 9) (TTL input) VIN = VDD VIN = 0 V (Note 9), (Note 10), (Note 11) Unit V “L” level Input voltage (3) Input leakage current Min V µA Note 9: SYNC, ELRI/O, EBCI/O, DIN0 to 2 Note 10: CS , IFCK, IFDI, I2CS, TST0, TST1 Note 11: XI Output Pins Characteristics “H” level Symbol Test Circuit VOH2 Test Condition IOH = −2.0 mA (Note 12) VDD − 0.5 ⎯ ⎯ IOL = 2.0 mA (Note 12), (Note 14) ⎯ ⎯ 0.5 IOL = 4.0 mA (Note 13) ⎯ ⎯ 0.5 V VOH = VDD (Note 12), (Note 14) ⎯ ⎯ ±10 µA ⎯ Output voltage (2) “L” level VOL2 Output voltage (3) “L” level VOL3 Output open leakage current IOZ4 ⎯ ⎯ Unit V Note 12: DOUT, IFDO (normally output) 2 Note 13: IFDI (I C mode output) Note 14: IFOK, ERR (open drain output) 32 2005-09-28 TC94A04AFG/AFDG AC Characteristics AD Converter: LIN1 to LIN4, RIN1 to RIN4 Pins Symbol Test Circuit Test Condition Min Typ. Max Unit Maximum input signal level Vin ⎯ Input level that ADC output at full-scale digital output (Note 15) 1.27 1.33 ⎯ Vrms Input impedance Zin ⎯ Each of LIN1 to LIN4, RIN1 to RIN4 pins ⎯ 19 ⎯ kΩ S/Na1 ⎯ A-Weight, X’tal: 36.864 MHz (Note 15) 87 95 ⎯ dB S/Na2 ⎯ CCIR-ARM, X’tal: 36.864 MHz (Note 15) 83 91 ⎯ dB THD + N THDa ⎯ 20 kHz LPF, X’tal: 36.864 MHz (Note 15) ⎯ −82 −70 dB Cross-talk CTa ⎯ 20 kHz LPF, Lch → Rch/Rch → Lch, X’tal: 36.864 MHz (Note 15) ⎯ −80 −72 dB Dynamic range DRa ⎯ A-Weight, X’tal: 36.864 MHz 83 90 ⎯ dB Characteristics S/(N + D) ratio (Note 15) Note 15: One input pin selected of four selector of each channels. Selector Output: OUTL, OUTR Pins Symbol Test Circuit Test Condition Min Typ. Max Unit Output signal level Vout ⎯ 1 kHz, 1.122 Vrms input (Note 15) 0.9 1.0 1.12 Vrms Output impedance Zout ⎯ OUTL/OUTR pins ⎯ 0.5 ⎯ kΩ S/(N + D) ratio S/Ns ⎯ A-Weight 93 104 ⎯ dB THD + N THDs ⎯ 20 kHz LPF ⎯ −94 −80 dB ⎯ OUTL → OUTR/ OUTR → OUTL ⎯ −88 −80 dB Min Typ. Max Unit 1.22 1.27 1.37 Vrms Characteristics Cross-talk CTs Note 15: One input pin selected of four selectors of each channels. DA Converter Symbol Test Circuit Ao ⎯ Output voltage at full-scale digital input S/N ratio S/Nd ⎯ A-Weight, X’tal: 36.864 MHz 90 98 ⎯ dB THD + N THDd ⎯ 20 kHz LPF, X’tal: 36.864 MHz ⎯ −86 −75 dB Cross-talk CTd ⎯ 20 kHz LPF, X’tal: 36.864 MHz ⎯ −95 −83 dB Dynamic range DRd ⎯ A-Weight, X’tal: 36.864 MHz 87 95 ⎯ dB Characteristics Output signal level Test Condition 33 2005-09-28 TC94A04AFG/AFDG Timing Clock Input Pin (XI) Symbol Test Circuit Test Condition Min Typ. Max Unit tXI ⎯ ⎯ 27 ⎯ ⎯ ns Clock “H” cycle width tXIH ⎯ ⎯ ⎯ 13.5 ⎯ ns Clock “L” cycle width tXIL ⎯ ⎯ ⎯ 13.5 ⎯ ns Symbol Test Circuit Test Condition Min Typ. Max Unit Standby time tRRS ⎯ ⎯ 10 ⎯ ⎯ ms Reset pulse width tWRS ⎯ ⎯ 1.0 ⎯ ⎯ µs Min Typ. Max Unit Characteristics Clock cycle Reset Pin ( RST ) Characteristics Audio Serial Interface (EBCI/O, ELRI/O, DIN0 to 2, DOUT) Symbol Test Circuit tLIH ⎯ −75 ⎯ 75 ns DIN 0, 1, 2 setup time tSDI ⎯ 50 ⎯ ⎯ ns DIN 0, 1, 2 hold time tHDI ⎯ 50 ⎯ ⎯ ns tEBCI ⎯ 150 ⎯ ⎯ ns tEBIH ⎯ 75 ⎯ ⎯ ns tEBIL ⎯ 75 ⎯ ⎯ ns tLOH ⎯ CL = 30 pF 0 ⎯ 60 ns DOUT output delay time (1) tDO1 ⎯ CL = 30 pF ⎯ ⎯ 35 ns DOUT output delay time (2) tDO2 ⎯ CL = 30 pF ⎯ ⎯ 35 ns Characteristics ELRI/O hold time (ELRI/O input) EBCI/O clock cycle EBCI/O clock (ELRI/O input) “H” cycle width EBCI/O clock “L” clock width ELRI/O output delay time (ELRI/O output) Test Condition Unless than fs = 48 kHz, EBCI/O input: Unless than 64 fs 34 2005-09-28 TC94A04AFG/AFDG Microcontroller Interface (1) Standard transmission mode ( CS , IFCK, IFDI, IFDO) Symbol Test Circuit Test Condition Min Typ. Max Unit Standby time tSTB ⎯ ⎯ 1.0 ⎯ ⎯ µs CS ↓-IFCK ↓ setup time tCCD ⎯ ⎯ 0.2 ⎯ ⎯ µs IFCK “L” cycle width tWLC ⎯ ⎯ 0.25 ⎯ ⎯ µs IFCK “H” cycle width tWHC ⎯ ⎯ 0.25 ⎯ ⎯ µs IFCK ↑- CS ↑ setup time tCKC ⎯ ⎯ 0.25 ⎯ ⎯ µs CS “H” cycle width tWCS ⎯ 0.5 ⎯ ⎯ µs IFDI-IFCK ↑ setup time tSCD ⎯ ⎯ 0.2 ⎯ ⎯ µs IFCK ↑-IFDI holed time tHCD ⎯ ⎯ 0.2 ⎯ ⎯ µs IFCK ↓-IFDO propagation delay time tDDO ⎯ ⎯ ⎯ 0.2 µs Characteristics (Note 16) CL = 30 pF Note 16: The command which is “Sync” in the transfer Sync with Sync signal of a 14 page table 1 control command table needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command. (It needs more than 22.68 µs at fs = 44.1 KHz.) (2) I2C mode ( CS , IFCK, IFDI) Symbol Test Circuit IFCK clock frequency tIFCK ⎯ IFCK “H” cycle width tH Characteristics Test Condition Min Typ. Max Unit CL = 400 pF 0 ⎯ 400 kHz ⎯ CL = 400 pF 0.6 ⎯ ⎯ µs tL ⎯ CL = 400 pF 1.3 ⎯ ⎯ µs Data setup time tDS ⎯ CL = 400 pF 0.1 ⎯ ⎯ µs Data hold time tDH ⎯ CL = 400 pF 0 ⎯ ⎯ µs Transmission start condition hold time tSCH ⎯ CL = 400 pF 0.6 ⎯ ⎯ µs Repeat transmission start setup time tSCS ⎯ CL = 400 pF 0.6 ⎯ ⎯ µs Transmission end condition setup time tECS ⎯ CL = 400 pF 0.6 ⎯ ⎯ µs Data transmission interval tBUF ⎯ CL = 400 pF 1.3 ⎯ ⎯ µs tR ⎯ CL = 400 pF ⎯ ⎯ 0.3 µs tF ⎯ CL = 400 pF ⎯ ⎯ 0.3 µs IFCK “L” cycle width 2 I C rising time 2 I C falling time 35 2005-09-28 TC94A04AFG/AFDG AC Characteristic Measurement Point (1) Clock pin (XI) XI 50% tXIL tXIH tXI (2) Reset 100% 90% VDD 0% 50% RST tRRS (3) tWRS Audio serial interface (ELRI/O, EBCI/O, DIN0 to 2, DOUT) tEBCI tEBIL tEBIH ELRI/O (I) EBCI/O (I) DIN0∼2 tLIH tSDI tLIH tHDI tEBCO tEBOL tEBOH ELRI/O (O) EBCI/O (O) DOUT tLOH tDO2 tDO1 36 tLOH 2005-09-28 TC94A04AFG/AFDG (4) Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO) RST CS tSTB tWLC tCCD tWHC tCKC tWCS CS IFCK IFDI tSCD tHCD IFDO tDDO (5) Microcontroller interface in I2C mode (IFCK, IFDI) tBUF IFDI IFCK tSCH tR tL tH tDS 37 tDH tSCS tF tECS 2005-09-28 TC94A04AFG/AFDG Peripheral Circuit Example 1 The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. 47 µF 0.1 µF MCU I/F 4.7 µF 1 kΩ Lch (LIN4) 2200 pF 4.7 µF 1 kΩ 35 34 33 32 31 DIN1 DIN2 36 DIN0 37 VDD 38 DOUT ERR 39 RST 40 CS 41 IFDI 42 IFCK 43 IFDO 44 GND 45 I2CS 2200 pF TST0 Rch (RIN4) TST1 4.7 µF 1 kΩ 46 LIN4 EBCI/O (O) 30 47 LIN3 ELRI/O (O) 29 Lch (LIN3) 2200 pF 4.7 µF 1 kΩ 48 LIN2 SYNC 28 49 LIN1 GNDR 27 4.7 µF 1 kΩ 50 RIN4 VDDR 26 51 RIN3 GNDA4 25 47 µF 2200 pF 0.1 µF Rch (RIN3) Rch (RIN2) 2200 pF 0.1 µF 47 µF 4.7 µF 1 kΩ AOT4 22 55 OUTL VDA34 21 56 VRAL AOT3 20 57 VDALR AO3 19 47 µF 2200 pF Rch (RIN1) 54 GNDAL 47 µF 58 VRAR AI3 18 59 OUTR GNDA3 17 11 12 13 14 15 36.8 MHz 4.7 µF (BP) 0.1 µF 0.1 µF 47 µF 47 µF 47 µF 4.7 µF (BP) 2.2 MΩ 10 kΩ AOT1 (L1 out) 38 4.7 µF 2200 pF 10 kΩ AOT2 (R1 out) 10 kΩ 270 Ω Analog VDD Digital VDD Analog GND Digital GND 2200 pF 4.7 µF 270 Ω 270 Ω 2200 pF 4.7 µF 270 Ω 2200 pF 4.7 µF 47 pF 1000 pF 2.2 µH 10 pF 10 kΩ 10 µF 560 pF 47 µF OUTR 47 µF VRI 10 0.1 µF 47 µF 9 VRO1 8 GNDA2 7 AI2 6 AO2 5 AOT2 4 VDA12 GNDA1 3 AOT1 GNDX 2 AO1 XO 1 AI1 XI 10 µF VRO2 16 VDX 10 kΩ OUTL 560 pF 60 GNDAR 4.7 µF (BP) 4.7 µF 1 kΩ Lch (LIN1) 0.1 µF 47 µF 2200 pF 47 µF AO4 23 47 µF AI4 24 TC94A04AFG (top view) 53 RIN1 0.1 µF 52 RIN2 4.7 µF 1 kΩ 0.1 µF 2200 pF 4.7 µF (BP) Lch (LIN2) GND 10 kΩ AOT3 (L2 out) AOT4 (R2 out) 2005-09-28 TC94A04AFG/AFDG Peripheral Circuit Example 2 The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. 47 µF 4.7 µF 1 kΩ 0.1 µF MCU I/F Lch (LIN4) 2200 pF 4.7 µF 1 kΩ 52 NC TST1 TST0 GND I2CS ERR NC IFDO IFDI IFCK CS 51 50 49 48 47 46 45 44 43 42 41 EBCI/O (O) 53 NC 54 DIN2 55 NC 56 DIN1 57 NC 58 DIN0 59 VDD 60 DOUT 61 NC 62 RST 63 LIN4 4.7 µF 1 kΩ 64 NC 2200 pF NC Rch (RIN4) ELRI/O (O) 40 4.7 µF 1 kΩ SYNC 39 67 LIN2 GNDR 38 68 LIN1 VDDR 37 Rch (RIN3) 2200 pF 4.7 µF 1 kΩ 69 RIN4 NC 36 70 RIN3 GNDA4 35 47 µF 2200 pF 66 LIN3 0.1 µF Lch (LIN3) 71 RIN2 NC 34 72 RIN1 AI4 33 TC94A04AFDG (top view) Rch (RIN2) 2200 pF 73 NC AO4 32 NC 31 74 GNDAL 4.7 µF 1 kΩ Lch (LIN1) 47 µF 4.7 µF 1 kΩ 0.1 µF 2200 pF 4.7 µF (BP) Lch (LIN2) 75 OUTL AOT4 30 76 VRAL NC 29 79 VRAR AO3 26 80 OUTR AI3 25 19 20 21 0.1 µF 0.1 µF 47 µF 47 µF 23 24 36.8 MHz 2.2 MΩ 270 Ω 270 Ω 270 Ω 2200 pF 270 Ω 47 pF 1000 pF Analog VDD 2200 pF 2200 pF Digital VDD 2200 pF 4.7 µF 4.7 µF 4.7 µF +5 V 4.7 µF 2.2 µH 10 pF 10 kΩ 10 µF 22 560 pF 47 µF OUTR GNDA3 18 47 µF 17 4.7 µF (BP) NC 16 47 µF 4.7 µF (BP) VRO2 15 0.1 µF 47 µF 14 VRI 13 VRO1 12 NC 11 GNDA2 10 NC 9 AI2 AOT2 8 AO2 7 VDA12 6 NC 5 AOT1 GNDA1 4 NC NC 3 AO1 GNDX 2 AI1 XO 1 47 µF AOT3 27 47 µF XI 0.1 µF VDA34 28 78 VDALR VDX 10 µF 77 NC GNDAR 10 kΩ OUTL 560 pF 47 µF 2200 pF 0.1 µF 0.1 µF 47 µF 4.7 µF 1 kΩ Rch (RIN1) 4.7 µF (BP) 47 µF 2200 pF GND Analog GND 10 kΩ AOT1 (L1 out) 39 10 kΩ AOT2 (R1 out) 10 kΩ Digital GND 10 kΩ AOT3 (L2 out) AOT4 (R2 out) 2005-09-28 TC94A04AFG/AFDG Package Dimensions P-QFP60-1414-0.80N U n it: m m (Note) Palladium plate Weight: 1.08 g (typ.) 40 2005-09-28 TC94A04AFG/AFDG Package Dimensions P-QFP80 -1420-0.80M U n it: m m (Note) Palladium plate Weight: 1.57 g (typ.) 41 2005-09-28 TC94A04AFG/AFDG 42 2005-09-28