Intel® Server Boards S5000PSL
and S5000XSL
Technical Product Specification
Intel order number: D41763-005
Revision 1.4
November 2007
Enterprise Platforms and Services Division – Marketing
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL
Revision History
Revision History
Date
November 2005
Revision
Number
0.5
Modifications
March 2006
0.9
Updated all sections with the latest product information, updated illustrations,
added section for Regulatory/Certification, added appendix for Sensor Table,
POST Code Diagnostic LED’s, POST Code & Error Handling, Supported Chassis,
Added references for the S5000XSL.
May 2006
1.0
Updated the Server Board picture and Block Diagram, added information for
which slot the ROMB card goes into, added information on the HDD LED Header,
added information on the Snoop Filter, and cleaned other general things up in the
document.
September 2006
1.1
Updated legal disclaimer; Updated Processor Table; Updated Memory Section
September 2006
1.2
Updated Reference Documents
Aug 2007
1.3
Updated to reflect new processor support and new product codes where
applicable. Updated Sections 3.1, 3.1.3.4.2.3, 3.2.1.4, 3.2.1.5, 3.2.2.1, 3.5.2, 6.1.
Added 3.1..3.4.2.3. Updated Table 1, 2, 46; Updated Fig 2; Updated Appendix A
and Appendix E;
November 2007
1.4
Added board dimension to Table 1, Server Board Features; Corrected processor
naming convention; Removed Table 2, Processor Support Matrix; Corrected
Table 8, NIC Status LED; Removed unused BNB temp sensor from Table 46,
BMC Sensors.
Preliminary Draft
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's
Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any
express or implied warranty, relating to sale and / or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make
changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Intel® Server Boards S5000PSL and S5000XSL may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Refer to the Intel® Server Boards S5000PSL and
S5000XSL Specification Update for published errata.
Intel Corporation server baseboards contain a number of high-density VLSI and power delivery components that need
adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of
these components when the fully integrated system is used together. It is the responsibility of the system integrator
that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters
to determine the amount of air flow required for their specific application and environmental conditions. Intel
Corporation can not be held responsible if components fail or the server board does not operate correctly when used
outside any of their published operating or non-operating limits.
iii
Revision 1.4
Intel order number: D41763-005
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2006, 2007.
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Table of Contents
Table of Contents
1.
2.
3.
Introduction ........................................................................................................................ 13
1.1
Chapter Outline...................................................................................................... 13
1.2
Server Board Use Disclaimer ................................................................................ 13
Server Board Overview ...................................................................................................... 15
2.1
Server Board Feature Set...................................................................................... 15
2.2
Server Board Layout.............................................................................................. 17
2.2.1
Server Board Connector and Component Layout.................................................. 18
2.2.2
Server Board Mechanical Drawings ...................................................................... 20
2.2.3
Server Board ATX I/O Layout ................................................................................ 26
Functional Architecture ..................................................................................................... 27
3.1
Intel® 5000P / 5000X Memory Controller Hub (MCH) ............................................ 29
3.1.1
System Bus Interface............................................................................................. 29
3.1.2
Processor Support ................................................................................................. 29
3.1.3
Memory Sub-system .............................................................................................. 31
3.1.4
Snoop Filter (5000X MCH only) ............................................................................. 41
3.2
Enterprise South Bridge (ESB2-E) ........................................................................ 41
3.2.1
PCI Sub-system..................................................................................................... 42
3.2.2
Serial ATA Support ................................................................................................ 44
3.2.3
Parallel ATA (PATA) Support ................................................................................ 45
3.2.4
USB 2.0 Support.................................................................................................... 45
3.3
Video Support ........................................................................................................ 45
3.3.1
Video Modes.......................................................................................................... 47
3.3.2
Video Memory Interface......................................................................................... 47
3.3.3
Dual Video ............................................................................................................. 47
3.4
SAS Controller ....................................................................................................... 48
3.4.1
SAS RAID Support ................................................................................................ 48
3.4.2
SAS / SATA Connector Sharing ............................................................................ 48
3.5
Network Interface Controller (NIC) ........................................................................ 48
3.5.1
Intel® I/O Acceleration Technolgy .......................................................................... 49
3.5.2
MAC Address Definition......................................................................................... 49
3.6
3.6.1
Super I/O ............................................................................................................... 49
Serial Ports ............................................................................................................ 50
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Intel® Server Boards S5000PSL and S5000XSL TPS
3.6.2
Floppy Disk Controller ........................................................................................... 50
3.6.3
Keyboard and Mouse Support ............................................................................... 50
3.6.4
Wake-up Control.................................................................................................... 50
3.6.5
System Health Support.......................................................................................... 50
4.
Platform Management........................................................................................................ 51
5.
Connector / Header Locations and Pin-outs.................................................................... 53
5.1
Board Connector Information................................................................................. 53
5.2
Power Connectors ................................................................................................. 54
5.3
System Management Headers .............................................................................. 56
5.3.1
Intel® Remote Management Module (Intel® RMM) Connector ............................... 56
5.3.2
LCP / AUX IPMB Header ....................................................................................... 57
5.3.3
IPMB Header ......................................................................................................... 58
5.3.4
HSBP Header ........................................................................................................ 58
5.3.5
SGPIO Header....................................................................................................... 58
5.3.6
SES I2C.................................................................................................................. 58
5.3.7
HDD Activity LED Header ...................................................................................... 59
5.4
Front Panel Connector........................................................................................... 59
5.5
I/O Connectors....................................................................................................... 59
5.5.1
VGA Connector...................................................................................................... 59
5.5.2
NIC Connectors ..................................................................................................... 60
5.5.3
IDE Connector ....................................................................................................... 60
5.5.4
Intel® Remote Management Module NIC Connector ............................................. 61
5.5.5
SATA / SAS Connectors ........................................................................................ 63
5.5.6
Serial Port Connectors........................................................................................... 63
5.5.7
Keyboard and Mouse Connector ........................................................................... 64
5.5.8
USB Connector...................................................................................................... 65
5.6
6.
Jumper Blocks.................................................................................................................... 68
6.1
7.
Fan Headers .......................................................................................................... 66
CMOS Clear and Password Reset Usage Procedure ........................................... 69
6.1.1
Clearing the CMOS................................................................................................ 69
6.1.2
Clearing the Password........................................................................................... 69
6.2
BMC Force Update Procedure .............................................................................. 70
6.3
BIOS Select Jumper .............................................................................................. 70
Intel® Light Guided Diagnostics........................................................................................ 71
7.1
5 Volt Standby LED ............................................................................................... 71
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7.2
Fan Fault LEDs...................................................................................................... 72
7.3
System ID LED and System Status LED ............................................................... 73
7.3.1
8.
System Status LED – BMC Initialization ................................................................ 74
7.4
DIMM Fault LEDs .................................................................................................. 76
7.5
Processor Fault LEDs............................................................................................ 77
7.6
Post Code Diagnostic LEDs .................................................................................. 78
Design and Environmental Specifications....................................................................... 79
8.1
Server Boards S5000PSL and S5000XSL Design Specifications ......................... 79
8.2
Board-level Calculated MTBF................................................................................ 79
8.3
Server Board Power Requirements ....................................................................... 80
8.3.1
8.4
9.
Table of Contents
Processor Power Support...................................................................................... 81
Power Supply Output Requirements ..................................................................... 81
8.4.1
Grounding .............................................................................................................. 82
8.4.2
Standby Outputs .................................................................................................... 82
8.4.3
Remote Sense ....................................................................................................... 82
8.4.4
Voltage Regulation ................................................................................................ 83
8.4.5
Dynamic Loading ................................................................................................... 83
8.4.6
Capacitive Loading ................................................................................................ 84
8.4.7
Ripple / Noise ........................................................................................................ 84
8.4.8
Timing Requirements............................................................................................. 84
8.4.9
Residual Voltage Immunity in Standby Mode ........................................................ 87
Regulatory and Certification Information......................................................................... 88
9.1
Product Regulatory Compliance ............................................................................ 88
9.1.1
Product Safety Compliance ................................................................................... 88
9.1.2
Product EMC Compliance – Class A Compliance ................................................. 88
9.1.3
Certifications / Registrations / Declarations ........................................................... 89
9.2
Product Regulatory Compliance Markings ............................................................ 89
9.3
Electromagnetic Compatibility Notices .................................................................. 90
9.3.1
FCC Verification Statement (USA) ........................................................................ 90
9.3.2
ICES-003 (Canada) ............................................................................................... 90
9.3.3
Europe (CE Declaration of Conformity) ................................................................. 91
9.3.4
VCCI (Japan) ......................................................................................................... 91
9.3.5
BSMI (Taiwan) ....................................................................................................... 91
9.3.6
RRL (Korea)........................................................................................................... 91
9.3.7
CNCA (CCC-China) ............................................................................................... 92
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9.4
Intel® Server Boards S5000PSL and S5000XSL TPS
Restriction of Hazardous Substances (RoHS) Compliance................................... 92
Appendix A: Integration and Usage Tips................................................................................ 93
Appendix B: BMC Sensor Tables ............................................................................................ 94
Appendix C: POST Code Diagnostic LED Decoder ............................................................. 109
Appendix D: POST Code Errors ............................................................................................ 114
Appendix E: Supported Intel® Server Chassis ..................................................................... 117
Glossary................................................................................................................................... 118
Reference Documents ............................................................................................................ 121
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List of Figures
List of Figures
Figure 1. Server Board Photograph ............................................................................................ 17
Figure 2. Major Board Components............................................................................................ 19
Figure 3. Mounting Hole Positions .............................................................................................. 20
Figure 4. Component Positions................................................................................................... 21
Figure 5. Restricted Areas on Side 1 .......................................................................................... 22
Figure 6. Restricted Areas on Side 2 .......................................................................................... 23
Figure 7. Restricted Areas on Side 2, “Detail B” ......................................................................... 24
Figure 8. CPU and Memory Duct Keepout ................................................................................. 25
Figure 9. ATX I/O Layout ............................................................................................................ 26
Figure 10. Functional Block Diagram.......................................................................................... 28
Figure 11. CEK Processor Mounting .......................................................................................... 31
Figure 12. Memory Layout .......................................................................................................... 32
Figure 13. Minimum Two DIMM Memory Configuration.............................................................. 37
Figure 14. Recommended Four DIMM Configuration ................................................................. 38
Figure 15. Single Branch Mode Sparing DIMM Configuration .................................................... 40
Figure 16. SMBUS Block Diagram.............................................................................................. 52
Figure 17. Jumper Blocks (J1C3, J1D1, J1D2, J1E32) .............................................................. 68
Figure 18. 5 Volt Standby Status LED Location.......................................................................... 71
Figure 19. Fan Fault LED Locations ........................................................................................... 72
Figure 20. System ID LED and System Status LED Locations................................................... 73
Figure 21. DIMM Fault LED Locations........................................................................................ 76
Figure 22. Processor Fault LED Locations ................................................................................. 77
Figure 23. POST Code Diagnostic LED Location ....................................................................... 78
Figure 24. Power Distribution Block Diagram ............................................................................. 80
Figure 25. Output Voltage Timing ............................................................................................... 85
Figure 26. Turn On/Off Timing (Power Supply Signals).............................................................. 86
Figure 27. Diagnostic LED Placement Diagram ....................................................................... 109
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List of Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
List of Tables
Table 1. Server Board Features.................................................................................................. 15
Table 2. I2C Addresses for Memory Module SMB ...................................................................... 33
Table 3. Maximum Eight-DIMM System Memory Configruation – x8 Single Rank ..................... 34
Table 4. Maximum Eight-DIMM System Memory Configuration – x4 Dual Rank........................ 34
Table 5. PCI Bus Segment Characteristics................................................................................. 42
Table 6. Video Modes ................................................................................................................. 47
Table 7. NIC Status LED............................................................................................................. 48
Table 8. Serial B Header Pin-out ................................................................................................ 50
Table 9. Board Connector Matrix ................................................................................................ 53
Table 10. Power Connector Pin-out (J9B5) ................................................................................ 54
Table 11. 12 V Power Connector Pin-out (J3J2) ........................................................................ 55
Table 12. Power Supply Signal Connector Pin-out (J9D1) ......................................................... 55
Table 13. P12V4 Power Connector Pin-out (J5A2) .................................................................... 55
Table 14. RMM Connector Pin-out (J5B1).................................................................................. 56
Table 15. LPC / AUX IPMB Header Pin-out (J2J1)..................................................................... 57
Table 16. IPMB Header Pin-out (J4J1) ....................................................................................... 58
Table 17. HSBP Header Pin-out (J1J7, J1J2) ............................................................................ 58
Table 18. SGPIO Header Pin-out (J2H1, J1J5) .......................................................................... 58
Table 19. SES I2C Header Pin-out (J1J3)................................................................................... 58
Table 20. HDD Activity LED Header Pin-out (J2J3).................................................................... 59
Table 21. Front Panel SSI Standard 24-pin Connector Pin-out (J1E4) ...................................... 59
Table 22. VGA Connector Pin-out (J7A1)................................................................................... 59
Table 23. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA6A2)...................................... 60
Table 24. IDE 40-pin Connector Pin-out (J2J2) .......................................................................... 60
Table 25. 40-pin RMM NIC Module Connector Pin-out (J3B2) ................................................... 61
Table 26. SATA / SAS Connector Pin-out (J1J1, J1H2, J1H1, J1G2, J1G1, J1F2) ................... 63
Table 27. External DB9 Serial A Port Pin-out (J7A1).................................................................. 63
Table 28. Internal 9-pin Serial B Header Pin-out (J1B1)............................................................. 64
Table 29. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) ........................................... 64
Table 30. External USB Connector Pin-out (JA6A1, JA6A2) ...................................................... 65
Table 31. Internal USB Connector Pin-out (J3J1)....................................................................... 65
Table 32. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4)............................................ 66
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List of Tables
Table 33. SSI 6-pin Fan Header Pin-out (J3H1, J3H2, J3H3, J3H4).......................................... 66
Table 34. Server Board Jumpers (J1C3, J1D1, J1D2, J1E3) ..................................................... 68
Table 35. System Status LED..................................................................................................... 74
Table 36. Server Board Design Specifications ........................................................................... 79
Table 37. Intel® Xeon® Processor Dual Processor TDP Guidelines ........................................... 81
Table 38. 550 W Load Ratings ................................................................................................... 81
Table 39. Voltage Regulation Limits ........................................................................................... 83
Table 40. Transient Load Requirements..................................................................................... 83
Table 41. Capacitive Loading Conditions ................................................................................... 84
Table 42. Ripple and Noise......................................................................................................... 84
Table 43. Output Voltage Timing ................................................................................................ 85
Table 44. Turn On/Off Timing ..................................................................................................... 86
Table 45. BMC Sensors.............................................................................................................. 96
Table 46. POST Progress Code LED Example ........................................................................ 110
Table 47. Diagnostic LED POST Code Decoder ...................................................................... 110
Table 48. POST Error Messages and Handling........................................................................ 114
Table 49. POST Error Beep Codes .......................................................................................... 116
Table 50. BMC Beep Codes ..................................................................................................... 116
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List of Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
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1.
List of Tables
Introduction
This Technical Product Specification (TPS) provides board-specific information about the features, functionality, and high-level
architecture of the Intel® Server Boards S5000PSL and S5000XSL. See the Intel® S5000 Server Board Family Datasheet for details
about board sub-systems, including the chipset, BIOS, and server management.
In addition, design level information for specific sub-systems can be obtained by ordering the External Product Specifications (EPS)
for a given sub-system. EPS documents are not publicly available and must be ordered through your local Intel representative.
1.1
Chapter Outline
This document is divided into the following chapters
1.2
Chapter 1 – Introduction
Chapter 2 – Server Board Overview
Chapter 3 – Functional Architecture
Chapter 4 – Platform Management
Chapter 5 – Connector and Header Location and Pin-out
Chapter 6 – Configuration Jumpers
Chapter 7 – Light-Guided Diagnostics
Chapter 8 – Power and Environmental specifications
Chapter 9 – Regulatory and Certification Information
Appendix A – Integration and Usage Tips
Appendix B – BMC Sensor Tables
Appendix C – POST Code Diagnostic LED Decoder
Appendix D – POST Code Errors
Appendix E – Supported Intel® Server Chassis
Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is
the responsibility of the system integrator who chooses not to use Intel-developed server building blocks to consult vendor
datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental
conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used
outside any of their published operating or non-operating limits.
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2.
List of Tables
Server Board Overview
The Intel® Server Boards S5000PSL and S5000XSL are monolithic printed circuit boards with features that support the pedestal
server markets.
2.1
Server Board Feature Set
Table 1. Server Board Features
Feature
Server Board Dimension
Processors
Description
13.0 inches x12.0 inches (330.2 mm x 304.8 mm)
Socket J (771-pin LGA sockets) supporting one or two Multi-Core Intel® Xeon® processors 5000 sequence, with system bus speeds of
667 MHz, 1066 MHz, and 1333 MHz.
Only the product code ending with an ‘R’ support 45nm Dual-Core 2P Intel® Xeon® Processors or 45nm Quad-Core 2P Intel® Xeon®
Processors.
Memory
Eight DIMM sockets supporting fully buffered DIMM technology (FBDIMM) memory. 240-pin DDR2-533 and DDR2-677 FBDIMMs can
be used.
Chipset
Intel® 5000P Memory Controller Hub (Server Board S5000PSL only)
®
Intel 5000X Memory Controller Hub (Server Board S5000XSL only)
®
Intel ESB2-E I/O Controller
Add-in PCI, PCI-X*, PCI
Express* Cards
One full-length / full-height PCI-X 64-bit slot with up to 133-MHz support when only one PCI-X slot is populated
One full-length / full-height PCI-X 64-bit slot with up to 100 MHz support
One full-length / full-height PCI Express* x8 (x4 throughput)[1] or x8 (x8 throughput) slot [2]
One half-length / full-height PCI Express* x8 (x4 throughput) slot
Two full-length / full-height PCI Express* x16 (x8 throughput) slots
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Server Board Overview
Feature
Server Board Dimension
On-board
Connectors/Headers
Intel® Server Boards S5000PSL and S5000XSL TPS
Description
13.0 inches x12.0 inches (330.2 mm x 304.8 mm)
External connections:
Stacked PS/2* ports for keyboard and mouse
Stacked video / DB9 serial port A connector
Two RJ45 / 2xUSB connectors for 10 / 100 / 1000 Mb and USB 2.0 support
One USB 2x5 pin header, which supports two USB ports
One USB port Type A connector
One DH10 serial port B header
[2]
Six SATA-2 connectors with embedded RAID 0, 1, and 10 support . Software RAID 5 support through an optional SATA
[3]
Software RAID 5 KEY
Two SATA-2 connectors and four SAS/ SATA-2 connectors with embedded RAID 0, 1, and 10 support[1]. Software RAID 5
[3]
support through an optional SAS RAID KEY . The embedded SAS RAID supports up to 8 hard drives with expander backplane
One ATA100 40-pin connector
One RMM/RMM2 connector to support the optional Intel® Remote Management Module or Intel® Remote Management Module 2
One I/O connector supporting an optional RMM/RMM2 NIC I/O module
SSI-compliant front panel header
SSI-compliant 24-pin main power connector, supporting the ATX-12 V standard on the first 20 pins
Video
On-board ATI* ES1000 video controller with 16-MB DDR SDRAM
Hard Drive
Support for six SATA-2 hard drives
[4]
Support for four SAS/SATA-2 hard drives with non-expanded backplane .
LAN
Two 10 / 100 / 1000 Intel® 82563EB PHYs supporting Intel® I/O Acceleration Technology
Fans
Support for
Two processor fans
Four front hot-swap fans
Two rear system fans
Server Management
Support for Intel® System Management Software
Note 1: Available with product codes S5000PSLSAS/S5000PSLSASR, BB5000PSLSAS/BB5000PSLSASR
Note 2: Available with product codes S5000PSLSATA/S5000PSLSATAR, S5000PSLROMB/S5000PSLROMBR,
BB5000PSLSATA/BB5000PRLSATAR, BB5000PSLROMB/BB5000PSLROMBR, or BB5000XSLSATA/BB5000XSLSATAR
Note 3: The SATA software RAID 5 key is same as SAS software RAID 5 key, but install to different on-board connector.
Note 4: Available with product codes S5000PSLSAS/S5000PSASR, BB5000PSLSAS/BB5000PSLSASR,
S5000PSLROMB/S5000PSLROMBR, or BB5000PSLSROMB/BB5000PSLROMBR
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2.2
List of Tables
Server Board Layout
Figure 1. Server Board Photograph
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Server Board Overview
2.2.1
Intel® Server Boards S5000PSL and S5000XSL TPS
Server Board Connector and Component Layout
The following figure shows the board layout of the server board. Each connector and major component is identified by a letter. A
table of component descriptions follows the figure.
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A. PCI-X 64-bit, 100-MHz slot 1
List of Tables
Q. DIMM sockets
GG. Enclosure management SAS SES I2C
R. Processor 1 socket
HH. Hot-swap backplane A header
C. PCI Express* x4 / or PCI Express* x8
slot 3 (x8 physical connector)
S. Processor 2 socket
II. SATA 0
D. RMM/RMM2 NIC connector
T. Processor 2 fan header
JJ. SATA 1
E. PCI Express* x4 slot 4 (x8 physical
connector, ROMB Slot)
U. Processor 1 fan header
KK. SATA 2 or SAS 0
F. PCI Express x8 slot 5 (x16 physical
connector)
V. System fan 4 header
LL. SATA 3 or SAS 1
G. PCI Express x8 slot 6 (x16 physical
connector)
W. System fan 3 header
MM. SATA 4 or SAS 2
H. CMOS battery
X. IPMB connector
NN. SATA 5 or SAS 3
Y. System fan 2 header
OO. USB port
J. Connector for Intel Remote
Management Module or Intel® Remote
Management Module 2
Z. System fan 1 header
PP. Front control panel header
K. Back panel I/O ports
AA. Processor power connector
QQ. SATA software RAID 5 key connector
L. Diagnostic and identify LEDs
BB. USB header
RR. SAS software RAID 5 key connector
M. System fan 6 header
CC. IDE connector
SS. Serial B / emergency management port
header
N. System fan 5 header
DD. Enclosure management SATA SGPIO header
B. PCI-X 64-bit, 133-/100-MHz slot 2
[1]
I. P12V4 connector
®
[2]
[1]
[3]
[3]
[3]
[3]
[2]
[2]
[1]
TT. Chassis intrusion header
®
O. Main power connector
EE. Intel Local Control Panel header
P. Auxilliary power signal connector
FF. Hot-swap backplane B header
Note 1 : Available with product codes S5000PSLSAS/S5000PSLSASR, BB5000PSLSAS/BB5000XSLSASR
Note 2: Available with product codes S5000PSLSATA / S5000PSLSATAR, S5000PSLSROMB / S5000PSLROMBR, BB5000PSLSATA / BB5000PSLSATAR,
BB5000PSLROMB / BB5000PSLROMBR, or BB5000XSLSATA/BB5000XSLSATAR
Note 3: SAS connector available with product codes S5000PSLSAS/S5000PSLSASR, BB5000PSLSAS/BB5000XSLSASR
Figure 2. Major Board Components
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2.2.2
Intel® Server Boards S5000PSL and S5000XSL TPS
Server Board Mechanical Drawings
Figure 3. Mounting Hole Positions
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List of Tables
Figure 4. Component Positions
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
11.20
[ 0.441
304.80
[ 12.000
116.000
[ 4.5669
18.72
[ 0.737 ]
TYP
]
]
60.100
[ 2.3661
]
20.32
[ 0.800
TYP
HEATSINK DISSASEMBLY AREA,
.275" [8.26mm] MAX COMPONENT
HEIGHT RESTRICTION, 4 PLACES
]
]
IMM3 COMPONENT
HEIGHT 3.6 MM
Ø 10.160
[ 0.4000 ]
GROUND PAD BOTH SIDES
NO COMPONENT
8 PLCS
72.800
[ 2.8661
]
.433" [14mm] MAX COMPONENT
HEIGHT RESTRICTION
301.50
[ 11.870
TYP
311.66
[ 12.270
TYP
322.40
[ 12.693
TYP
326.57
[ 12.857
TYP
330.20
[ 13.000
]
SOCKET AREA, NO COMPONENT
PLACEMENT ALLOWED, 2 PLACES
]
]
]
]
93.98
[ 3.700
6.35
[ 0.250
60.96
[ 2.400
5.33
[ 0.210 ]
TYP
7.92
[ 0.312 ]
TYP
16.05
[ 0.632 ]
TYP
]
]
22.86
]
3
.118" [3.81mm] MAX COMPONENT
HEIGHT RESTRICTION, 2 PLACES
HEATSINK AREA. .325" [8.26mm] MAX
COMPONENT HEIGHT RESTRICTIO, 2 PLACES
MAX HEIGHT OF COMPONENTS AND MATING COMPONENTS
SHALL NOT EXCEED 15.24mm [.600"]
Figure 5. Restricted Areas on Side 1
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LIMITED COMPONENT HEIGHT
.058" MAXIMUM 13 PLACES
2X 3.120
[ 0.1228
78.74
[ 3.100
7.620
[ 0.3000
TYP
20.320
[ 0.8000
]
]
]
]
SEE DETAIL B
20.320
[ 0.8000 ]
11 PLCS
3
R 25.40
[ 1.000
TYP
]
2X 8.000
[ 0.3150
2X 0.350
[ 0.0138
]
]
NO COMPONENTS ALLOWED
TRACES OKAY IN THIS REGION
5.08
[ 0.200 ]
TYP
R 14.730
[ 0.5799
66.554
[ 2.6202
]
TYP
]
177.80
[ 7.000
]
Ø 10.160
GROUND PAD
[ 0.4000 ]
NO COMPONENT
1 PLACE
.100 [2.54<<] MAX COMPONENT
HEIGHT IN THESE ZONES
2
96.52
[ 3.800
]
57.15
[ 2.250
12.07
[ 0.475
]
]
7.62
[ 0.300
]
5.08
[ 0.200
17.78
[ 0.700
]
]
12.70
[ 0.500
5.08
[ 0.200
]
]
NO COMPONENTS
THIS ZONE 16 PLCS
CEK HEATSINK SPRING PLATE ZONE
NO COMPONENT PLACEMENT OR
THROUGH HOLE LEADS ALLOWED
Figure 6. Restricted Areas on Side 2
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5.00
[ 0.197
3X 4.00
[ 0.157
]
5.00
[ 0.197
]
]
3X 3.00
[ 0.118
3X 10.13
[ 0.399
]
]
CHASSIS ID PADS
Figure 7. Restricted Areas on Side 2, “Detail B”
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288.290 [11.3500]
273.091 [10.7516]
188.152 [7.4076]
193.152 [7.6044]
List of Tables
0.000 [0.0000]
16.510 [0.6500]
Intel® Server Boards S5000PSL and S5000XSL TPS
10.160 [0.4000]
0.000 [0.0000]
14.0mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
26.635
[1.0486]
26.578 [1.0464]
SUPPORT AREA,
NO COMPONENT
ALLOWED
111.351 [4.3839]
118.351
[4.6595]
14.0mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
SUPPORT AREA,
NO COMPONENT
ALLOWED
145.600 [5.7323]
43.302 [1.7048]
16.5mm COMPONENT HEIGHT
LIMIT DEFINE BY DUCT DETAIL
73.482
[2.8930]
97.846
[3.8522]
1.25mm COMPONENT HEIGHT
LIMIT DEFINE BY DUCT DETAIL
143.732
[5.6588]
143.136 [5.6353]
NO COMPONENT ALLOWED
194.152
[7.6438]
154.685 [6.0900]
178.578 [7.0306]
187.152
[7.3682]
15.0mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
168.123 [6.6190]
235.085 [9.2553]
9.0 mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
27.0 mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
101.402 [3.9922]
112.851 [4.4430]
107.920 [4.2488]
13.0 mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
317.580 [12.5032]
117.851 [4.6398]
320.040
[12.6000]
282.585
[11.1254]
Figure 8. CPU and Memory Duct Keepout
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2.2.3
Intel® Server Boards S5000PSL and S5000XSL TPS
Server Board ATX I/O Layout
The drawing below shows the layout of the rear I/O components for the server board.
A
C
B
D
E
G
F
H
AF000222
A. PS/2 mouse
E. NIC port 1 (1 Gb)
B. PS/2 keyboard
F. USB port 2 (top), 3 (bottom)
C. Serial port
G. NIC port 2 (1 Gb)
D. Video
H. USB port 0 (top), 1 (bottom)
Figure 9. ATX I/O Layout
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3.
List of Tables
Functional Architecture
The architecture and design of the Intel® Server Boards S5000PSL and S5000XSL are based on the Intel® S5000P and S5000X
chipsets respectively. These chipsets are designed for systems that use the Intel® Multi-Core Xeon® processor with system bus
speeds of 667 MHz, 1066 MHz, and 1333 MHz.
The chipset contains two main components: the Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the
I/O sub-system. The chipset uses the Enterprise South Bridge (ESB2-E) for the I/O controller hub. This chapter provides a high-level
description of the functionality associated with each chipset component and the architectural blocks that make up the server board.
For more information about the functional architecture blocks, see the Intel® S5000 Server Board Family Datasheet.
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Figure 10. Functional Block Diagram
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3.1
List of Tables
Intel® 5000P / 5000X Memory Controller Hub (MCH)
The Memory Controller Hub (MCH) is a single 1432-pin FCBGA package, which includes the following core platform functions:
System Bus Interface for the processor sub-system
Memory Controller
PCI-Express Ports including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBUS Interface
This section provides a high-level overview of some of these core functions as they pertain to this server board. Additional
information can be obtained from the Intel S5000 Server Board Family Datasheet and the Intel 5000 Series Chipset Memory
Controller Hub Datasheet.
3.1.1
System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the MultiCore Intel® Xeon® processors. Each front side bus on the MCH uses a 64-bit wide 667-, 1066-, or 1333-MHz data bus. The 1333MHz data bus is capable of transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of
addressing up to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one
processor on each bus.
3.1.2
Processor Support
The server board supports the following processors:
• One or two Dual-Core Intel® Xeon® Processors 5000 series with a 667-, 1066-, or 1333-MHz front side bus with frequencies
starting at 2.67GHz.
• One or two Dual-Core Intel® Xeon® Processors 5100 series with a 1066- , or 1333-MHz front side bus with frequencies starting
at 1.60GHz.
• One or two Dual-Core Intel® Xeon® Processors 5300 series with a 1066-, or 1333-MHz front side bus with frequencies starting at
1.60GHz.
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• One or two Dual-Core Intel® Xeon® Processors 5200 series with a 1066-, or 1333-MHz front side bus with frequencies starting at
1.86GHz. – only product code ending with “R” supports this processor series.
• One or two Quad-Core Intel® Xeon® Processors 5400 series with a 1066-, or 1333-MHz front side bus with frequencies starting
at 2.33GHz. – only product code ending with “R” supports this processor series.
Previous generations of the Intel® Xeon® Processors are not supported on the server board. See the following table for a detailed list
of supported Multi-Core Intel® Xeon® Processors. See http://support.intel.com/support/motherboards/server/s5000psl/ for a complete
updated list of supported processors. On the Support tab, look for “Compatibility” and then “Supported processor list”.
Note: Only Intel® multi-core Xeon processors with 667MHz, 1066MHz or 1333MHz front side bus are supported.
3.1.2.1
Processor Population Rules
When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. When only one processor is
installed, it must be in the socket labeled CPU1. The other socket must be empty.
The board is designed to provide up to 130A of current per processor. Processors with higher current requirements are not
supported.
No terminator is required in the second processor socket when using a single processor configuration.
3.1.2.2
Common Enabling Kit (CEK) Design Support
The server board complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink retention solution. The server
board ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heatsink
attaches to the CEK, over the top of the processor and the thermal interface material (TIM). See the figure below for the stacking
order of the chassis, CEK spring, server board, TIM, and heatsink.
The CEK spring is removable, allowing for the use of non-Intel heatsink retention solutions.
Note: The processor heat sink and CEK spring shown in the following diagram are for reference purposes only. The actual
processor heat sink and CEK solutions compatible with this generation server board may be of a different design.
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Heatsink assembly
Thermal Interface
Material (TIM)
Server Board
TP02091
CEK Spring
Chassis
AF000196
Figure 11. CEK Processor Mounting
3.1.3
Memory Sub-system
The MCH masters four fully buffered DIMM (FBD) memory channels. FBD memory utilizes a narrow high speed frame oriented
interface referred to as a channel. The four FBD channels are organized into two branches of two channels per branch. Each branch
is supported by a separate memory controller. The two channels on each branch operate in lock-step to increase FBD bandwidth.
The four channels are routed to eight DIMM sockets and are capable of supporting registered DDR2-533 and DDR2-667 FBDIMM
memory (stacked or unstacked). The read bandwidth of each FBDIMM channel 4.25 GB/s for DDR2-533 FBDIMM memory which
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gives a total read bandwidth of 17 GB/s for four DIMM channels. The read bandwidth of each FBDIMM channel 5.35 GB/s for DDR2667 FBDIMM memory which gives a total read bandwidth of 21.4 GB/s for four DIMM channels.
On the Intel® Server Boards S5000PSL and S5000XSL, a pair of channels becomes a branch where Branch 0 consists of channels A
and B, and Branch 1 consists of channels C and D. FBD memory channels are organized into two branches for support of RAID 1
(mirroring).
Channel B
Channel C
Channel A
Channel D
H
MC
1
M A A2
M
I
D
M
DIM M B1 2
DIM M B 1
DIM M C 2
DIM M C 1
DIM M D 2
DIM M D
DIM
Branch 0
Branch 1
TP02299
Figure 12. Memory Layout
To boot the system, the system BIOS on the server board uses a dedicated I2C bus to retrieve DIMM information needed to program
the MCH memory registers. The following table provides the I2C addresses for each DIMM socket.
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Table 2. I2C Addresses for Memory Module SMB
3.1.3.1
Device
DIMM A1
Address
0xA0
DIMM A2
0xA2
DIMM B1
0xA0
DIMM B2
0xA2
DIMM C1
0xA0
DIMM C2
0xA2
DIMM D1
0xA0
DIMM D2
0xA2
Memory RASUM Features
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features. These
features include the Intel® x4 Single Device Data Correction (Intel® x4 SDDC) for the following:
Memory error detection and correction
Memory scrubbing
Retry on correctable errors
Memory built-in self-test
DIMM sparing
Memory mirroring
See the Intel® S5000 Server Board Family Datasheet for more information about these features.
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3.1.3.2
Intel® Server Boards S5000PSL and S5000XSL TPS
Supported Memory
The server board supports up to eight DDR2-533 or DDR2-667 fully-buffered DIMMs (FBD memory). The following tables show the
maximum memory configurations supported with the specified memory technology.
Table 3. Maximum Eight-DIMM System Memory Configruation – x8 Single Rank
DRAM Technology
x8 Single Rank
256 Mb
Maximum Capacity
Mirrored Mode
1 GB
Maximum Capacity
Non-mirrored Mode
2 GB
512 Mb
2 GB
4 GB
1024 Mb
4 GB
8 GB
2048 Mb
8 GB
16 GB
Table 4. Maximum Eight-DIMM System Memory Configuration – x4 Dual Rank
DRAM Technology
x4 Dual Rank
256 Mb
Maximum Capacity
Mirrored Mode
4 GB
Maximum Capacity
Non-mirrored Mode
8 GB
512 Mb
8 GB
16 GB
1024 Mb
16 GB
32 GB
2048 Mb
16 GB
32 GB
Note: Only fully buffered DDR2 DIMMs (FBDIMMs) are supported on this server board. See the Intel® Server Board
S5000PSL/S5000XSL Tested Memory List for a list of supported memory for this server board.
3.1.3.3
DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller, which is determined by the number of DIMMs
installed. DIMMs must be populated in pairs. DIMM pairs are populated in the following DIMM slot order: A1 & B1, C1 & D1, A2 &
B2, C2 & D2. DIMMs within a given pair must be identical with respect to size, speed, and organization. However, DIMM capacities
can be different between different DIMM pairs.
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For example, a valid mixed DIMM configuration may have 512MB DIMMs installed in DIMM Slots A1 & B1, and 1GB DIMMs installed
in DIMM slots C1 & D1.
Intel supported DIMM configurations for this server board are shown in the following table.
Supported and Validated configuration : Slot is populated
Supported but not validated configuration : Slot is
populated
Slot is not populated
Mirroring:
Sparing:
Y = Yes. Indicates that configuration supports Memory Mirroring.
Y(x) = Yes. Indicates that configuration supports Memory Sparing.
Where x = 0 : Sparing supported on Branch0 only
1 : Sparing supported on Branch1 only
0,1 : Sparing supported on both branches
Branch 0
Channel A
DIMM_A1
DIMM_A2
Branch 1
Channel B
DIMM_B1
DIMM B2
Channel C
DIMM C1
Channel D
DIMM C2
DIMM D1
Mirroring
Possible
Sparing
Possible
DIMM D2
Y (0)
Y
Y (0)
Y
Y (0, 1)
Notes:
- Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1.
- The supported memory configurations must meet population rules defined above.
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Intel® Server Boards S5000PSL and S5000XSL TPS
For best performance, the number of DIMMs installed should be balanced across both memory branches. For Example: a four
DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1.
An eight DIMM configuration will perform better then a six DIMM configuration.
Although mixed DIMM capacities between channels is supported, Intel does not validate DIMMs in mixed DIMM configurations.
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3.1.3.3.1
Design and Environmental Specifications
Minimum Non-Mirrored Mode Configuration
The server board is capable of supporting a minimum of one DIMM installed. However, for
system performance reasons, Intel’s recommendation is that at least 2 DIMMs be installed.
The following diagram shows the recommended minimum DIMM memory configuration.
Populated DIMM slots are shown in Grey.
Channel B
Channel C
Channel A
Channel D
H
MC
1
M A A2
M
I
D
M
DIM M B1 2
DIM M B 1
DIM M C 2
DIM M C 1
DIM M D 2
DIM M D
DIM
Branch 0
Branch 1
TP02300
Figure 13. Minimum Two DIMM Memory Configuration
Note: The server board supports single DIMM mode operation. Intel will only validate and
support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1.
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3.1.3.4
Intel® Server Boards S5000PSL and S5000XSL TPS
Non-mirrored Mode Memory Upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the
same slot position on both channels. DIMMs pairs must be identical with respect to size, speed,
and organization. DIMMs that cover adjacent slot positions do not need to be identical.
When adding two DIMMs to the configuration shown in Figure 13 (above), the DIMMs should be
populated in DIMM sockets C1 and D1 as shown in the following diagram. Populated DIMM
sockets are shown in Grey.
Channel B
Channel C
Channel A
Channel D
H
MC
1
MA
DIM M A2 1
DIM M B 2
DIM M B 1
DIM M C 2
DIM M C 1
DIM M D 2
DIM M D
DIM
Branch 0
Branch 1
TP02301
Figure 14. Recommended Four DIMM Configuration
Functionally, DIMM sockets A2 and B2 could also have been populated instead of DIMM
sockets C1 and D1. However, your system will not achieve equivalent performance. Figure 13,
on the previous page, shows the supported DIMM configuration that is recommended because it
allows both branches to operate independently and simultaneously. FBD bandwidth is doubled
when both branches operate in parallel.
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3.1.3.4.1
Design and Environmental Specifications
Mirrored Mode Memory Configuration
When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch
1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support
memory mirroring is four DIMMs, populated as shown in Figure 14, above. All four DIMMs must
be identical with respect to size, speed, and organization.
To upgrade a four DIMM mirrored memory configuration, four additional DIMMs must be added
to the system. All four DIMMs in the second set must be identical to the first with the exception
of speed. The MCH will adjust to the lowest speed DIMM.
3.1.3.4.2
Sparing Mode Memory Configuration
The MCH provides memory sparing capabilities. Sparing is a RAS feature that involves
configuring a DIMM to be placed in reserve so it can be use to replace a DIMM that fails. DIMM
sparing occurs within a given bank of memory and is not supported across branches. There are
two supported Memory Sparing configurations.
Single Branch Mode Sparing
Dual Branch Mode Sparing
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3.1.3.4.2.1
Intel® Server Boards S5000PSL and S5000XSL TPS
Single Branch Mode Sparing
Slot 2
DIMM_A2
DIMM_B2
DIMM_C2
DIMM_D2
Slot 1
DIMM_A1
DIMM_B1
DIMM_C1
DIMM_D1
Channel B
Channel C
Channel D
Channel A
Branch 0
Branch 1
Intel® 5000P/5000X Memory Controller Hub
Figure 15. Single Branch Mode Sparing DIMM Configuration
DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.
DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.
DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.
Sparing should be enabled in BIOS setup.
The BIOS will configure Rank Sparing Mode.
The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} will be
selected as the spare pair unit.
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Design and Environmental Specifications
3.1.3.4.2.2
Dual Branch Mode Sparing
Dual branch mode sparing requires that all eight DIMM sockets be populated and must comply
with the following population rules.
DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.
DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
DIMM_C1 and DIMM_D1 must be identical in organization, size and speed.
DIMM_C2 and DIMM_D2 must be identical in organization, size and speed.
DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.
DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.
DIMM_C1 and DIMM_C2 need not be identical in organization, size and speed.
DIMM_D1 and DIMM_D2 need not be identical in organization, size and speed.
Sparing should be enabled in BIOS setup.
The BIOS will configure Rank Sparing Mode.
The larger of the pairs {DIMM_A1, DIMM_B1}, {DIMM_A2, DIMM_B2},
{DIMM_C1, DIMM_D1}, and {DIMM_C2, DIMM_D2} are selected as the spare pair units.
3.1.3.4.2.3
Dual-Ranked DIMM Sparing
When a dual-ranked FBDIMM is used as a spare, the BIOS has the ability to independently
select a physical rank on that FBDIMM as the spare unit and utilize the other physical rank as a
normal unit. This selective sparing ensures maximization of available memory while still
providing RAS. However, populating differently-ranked FBDIMMs for sparing is not a good
practice and may yield unpredictable results.
3.1.4
Snoop Filter (5000X MCH only)
The 5000X version of the MCH includes a snoop filter. Depending on the application of the
server, this feature can be used to enhance the performance of the server by eliminating traffic
on the snooped system bus of the processor being snooped. By removing snoops form the
snooped bus, the full bandwidth is available for other transactions.
3.2
Enterprise South Bridge (ESB2-E)
The ESB2-E is a multi-function device that provides four distinct functions: an I/O controller, a
PCI-X* bridge, a GB Ethernet controller, and a baseboard management controller (BMC). Each
function has its own set of configuration registers. Once configured, each appears to the system
as a distinct hardware controller.
The ESB2-E provides the gateway to all PC-compatible I/O devices and features. The server
boards use the following ESB2-E features:
PCI-X bus interface
Six-channel SATA interface with SATA Busy LED Control
Dual GbE MAC
Baseboard Management Controller (BMC)
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Design and Environmental Specifications
Intel® Server Boards S5000PSL and S5000XSL TPS
Single ATA interface, with Ultra DMA 100 capability
Universal Serial Bus 2.0 (USB) interface
Removable media drives
LPC bus interface
PC-compatible timer/counter and DMA controllers
APIC and 8259 interrupt controller
Power management
System RTC
General purpose I/O
This section describes the function of most of the listed features as they pertain to these server
boards. For more detail information, see the Intel S5000 Server Board Family Datasheet or the
Intel 631xESB/632xESB I/O Controller Hub Datasheet.
3.2.1
PCI Sub-system
The primary I/O buses for the server board are PCI, PCI Express*, and PCI-X,* with six
independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification,
Revision 2.3. The table below lists the characteristics of the PCI bus segments. Details about
each bus segment follow the table.
Table 5. PCI Bus Segment Characteristics
PCI Bus Segment
PCI32
ESB2-E
Voltage
3.3 V
Width
32 bit
Speed
33 MHz
Type
PCI
PCI I/O Card Slots
None. Used internally for video controller
PXA
ESB2-E
3.3 V / 5.0 V
64 bit
100 MHz
PCI-X*
PCI-X Slot 1
PXA
ESB2-E
3.3 V / 5.0 V
64 bit
133 MHz
PCI-X*
PCI-X Slot 2
PE0
ESB2-E PCI
Express* Port0
3.3 V
X4
10 Gb/S
PCI
Express*
X4 throughput PCI Express* Slot 4
(Special keyed for ROMB card)
PE1
ESB2-E PCI
Express* Port1
3.3 V
X4
10 Gb/S
PCI
Express
x4 throughput PCI Express* Slot 3 (SAS
SKU); x8 throughput PCI Express* Slot 3
by combining PE2 and PE1 (SATA and
ROMB SKU)
PE2
ESB2-E PCI
Express* Port2
3.3 V
X4
10 Gb/S
PCI
Express
x4 throughput to onboard SAS (re-routed
to Slot 3 in SATA SKU or ROMB SKU)
PE4, PE5
BNB PCI Express*
Ports 4, 5
3.3 V
X8
20 Gb/S
PCI
Express
X8 throughput PCI Express* Slot 5
PE6, PE7
BNB PCI Express*
Ports 6, 7
3.3 V
X8
20 Gb/S
PCI
Express
X8 throughput PCI Express* Slot 6
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Intel® Server Boards S5000PSL and S5000XSL TPS
3.2.1.1
Design and Environmental Specifications
PCI32: 32-bit, 33-MHz PCI Sub-system
All 32-bit, 33-MHz PCI I/O is directed through the ESB2-E ICH6. The 32-bit, 33-MHz PCI
segment created by the ESB2-E-ICH6 is known as the PCI32 segment. The PCI32 segment
supports the following embedded devices:
2D Graphics Accelerator: ATI* ES1000 Video Controller
3.2.1.2
PXA: 64-bit, 133-MHz PCI Sub-system
One 64-bit PCI-X bus segment is directed through the ESB2-E ICH6. This PCI-X segment, PXA,
is routed to PCI-X Slots 1 and 2. With only one PCI-X adapter populated in Slot 2 and Slot 1 left
empty, PCI-X Slot 2 supports a maximum speed of 133MHz. With both Slot 1 and Slot 2
populated, Slot 2 supports a maximum speed of 100MHz. PCI-X Slot 1 supports a maximum
speed of 100MHz even when Slot 2 is not populated.
3.2.1.3
PE0: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment,
PE0, is routed to PCI Express* Slot 4 that is special keyed to support ROMB card.
3.2.1.4
PE1: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment,
PE1, is routed to PCI Express* Slot 3. This becomes a x8 PCI Express* bus segment by
combining PE2 with PE1 for SATA server board or ROMB server board that do not have onboard SAS controller.
3.2.1.5
PE2: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment,
PE2, is routed to PCI Express* Slot 3 for server boards that do not have on-board SAS
controller (SATA server board or ROMB server board), or to the onboard SAS controller for
server boards that do have on-board SAS controller (SAS server board).
3.2.1.6
PE4, PE5: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express*
segments, PE4 and PE5, are routed to PCI Express* Slot 5.
3.2.1.7
PE6, PE7: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express*
segments, PE6 and PE7, are routed to PCI Express* Slot 6.
3.2.1.8
PCI Express* Riser Slot
PCI Express* Slot 6 supports 3rd party riser cards for both 1U and 2U system configurations.
Two PCI Express* pins are designated as Riser Type pins with the definitions noted in the table
below.
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SLOT 6 SETUP
1
Intel® Server Boards S5000PSL and S5000XSL TPS
LP Riser TYPE 1
GPI:
ESB2 GPI 28
PCI-E Pin: B48 [RSVD]
0
1
2U Riser, 2 x4 PCI Express* Slots2
1U Riser, 1 x8 PCI Express* Slot3
LP Riser Type 0
GPI:
ESB2 GPI 27
PCI-E Pin: B49 [GND]
1
0
Notes:
1 The server board contains a weak pull-up resistor on the two Riser Type nets.
2 The 2U riser card needs to pull-down the PCI Express* pin B48 with a 0 ohm resistor
and leave as a No-Connect (NC) PCI Express* pin B49.
3 The 1U riser card needs to follow the standard PCI Express* Adapter pin-out by leaving
pin B48 as a No-Connect (NC) and pin B49 as ground.
The following table provides the supported bus throughput for the given riser card used and the
number of add-in cards installed.
PCI Express* Slot 6 Riser
Support
1U Riser Card
2U Riser Card
1 add-in card
X8
X4
2 add-in cards
NA
X4
Note: There are no population rules for installing a single add-in card in the 2U riser card; a
single add in card can be installed in either PCI Express* slot.
3.2.2
Serial ATA Support
The ESB2-E has an integrated Serial ATA (SATA) controller that supports independent DMA
operation on six ports and supports data transfer rates of up to 3.0 Gb/s. The six SATA ports on
the server board are numbered SATA-0 thru SATA-5. The SATA ports can be enabled/disabled
and/or configured by accessing the BIOS Setup utility during POST.
3.2.2.1
Intel® Embedded Server RAID Technology II Support
The onboard storage capability of this server board includes support for Intel® Embedded
Server RAID Technology which provides three standard software RAID levels: data stripping
(RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring (RAID Level
10). For higher performance, data stripping can be used to alleviate disk bottlenecks by taking
advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is
used for data security. Should a disk fail, a mirrored copy of the failed disk is brought on-line.
There is no loss of either PCI resources (request/grant pair) or add-in card slots.
With the addition of an optional Intel RAID Activation Key, Intel® Embedded Server RAID
Technology is also capable of providing fault tolerant data stripping (software RAID Level 5),
such that if a SATA hard drive should fail, the lost data can be restored on a replacement drive
from the other drives that make up the RAID 5 pack.
See Figure 2 Major Board Components for the location of Intel RAID Activation Key connector
location.
Intel® Embedded Server RAID Technology functionality requires the following items:
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•
•
•
•
Design and Environmental Specifications
Intel® ESB-2 IO Controller Hub
Intel® Embedded Server RAID Technology Option ROM
Intel® Embedded Server RAID Technology II drivers, most recent revision
At least two SATA hard disk drives
Intel® Embedded Server RAID Technology is not available in the following configurations:
•
•
The SATA controller in Legacy mode or AHCI mode
Intel® Embedded Server RAID Technology II has been disabled
Intel® Embedded Server RAID Technology Option ROM
3.2.2.2
The Intel® Embedded Server RAID Technology for SATA Option ROM provides a pre-OS user
interface for the Intel® Embedded Server RAID Technology implementation and provides the
ability for an Intel® Embedded Server RAID Technology volume to be used as a boot disk as
well as to detect any faults in the Intel® Embedded Server RAID Technology volume(s) attached
to the Intel® RAID controller.
3.2.3
Parallel ATA (PATA) Support
The integrated IDE controller of the ESB2-E ICH6 provides one IDE channel. It redefines
signals on the IDE cable to allow both host and target throttling of data and transfer rates of up
to 100 MB/s. For this server board, the IDE channel was designed to provide optical drive
support to the platform. The BIOS initializes and supports ATAPI devices such as LS-120/240,
CD-ROM, CD-RW and DVD-ROM. The IDE channel is accessed through a single standard 40pin IDE connector (J2J2) that provides the I/O signals. The ATA channel can be configured and
enabled or disabled by accessing the BIOS Setup utility during POST.
3.2.4
USB 2.0 Support
The USB controller functionality integrated into ESB2-E provides the server board with the
interface for up to eight USB 2.0 ports. Four external connectors are located on the back edge
of the server board. One internal 2x5 header (J3J1) is provided, capable of supporting two
optional USB 2.0 ports. One USB port Type A connector (J3G1) is provided to support
installation of a USB device inside the server chassis. An additional USB port is dedicated to the
Intel® Remote Management Module (Intel® RMM) connector.
3.3
Video Support
The server board provides an ATI* ES1000 PCI graphics accelerator, along with 16 MB of video
DDR SDRAM and support circuitry for an embedded SVGA video sub-system. The ATI ES1000
chip contains an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin
BGA. One 4M x 16 x 4-bank DDR SDRAM chip provides 16 MB of video memory.
The SVGA sub-system supports a variety of modes, up to 1024 x 768 resolution in 8 / 16 /
32 bpp modes under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical
refresh rate.
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Intel® Server Boards S5000PSL and S5000XSL TPS
Video is accessed using a standard 15-pin VGA connector found on the back edge of the server
board. The on-board video controller can be disabled using the BIOS Setup Utility or when an
add-in video card is installed. The system BIOS provides the option for dual-video operation
when an add-in video card is configured in the system.
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3.3.1
Design and Environmental Specifications
Video Modes
The ATI* ES1000 chip supports all standard IBM* VGA modes. The following table shows the
2D modes supported for both CRT and LCD.
Table 6. Video Modes
2D Mode
Refresh Rate (Hz)
8 bpp
Supported
2D Video Mode Support
16 bpp
32 bpp
Supported
Supported
640x480
60, 72, 75, 85, 90,
100, 120, 160, 200
800x600
60, 70, 72, 75, 85,
90, 100, 120,160
Supported
Supported
Supported
1024x768
60, 70, 72,
75,85,90,100
Supported
Supported
Supported
1152x864
43,47,60,70,75,80,85
Supported
Supported
Supported
1280x1024
60,70,74,75
Supported
Supported
Supported
1600x1200
52
Supported
Supported
Supported
3.3.2
Video Memory Interface
The memory controller sub-system of the ES1000 arbitrates requests from the direct memory
interface, the VGA graphics controller, the drawing co-processor, the display controller, the
video scalar, and the hardware cursor. Requests are serviced in a manner that ensures display
integrity and maximum CPU/co-processor drawing performance.
The server board supports a 16 MB (4 Meg x 16-bit x 4 banks) DDR SDRAM device for video
memory.
3.3.3
Dual Video
The BIOS supports single- and dual-video modes. The dual-video mode is enabled by default.
In single mode (Dual Monitor Video = disabled), the on-board video controller is disabled
when an add-in video card is detected.
In dual mode (On-board Video = enabled, Dual Monitor Video = enabled), the on-board
video controller is enabled and will be the primary video device. The external video card
will be allocated resources and is considered the secondary video device. The BIOS
Setup utility provides options to configure the feature as follows.
On-board Video
Enabled
Disabled
Dual Monitor Video
Enabled
Disabled
Shaded if on-board video is set to "Disabled"
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3.4
Intel® Server Boards S5000PSL and S5000XSL TPS
SAS Controller
The SAS1064e controller supports x4 PCI Express* link widths and is a single-function PCI
Express end-point device. The SAS controller supports the SAS protocol as described in the
Serial Attached SCSI Standard, version 1.0. The controller also supports SAS 1.1 features.
The SAS1064e controller supports a 32-bit external memory bus that provides an interface for
Flash ROM and NVSRAM devices.
3.4.1
SAS RAID Support
RAID modes 0, 1, and 10 are supported. An optional SAS RAID Key can be used to support SW
RAID 5. Support up to four hard drives with non-expander backplane or support up to eight hard
drives with expander backplane.
3.4.2
SAS / SATA Connector Sharing
Four SATA connectors are shared between SATA and SAS, depending on the version of the
server board. For SAS server boards, four of the six SATA connectors are used for SAS
functionality. For SATA server boards, all six SATA connectors are used for SATA functionality.
3.5
Network Interface Controller (NIC)
Network interface support is provided from the built in Dual GbE MAC features of the ESB2 in
®
conjunction with the Intel 82563EB compact Physical Layer Transceiver (PHY). Together, they
provide the server board with support for dual LAN ports designed for 10/100/1000 Mbps
operation.
The 82563EB device is based upon proven PHY technology integrated into Intel’s gigabit
Ethernet controllers. The physical layer circuitry provides a standard IEEE 802.3 Ethernet
interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and
802.3ab). The 82563EB device is capable of transmitting and receiving data at rates of
1000 Mbps, 100 Mbps, or 10 Mbps.
Each network interface controller (NIC) drives two LEDs located on each network interface
connector. The link / activity LED (at the right of the connector) indicates network connection
when on, and transmit / receive activity when blinking. The speed LED (at the left of the
connector) indicates 1000-Mbps operation when amber, 100-Mbps operation when green, and
10-Mbps when off. The table below provides an overview of the LEDs.
Table 7. NIC Status LED
LED Color
Green/Amber (Right)
Green (Left)
LED State
NIC State
Off
10 Mbps
Green
100 Mbps
Amber
1000 Mbps
On
Active Connection
Blinking
Transmit / Receive activity
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Design and Environmental Specifications
Intel® I/O Acceleration Technolgy
3.5.1
®
Intel I/O Acceleration Technology moves network data more efficiently through Dual-Core
Intel® Xeon® processor 5000 sequence-based servers for improved application responsiveness
across diverse operating systems and virtualized environments. Intel® I/OAT improves network
application responsiveness by unleashing the power of Dual-Core Intel® Xeon® processors 5000
sequence through more efficient network data movement and reduced system overhead. Intel
multi-port network adapters with Intel® I/OAT provide high-performance I/O for server
consolidation and virtualization via stateless network acceleration that seamlessly scales across
multiple ports and virtual machines. Intel® I/OAT provides safe and flexible network acceleration
through tight integration into popular operating systems & virtual machine monitors, avoiding the
support risks of 3rd-party network stacks and preserving existing network requirements such as
teaming and failover.
3.5.2
MAC Address Definition
Each Intel® Server Board S5000PSL / S5000XSL has four MAC addresses assigned to it at the
Intel factory. During the manufacturing process, each server board will have a white MAC
address sticker placed on the board. The sticker will display the MAC address in both bar code
and alpha numeric formats. The printed MAC address is assigned to NIC 1 on the server board.
NIC 2 is assigned the NIC 1 MAC address + 1.
Two additional MAC addresses are assigned to the Baseboard Management Controller (BMC)
embedded in the ESB-2. These MAC addresses are used by the BMC’s embedded network
stack to enable IPMI remote management over LAN. BMC LAN Channel 1 is assigned the NIC1
MAC address + 2, and BMC LAN Channel 2 is assigned the NIC2 MAC address + 2
3.6 Super I/O
Legacy I/O support is provided by using a National Semiconductor* PC87427 Super I/O device.
This chip contains all of the necessary circuitry to support the following functions:
GPIOs
Two serial ports
Keyboard and mouse support
Wake up control
System health support
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3.6.1
Intel® Server Boards S5000PSL and S5000XSL TPS
Serial Ports
The server board provides two serial ports: an external DB9 serial port and an internal DH10
serial header. The rear DB9 serial A port is a fully-functional serial port that can support any
standard serial device.
Serial B is an optional port that is accessed through a 9-pin internal DH-10 header. A standard
DH10 to DB9 cable can be used to direct serial B to the rear of a chassis. The serial B interface
follows the standard RS232 pin-out as defined in the following table.
Table 8. Serial B Header Pin-out
Pin
1
3.6.2
Signal Name
Serial Port B Header Pin-out
DCD
2
DSR
3
RX
4
RTS
5
TX
6
CTS
7
DTR
8
RI
9
GND
Floppy Disk Controller
The server board does not support a floppy disk controller interface. However, the system BIOS
recognizes USB floppy devices.
3.6.3
Keyboard and Mouse Support
Dual-stacked PS/2* ports are provided on the back edge of the server board for keyboard and
mouse support. Either port can support a mouse or keyboard. Neither port supports hot
plugging.
3.6.4
Wake-up Control
The super I/O contains functionality that allows various events to power on and power off the
system.
3.6.5
System Health Support
The super I/O provides an interface via GPIOs for BIOS and system management firmware to
activate the diagnostic LEDs, the FRU fault indicator LEDs for processors, FBDIMMS, fans and
the system status LED. See section 7 for the location of the LEDs on the server board.
The super I/O provides PMW fan control to the system fans, monitors tach and presence signals
for the system fans and monitors server board and front panel temperature.
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4.
Design and Environmental Specifications
Platform Management
The platform management sub-system is based on the integrated Baseboard Management
Controller features of the ESB2-E. The on-board platform management sub-system consists of
communication buses, sensors, system BIOS, and server management firmware. The following
diagram provides an overview of the Server Management Bus (SMBUS) architecture used on
this server board.
See Appendix B for on-board sensor data.
For more detailed platform management information, see the Intel® S5000 Server Board Family
Datasheet.
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Intel® Server Boards S5000PSL and S5000XSL TPS
Figure 16. SMBUS Block Diagram
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Design and Environmental Specifications
5.
Connector / Header Locations and Pin-outs
5.1
Board Connector Information
The following section provides detailed information regarding all connectors, headers and
jumpers on the server board. Table 9. Board Connector Matrix
Lists all connector types available on the board and the corresponding reference designators
printed on the silkscreen.
Table 9. Board Connector Matrix
Connector
Quantity
Reference Designators
Connector Type
Power supply
4
J9B5
J3J2
J9D1
J5A2
Main power
CPU power
P/S aux / IPMB
P12V4 power
Pin
Count
24
8
5
4
CPU
2
J8G1, J5G1
CPU sockets
771
Main memory
8
J7B1, J7B2, J7B3, J8B1, J8B2, J8B3, J9B1, J9B2
DIMM sockets
240
PCI-X
2
J1B2, J2B1
Card edge
PCI Express* x8
2
J2B2, J3B1
Card edge
PCI Express* x16
2
J4B2, J4B1
Card edge
Intel® RMM
1
J5B1
Mezzanine
120
RMM NIC
1
J3B2
Mezzanine
40
RAID Key
2
J1E1, J1D3
Key holder
3
IDE
1
J2J2
Shrouded header
40
System fans
4
J3H1, J3H2, J3H3, J3H4
Header
6
System fans
2
J9B3, J9B4
Header
4
CPU fans
2
J9J1, J5J1
Header
4
Battery
1
XBT4D1
Battery holder
3
Keyboard / mouse
1
J9A1
PS2, stacked
12
Stacked RJ45 /
2xUSB
2
JA6A1, JA6A2
External LAN
built-in magnetic
and dual USB
22
Stacked video /
verial port A
1
J7A1
External DSub /
DB9
24
Serial port B
1
J1B1
Header
10
Front panel
1
J1E4
Header
24
Internal USB
1
J3J1
Header
10
Internal USB
1
J3G1
Type A
connector
4
Chassis Intrusion
1
J1A1
Header
2
Serial ATA / SAS
6
J1G1, J1F2, J1H1, J1G2, J1J1, J1H2
Header
7
HSBP / SGPIO
4
J1J2, J1J7, J2H1, J1J5
Header
4
SES I2C
1
J1J3
Header
3
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Connector
LCP/AUX IPMB
1
J2J1
Header
Pin
Count
4
IPMB
1
J4J1
Header
3
HDD Activity
1
J2J3
Header
2
Configuration
jumpers
4
J1D2 (Password Clear), J1D1 (CMOS Clear), J1C3
(BIOS Bank Select), J1E3 (BMC Force Update)
Jumper
3
5.2
Quantity
Intel® Server Boards S5000PSL and S5000XSL TPS
Reference Designators
Connector Type
Power Connectors
The main power supply connection uses an SSI-compliant 2x12 pin connector (J9B5). In
addition, there are three additional power related connectors:
One SSI-compliant 2x4 pin power connector (J3J2) provides 12V power to the CPU
Voltage Regulators
One SSI-compliant 1x5 pin connector (J9D1) provides I2C monitoring of the power
supply
One SSI-compliant 2x2 pin connector (J5A2) provides additional 12V power to the
server board
The following tables define the connector pin-outs.
Table 10. Power Connector Pin-out (J9B5)
Pin
1
Signal
+3.3 Vdc
Color
Orange
Pin
13
Signal
+3.3 Vdc
Color
Orange
2
+3.3 Vdc
Orange
14
-12 Vdc
Blue
3
GND
Black
15
GND
Black
4
+5 Vdc
Red
16
PS_ON#
Green
5
GND
Black
17
GND
Black
6
+5 Vdc
Red
18
GND
Black
7
GND
Black
19
GND
Black
8
PWR_OK
Gray
20
RSVD_(-5 V)
White
9
5 VSB
Purple
21
+5 Vdc
Red
10
+12 Vdc
Yellow
22
+5 Vdc
Red
11
+12 Vdc
Yellow
23
+5 Vdc
Red
12
+3.3 Vdc
Orange
24
GND
Black
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Design and Environmental Specifications
Table 11. 12 V Power Connector Pin-out (J3J2)
Pin
1
Signal
GND
Color
Black
2
GND
Black
3
GND
Black
4
GND
Black
5
+12 Vdc
Yellow / black
6
+12 Vdc
Yellow / black
7
+12 Vdc
Yellow / black
8
+12 Vdc
Yellow / black
Table 12. Power Supply Signal Connector Pin-out (J9D1)
Pin
Signal
1
SMB_CLK_ESB_FP_PWR_R
Color
Orange
2
SMB_DAT_ESB_FP_PWR_R
Black
3
SMB_ALRT_3_ESB_R
Red
4
3.3 V SENSE-
Yellow
5
3.3 V SENSE+
Green
Table 13. P12V4 Power Connector Pin-out (J5A2)
Pin
1
GND
Signal
Color
Black
2
GND
Black
3
+12 Vdc
Yellow / black
4
+12 Vdc
Yellow / black
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5.3
5.3.1
Intel® Server Boards S5000PSL and S5000XSL TPS
System Management Headers
Intel® Remote Management Module (Intel® RMM) Connector
A 120-pin Intel® RMM connector (J5B1) is included on the server board to support the optional
Intel® Remote Management Module. There is no support for third party ASMI cards on this
server board.
Note: This connector is not compatible with the Intel® Server Management Module Professional
Edition (Product Code AXXIMMPRO) or the Intel® Server Management Module Advanced
Edition (Product Code AXXIMMADV).
Table 14. RMM Connector Pin-out (J5B1)
Pin
1
Signal Name
Reserved - NC
Pin
2
Signal Name
GND
3
ESB_PLT_RST_G1_N
4
Reserved - NC
5
GND
6
Reserved - NC
7
Reserved - NC
8
GND
9
Reserved - NC
10
GND
11
GND
12
Reserved - NC
13
GND
14
IRQ_SERIAL_R
15
USB_ESB_P7P
16
GND
17
USB_ESB_P7N
18
GND
19
GND
20
Reserved - NC
21
P3V3
22
Reserved - NC
23
LPC_LAD<0>
24
GND
25
LPC_LAD<1>
26
LPC_FRAME_N
27
P3V3
28
LPC_LAD<2>
29
LPC_LCLK
30
LPC_LAD<3>
31
P3V3
32
P3V3
33
SMB_1_3V3SB_MS_DAT
34
SMB_IPMB_3V3SB_DAT
35
SMB_1_3V3SB_SL_DAT
36
SMB_IPMB_3V3SB_CLK
37
SMB_1_3V3SB_MS_CLK
38
SMB_0_3V3SB_MS_CLK
39
SMB_1_3V3SB_INT
40
SMB_0_3V3SB_INT
41
P3V3_AUX
42
SMB_0_3V3SB_MS_DAT
43
SPB_IMM_DSR_N
44
SMB_0_3V3SB_SL_DAT
45
SPB_IMM_RTS_N
46
P3V3_AUX
47
SPB_IMM_CTS_N
48
FM_IMM_PRESENT_N
49
SPB_IMM_DCD_N
50
SPB_IMM_DTR_N
51
SPB_RI_N
52
SPB_IMM_SIN
53
SPB_IMM_SOUT
54
P3V3_AUX
55
P3V3_AUX
56
V_LCDDATA7
57
V_LCDCNTL3
56
V_LCDDATA6
59
P3V3_AUX
60
V_LCDDATA5
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5.3.2
Design and Environmental Specifications
Pin
61
Signal Name
Reserved - NC
Pin
62
Signal Name
V_LCDDATA4
63
Reserved - NC
64
V_LCDDATA3
65
GND
66
V_LCDCNTL1
67
V_LCDCNTL0
68
GND
69
Reserved - NC
70
V_LCDDATA15
71
GND
72
V_LCDDATA714
73
V_LCDDATA23
74
V_LCDDATA13
75
V_LCDDATA22
76
V_LCDDATA12
77
V_LCDDATA21
78
V_LCDDATA11
79
V_LCDDATA20
80
GND
81
V_LCDDATA19
82
V_LCDCNTL2
83
GND
84
V_DVO_DDC_SDA
85
FM_MAN_LAN_TYPE1
86
V_DVO_DDC_SCL
87
FM_MAN_LAN_TYPE2
88
RST_PS_PWRGD
89
Reserved - NC
90
Reserved - NC
91
Reserved - NC
92
Reserved - NC
93
MII_MDC_RMII_SPARE
94
Reserved - NC
95
MII_COL_RMIIB_RXER
96
GND
97
GND
98
MII_CRS_RMIIB_CRS
99
MII_TXER_RMIIB_TXEN
100
MII_TXCLK_RMIIB_RXCLK
101
MII_MDIO_RMIIB_PRESENT
102
GND
103
GND
104
MII_TXD3_RMIIB_TXD1
105
MII_RXD3_RMIIB_RXD1
106
MII_TXD2_RMIIB_TXD0
107
MII_RXD2_RMIIB_RXD0
108
GND
109
GND
110
MII_TXD1_RMIIA_TXD1
111
MII_RXD1_RMIIA_RXD1
112
MII_TXD0_RMIIA_TXD0
113
MII_RXD0_RMIIA_RXD0
114
GND
115
GND
116
MII_TXEN_RMIIA_TXEN
117
MII_RXCLK
118
MII_RXER_RMIIA_TXER
119
MII_RXDV_RMIIA_CRS
120
GND
LCP / AUX IPMB Header
Table 15. LPC / AUX IPMB Header Pin-out (J2J1)
Pin
1
Signal Name
SMB_IPMB_5VSB_DAT
Description
BMC IMB 5V standby data line
2
GND
Ground
3
SMB_IPMB_5VSB_CLK
BMC IMB 5V standby clock line
4
P5V_STBY
+5 V standby power
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5.3.3
Intel® Server Boards S5000PSL and S5000XSL TPS
IPMB Header
Table 16. IPMB Header Pin-out (J4J1)
5.3.4
Pin
1
Signal Name
SMB_IPMB_5VSB_DAT
Description
BMC IMB 5V Standby Data Line
2
GND
Ground
3
SMB_IPMB_5VSB_CLK
BMC IMB 5V Standby Clock Line
HSBP Header
Table 17. HSBP Header Pin-out (J1J7, J1J2)
Pin
5.3.5
1
Signal Name
SMB_IPMB_5V_DAT
Description
BMC IMB 5V Data Line
2
GND
Ground
3
SMB_IPMB_5V_CLK
BMC IMB 5V Clock Line
4
GND – HSBP_A
P5V – HSBP_B
Ground for HSBP A
+5V for HSBP B
SGPIO Header
Table 18. SGPIO Header Pin-out (J2H1, J1J5)
5.3.6
Pin
1
Signal Name
SGPIO_CLOCK
Description
SGPIO Clock Signal
2
SGPIO_LOAD
SGPIO Load Signal
3
SGPIO_DATAOUT
SGPIO Data Out
4
SGPIO_DATAIN
SGPIO Data In
SES I2C
Table 19. SES I2C Header Pin-out (J1J3)
1
Pin
Signal Name
SMB_SAS_3V3_DAT
Description
BMC SAS 3V Data Line
2
GND
Ground
3
SMB_SAS_3V3_CLK
BMC SAS 3V Clock Line
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5.3.7
Design and Environmental Specifications
HDD Activity LED Header
Table 20. HDD Activity LED Header Pin-out (J2J3)
Pin
5.4
1
Signal Name
LED_SCSI_CONN_N
Description
HDD Activity LED Input
2
GND
Ground
Front Panel Connector
The server board provides a 24-pin SSI front panel connector (J1E4) for use with Intel® and
third-party chassis. The following table provides the pin-out for this connector.
Table 21. Front Panel SSI Standard 24-pin Connector Pin-out (J1E4)
Pin
5.5
1
Signal Name
P3V3_STBY
2
Pin
Signal Name
P3V3_STBY
3
Key
4
P5V_STBY
5
FP_PWR_LED_N
6
FP_ID_LED_BUF_N
7
P3V3
8
FP_LED_STATUS_GREEN_N
9
LED_HDD_ACTIVITY_N
10
FP_LED_STATUS_A MBER_N
11
FP_PWR_BTN_N
12
NIC1_ACT_LED_N
13
GND
14
NIC1_LINK_LED_N
15
BMC_RST_BTN_N
16
SMB_SENSOR_3V3STB_DATA
17
GND
18
SMB_SENSOR_3V3STB_CLK
19
FP_ID_BTN_N
20
FP_CHASSIS_INTRU
21
FM_SIO_TEMP_SENSOR
22
NIC2_ACT_LED_N
23
FP_NMI_BTN_N
24
NIC2_LINK_LED_N
I/O Connectors
5.5.1
VGA Connector
The following table details the pin-out definition of the VGA connector (J7A1) that is part of the
stacked video / serial port A connector.
Table 22. VGA Connector Pin-out (J7A1)
1
Pin
Signal Name
V_IO_R_CONN
Description
Red (analog color signal R)
2
V_IO_G_CONN
Green (analog color signal G)
3
V_IO_B_CONN
Blue (analog color signal B)
4
TP_VID_CONN_B4
No connection
5
GND
Ground
6
GND
Ground
7
GND
Ground
8
GND
Ground
9
TP_VID_CONN_B9
No connection
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5.5.2
Intel® Server Boards S5000PSL and S5000XSL TPS
Pin
10
GND
Signal Name
Ground
Description
11
TP_VID_CONN_B11
No connection
12
V_IO_DDCDAT
DDCDAT
13
V_IO_HSYNC_CONN
HSYNC (horizontal sync)
14
V_IO_VSYNC_CONN
VSYNC (vertical sync)
15
V_IO_DDCCLK
DDCCLK
NIC Connectors
The server board provides two stacked RJ45 / 2xUSB connectors side-by-side on the back
edge of the board (JA6A1, JA6A2). The pin-out for NIC connectors are identical and are defined
in the following table.
Table 23. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA6A2)
Pin
5.5.3
Signal Name
1
GND
2
P1V8_NIC
3
NIC_A_MDI3P
4
NIC_A_MDI3N
5
NIC_A_MDI2P
6
NIC_A_MDI2N
7
NIC_A_MDI1P
8
NIC_A_MDI1N
9
NIC_A_MDI0P
10
NIC_A_MDI0N
11 (D1)
NIC_LINKA_1000_N (LED
12 (D2)
NIC_LINKA_100_N (LED)
13 (D3)
NIC_ACT_LED_N
14
NIC_LINK_LED_N
15
GND
16
GND
IDE Connector
The server board provides one legacy IDE ATA100 40-pin connector (J2J2). The pin-out is
defined in the following table.
Table 24. IDE 40-pin Connector Pin-out (J2J2)
1
Pin
Signal Name
ESB_PLT_RST_IDE_N
2
Pin
GND
Signal Name
3
RIDE_DD_7
4
RIDE_DD_8
5
RIDE_DD_6
6
RIDE_DD_9
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Pin
Design and Environmental Specifications
7
Signal Name
RIDE_DD_5
8
Pin
Signal Name
RIDE_DD_10
9
RIDE_DD_4
10
RIDE_DD_11
11
RIDE_DD_3
12
RIDE_DD_12
13
RIDE_DD_2
14
RIDE_DD_13
15
RIDE_DD_1
16
RIDE_DD_14
17
RIDE_DD_0
18
RIDE_DD_15
19
GND
20
KEY
21
RIDE_DDREQ
22
GND
23
RIDE_DIOW_N
24
GND
25
RIDE_DIOR_N
26
GND
27
RIDE_PIORDY
28
GND
29
RIDE_DDACK_N
30
GND
31
IRQ_IDE
32
TP_PIDE_32
33
RIDE_DA1
34
IDE_PRI_CBLSNS
35
RIDE_DA0
36
RIDE_DA2
37
RIDE_DCS1_N
38
RIDE_DCS3_N
39
LED_IDE_N
40
GND
Intel® Remote Management Module NIC Connector
5.5.4
The server board provides an internal 40-pin connector (J3B2) to accommodate a proprietary
form factor Intel® Remote Management Module NIC module. The following table details the pinout of the Intel® RMM NIC module connector.
Table 25. 40-pin RMM NIC Module Connector Pin-out (J3B2)
1
Pin
Signal Name
FM_MAN_LAN_TYPE2
2
Pin
Signal Name
FM_MAN_LAN_TYPE1
3
P3V3_AUX
4
MII_MDIO_RMIIB_PRESENT
5
P3V3_AUX
6
MII_MDC_RMII_SPARE
7
GND
8
MII_RXD3_RMIIB_RXD1
9
GND
10
MII_RXD2_RMIIB_RXD0
11
GND
12
MII_RXD1_RMIIA_RXD1
13
GND
14
MII_RXD0_RMIIA_RXD0
15
GND
16
MII_RXDV_RMIIA_CRS
17
GND
18
MII_RXCLK
19
GND
20
MII_RXER_RMIIA_RXER
21
GND
22
KEY
23
GND
24
MII_TXCLK_RMIIB_RXCLK
25
GND
26
MII_TXEN_RMIIA_TXEN
27
GND
28
MII_TXD0_RMIIA_TXD0
29
GND
30
MII_TXD1_RMIIA_TXD1
31
GND
32
MII_TXD2_RMIIB_TXD0
33
GND
34
MII_TXD3_RMIIB_TXD1
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Intel® Server Boards S5000PSL and S5000XSL TPS
Pin
35
Signal Name
P3V3_AUX
Pin
36
Signal Name
MII_COL_RMIIB_RXER
37
P3V3_AUX
38
MII_CRS_RMIIB_CRS
39
P3V3_AUX
40
MII_TXER_RMIIB_TXEN
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5.5.5
Design and Environmental Specifications
SATA / SAS Connectors
The server board provides up to six SATA / SAS connectors:
SATA-0 (J1J1)
SATA-1 (J1H2)
SATA-2 / SAS-0 (J1H1)
SATA-3 / SAS-1 (J1G2)
SATA-4 / SAS-2 (J1G1)
SATA-5 / SAS-3 (J1F2)
The pin configuration for each connector is identical and is defined in the following table.
Table 26. SATA / SAS Connector Pin-out (J1J1, J1H2, J1H1, J1G2, J1G1, J1F2)
Pin
1
5.5.6
Signal Name
GND
Description
Ground
2
SATA/SAS_TX_P_C
Positive side of transmit differential pair
3
SATA/SAS_TX_N_C
Negative side of transmit differential pair
4
GND
Ground
5
SATA/SAS_RX_N_C
Negative side of receive differential pair
6
SATA/SAS_RX_P_C
Positive side of receive differential pair
7
GND
Ground
Serial Port Connectors
The server board provides one external DB9 Serial A port (J7A1) and one internal 9-pin serial B
header (J1B1). The following tables define the pin-outs.
Table 27. External DB9 Serial A Port Pin-out (J7A1)
1
Pin
Signal Name
SPA_DCD
Description
DCD (carrier detect)
2
SPA_SIN_L
RXD (receive data)
3
SPA_SOUT_N
TXD (Transmit data)
4
SPA_DTR
DTR (Data terminal ready)
5
GND
Ground
6
SPA_DSR
DSR (data set ready)
7
SPA_RTS
RTS (request to send)
8
SPA_CTS
CTS (clear to send)
9
SPA_RI
RI (Ring Indicate)
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Intel® Server Boards S5000PSL and S5000XSL TPS
Table 28. Internal 9-pin Serial B Header Pin-out (J1B1)
5.5.7
Pin
1
Signal Name
SPB_DCD
Description
DCD (carrier detect)
2
SPB_DSR
DSR (data set ready)
3
SPB_SIN_L
RXD (receive data)
4
SPB_RTS
RTS (request to send)
5
SPB_SOUT_N
TXD (Transmit data)
6
SPB_CTS
CTS (clear to send)
7
SPB_DTR
DTR (Data terminal ready)
8
SPB_RI
RI (Ring indicate)
9
SPB_EN_N
Enable
Keyboard and Mouse Connector
Two stacked PS/2* ports (J9A1) support a keyboard and a mouse. Either PS/2 port can support
a mouse or keyboard. The following table details the pin-out of the PS/2 connectors.
Table 29. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1)
Pin
1
Signal Name
KB_DATA_F
Description
Keyboard data
2
TP_PS2_2
Test point – keyboard
3
GND
Ground
4
P5V_KB_F
Keyboard / mouse power
5
KB_CLK_F
Keyboard clock
6
TP_PS2_6
Test point – keyboard / mouse
7
MS_DAT_F
Mouse data
8
TP_PS2_8
Test point – keyboard / mouse
9
GND
Ground
10
P5V_KB_F
Keyboard / mouse power
11
MS_CLK_F
Mouse clock
12
TP_PS2_12
Test point – keyboard / mouse
13
GND
Ground
14
GND
Ground
15
GND
Ground
16
GND
Ground
17
GND
Ground
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5.5.8
Design and Environmental Specifications
USB Connector
The following table details the pin-out of the external USB connectors (JA6A1, JA6A2) found on
the back edge of the server board.
Table 30. External USB Connector Pin-out (JA6A1, JA6A2)
Pin
1
Signal Name
USB_OC
Description
2
USB_PN
DATAL0 (Differential data line paired with DATAH0)
3
USB_PP
DATAH0 (Differential data line paired with DATAL0)
4
GND
Ground
USB_PWR
One 2x5 connector on the server board (J3J1) provides an option to support an additional two
USB ports. The pin-out of the connector is detailed in the following table.
Table 31. Internal USB Connector Pin-out (J3J1)
Pin
1
Signal Name
USB2_VBUS5
Description
USB power (port 5)
2
USB2_VBUS4
USB power (port 4)
3
USB_ESB_P5N_CONN
USB port 5 negative signal
4
USB_ESB_P4N_CONN
USB port 4 negative signal
5
USB_ESB_P5P_CONN
USB port 5 positive signal
6
USB_ESB_P4P_CONN
USB port 4 positive signal
7
Ground
8
Ground
9
Key
No pin
10
TP_USB_ESB_NC
Test point
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5.6
Intel® Server Boards S5000PSL and S5000XSL TPS
Fan Headers
The server board provides four SSI-compliant 4-pin and four SSI-compliant 6-pin fan headers to
be used as CPU, and IO cooling fans. 3-pin fans are supported on all fan headers. 6-pin fans
are supported on header J3H4, J3H3, J3H2, and J3H1. 4-pin fans are supported on header
J9J1, J5J1, J3H4, J3H3, J9B4, and J9B3. 4-pin fans are not supported on header J3H2, and
J3H1, since these headers are tied to the CPU1 PWM. These fan headers should also not be
used for CPU cooling fans. The pin configuration for each of the 4-pin and 6-pin fan headers is
identical and is defined in the following tables.
Two 4-pin fan headers are designated as processor cooling fans:
- CPU1 fan (J9J1)
- CPU2 fan (J5J1)
Four 6-pin fan headers are designated as hot-swap system fans:
- Hot-swap system fan 1 (J3H4)
- Hot-swap system fan 2 (J3H3)
- Hot-swap system fan 3 (J3H2)
- Hot-swap system fan 4 (J3H1)
Two 4-pin fan headers are designated as rear system fans:
-
System fan 5 (J9B4)
System fan 6 (J9B3)
Table 32. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4)
1
Pin
Signal Name
Ground
Type
GND
Description
Ground is the power supply ground
2
12V
Power
Power supply 12 V
3
Fan Tach
In
FAN_TACH signal is connected to the BMC to monitor the fan speed
4
Fan PWM
Out
FAN_PWM signal to control fan speed
Table 33. SSI 6-pin Fan Header Pin-out (J3H1, J3H2, J3H3, J3H4)
1
Pin
Signal Name
Ground
Type
GND
Description
Ground is the power supply ground
2
12V
Power
Power supply 12 V
3
Fan Tach
In
FAN_TACH signal is connected to the BMC to monitor the fan speed
4
Fan PWM
Out
FAN_PWM signal to control fan speed
5
Fan Presence
In
Indicates the fan is present
6
Fan Fault LED
Out
Lights the fan fault LED
Note: Intel Corporation server boards support peripheral components and contain a number of
high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s
own chassis are designed and tested to meet the intended thermal requirements of these
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Design and Environmental Specifications
components when the fully integrated system is used together. It is the responsibility of the
system integrator that chooses not to use Intel developed server building blocks to consult
vendor datasheets and operating parameters to determine the amount of air flow required for
their specific application and environmental conditions. Intel Corporation can not be held
responsible if components fail or the server board does not operate correctly when used outside
any of their published operating or non-operating limits.
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Design and Environmental Specifications
6.
Intel® Server Boards S5000PSL and S5000XSL TPS
Jumper Blocks
The server board has several 3-pin jumper blocks that can be used to configure, protect, or
recover specific features of the server board.
Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: ▼
BIOS Bank Select
Force Lower
Bank
Normal
Operation
(default)
2
3
J1C3
CMOS Clear
Disable
2
Enable
3
J1D1
Password Clear
Protect
2
Clear
3
J1D2
BMC Force Update
Disable
2
Enable
3
J1E3
AF000422
Figure 17. Jumper Blocks (J1C3, J1D1, J1D2, J1E32)
Table 34. Server Board Jumpers (J1C3, J1D1, J1D2, J1E3)
Jumper Name
J1C3: BIOS Bank
Select
Pins
1-2
System Results
If these pins are jumper the system will boot from an alternate BIOS image.
2-3
System is configured for normal operation. (Default)
J1D1: CMOS
Clear
1-2
These pins should have a jumper in place for normal system operation. (Default)
2-3
If these pins are jumpered, the CMOS settings will be cleared 5 seconds after removing
AC power. These pins should not be jumpered for normal operation
J1D2: Password
Clear
1-2
These pins should have a jumper in place for normal system operation. (Default)
2-3
If these pins are jumpered, administrator and user passwords will be cleared 5 seconds
after removing AC power. These pins should not be jumpered for normal operation.
J1E3: BMC
Forced Update
1-2
BMC Firmware Force Update Mode – Disabled (Default)
2-3
BMC Firmware Force Update Mode – Enabled
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6.1
Design and Environmental Specifications
CMOS Clear and Password Reset Usage Procedure
The CMOS Clear (J1D1) and Password Reset (J1D2) recovery features are designed such that
the desired operation can be achieved with minimal system down time. The usage procedure for
these two features has changed from previous generation Intel server boards. The following
procedure outlines the new usage model.
6.1.1
Clearing the CMOS
1. Power down server. Do not unplug the power cord.
2. Open the server chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1D1) from the default operating position, covering pins 1 and 2, to the
reset / clear position, covering pins 2 and 3.
4. Remove AC power.
5. Wait 5 seconds.
6. Move the jumper back to default position, covering pins 1 and 2.
7. Close the server chassis.
8. Power up the server.
The CMOS is now cleared and can be reset by going into BIOS setup.
Note: Removing AC Power before performing the CMOS Clear operation will cause the system
to automatically power up and immediately power down, after the procedure is followed and AC
power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and reinstall the AC power cord. Power up system and proceed to the <F2> BIOS Setup Utility to reset
the desired settings.
6.1.2
Clearing the Password
1. Power down server. Do not unplug the power cord.
2. Open the chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1D20 from the default operating position, covering pins 1 and 2, to the
password clear position, covering pins 2 and 3.
4. Close the server chassis.
5. Power up the server, wait 10 seconds or POST completes.
6. Power down the server.
7. Open the chassis and move the jumper back to default position, covering pins 1 and 2.
8.
Close the server chassis.
9. Power up the server.
The password is now cleared and can be reset by going into BIOS setup.
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6.2
Intel® Server Boards S5000PSL and S5000XSL TPS
BMC Force Update Procedure
When performing a standard BMC firmware update procedure, the update utility places the
BMC into an update mode, allowing the firmware to load safely onto the flash device. In the
unlikely event that the BMC firmware update process fails due to the BMC not being in the
proper update state, the server board provides a BMC Force Update jumper (J1E3) which will
force the BMC into the proper update state. The following procedure should be following in the
event the standard BMC firmware update process fails.
1. Power down and remove the AC power cord.
2. Open the server chassis. See your server chassis documentation for instructions.
3. Move jumper from the default operating position, covering pins1 and 2, to the enabled
position, covering pins 2 and 3.
4. Close the server chassis.
5. Reconnect the AC cord and power up the server.
6. Perform the BMC firmware update procedure as documented in the README.TXT file
that is included in the given BMC firmware update package. After successful completion
of the firmware update process, the firmware update utility may generate an error stating
that the BMC is still in update mode.
7. Power down and remove the AC power cord.
8. Open the server chassis.
9. Move jumper from the enabled position, covering pins 2 and 3 to the disabled position,
covering pins 1 and 2.
10. Close the server chassis.
11. Reconnect the AC cord and power up the server.
Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the
enabled position. The server should never be run with the BMC Force Update jumper set in this
position. This jumper setting should only be used when the standard firmware update process
fails. This jumper should remain in the default / disabled position when the server is running
normally.
6.3
BIOS Select Jumper
The jumper block at J1C3, located at the left of PCI-X* slot 1, is used to select which BIOS
image the system will boot to. Pin 1 on the jumper is identified with a ‘▼’. This jumper should
only be moved if you want to force the BIOS to boot to the secondary bank, which may hold a
different version of BIOS.
The rolling BIOS feature of the server board will automatically alternate the boot BIOS to the
secondary bank if the BIOS image in the primary bank is corrupted and cannot boot.
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7.
Design and Environmental Specifications
Intel® Light Guided Diagnostics
The server boards have several on-board diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description the location and function of each LED on the
server board. For a more detailed description of what drives the diagnostic LED operation, see
the Intel® S5000 Server Board Family Datasheet.
7.1
5 Volt Standby LED
Several server management features of this server board require that a 5 volt stand-by voltage
be supplied from the power supply. Some of the features and components that require this
voltage be present when the system is “Off” include the BMC within the ESB2-E, onboard NICs,
and optional RMM connector with Intel RMM installed.
The LED is located just to the right of the CMOS Battery in the center of the server board and is
labeled “5VSB_LED” is illuminated when AC power is applied to the platform and 5 volt standby
voltage is supplied to the server board by the power supply.
AF000224
Figure 18. 5 Volt Standby Status LED Location
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Fan Fault LEDs
Fan fault LEDs are present for the two CPU fans and the two rear system fans. The two CPU
fan fault LEDs are located next to each CPU fan header. The two rear system fan fault LEDs
are located next to each rear system fan header are shown in the following figure.
AF000203
Figure 19. Fan Fault LED Locations
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7.3
Design and Environmental Specifications
System ID LED and System Status LED
The server board provides LEDs for both system ID and system status. These LEDs are located
in the rear I/O area of the server board between the PS/2* mouse / keyboard stacked
connectors and the video / serial stacked connectors. The location of these LEDs are shown in
the following figure.
A
B
AF000204
A. System ID LED
B. System Status LED
Figure 20. System ID LED and System Status LED Locations
The blue System ID LED can be illuminated using either of two mechanisms.
By pressing the System ID Button on the system front panel the ID LED will display a
solid blue color, until the button is pressed again.
By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either Blink
Blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI
Chassis Identify value is issued to turn it off.
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The bi-color System Status LED operates as follows:
Table 35. System Status LED
Color
Off
Green /
Amber
State
N/A
Alternating
Blink
Criticality
Not ready
Not ready
Green
Green
Solid on
Blink
System OK
Degraded
Amber
Blink
Non-critical
Amber
7.3.1
Solid on
Critical, nonrecoverable
Description
AC power off
Pre DC Power On – 20-30 second BMC Initialization when AC is
applied to the server. Control Panel buttons are disabled until BMC
initialization is complete.
System booted and ready.
System degraded
•
Unable to use all of the installed memory (more than one
DIMM installed).
•
Correctable errors over a threshold of 10 and migrating to a
spare DIMM (memory sparing). This indicates that the user
no longer has spared DIMMs indicating a redundancy lost
condition. Corresponding DIMM LED should light up.
•
In mirrored configuration, when memory mirroring takes
place and system loses memory redundancy. This is not
covered by (2).
•
Redundancy loss such as power-supply or fan. This does
not apply to non-redundant sub-systems.
•
PCI-e link errors
•
CPU failure / disabled – if there are two processors and one
of them fails
•
Fan alarm – Fan failure. Number of operational fans should
be more than minimum number needed to cool the system
•
Non-critical threshold crossed – Temperature and voltage
Non-fatal alarm – system is likely to fail
•
Critical voltage threshold crossed
•
VRD hot asserted
•
Minimum number of fans to cool the system not present or
failed
•
In non-sparing and non-mirroring mode if the threshold of
ten correctable errors is crossed within the window
Fatal alarm – system has failed or shutdown
•
DIMM failure when there is one DIMM present, no good
memory present
•
Run-time memory uncorrectable error in non-redundant
mode
•
IERR signal asserted
•
Processor 1 missing
•
Temperature (CPU ThermTrip, memory TempHi, critical
threshold crossed)
•
No power good – power fault
•
Processor configuration error (for instance, processor
stepping mismatch)
System Status LED – BMC Initialization
When the AC power is first applied to the system and 5V-STBY is present, the BMC
controller on the server board requires 5-10 seconds to initialize. During this time, the
system status LED will blink, alternating between amber and green, and the power button
functionality of the control panel is disabled preventing the server from powering up. Once
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BMC initialization has completed, the status LED will stop blinking and the power button
functionality is restored and can be used to turn on the server.
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DIMM Fault LEDs
The server board provides a memory fault LED for each DIMM socket. These LEDs are located
towards the rear of the server board next to each DIMM connector.
AF000205
Figure 21. DIMM Fault LED Locations
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7.5
Design and Environmental Specifications
Processor Fault LEDs
The server board provides a fault LED for each processor socket. These LEDs are located near
the processor sockets.
AF000206
Figure 22. Processor Fault LED Locations
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Intel® Server Boards S5000PSL and S5000XSL TPS
Post Code Diagnostic LEDs
POST code diagnostic LEDs are located on the back edge of the server board in the rear I/O
area of the server board between the PS/2 mice / keyboard stacked connectors and the video /
serial stacked connectors.
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS will display the given POST code to the POST code diagnostic
LEDs on the back edge of the server board. To assist in troubleshooting a system hang during
the POST process, the Diagnostic LEDs can be used to identify the last POST process to be
executed. See Appendix C for a complete description of how these LEDs are read, and for a list
of all supported POST codes.
A. Status LED
D. Bit 2 LED (POST LED)
B. ID LED
E. Bit 1 LED (POST LED)
C. MSB LED (POST LED)
F. LSB LED (POST LED)
Figure 23. POST Code Diagnostic LED Location
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Design and Environmental Specifications
8.
Design and Environmental Specifications
8.1
Server Boards S5000PSL and S5000XSL Design Specifications
The operation of the server boards at conditions beyond those shown in the following table may
cause permanent damage to the system. Exposure to absolute maximum rating conditions for
extended periods may affect system reliability.
Table 36. Server Board Design Specifications
Operating Temperature
0º C to 55º C 1 (32º F to 131º F)
Non-Operating Temperature
-40º C to 70º C (-40º F to 158º F)
DC Voltage
± 5% of all nominal voltages
Shock (Unpackaged)
Trapezoidal, 50 G, 170 inches / sec
Shock (Packaged)
<20 pounds
20 to <40 pounds
40 to <80 pounds
80 to <100 pounds
100 to <120 pounds
120 pounds
36 inches
30 inches
24 inches
18 inches
12 inches
9 inches
Vibration (Unpackaged)
5 Hz to 500 Hz 3.13 g RMS random
Note:
1
Chassis design must provide proper airflow to avoid exceeding the Dual-Core Intel® Xeon®
processor 5000 sequence maximum case temperature.
Disclaimer Note: Intel Corporation server boards contain a number of high-density VLSI and
power delivery components that need adequate airflow to cool. Intel ensures through its own
chassis development and testing that when Intel server building blocks are used together, the
fully integrated system will meet the intended thermal requirements of these components. It is
the responsibility of the system integrator who chooses not to use Intel developed server
building blocks to consult vendor datasheets and operating parameters to determine the amount
of air flow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible, if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
8.2
Board-level Calculated MTBF
The predicted board Mean Time Between Failures is 97,549 hours of operation. As of this
writing actual MTBF testing across multiple systems is complete with a demonstrated 25,222
hours. Since our validation test is only run up to about 25,000 hours across multiple servers, we
still maintain that actual MTBF data will likely be over 97,549 hours of operation based on
statistical regression.
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Intel® Server Boards S5000PSL and S5000XSL TPS
Server Board Power Requirements
This section provides power supply design guidelines for a system using the Intel® Server Boards S5000PSL and S5000XSL,
including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the
power distribution implemented on these server boards.
Figure 24. Power Distribution Block Diagram
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8.3.1
Design and Environmental Specifications
Processor Power Support
The server board supports the Thermal Design Point (TDP) guideline for Intel® Xeon®
processors. The Flexible Motherboard Guidelines (FMB) has also been followed to help
determine the suggested thermal and current design values for anticipating future processor
needs. The following table provides maximum values for Icc, TDP power and TCASE for the dual
core Intel® Xeon® processor 5000 sequence family.
Table 37. Intel® Xeon® Processor Dual Processor TDP Guidelines
TDP Power
130 W
Max TCASE
70º C
Icc MAX
150 A
Note: These values are for reference only. The Dual-Core Intel® Xeon®) processor 5000
sequence Datasheet contains the actual specifications for the processor. If the values found in
the Dual-Core Intel(r) Xeon(r) processor 5000 sequence Datasheet are different than those
published here, the Dual-Core Intel(r) Xeon(r) processor 5000 sequence Datasheet values will
supersede these, and should be used.
8.4
Power Supply Output Requirements
This section is for reference purposes only. The intent is to provide guidance to system
designers to determine a power supply for use with this server board. This section specifies the
power supply requirements Intel used to develop a power supply for its 5U server system.
The combined power of all outputs shall not exceed the rated output power of the power supply.
The power supply must meet both static and dynamic voltage regulation requirements for the
minimum loading conditions.
Table 38. 550 W Load Ratings
Voltage
+3.3 V
+5 V
+12 V1
+12 V2
+12 V3
+12 V4
-12 V
+5 VSB
1.
2.
3.
4.
5.
6.
Minimum
Continuous
1.5 A
1.0 A
0.5 A
0.5 A
0.5 A
0.5 A
0A
0.1 A
Maximum
Continuous
24 A
24 A
16 A
16 A
14 A
8A
0.5 A
3.0 A
Peak
18 A
18 A
13 A
3.5 A
Maximum continuous total DC output power should not exceed 550 W.
Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 140W.
Maximum peak total DC output power should not exceed 660W.
Peak power and current loading shall be supported for a minimum of 12 seconds.
Maximum combined current for the 12 V outputs shall be 41 A.
Peak current for the combined 12 V outputs shall be 50A.
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Intel® Server Boards S5000PSL and S5000XSL TPS
Grounding
The grounds of the pins of the power supply output connector provide the power return path.
The output connector ground pins is connected to safety ground (power supply enclosure). This
grounding should is designed to ensure passing the maximum allowed common mode noise
levels.
8.4.2
Standby Outputs
The 5 VSB output shall be present when an AC input greater than the power supply turn on
voltage is applied.
8.4.3
Remote Sense
The power supply has remote sense return to regulate out ground drops for all output voltages:
+3.3 V, +5 V, +12 V1, +12 V2, +12 V3, -12 V, and 5 VSB. The power supply uses remote sense
(3.3 VS) to regulate out drops in the system for the +3.3 V output.
The +5 V, +12 V1, +12 V2, +12 V3, –12 V and 5 VSB outputs only use remote sense referenced
to the remote sense return signal. The remote sense input impedance to the power supply must
be greater than 200 Ω on 3.3 VS and 5 VS. This is the value of the resistor connecting the
remote sense to the output voltage internal to the power supply.
Remote sense must be able to regulate out a minimum of a 200 mV drop on the +3.3 V output.
The remote sense return must be able to regulate out a minimum of a 200 mV drop in the power
ground return. The current in any remote sense line shall be less than 5 mA to prevent voltage
sensing errors.
The power supply must operate within specification over the full range of voltage drops from the
power supply’s output connector to the remote sense points.
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8.4.4
Design and Environmental Specifications
Voltage Regulation
The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple / noise.
Table 39. Voltage Regulation Limits
Parameter
+3.3V
Tolerance
- 5% / +5%
Minimum
+3.14
Nominal
+3.30
Maximum
+3.46
Units
Vrms
+5V
- 5% / +5%
+4.75
+5.00
+5.25
Vrms
1
- 5% / +5%
+11.40
+12.00
+12.60
Vrms
+12V 2
- 5% / +5%
+11.40
+12.00
+12.60
Vrms
3
- 5% / +5%
+11.40
+12.00
+12.60
Vrms
+12V 4
- 5% / +5%
+11.40
+12.00
+12.60
Vrms
+12V
+12V
- 12V
- 5% / +9%
- 11.40
-12.00
-13.08
Vrms
+5VSB
- 5% / +5%
+4.75
+5.00
+5.25
Vrms
1.
2.
3.
4.
8.4.5
Maximum continuous total output power should not exceed 670 W.
Maximum continuous load on the combined 12 V output shall not exceed 48 A.
Peak load on the combined 12 V output shall not exceed 52 A.
Peak total DC output power should not exceed 730 W.
Dynamic Loading
The output voltages shall remain within limits for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50 Hz
and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere within the minimum load to the maximum
load conditions.
Table 40. Transient Load Requirements
Output
+3.3V
Δ Step Load Size 1
7.0A
Load Slew Rate
0.25 A/μsec
Test Capacitive Load
4700 μF
+5V
7.0A
0.25 A/μsec
1000 μF
+12V
25A
0.25 A/μsec
4700 μF
+5VSB
0.5A
0.25 A/μsec
20 μF
1.
Step loads on each 12V output may happen simultaneously.
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Intel® Server Boards S5000PSL and S5000XSL TPS
Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive
loading ranges.
Table 41. Capacitive Loading Conditions
Output
+3.3 V
Minimum
250
Maximum
6800
Units
μF
+5 V
400
4700
μF
500 each
11,000
μF
+12 V
1.
2.
3.
4.
8.4.7
1, 2, 3, 4
-12 V
1
350
μF
+5 VSB
20
350
μF
Maximum continuous total output power should not exceed 670 W.
Maximum continuous load on the combined 12 V output shall not exceed 48 A.
Peak load on the combined 12 V output shall not exceed 52 A.
Peak total DC output power should not exceed 730 W.
Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0Hz to 20MHz at the power supply output connectors. A
10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor are placed at the point of
measurement.
Table 42. Ripple and Noise
+3.3 V
50mVp-p
1.
2.
3.
4.
8.4.8
+5 V
50mVp-p
+12 V 1, 2, 3, 4
120mVp-p
-12 V
120mVp-p
+5 VSB
50mVp-p
Maximum continuous total output power should not exceed 670 W.
Maximum continuous load on the combined 12 V output shall not exceed 48 A.
Peak load on the combined 12 V output shall not exceed 52 A.
Peak total DC output power should not exceed 730 W.
Timing Requirements
The following are the timing requirements for the power supply operation. The output voltages
must rise from 10% to within regulation limits (Tvout_rise) within 5 to 70 ms. 5 VSB is allowed to
rise from 1.0 to 25 ms. All outputs must rise monotonically. Each output voltage shall reach
regulation within 50 ms (Tvout_on) of each other during turn on of the power supply. Each output
voltage shall fall out of regulation within 400 msec (Tvout_off) of each other during turn off.
The following tables and diagrams show the timing requirements for the power supply being
turned on and off via the AC input with PSON held low, and the PSON signal with the AC input
applied.
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Table 43. Output Voltage Timing
Item
Tvout_rise
Description
Output voltage rise time from each main output.
Tvout_on
Minimum
5.0 1
Maximum
70 1
Units
ms
All main outputs must be within regulation of each other within this
time.
50
ms
Tvout_off
All main outputs must leave regulation within this time.
400
ms
1.
The 5VSB output voltage rise time is from 1.0 ms to 25 ms
V out
10% V out
V1
V2
V3
V4
Tvout_rise
Tvout_off
Tvout_on
TP02313
Figure 25. Output Voltage Timing
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Table 44. Turn On/Off Timing
Item
Tsb_on_delay
Description
Delay from AC being applied to 5VSB being within regulation.
Minimum
Maximum
1500
Tac_on_delay
Delay from AC being applied to all output voltages being within
regulation.
Tvout_holdup
Time all output voltages stay within regulation after loss of AC.
21
ms
Tpwok_holdup
Delay from loss of AC to de-assertion of PWOK
20
ms
Tpson_on_delay
Delay from PSON# active to output voltages within regulation
limits.
5
2500
400
Tpson_pwok
Delay from PSON# deactivate to PWOK being de-asserted.
Tpwok_on
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
50
100
Tpwok_off
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
1
Tpwok_low
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSON signal.
100
Tsb_vout
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
50
T5VSB_holdup
Time the 5VSB output voltage stays within regulation after loss
of AC.
70
500
Units
ms
ms
ms
ms
ms
ms
ms
1000
ms
ms
AC Input
Tvout_holdup
Vout
Tpwok_low
TAC_on_delay
Tsb_on_delay
PWOK
5VSB
Tpwok_off
Tpwok_on
Tsb_on_delay
Tpwok_on
Tpwok_off
Tpson_pwok
Tpwok_holdup
T5VSB_holdup
Tsb_vout
Tpson_on_delay
PSON
AC turn on/off cycle
PSON turn on/off cycle
Figure 26. Turn On/Off Timing (Power Supply Signals)
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8.4.9
Design and Environmental Specifications
Residual Voltage Immunity in Standby Mode
The power supply should be immune to any residual voltage placed on its outputs (typically, a
leakage voltage through the system from standby output) up to 500 mV. There shall be no
additional heat generated, nor stressing of any internal components with this voltage applied to
any individual output, and all outputs simultaneously. It also should not trip the power supply
protection circuits during turn on.
Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV
when AC voltage is applied and the PSON# signal is de-asserted.
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9.
Intel® Server Boards S5000PSL and S5000XSL TPS
Regulatory and Certification Information
To help ensure EMC compliance with your local regional rules and regulations, before computer
integration, make sure that the chassis, power supply, and other modules have passed EMC
testing using a server board with a microprocessor from the same family (or higher) and
operating at the same (or higher) speed as the microprocessor used on this server board. The
final configuration of your end system product may require additional EMC compliance testing.
For more information please contact your local Intel Representative.
This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class
B device.
9.1 Product Regulatory Compliance
Intended Application – This product was evaluated as Information Technology Equipment
(ITE), which may be installed in offices, schools, computer rooms, and similar commercial type
locations. The suitability of this product for other product categories and environments (such as:
medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment,
etc.), other than an ITE application, may require further evaluation.
9.1.1
Product Safety Compliance
UL60950 – CSA 60950(USA / Canada)
EN60950 (Europe)
IEC60950 (International)
CB Certificate & Report, IEC60950 (report to include all country national deviations)
GOST R 50377-92 – Listed on one System License (Russia)
Belarus License – Listed on System License (Belarus)
CE - Low Voltage Directive 73/23/EEE (Europe)
IRAM Certification (Argentina)
9.1.2
Product EMC Compliance – Class A Compliance
FCC /ICES-003 - Emissions (USA/Canada) Verification
CISPR 22 – Emissions (International)
EN55022 - Emissions (Europe)
EN55024 - Immunity (Europe)
CE – EMC Directive 89/336/EEC (Europe)
VCCI Emissions (Japan)
AS/NZS 3548 Emissions (Australia / New Zealand)
BSMI CNS13438 Emissions (Taiwan)
GOST R 29216-91 Emissions - Listed on one System License (Russia)
GOST R 50628-95 Immunity –Listed on one System License (Russia)
Belarus License – Listed on one System License (Belarus)
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Design and Environmental Specifications
RRL MIC Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea)
9.1.3
Certifications / Registrations / Declarations
UL Certification or NRTL (US/Canada)
CB Certifications (International)
CE Declaration of Conformity (CENELEC Europe)
FCC/ICES-003 Class A Attestation (USA/Canada)
C-Tick Declaration of Conformity (Australia)
MED Declaration of Conformity (New Zealand)
BSMI Certification (Taiwan)
RRL Certification (Korea)
Ecology Declaration (International)
9.2
Product Regulatory Compliance Markings
The Intel® Server Board bears the following regulatory marks.
Regulatory Compliance
Region
UL Mark
USA/Canada
Marking
CE Mark
Europe
EMC Marking (Class A)
Canada
BSMI Marking (Class A)
Taiwan
C-tick Marking
Australia / New Zealand
RRL MIC Mark
Korea
Country of Origin
Exporting Requirements
Made in xxxxx (Provided by label, not silkscreen)
Model Designation
Regulatory Identification
Examples (Server Board S5000PSL) for boxed
type boards; or Board PB number for non-boxed
boards (typically high-end boards)
CANADA ICES-003 CLASS A
CANADA NMB-003 CLASSE A
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9.3 Electromagnetic Compatibility Notices
9.3.1
FCC Verification Statement (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
Intel Corporation
5200 N.E. Elam Young Parkway
Hillsboro, OR 97124-6497
Phone: 1-800-628-8686
This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is no
guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning
the equipment off and on, the user is encouraged to try to correct the interference by one or
more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and the receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver
is connected.
Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the grantee of this device could void
the user’s authority to operate the equipment. The customer is responsible for ensuring
compliance of the modified product.
All cables used to connect to peripherals must be shielded and grounded. Operation with
cables, connected to peripherals that are not shielded and grounded may result in interference
to radio and TV reception.
9.3.2
ICES-003 (Canada)
Cet appareil numérique respecte les limites bruits radioélectriques applicables aux
appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur:
“Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications.
English translation of the notice above:
This digital apparatus does not exceed the Class B limits for radio noise emissions from digital
apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,”
ICES-003 of the Canadian Department of Communications.
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9.3.3
Design and Environmental Specifications
Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive
(73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark
to illustrate its compliance.
9.3.4
VCCI (Japan)
English translation of the notice above:
This is a Class B product based on the standard of the Voluntary Control Council for
Interference (VCCI) from Information Technology Equipment. If this is used near a radio or
television receiver in a domestic environment, it may cause radio interference. Install and use
the equipment according to the instruction manual.
9.3.5
BSMI (Taiwan)
The BSMI Certification Marking and EMC warning is located on the outside rear area of
the product.
9.3.6
RRL (Korea)
Following is the RRL certification information for Korea.
English translation of the notice above:
1.
2.
3.
4.
5.
Type of Equipment (Model Name): On License and Product
Certification No.: On RRL certificate. Obtain certificate from local Intel representative
Name of Certification Recipient: Intel Corporation
Date of Manufacturer: Refer to date code on product
Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product
Revision 1.4
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Design and Environmental Specifications
9.3.7
Intel® Server Boards S5000PSL and S5000XSL TPS
CNCA (CCC-China)
The CCC Certification Marking and EMC warning is located on the outside rear area of
the product.
A
9.4 Restriction of Hazardous Substances (RoHS)
Compliance
Intel has a system in place to restrict the use of banned substances in accordance with the
European Directive 2002/95/EC. Compliance is based on declaration that materials banned in
the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an
approved/pending RoHS exemption applies.
Note: RoHS implementation details are not fully defined and may change.
Threshold limits and banned substances are noted below.
Quantity limit of 0.1% by mass (1000 PPM) for:
- Lead
- Mercury
- Hexavalent Chromium
- Polybrominated Biphenyls Diphenyl Ethers (PBDE)
Quantity limit of 0.01% by mass (100 PPM) for:
-
Cadmium
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix A: Integration and Usage Tips
Appendix A: Integration and Usage Tips
When adding or removing components or peripherals from the server board, AC power
must be removed. With AC power plugged into the server board, 5-volt standby is still
present even though the server board is powered off.
Processors must be installed in order. CPU 1 is located near the edge of the server
board and must be populated to operate the board.
On the back edge of the server board are four diagnostic LEDs that display a sequence
of red, green, or amber POST codes during the boot process. If the server board hangs
during POST, the LEDs will display the last POST event run before the hang.
Only Fully Buffered DIMMs (FBDIMMs) are supported on this server board. For a list of
supported memory for this server board, see the Intel® S5000PSL, S5000XSL,
S5000XVN, and Server System SC5400RA Tested Memory List.
For a list of Intel supported operating systems, add-in cards, and peripherals for this
server board, see the Intel® S5000PSL, S5000XSL, S5000XVN, and Server System
SC5400RA Tested Hardware and OS List.
For a list of Intel supported hard disk drives for this workstation board, see the Intel®
Server Board/Systems Tested Hard Drive List.
Only Multi-Core Intel® Xeon® processors with system bus speeds of 667 (Intel® Xeon®
processors 5000 series only), 1066, or 1333 MHz are supported on this server board.
Previous generation Intel® Xeon® processors are not supported.
For the best performance, the number of FBDIMMs installed should be balanced across
both memory branches. For example: a four-DIMM configuration will perform better than
a two DIMM configuration. In a four-DIMM configuration, FBDIMMs should be installed in
DIMM sockets A1, B1, C1, and D1. An eight-DIMM configuration will perform better then
a six DIMM configuration.
The Intel® RMM connector is not compatible with the Intel® Server Management Module
Professional Edition (Product Code AXXIMMPRO) or with the Intel® Server Management
Module Advanced Edition (Product Code AXXIMMADV)
Removing AC power before performing the CMOS Clear operation will cause the system
to automatically power up and immediately power down after the CMOS Clear procedure
is followed and AC power is re-applied. If this happens, remove the AC power cord, wait
30 seconds, and then re-connect the AC power cord. Power up the system and proceed
to the <F2> BIOS Setup Utility to reset the desired settings.
Normal BMC functionality is disabled with the force BMC update jumper set to the
“enabled” position (pins 2-3). The server should never be run with the BMC force update
jumper set in this position and should only be used when the standard firmware update
process fails. This jumper should remain in the default (disabled) position (pins 1-2)
when the server is running normally.
When performing a BIOS update procedure, the BIOS select jumper must be set to its
default position (pins 2-3).
Revision 1.4
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix B: BMC Sensor Tables
This appendix lists the sensor identification numbers and information about the sensor type,
name, supported thresholds, assertion and de-assertion information, and a brief description of
the sensor purpose. See the Intelligent Platform Management Interface Specification, Version
2.0, for sensor and event/reading-type table information.
Sensor Type
The Sensor Type is the values enumerated in the Sensor Type Codes table in the IPMI
specification. The Sensor Type provides the context in which to interpret the sensor,
such as the physical entity or characteristic that is represented by this sensor.
Event / Reading Type
The Event/Reading Type values are from the Event/Reading Type Code Ranges and
Generic Event/Reading Type Codes tables in the IPMI specification. Digital sensors are
a specific type of discrete sensor, which have only two states.
Event Offset/Triggers
Event Thresholds are event-generating thresholds for threshold types of sensors.
[u,l][nr,c,nc]: upper nonrecoverable, upper critical, upper noncritical, lower
nonrecoverable, lower critical, lower noncritical
- uc, lc: upper critical, lower critical
Event Triggers are supported event-generating offsets for discrete type sensors. The
offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes
tables in the IPMI specification, depending on whether the sensor event/reading type is
generic or a sensor-specific response.
-
Assertion / De-assertion Enables
Assertion and de-assertion indicators reveal the type of events the sensor generates:
- As: Assertions
- De: De-assertion
Readable Value / Offsets
Readable Value indicates the type of value returned for threshold and other nondiscrete type sensors.
- Readable Offsets indicate the offsets for discrete sensors that are readable with the
Get Sensor Reading command. Unless otherwise indicated, all event triggers are
readable; Readable Offsets consist of the reading type offsets that do not generate
events.
Event Data
-
Event data is the data that is included in an event message generated by the sensor. For
threshold-based sensors, the following abbreviations are used:
-
R: Reading value
T: Threshold value
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix B: BMC Sensor Tables
Rearm Sensors
The rearm is a request for the event status for a sensor to be rechecked and updated
upon a transition between good and bad states. Rearming the sensors can be done
manually or automatically. This column indicates the type supported by the sensor. The
following abbreviations are used in the comment column to describe a sensor:
- A: Auto-rearm
- M: Manual rearm
Default Hysteresis
The hysteresis setting applies to all thresholds of the sensor. This column provides the
count of hysterisis for the sensor, which can be 1 or 2 (positive or negative hysteresis).
Criticality
Criticality is a classification of the severity and nature of the condition. It also controls the
behavior of the Control Panel Status LED
Standby
Some sensors operate on standby power. These sensors may be accessed and / or
generate events when the main (system) power is off, but AC power is present.
Revision 1.4
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Table 45. BMC Sensors
Sensor
Name[1]
Power Unit
Status
Power Unit
Redundancy
Watchdog
Sensor
Number
01h
02h
03h
System
Applicability
All
Chassisspecific
All
Sensor Type
Power Unit
09h
Power Unit
09h
Watchdog 2
23h
Event /
Reading
Type
Sensor
Specific
6Fh
Generic
0Bh
Sensor
Specific
6Fh
Event Offset
Triggers
Criticality
Power down
Power cycle
A/C lost
OK
Soft power control
failure
Power unit failure
Crit
Fully redundant
OK
Redundancy Lost
Degraded
Redundancy
degraded
Degraded
Non-red: stuff res
from redund
Degraded
Non-red: suff from
insuff
Degraded
Non-red:
insufficient
Critical
Redun degrade
from full
Degraded
Redun degrade
from nonredundant
Degraded
Timer expired,
status only
Hard reset
Power down
Power cycle
Timer interrupt
OK
Assert /
De-assert
Event Data
Rearm
As and De
Readable
Value /
Offsets
–
Standby
Trig Offset
A, I
X
As and De
–
Trig Offset
A
X
As
–
Trig Offset
A, I
X
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Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name[1]
Sensor
Number
Platform
Security
Violation
04h
Physical
Security
05h
System
Applicability
All
Sensor Type
Platform
Security
Violation
Attempt
06h
Appendix B: BMC Sensor Tables
Event /
Reading
Type
Sensor
Specific
6Fh
Event Offset
Triggers
Criticality
Secure mode
violation attempt
Out-of-band
access password
violation
OK
As and De
Readable
Value /
Offsets
–
As and De
–
Trig Offset
A
X
Physical
Chassis
Security
Intrusion
is chassis- 05h
specific
Sensor
Specific
6Fh
Chassis intrusion
OK
LAN leash lost [2]
Degraded
Assert /
De-assert
Event Data
Rearm
Standby
Trig Offset
A, I
X
FP Diag
Interrupt
(NMI)
07h
All
Critical
Interrupt
13h
Sensor
Specific
6Fh
Front panel NMI /
diagnostic
interrupt
Bus uncorrectable
error
OK
As
–
Trig Offset
A, I
–
System
Event Log
09h
All
Event
Logging
Disabled
10h
Sensor
Specific
6Fh
Log area reset /
cleared
OK
As
–
Trig Offset
A, I
X
Session
Audit
0Ah
All
Session Audit Sensor
Specific
2Ah
6Fh
00h – Session
activation
01h – Session
deactivation
OK
–
As defined
by IPMI
A, I
X
System
Event
('System
Event')
0Bh
All
System Event Sensor
Specific
12h
6Fh
00 – System
reconfigured
04 – PEF action
OK
As
–
Trig Offset
A, I
X
BB +1.2V Vtt 10h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
BB+1.8V
NIC Core
11h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
X
BB +1.5V
AUX
12h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
BB +1.5V
13h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Revision 1.4
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Appendix B: BMC Sensor Tables
Sensor
Name[1]
Sensor
Number
BB +1.8V
14h
System
Applicability
All
BB +3.3V
15h
BB +3.3V
STB
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor Type
Voltage
02h
Event /
Reading
Type
Threshold
01h
Event Offset
Triggers
Criticality
Assert /
De-assert
Event Data
Rearm
As and De
Readable
Value /
Offsets
Analog
[u,l] [c,nc]
Threshold
defined
R, T
A, I
–
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
16h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
X
BB +1.5V
ESB
17h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
X
BB +5V
18h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
BB +1.2V
NIC
19h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
BB +12V
AUX
1Ah
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
BB 0.9V
1Bh
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
BB Vbat
1Eh
All
Voltage
02h
Digital
Discrete
05h
01h – Limit
exceeded
Critical
As and De
–
R, T
A, I
X
BB Temp
30h
All
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
X
Front Panel
Temp
32h
All
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
X
FBDIMM
Aggregate[3]
48h
All
Temperature
01h
Threshold
01h
–
–
–
A, I
–
CPU 1 FAN
50h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
CPU 2 FAN
51h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
SYS FAN 1
TACH
52h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
–
–
Standby
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name[1]
Sensor
Number
Sensor Type
Appendix B: BMC Sensor Tables
System
Applicability
Chassisspecific
Fan
04h
Event /
Reading
Type
Threshold
01h
Event Offset
Triggers
Criticality
Assert /
De-assert
Event Data
Rearm
As and De
Readable
Value /
Offsets
Analog
[l] [c,nc] [4]
Threshold
defined
Standby
R, T
M, I
–
SYS FAN 2
TACH
53h
SYS FAN 3
TACH'
54h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
SYS FAN 4
TACH
55h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
SYS FAN 5
TACH'
56h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
SYS FAN 6
TACH
57h
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
58h
Tach Fan
(Not used on
this server)
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
59h
Tach Fan
(Not used on
this server)
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
5Ah
Tach Fan
(Not used on
this server)
Chassisspecific
Fan
04h
Threshold
01h
[l] [c,nc] [4]
Threshold
defined
As and De
Analog
R, T
M, I
–
Fan 1
Present
60h
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Fan 2
Present
61h
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Fan 3
Present
62h
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Fan 4
Present
63h
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Fan 5
Present
64h
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Fan 6
Present
65h
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Revision 1.4
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Appendix B: BMC Sensor Tables
Sensor
Name[1]
Sensor
Number
Intel® Server Boards S5000PSL and S5000XSL TPS
System
Applicability
Chassisspecific
Sensor Type
Fan
04h
Event /
Reading
Type
Generic
08h
Device present
OK
As and De
Readable
Value /
Offsets
–
Generic
08h
Device present
OK
As and De
–
T
A
–
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Chassisspecific
Fan
04h
Generic
08h
Device present
OK
As and De
–
T
A
–
Chassisspecific
Fan
04h
Generic
0Bh
Full redundant
OK
As and De
–
Trig Offset
A
X
Redundancy lost
Degraded
Redundancy
degraded
Degraded
Non-red: suff res
from redund
Degraded
Non-red: suff from
insuff
Degraded
Non-red:
insufficient
Non
Critical
Redun degrade
from full
Degraded
Redun degrade
from nonredundant
Degraded
As and De
–
Trig Offset
A
X
As and De
–
Trig Offset
A
X
Fan 7
Present
66h
Fan 8
Present
67h
Chassisspecific
Fan
04h
Fan 9
Present
68h
Chassisspecific
Fan 10
Present
69h
Fan Redundancy[5]
6Fh
Power
Supply
Status[5] 1
70h
Chassisspecific
Power Supply Sensor
Specific
08h
6Fh
Event Offset
Triggers
Criticality
Presence
OK
Failure
Degraded
Predictive fail
Degraded
A/C lost
Degraded
Assert /
De-assert
Event Data
Rearm
Standby
T
A
–
Configuration error OK
Power
Supply
Status[5] 2
71h
Chassisspecific
Power Supply Sensor
Specific
08h
6Fh
Presence
OK
Failure
Degraded
Predictive fail
Degraded
A/C lost
Degraded
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name[1]
Sensor
Number
System
Applicability
Sensor Type
Appendix B: BMC Sensor Tables
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable
Value /
Offsets
Event Data
Rearm
Standby
Configuration error OK
Power
Nozzle
Power
Supply 1
78h
Chassisspecific
Current
03h
Threshold
01h
[u] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Power
Nozzle
Power
Supply 2
79h
Chassisspecific
Current
03h
Threshold
01h
[u] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Power
Gauge
V1 rail
(+12v)
Power
Supply 1
7Ah
Chassisspecific
Current
03h
Threshold
01h
[u] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Power
Gauge
V1 rail
(+12v)
Power
Supply 2
7Bh
Chassisspecific
Current
03h
Threshold
01h
[u] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Power
Gauge
(aggre-gate
power)
Power
Supply 1
7Ch
Chassisspecific
Other Units
0Bh
Threshold
01h
[u] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Power
Gauge
(aggregate
power)
Power
Supply 2
7Dh
Chassisspecific
Other Units
0Bh
Threshold
01h
[u] [c,nc]
Threshold
defined
As and De
Analog
R, T
A, I
–
Revision 1.4
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Appendix B: BMC Sensor Tables
Sensor
Name[1]
System
ACPI Power
State
82h
System
Applicability
All
S0 / G0
S1
S3
S4
S5 / G2
G3 mechanical off
OK
As
Readable
Value /
Offsets
–
Button
84h
All
Button
14h
Sensor
Specific
6Fh
Power button
Reset button
OK
As
–
Trig Offset
A, I
X
SMI Timeout
85h
All
SMI Timeout
F3h
Digital
Discrete
03h
01h – State
asserted
Critical
As and De
–
Trig Offset
A, I
–
Sensor
Failure
86h
All
Sensor
Failure
F6h
OEM
Sensor
Specific
73h
I2C device not
found
I2C device error
detected
I2C bus timeout
OK
As
–
Trig Offset
A
X
NMI Signal
State
87h
All
OEM
C0h
Digital
Discrete
03h
01h – State
asserted
OK
–
01h
–
A, I
–
SMI Signal
State
88h
All
OEM
C0h
Digital
Discrete
03h
01h – State
asserted
OK
–
01h
–
A, I
–
Proc 1
Status
90h
All
Processor
07h
Sensor
Specific
6Fh
IERR
Critical
Thermal trip
Critical
Proc 2
Status
Sensor
Number
Intel® Server Boards S5000PSL and S5000XSL TPS
91h
All
Sensor Type
System ACPI
Power State
22h
Processor
07h
Event /
Reading
Type
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Event Offset
Triggers
Criticality
Config error
Critical
Presence
OK
Disabled
Degraded
IERR
Critical
Thermal trip
Critical
Config error
Critical
Presence
OK
Assert /
De-assert
Event Data
Rearm
Standby
Trig Offset
A, I
X
As and De
–
Trig Offset
M
X
As and De
–
Trig Offset
M
X
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name[1]
Sensor
Number
System
Applicability
Sensor Type
Appendix B: BMC Sensor Tables
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Disabled
Degraded
Threshold
defined
As and De
–
–
Threshold
defined
As and De
Readable
Value /
Offsets
Event Data
Rearm
Standby
R, T
A, I
–
A, I
–
A, I
–
Proc 1
Temp[6]
98h
All
Temperature
01h
Threshold
01h
[u,l] [c,nc]
P1 Therm
Margin[7]
99h
All
Temperature
01h
Threshold
01h
–
Proc 2
Temp[6]
9Ah
All
Temperature
01h
Threshold
01h
[u,l] [c,nc]
P2 Therm
Margin[7]
9Bh
All
Temperature
01h
Threshold
01h
–
–
–
–
–
A, I
–
P1B Therm
Margin[8]
9Ch
All
Temperature
01h
Threshold
01h
–
–
–
–
–
A, I
–
P2B Therm
Margin[8]
9Dh
All
Temperature
01h
Threshold
01h
–
–
–
–
–
A, I
–
PCIe Link0
A0h
All
Sensor
Specific
6Fh
PCIe
Link0
Sensor
Specific
6Fh
PCIe Link1
PCIe Link2
PCIe Link3
PCIe Link4
A1h
A2h
A3h
A4h
All
All
All
All
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Revision 1.4
Analog
–
Analog
–
R, T
As
–
See the
BIOS EPS
A, i
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
103
Intel order number: D41763-005
Appendix B: BMC Sensor Tables
Sensor
Name[1]
PCIe Link5
PCIe Link6
PCIe Link7
PCIe Link8
PCIe Link9
PCIe Link10
PCIe Link11
PCIe Link12
PCIe Link13
Sensor
Number
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
System
Applicability
All
All
All
All
All
All
All
All
All
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor Type
Sensor
Specific
6Fh
Event /
Reading
Type
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Event Offset
Triggers
Criticality
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Bus correctable
error
OK
Bus uncorrectable
error
Degraded
Sensor
Specific
Sensor
Specific
Bus correctable
error
OK
Assert /
De-assert
As
Readable
Value /
Offsets
–
Event Data
Rearm
Standby
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
As
–
See the
BIOS EPS
A, I
–
Revision 1.4
104
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Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name[1]
Sensor
Number
System
Applicability
Sensor Type
Appendix B: BMC Sensor Tables
6Fh
Event /
Reading
Type
6Fh
Event Offset
Triggers
Criticality
Bus uncorrectable
error
Degraded
Assert /
De-assert
Readable
Value /
Offsets
Event Data
Rearm
Standby
Proc 1
Thermal
Control
C0h
All
Temperature
01h
Threshold
01h
[u] [c]
NonCritical
As and De
Analog
Trig Offset
M
–
Proc 2
Thermal
Control
C1h
All
Temperature
01h
Threshold
01h
[u] [c]
NonCritical
As and De
Analog
Trig Offset
M
–
Proc 1 VRD
Over Temp
C8h
All
Temperature
01h
Digital
Discrete
05h
01h – Limit
exceeded
NonCritical
As and De
–
Trig Offset
M
–
Proc 2 VRD
Over Temp
C9h
All
Temperature
01h
Digital
Discrete
05h
01h – Limit
exceeded
NonCritical
As and De
–
Trig Offset
M
–
Proc 1 Vcc
D0h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A
–
Proc 2 Vcc
D1h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Threshold
defined
As and De
Analog
R, T
A
–
Proc 1 Vcc
Out-ofRange
D2h
All
Voltage
02h
Digital
Discrete
05h
01h – Limit
exceeded
NonCritical
As and De
Discrete
R, T
A
–
Proc 2
Vcc Out-ofRange
D3h
All
Voltage
02h
Digital
Discrete
05h
01h – Limit
exceeded
NonCritical
As and De
Discrete
R, T
A
–
CPU
Population
Error
D8h
All
Processor
07h
Generic
03h
01h –- State
asserted
Critical
As and De
–
R, T
A
–
DIMM A1
E0h
All
Slot
Connector
21h
Sensor
Specific
6Fh
Fault status
asserted
Degraded
As
–
Trig Offset
A
–
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
As
–
Trig Offset
A
–
DIMM A2
E1h
All
Slot
Connector
Sensor
Specific
Revision 1.4
105
Intel order number: D41763-005
Appendix B: BMC Sensor Tables
Sensor
Name[1]
Sensor
Number
System
Applicability
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor Type
21h
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
E2h
E3h
E4h
E5h
E6h
E7h
All
All
All
All
All
All
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Event /
Reading
Type
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Event Offset
Triggers
Criticality
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
Device installed
OK
Disabled
Degraded
Sparing
OK
Fault status
asserted
Degraded
Device installed
OK
Disabled
Degraded
Assert /
De-assert
Readable
Value /
Offsets
Event Data
Rearm
Standby
As
–
Trig Offset
A
–
As
–
Trig Offset
A
–
As
–
Trig Offset
A
–
As
–
Trig Offset
A
–
As
–
Trig Offset
A
–
As
–
Trig Offset
A
–
Revision 1.4
106
Intel order number: D41763-005
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name[1]
Sensor
Number
System
Applicability
Sensor Type
Appendix B: BMC Sensor Tables
Event /
Reading
Type
Event Offset
Triggers
Criticality
Sparing
OK
Assert /
De-assert
Readable
Value /
Offsets
Event Data
Rearm
Standby
Memory A
Error
ECh
All
Memory
0Ch
Sensor
Specific
6Fh
Correctable ECC
Uncorrectable
ECC
OK
As
–
Trig Offset
A
–
Memory B
Error
EDh
All
Memory
0Ch
Sensor
Specific
6Fh
Correctable ECC
Uncorrectable
ECC
OK
As
–
Trig Offset
A
–
Memory C
Error
EEh
All
Memory
0Ch
Sensor
Specific
6Fh
Correctable ECC
Uncorrectable
ECC
OK
As
–
Trig Offset
A
–
Memory D
Error
EFh
All
Memory
0Ch
Sensor
Specific
6Fh
Correctable ECC
Uncorrectable
ECC
OK
As
–
Trig Offset
A
–
B0 DIMM
Sparing
Enabled
F0h
All
Entity
Presence
25h
Sensor
Specific
6Fh
Entity present
OK
As
–
Trig Offset
A
–
B0 DIMM
Sparing
Redundancy
F1h
All
Memory
0Ch
Discrete
0Bh
Fully redundant
OK
As
–
Trig Offset
A
–
Non-red: suff res
from redund
Non-red: suff res
from insuff res
Degraded
Non-red: Insuff res Crtical
B1 DIMM
Sparing
Enabled
F2h
All
Entity
Presence
25h
Sensor
Specific
6Fh
Entity present
OK
As
–
Trig Offset
A
–
B1 DIMM
Sparing
Redundancy
F3h
All
Memory
0Ch
Discrete
0Bh
Fully redundant
OK
As
–
Trig Offset
A
–
Non-red: suff res
from redund
Non-red: suff res
from insuff res
Degraded
Non-red: insuff res
Crtical
Revision 1.4
107
Intel order number: D41763-005
Appendix B: BMC Sensor Tables
Sensor
Name[1]
Sensor
Number
B01 DIMM
Mirroring
Enabled
F4h
System
Applicability
All
B01 DIMM
Mirroring
Redundancy
F5h
All
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor Type
Entity
Presence
25h
Event /
Reading
Type
Sensor
Specific
6Fh
Memory
0Ch
Discrete
0Bh
Event Offset
Triggers
Criticality
Assert /
De-assert
Entity present
OK
As
Readable
Value /
Offsets
–
Fully redundant
OK
As
–
Non-red:suff res
from redund
Non-red:suff res
from insuff res
Degraded
Non-red: insuff res
Crtical
Event Data
Rearm
Standby
Trig Offset
A
–
Trig Offset
A
–
Note 1: Actual sensor name strings in SDR may vary from the names in this table, according to platform-specific usage.
Note 2: Not supported except for ESB2 embedded NICs.
Note 3: FBDIMM Aggregate sensor will only have effect when CLTT enabled.
Note 4: For system with redundant cooling capability, the contribution to system status is determined by the fan redundancy sensor.
Note 5: Sensor only presents on systems that have applicable redundancy 9for instance, fan or power supply)
Note 6: Applicable with Intel® Xeon® Processor 5000 series
Note 7: Applicable with Intel® Xeon® Processor 5100 series and 45nm 2P Dual-Core Intel® Xeon® Processor
Note 8: Applicable with Intle® Xeon® Processor 5300 series and 45nm 2P Quad-Core Intel® Xeon® Processor
Revision 1.4
108
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Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder
Appendix C: POST Code Diagnostic LED Decoder
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the
back edge of the server board. To assist in troubleshooting a system hang during the POST
process, the Diagnostic LEDs can be used to identify the last POST process that was executed.
Each POST code is represented by a combination of colors from the four LEDs. The LEDs are
capable of displaying three colors: green, red, and amber. The POST codes are divided into two
nibbles, an upper nibble and a lower nibble. Each bit in the upper nibble is represented by a red
LED and each bit in the lower nibble is represented by a green LED. If both bits are set in the
upper and lower nibbles then both red and green LEDs are lit, resulting in an amber color. If
both bits are clear, then the LED is off.
A. Status LED
D. Bit 2 LED (POST LED)
B. ID LED
E. Bit 1 LED (POST LED)
C. MSB LED (POST LED)
F. LSB LED (POST LED)
Figure 27. Diagnostic LED Placement Diagram
Revision 1.4
109
Intel order number: D41763-005
Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS
In the below example, BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs
are decoded as follows:
Red bits = 1010b = Ah
Green bits = 1100b = Ch
Since the red bits correspond to the upper nibble and the green bits correspond to the lower
nibble, the two are concatenated as ACh.
Table 46. POST Progress Code LED Example
8h
LEDs
ACh
1
Result
Amber
4h
Red
Green
2h
Red
1
0
MSB
Green
1
1h
Red
Green
1
Green
Red
Bit 2
Bit 1
0
Red
0
Green
0
Off
LSB
Table 47. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
Bit 2 Bit 1 LSB
Host Processor
Description
Checkpoint
0x10h
Off
Off
Off
R
Power-on initialization of the host processor (bootstrap processor)
0x11h
Off
Off
Off
A
Host processor cache initialization (including AP)
0x12h
Off
Off
G
R
Starting application processor initialization
0x13h
Off
Off
G
A
SMM initialization
Off
Off
R
G
Initializing a chipset component
Off
Off
A
Off
Reading configuration data from memory (SPD on DIMM)
Chipset
0x21h
Memory
0x22h
0x23h
Off
Off
A
G
Detecting presence of memory
0x24h
Off
G
R
Off
Programming timing parameters in the memory controller
0x25h
Off
G
R
G
Configuring memory parameters in the memory controller
0x26h
Off
G
A
Off
Optimizing memory controller settings
0x27h
Off
G
A
G
Initializing memory, such as ECC init
0x28h
G
Off
R
Off
Testing memory
0x50h
Off
R
Off
R
Enumerating PCI busses
0x51h
Off
R
Off
A
Allocating resources to PCI busses
0x52h
Off
R
G
R
Hot Plug PCI controller initialization
0x53h
Off
R
G
A
Reserved for PCI bus
0x54h
Off
A
Off
R
Reserved for PCI bus
0x55h
Off
A
Off
A
Reserved for PCI bus
0x56h
Off
A
G
R
Reserved for PCI bus
PCI Bus
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder
Checkpoint
0x57h
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
Bit 2 Bit 1 LSB
Off
A
G
A
Description
Reserved for PCI bus
USB
0x58h
G
R
Off
R
Resetting USB bus
0x59h
G
R
Off
A
Reserved for USB devices
ATA / ATAPI / SATA
0x5Ah
G
R
G
R
Resetting PATA / SATA bus and all devices
0x5Bh
G
R
G
A
Reserved for ATA
0x5Ch
G
A
Off
R
Resetting SMBUS
0x5Dh
G
A
Off
A
Reserved for SMBUS
SMBUS
Local Console
0x70h
Off
R
R
R
Resetting the video controller (VGA)
0x71h
Off
R
R
A
Disabling the video controller (VGA)
0x72h
Off
R
A
R
Enabling the video controller (VGA)
R
R
R
Resetting the console controller
Remote Console
0x78h
G
0x79h
G
R
R
A
Disabling the console controller
0x7Ah
G
R
A
R
Enabling the console controller
Keyboard (PS2 or USB)
0x90h
R
Off
Off
R
Resetting the keyboard
0x91h
R
Off
Off
A
Disabling the keyboard
0x92h
R
Off
G
R
Detecting the presence of the keyboard
0x93h
R
Off
G
A
Enabling the keyboard
0x94h
R
G
Off
R
Clearing keyboard input buffer
0x95h
R
G
Off
A
Instructing keyboard controller to run Self Test (PS2 only)
Off
Off
R
Resetting the mouse
Mouse (PS2 or USB)
0x98h
A
0x99h
A
Off
Off
A
Detecting the mouse
0x9Ah
A
Off
G
R
Detecting the presence of mouse
0x9Bh
A
Off
G
A
Enabling the mouse
0xB0h
R
Off
R
R
Resetting fixed media device
0xB1h
R
Off
R
A
Disabling fixed media device
R
Off
A
R
Detecting presence of a fixed media device (IDE hard drive detection,
etc.)
R
Off
A
A
Enabling / configuring a fixed media device
Fixed Media
0xB2h
0xB3h
Removable Media
0xB8h
A
Off
R
R
Resetting removable media device
0xB9h
A
Off
R
A
Disabling removable media device
A
Off
A
R
Detecting presence of a removable media device (IDE CDROM
detection, etc.)
A
G
R
R
Enabling / configuring a removable media device
0xBAh
0xBCh
Boot Device Selection
Revision 1.4
111
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Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS
0xD0
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
Bit 2 Bit 1 LSB
R
R
Off
R
Trying boot device selection
0xD1
R
R
Off
A
Trying boot device selection
0xD2
R
R
G
R
Trying boot device selection
0xD3
R
R
G
A
Trying boot device selection
Checkpoint
Description
0xD4
R
A
Off
R
Trying boot device selection
0xD5
R
A
Off
A
Trying boot device selection
0xD6
R
A
G
R
Trying boot device selection
0xD7
R
A
G
A
Trying boot device selection
0xD8
A
R
Off
R
Trying boot device selection
0xD9
A
R
Off
A
Trying boot device selection
0XDA
A
R
G
R
Trying boot device selection
0xDB
A
R
G
A
Trying boot device selection
0xDC
A
A
Off
R
Trying boot device selection
0xDE
A
A
G
R
Trying boot device selection
0xDF
A
A
G
A
Trying boot device selection
Pre-EFI Initialization (PEI) Core
0xE0h
R
R
R
Off
Started dispatching early initialization modules (PEIM)
0xE2h
R
R
A
Off
Initial memory found, configured, and installed correctly
0xE1h
R
R
R
G
Reserved for initialization module use (PEIM)
0xE3h
R
R
A
G
Reserved for initialization module use (PEIM)
Driver Execution Environment (DXE) Core
0xE4h
R
A
R
Off
Entered EFI driver execution phase (DXE)
0xE5h
R
A
R
G
Started dispatching drivers
0xE6h
R
A
A
Off
Started connecting drivers
0xE7h
R
A
A
G
Waiting for user input
0xE8h
A
R
R
Off
Checking password
DXE Drivers
0xE9h
A
R
R
G
Entering BIOS setup
0xEAh
A
R
A
Off
Flash Update
0xEEh
A
A
A
Off
Calling Int 19. One beep unless silent boot is enabled.
0xEFh
A
A
A
G
Unrecoverable boot failure / S3 resume failure
Runtime Phase / EFI Operating System Boot
0xF4h
R
A
R
R
Entering Sleep state
0xF5h
R
A
R
A
Exiting Sleep state
A
R
R
R
Operating system has requested EFI to close boot services
(ExitBootServices ( ) has been called)
A
R
R
A
Operating system has switched to virtual address mode
(SetVirtualAddressMap ( ) has been called)
A
R
A
R
Operating system has requested the system to reset (ResetSystem ()
has been called)
0xF8h
0xF9h
0xFAh
Pre-EFI Initialization Module (PEIM) / Recovery
0x30h
Off
Off
R
R
Crisis recovery has been initiated because of a user request
0x31h
Off
Off
R
A
Crisis recovery has been initiated by software (corrupt flash)
Revision 1.4
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Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder
0x34h
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
Bit 2 Bit 1 LSB
Off
G
R
R
Loading crisis recovery capsule
0x35h
Off
G
R
A
Handing off control to the crisis recovery capsule
0x3Fh
G
G
A
A
Unable to complete crisis recovery.
Checkpoint
Description
Revision 1.4
113
Intel order number: D41763-005
Appendix D: POST Code Errors
Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix D: POST Code Errors
Whenever possible, the BIOS will output the current boot progress codes on the video screen.
Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class,
subclass, and operation information. The class and subclass fields point to the type of hardware
that is being initialized. The operation field represents the specific initialization activity. Based on
the data bit availability to display progress codes, a progress code can be customized to fit the
data width. The higher the data bit, the higher the granularity of information that can be sent on
the progress port. The progress codes may be reported by the system BIOS or option ROMs.
The response column in the following table is divided into two types:
Pause: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and user input is required to continue. The user can take immediate corrective
action or choose to continue booting.
Halt: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and the system cannot boot unless the error is resolved. The user needs to replace
the faulty part and restart the system.
Table 48. POST Error Messages and Handling
Error Code
004C
Error Message
Keyboard / interface error
Response
Pause
0012
CMOS date / time not set
Pause
5220
Configuration cleared by jumper
Pause
5221
Passwords cleared by jumper
Pause
5223
Configuration default loaded
Pause
0048
Password check failed
Halt
0141
PCI resource conflict
Pause
0146
Insufficient memory to shadow PCI ROM
Pause
8110
Processor 01 internal error (IERR) on last boot
Pause
8111
Processor 02 internal error (IERR) on last boot
Pause
8120
Processor 01 thermal trip error on last boot
Pause
8121
Processor 02 thermal trip error on last boot
Pause
8130
Processor 01 disabled
Pause
8131
Processor 02 disabled
Pause
8160
Processor 01 unable to apply BIOS update
Pause
8161
Processor 02 unable to apply BIOS update
Pause
8190
Watchdog timer failed on last boot
Pause
8198
Operating system boot watchdog timer expired on last boot
Pause
0192
L3 cache size mismatch
Halt
0194
CPUID, processor family are different
Halt
0195
Front side bus mismatch
Pause
0197
Processor speeds mismatched
Pause
8300
Baseboard management controller failed self-test
Pause
8306
Front panel controller locked
Pause
8305
Hotswap controller failed
Pause
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Appendix D: POST Code Errors
Error Code
84F2
Error Message
Baseboard management controller failed to respond
Response
Pause
84F3
Baseboard management controller in update mode
Pause
84F4
Sensor data record empty
Pause
84FF
System event log full
Pause
8500
Memory Component could not be configured in the selected RAS mode.
Pause
8520
DIMM_A1 failed Self Test (BIST).
Pause
8521
DIMM_A2 failed Self Test (BIST).
Pause
8522
DIMM_A3 failed Self Test (BIST).
Pause
8523
DIMM_A4 failed Self Test (BIST).
Pause
8524
DIMM_B1 failed Self Test (BIST).
Pause
8525
DIMM_B2 failed Self Test (BIST).
Pause
8526
DIMM_B3 failed Self Test (BIST).
Pause
8527
DIMM_B4 failed Self Test (BIST).
Pause
8528
DIMM_C1 failed Self Test (BIST).
Pause
8529
DIMM_C2 failed Self Test (BIST).
Pause
852A
DIMM_C3 failed Self Test (BIST).
Pause
852B
DIMM_C4 failed Self Test (BIST).
Pause
852C
DIMM_D1 failed Self Test (BIST).
Pause
852D
DIMM_D2 failed Self Test (BIST).
Pause
852E
DIMM_D3 failed Self Test (BIST).
Pause
852F
DIMM_D4 failed Self Test (BIST).
Pause
8540
Memory component lost redundancy during the last boot.
Pause
8580
DIMM_A1 correctable ECC error encountered.
Pause
8581
DIMM_A2 correctable ECC error encountered.
Pause
8582
DIMM_A3 correctable ECC error encountered.
Pause
8583
DIMM_A4 correctable ECC error encountered.
Pause
8584
DIMM_B1 correctable ECC error encountered.
Pause
8585
DIMM_B2 correctable ECC error encountered.
Pause
8586
DIMM_B3 correctable ECC error encountered.
Pause
8587
DIMM_B4 correctable ECC error encountered.
Pause
8588
DIMM_C1 correctable ECC error encountered.
Pause
8589
DIMM_C2 correctable ECC error encountered.
Pause
858A
DIMM_C3 correctable ECC error encountered.
Pause
858B
DIMM_C4 correctable ECC error encountered.
Pause
858C
DIMM_D1 correctable ECC error encountered.
Pause
858D
DIMM_D2 correctable ECC error encountered.
Pause
858E
DIMM_D3 correctable ECC error encountered.
Pause
858F
DIMM_D4 correctable ECC error encountered.
Pause
8600
Primary and secondary BIOS IDs do not match.
Pause
8601
Override jumper is set to force boot from lower alternate BIOS bank of flash ROM
Pause
8602
Watchdog timer expired (secondary BIOS may be bad!)
Pause
8603
Secondary BIOS checksum fail
Pause
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Appendix D: POST Code Errors
Intel® Server Boards S5000PSL and S5000XSL TPS
POST Error Beep Codes
The following table lists POST error beep codes. Prior to system Video initialization, BIOS uses
these beep codes to inform users on error conditions. The beep code is followed by a user
visible code on POST Progress LEDs.
Table 49. POST Error Beep Codes
Beeps
3
Error Message
Memory error
6
BIOS rolling back
error
POST Progress Code
Description
System halted because a fatal error related to the memory
was detected.
The system has detected a corrupted BIOS in the flash
part, and is rolling back to the last good BIOS.
The BMC may generate beep codes upon detection of failure conditions. Beep codes are
sounded each time the problem is discovered, such as on each power-up attempt, but are not
sounded continuously. Codes that are common across all Intel® server boards and systems that
use the Intel® 5000 chipset are listed in the following table. Each digit in the code is represented
by a sequence of beeps whose count is equal to the digit.
Table 50. BMC Beep Codes
Code
1-5-2-1
Reason for Beep
CPU: Empty slot / population error – Processor
slot 1 is not populated.
Associated Sensors
CPU Population Error
Supported?
Yes
1-5-2-2
CPU: No processors (terminators only)
N/A
No
1-5-2-3
CPU: Configuration error (e.g., VID mismatch)
N/A
No
1-5-2-4
CPU: Configuration error (e.g, BSEL mismatch)
N/A
No
1-5-4-2
Power fault: DC power unexpectedly lost (power
good dropout)
Power Unit – power unit
failure offset
Yes
1-5-4-3
Chipset control failure
N/A
No
1-5-4-4
Power control fault
Power Unit – soft power
control failure offset
Yes
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Appendix D: POST Code Errors
Appendix E: Supported Intel® Server Chassis
The Intel® Server Boards S5000PSL and S5000XSL are supported in the following Intel®
pedestal server chassis:
Intel® Server Chassis SC5400 BASE
Intel® Server Chassis SC5400 BRP
Intel® Server Chassis SC5400 LX
Intel® Server Chassis SC5400 LXi
Intel® Entry Server Chassis SC5299-E DP
Intel® Entry Server Chassis SC5299-E BRP
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Glossary
Intel® Server Boards S5000PSL and S5000XSL TPS
Glossary
This appendix contains important terms used in the preceding chapters. For ease of use,
numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”).
Acronyms are then entered in their respective place, with non-acronyms following.
Term
ACPI
Definition
Advanced Configuration and Power Interface
AP
Application Processor
APIC
Advanced Programmable Interrupt Control
ASIC
Application Specific Integrated Circuit
ASMI
Advanced Server Management Interface
BIOS
Basic Input / Output System
BIST
Built-In Self Test
BMC
Baseboard Management Controller
Bridge
Circuitry connecting one computer bus to another, allowing an agent on one to access the other
BSP
Bootstrap Processor
byte
8-bit quantity.
CBC
Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they
bridge the IPMB buses of multiple chassis.
CEK
Common Enabling Kit
CHAP
Challenge Handshake Authentication Protocol
CMOS
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes
of memory, which normally resides on the server board.
DPC
Direct Platform Control
EEPROM
Electrically Erasable Programmable Read-Only Memory
EHCI
Enhanced Host Controller Interface
EMP
Emergency Management Port
EPS
External Product Specification
ESB2
Enterprise South Bridge 2
FBD
Fully Buffered DIMM
F MB
Flexible Mother Board
FRB
Fault Resilient Booting
FRU
Field Replaceable Unit
FSB
Front Side Bus
GB
1024 MB
GPIO
General Purpose I/O
GTL
Gunning Transceiver Logic
HSC
Hot-Swap Controller
Hz
Hertz (1 cycle / second)
I2C
Inter-Integrated Circuit Bus
IA
Intel® Architecture
IBF
Input Buffer
ICH
I/O Controller Hub
IC MB
Intelligent Chassis Management Bus
IERR
Internal Error
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Term
Glossary
Definition
IFB
I/O and Firmware Bridge
INTR
Interrupt
IP
Internet Protocol
IPMB
Intelligent Platform Management Bus
IPMI
Intelligent Platform Management Interface
IR
Infrared
ITP
In-Target Probe
KB
1024 bytes
KCS
Keyboard Controller Style
LAN
Local Area Network
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LPC
Low Pin Count
LUN
Logical Unit Number
MAC
Media Access Control
MB
1024KB
MCH
Memory Controller Hub
MD2
Message Digest 2 – Hashing Algorithm
MD5
Message Digest 5 – Hashing Algorithm – Higher Security
ms
milliseconds
MTTR
Memory Type Range Register
Mux
Multiplexor
NIC
Network Interface Controller
NMI
Nonmaskable Interrupt
OBF
Output Buffer
OEM
Original Equipment Manufacturer
Ohm
Unit of electrical resistance
PEF
Platform Event Filtering
PEP
Platform Event Paging
PIA
Platform Information Area (This feature configures the firmware for the platform hardware)
PLD
Programmable Logic Device
PMI
Platform Management Interrupt
POST
Power-On Self Test
PSMI
Power Supply Management Interface
PWM
Pulse-Width Modulation
RAM
Random Access Memory
RASUM
Reliability, Availability, Serviceability, Usability, and Manageability
RISC
Reduced Instruction Set Computing
ROM
Read Only Memory
RTC
Real-Time Clock (Component of ICH peripheral chip on the server board)
SDR
Sensor Data Record
SECC
Single Edge Connector Cartridge
SEEPROM
Serial Electrically Erasable Programmable Read-Only Memory
SEL
System Event Log
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Glossary
Intel® Server Boards S5000PSL and S5000XSL TPS
Term
Definition
SIO
Server Input / Output
SMI
Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)
SMM
Server Management Mode
SMS
Server Management Software
SNMP
Simple Network Management Protocol
TBD
To Be Determined
TIM
Thermal Interface Material
UART
Universal Asynchronous Receiver / Transmitter
UDP
User Datagram Protocol
UHCI
Universal Host Controller Interface
UTC
Universal time coordinare
VID
Voltage Identification
VRD
Voltage Regulator Down
Word
16-bit quantity
ZIF
Zero Insertion Force
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Reference Documents
Reference Documents
See the following documents for additional information:
Intel® S5000 Server Board Family Datasheet
Intel Server Boards S5000PSL and S5000XSL Specification Update
Intel 5000 Series Chipset Memory Controller Hub Datasheet.
Intel 631xESB/632xESB I/O Controller Hub Datasheet.
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