Revised November 1999 74ABT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs General Description Features The ABT16541 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Individual 3STATE control inputs can be shorted together for 8-bit or 16-bit operation. ■ Separate control logic for each nibble ■ 16-bit version of the ABT541 ■ Outputs sink capability of 64 mA, source capability of 32 mA ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability Ordering Code: Order Number Package Number 74ABT16541CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ABT16541CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description OE n Output Enable Inputs (Active Low) I0–I15 Inputs O0–O15 Outputs © 1999 Fairchild Semiconductor Corporation DS012149 www.fairchildsemi.com 74ABT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs July 1996 74ABT16541 Truth Tables Functional Description Inputs The ABT16541 contains sixteen non-inverting buffers with 3-STATE outputs. The device is byte (8 bits) controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Outputs OE 1 OE 2 I0–I7 L L L L L L H H H X X Z X H X Z OE 4 OE 3 L L L L L L H H H X X Z X H X Z Inputs O0–O7 Logic Diagrams Outputs I8–I15 O8–O15 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance www.fairchildsemi.com 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. twice the rated IOL (mA) −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) Note 2: Either voltage limit or current limit is sufficient to protect inputs. 10V DC Electrical Characteristics Symbol Parameter Min Typ Max VCC V Conditions Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA IOH = −3 mA VOH 2.0 Units VIH Output HIGH 2.5 V Min 2.0 V Min IOH = −32 mA V Min IOL = 64 mA µA Max µA Max µA Max V 0.0 Output LOW Voltage IIH Input HIGH Current 0.55 1 1 Input HIGH Current 7 Breakdown Test IIL Recognized LOW Signal Voltage VOL IBVI Recognized HIGH Signal −1 Input LOW Current −1 4.75 VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA VID Input Leakage Test IOZH Output Leakage Current 10 µA 0–5.5V VOUT = 2.7V; OEn = 2.0V IOZL Output Leakage Current −10 µA 0–5.5V VOUT = 0.5V; OEn = 2.0V IOS Output Short-Circuit Current −275 mA Max VOUT = 0.0V ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 All Other Pins Grounded −100 VOUT = 5.5V All Other Pins GND ICCH Power Supply Current 100 µA Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 100 µA Max OEn = VCC ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs 3-STATE 2.5 mA Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V mA/ Outputs Open, OEn = GND All Others at VCC or GND VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load (Note 3) 0.1 MHz Max One Bit Toggling, 0.7 V 5.0 TA = 25°C (Note 4) 50% Duty Cycle VOLP Quiet Output Maximum Dynamic VOL 0.4 VOLV Quiet Output Minimum Dynamic VOL −1.3 −1.0 V 5.0 TA = 25°C (Note 4) VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.0 V 5.0 TA = 25°C (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.4 V 5.0 TA = 25°C (Note 5) 3 www.fairchildsemi.com 74ABT16541 Absolute Maximum Ratings(Note 1) 74ABT16541 DC Electrical Characteristics Symbol VILD Parameter (Continued) Min Maximum LOW Level Dynamic Input Voltage Typ Max Units VCC 1.2 0.8 V 5.0 Conditions TA = 25°C (Note 5) Note 3: Guaranteed but not tested. Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD ). Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter TA=+25°C TA = −40°C to +85°C VCC=+5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation 1.0 2.3 3.4 1.0 3.4 tPHL Delay Data to Outputs 1.0 2.7 3.9 1.0 3.9 tPZH Output Enable 1.5 3.5 5.2 1.5 5.2 tPZL Time 1.5 3.5 6.0 1.5 6.0 tPHZ Output Disable 1.0 4.2 5.1 1.0 5.1 tPLZ Time 1.0 3.2 5.1 1.0 5.1 Units ns ns ns Extended AC Electrical Characteristics Symbol −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 16 Outputs Switching 1 Output Switching 16 Outputs Switching Parameter (Note 7) Min (Note 8) Typ Units (Note 9) Max Min Max Min Max fTOGGLE Maximum Toggle Frequency 100 tPLH Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.0 MHz tPHL Data to Outputs 1.5 5.3 1.5 6.0 2.5 8.0 tPZH Output Enable 1.5 6.5 2.5 7.8 2.5 9.5 tPZL Time 1.5 6.5 2.5 7.8 2.5 8.5 tPHZ Output Disable 1.0 6.7 tPLZ Time 1.0 6.7 (Note 10) (Note 10) ns ns ns Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 10: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet. www.fairchildsemi.com 4 Symbol Parameter tOSHL Pin to Pin Skew (Note 13) HL Transitions tOSLH Pin to Pin Skew (Note 13) LH Transitions tPS Duty Cycle (Note 14) LH–HL Skew tOST Pin to Pin Skew (Note 13) LH/HL Transitions tPV Device to Device Skew (Note 15) LH/HL Transitions TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 16 Outputs Switching 16 Outputs Switching (Note 11) (Note 12) Max Max 1.0 1.5 ns 1.0 1.5 ns 1.5 1.5 ns 1.7 2.0 ns 2.0 2.5 ns Units Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). The specification is guaranteed but not tested. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 5.0V COUT (Note 16) Output Capacitance 9.0 pF VCC = 5.0V Note 16: COUT is measured at frequency f = 1 MHz; per MIL STD-883, Method 3012. 5 www.fairchildsemi.com 74ABT16541 Skew 74ABT16541 AC Loading * Includes jig and probe capacitance FIGURE 2. Test Input Pulse Requirements FIGURE 1. Standard AC Test Load Amplitude 3.0V Rep Rate tW tr tf 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT16541 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A 7 www.fairchildsemi.com 74ABT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8