Revised March 2005
74AC273 • 74ACT273
Octal D-Type Flip-Flop
General Description
Features
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
■ Ideal buffer for microprocessor or memory
The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
■ Buffered, asynchronous master reset
■ See 377 for clock enable version
■ See 373 for transparent latch version
■ See 374 for 3-STATE version
■ Outputs source/sink 24 mA
■ 74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number
Package
74AC273SC
M20B
74AC273SJ
M20D
74AC273MTC
Package Description
Number
MTC20
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT273SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT273MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009954
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74AC273 • 74ACT273 Octal D-Type Flip-Flop
November 1988
74AC273 • 74ACT273
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
Data Inputs
MR
Master Reset
CP
Clock Pulse Input
Q0–Q7
Data Outputs
Mode Select-Function Table
Inputs
Logic Symbols
Outputs
Operating Mode
MR
CP
Reset (Clear)
L
Load ‘1'
H
Load ‘0'
H
X
Dn
X
L
H
H
L
L
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
LOW-to-HIGH Transition
IEEE/IEC
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Qn
Supply Voltage (VCC)
Recommended Operating
Conditions
0.5V to 7.0V
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
DC Input Voltage (VI)
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
20 mA
20 mA
0.5V to VCC 0.5V
per Output Pin (ICC or IGND)
0V to VCC
Output Voltage (VO)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
AC Devices
VIN from 30% to 70% of VCC
r 50 mA
VCC @ 3.3V, 4.5V, 5.5V for AC
125 mV/ns
Minimum Input Edge Rate ('V/'t)
r 50 mA
65qC to 150qC
ACT Devices
VIN from 0.8V to 2.0V
Junction Temperature (TJ)
VCC @ 4.5V, 5.5V for ACT
140qC
(PDIP)
4.5V to 5.5V
Minimum Input Edge Rate ('V/'t)
DC VCC or Ground Current
Storage Temperature (TSTG)
2.0V to 6.0V
ACT
Input Voltage (VI)
DC Output Source
or Sink Current (IO)
AC
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
TA
25qC
TA
40qC to 85qC
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
3.0
1.5
2.1
2.1
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
Units
Conditions
VOUT
V
VOUT
0.1V
V
or VCC 0.1V
V
IOUT
50 PA
VIN
VIL or VIH
IOH
12 mA
IOH
24 mA
IOH
24 mA (Note 3)
V
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
r1.0
PA
VI
V
V
50 PA
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL
24 mA
IOL
24 mA (Note 3)
IIN
Maximum Input
(Note 5)
Leakage Current
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 4)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
5.5
40.0
PA
VIN
(Note 5)
Supply Current
4.0
0.1V
or VCC 0.1V
VCC, GND
1.65V Max
3.85V Min
VCC
or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC273 • 74ACT273
Absolute Maximum Ratings(Note 2)
74AC273 • 74ACT273
AC Electrical Characteristics for AC
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 6)
fMAX
tPLH
tPHL
tPHL
Min
Typ
40qC to 85qC
TA
CL
Max
50 pF
Min
Units
Max
Maximum Clock
3.3
90
125
75
Frequency
5.0
140
175
125
Propagation Delay
3.3
4.0
7.0
12.5
3.0
14.0
Clock to Output
5.0
3.0
5.5
9.0
2.5
10.0
Propagation Delay
3.3
4.0
7.0
13.0
3.5
14.5
Clock to Output
5.0
3.0
5.0
10.0
2.5
11.0
Propagation Delay
3.3
4.0
7.0
13.0
3.5
14.0
MR to Output
5.0
3.0
5.0
10.0
2.5
10.5
MHz
ns
ns
ns
Note 6: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
AC Operating Requirements for AC
VCC
Symbol
tS
tH
tW
tW
trec
Parameter
(V)
TA
25qC
CL
50 pF
TA
40qC to 85qC
CL
50 pF
(Note 7)
Typ
Setup Time, HIGH or LOW
3.3
3.5
5.5
6.0
Data to CP
5.0
2.5
4.0
4.5
Units
Guaranteed Minimum
ns
Hold Time, HIGH or LOW
3.3
2.0
0
0
Data to CP
5.0
1.0
1.0
1.0
Clock Pulse Width
3.3
3.5
5.5
6.0
HIGH or LOW
5.0
2.5
4.0
4.5
ns
ns
MR Pulse Width
3.3
2.0
5.5
6.0
HIGH or LOW
5.0
1.5
4.0
4.5
Recovery Time
3.3
1.5
3.5
4.5
MR to CP
5.0
1.0
2.0
3.0
ns
ns
Note 7: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
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4
Symbol
VIH
VIL
VOH
VOL
IIN
Parameter
TA
25qC
TA
40qC to 85qC
(V)
Typ
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Guaranteed Limits
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
4.76
Units
V
V
V
V
Conditions
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
IOUT
50 PA
VIN
VIL or VIH
IOH
24 mA
IOH
24 mA (Note 8)
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
r0.1
r1.0
PA
VI
VCC, GND
1.5
mA
VI
VCC 2.1V
Maximum Input
Leakage Current
ICCT
VCC
Maximum
5.5
5.5
0.6
50 PA
V
IOUT
VIN
VIL or VIH
V
IOL
24 mA
IOL
24 mA (Note 8)
ICC/Input
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 9)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
5.5
40.0
PA
VIN
4.0
Supply Current
1.65V Max
3.85V Min
VCC
or GND
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for ACT
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
CP to Qn
tPHL
Propagation Delay
MR to Qn
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
Max
Min
50 pF
Units
(Note 10)
Min
Typ
Max
2.0
125
189
5.0
1.5
6.5
8.5
1.5
9.0
ns
5.0
1.5
7.0
9.0
1.5
8.5
ns
110
MHz
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
5
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74AC273 • 74ACT273
DC Electrical Characteristics for ACT
74AC273 • 74ACT273
AC Operating Requirements for ACT
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Units
(Note 11)
Typ
Guaranteed Minimum
5.0
1.0
3.5
3.5
ns
5.0
0.5
1.5
1.5
ns
5.0
2.0
4.0
4.0
ns
5.0
1.5
4.0
4.0
ns
5.0
0.5
3.0
3.0
ns
Setup Time, HIGH or LOW
tS
Dn to CP
tH
Hold Time, HIGH or LOW
Dn to CP
tW
Clock Pulse Width
HIGH or LOW
tW
MR Pulse Width
HIGH or LOW
tW
Recovery Time
MR to CP
Note 11: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
CPD
Power Dissipation Capacitance for AC
50.0
Power Dissipation Capacitance for ACT
40.0
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6
pF
Conditions
VCC
VCC
OPEN
5.0V
74AC273 • 74ACT273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74AC273 • 74ACT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74AC273 • 74ACT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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74AC273 • 74ACT273 Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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