MAXIM MAX9969

19-3389; Rev 0; 8/04
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
The MAX9969 dual, low-power, high-speed, pin electronics driver/comparator with 35mA load IC includes,
for each channel, a three-level pin driver, a dual comparator, variable clamps, and an active load. An additional differential comparator allows comparisons
between the two channels. The driver features a wide
voltage range and high-speed operation, includes highimpedance and active-termination (3rd-level drive)
modes, and is highly linear even at low voltage swings.
The dual comparator provides low dispersion (timing
variation) over a wide variety of input conditions, and
differential outputs. The clamps provide damping of
high-speed device-under-test (DUT) waveforms when
the device is configured as a high-impedance receiver.
The programmable load supplies up to 35mA of source
and sink current. The load facilitates contact/continuity
testing, at-speed parametric testing of IOH and IOL,
and pullup of high-output-impedance devices. The
MAX9969A features tighter matching of offset for the
drivers and the comparators.
The MAX9969 provides high-speed, differential control
inputs with optional internal termination resistors that
are compatible with LVPECL, LVDS, and GTL. Flexible
open-collector outputs with optional internal pullup
resistors are available for the comparators. These features significantly reduce the discrete component count
on the circuit board.
A 3-wire, low-voltage, CMOS-compatible serial interface programs the low-leakage, slew-rate limit, and tristate/terminate operational configurations of the
MAX9969.
The MAX9969’s operating range is -1.5V to +6.5V with
power dissipation of only 1.4W per channel. The device
is available in a 100-pin, 14mm x 14mm body, and
0.5mm pitch TQFP. An exposed 8mm x 8mm die pad
on the top of the package facilitates efficient heat
removal. The device is specified to operate with an
internal die temperature of +60°C to +100°C, and features a die temperature monitor output.
Features
♦ Low-Power Dissipation: 1.4W/Channel (typ)
♦ Greatly Reduced Power Penalty when Load
Commutated
♦ High Speed: 1200Mbps at 3VP-P and 1800Mbps
at 1VP-P
♦ Programmable 35mA Active-Load Current
♦ Low Timing Dispersion
♦ Wide -1.5V to +6.5V Operating Range
♦
♦
♦
♦
Active Termination (3rd-Level Drive)
Low-Leakage Mode: 15nA
Integrated Clamps
Integrated Differential Comparator
♦ Interfaces Easily with Most Logic Families
♦ Digitally Programmable Slew Rate
♦ Internal Termination Resistors
♦ Low Offset Error
♦ Pin Compatible with the MAX9967
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9969ADCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9969AGCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9969ALCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9969ARCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9969BDCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9969BGCCQ*
0°C to +70°C
100 TQFP-EPR**
MAX9969BLCCQ
0°C to +70°C
100 TQFP-EPR**
MAX9969BRCCQ
0°C to +70°C
100 TQFP-EPR**
*Future product—contact factory for availability.
**EPR = Exposed pad reversed (TOP).
Applications
High-Performance Mixed-Signal/
System-on-Chip ATE
High-Performance Memory ATE
Pin Configuration and Selector Guide appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1
MAX9969
General Description
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ABSOLUTE MAXIMUM RATINGS
DHV_, DLV_, DTV_, CHV_, CLV_,
COM_ to GND ...................................................-2.5V to +7.5V
CPHV_ to GND .........................................................-1V to +8.5V
CPLV_ to GND..........................................................-3.5V to +6V
DHV_ to DLV_ ......................................................................±10V
DHV_ to DTV_ ......................................................................±10V
DLV_ to DTV_.......................................................................±10V
CHV_ or CLV_ to DUT_ ........................................................±10V
CH_, NCH_, CL_, NCL_ to GND..................................-1V to +5V
All Other Pins to GND ......................(VEE - 0.3V) to (VCC + 0.3V)
TEMP Current...................................................-0.5mA to +20mA
DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous
Continuous Power Dissipation (TA = +70°C)
MAX9969_ _CCQ (derate 167mW/°C above +70°C) ...13.3W*
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature .....................................................+125°C
VCC to GND ............................................................-0.3V to +11V
VEE to GND..........................................................-5.75V to +0.3V
VCC - VEE ...........................................................-0.3V to +16.75V
GS to GND .............................................................................±1V
DUT_ to GND.......................................................-2.75V to +7.5V
LDH_, LDL_ to GND .................................................-0.3V to +6V
DATA_, NDATA_, RCV_, NRCV_, LDEN_,
NLDEN_ to GND...................................................-2.5V to +5V
DATA_ to NDATA_, RCV_ to NRCV_,
LDEN_ to NLDEN_ ..........................................................±1.5V
TDATA_, TRCV_, TLDEN_ to GND ...........................-2.5V to +5V
DATA_, NDATA_, to TDATA_.................................................±2V
RCV_, NRCV_, to TRCV_ .......................................................±2V
LDEN_, NLDEN_ to TLDEN_..................................................±2V
VCCO_ to GND ..........................................................-0.3V to +5V
SCLK, DIN, CS, RST to GND ......................................-1V to +5V
*Dissipation wattage values are based on still air with no heat sink. Actual maximum power dissipation is a function of heat extraction
technique and may be substantially higher.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Positive Supply
VCC
9.5
9.75
10.5
V
Negative Supply
VEE
-5.25
-4.75
-4.50
V
VLDH_ = VLDL_ = 0, RL ≥ 10MΩ
165
185
VLDH_ = VLDL_ = 3.5V, RL = 0,
VCOM_ = 1.5V, load enabled,
driver = high impedance
245
275
VLDH_ = VLDL_ = 0, RL ≥ 10MΩ
-235
-260
VLDH_ = VLDL_ = 3.5V, RL = 0,
VCOM_ = -1V, load enabled,
driver = high impedance
-315
-350
VLDH_ = VLDL_ = 0
2.8
3.2
VLDH_ = VLDL_ = 3.5V, RL = 0,
VCOM_ = 1.5V, load enabled,
driver = high impedance
3.3
3.7
Positive Supply Current (Note 2)
Negative Supply Current (Note 2)
Power Dissipation (Notes 2, 3)
ICC
IEE
PD
mA
mA
W
DUT_ CHARACTERISTICS
Operating Voltage Range
VDUT
(Note 4)
Leakage Current in
High-Impedance Mode
IDUT
Leakage Current in
Low-Leakage Mode
2
-1.5
+6.5
V
LLEAK = 0; VDUT_ = -1.5V, 0, +3V, +6.5V
±3
µA
LLEAK = 1; VDUT_ = -1.5V, 0, +3V, +6.5V
±15
nA
_______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
Combined Capacitance
SYMBOL
CDUT
CONDITIONS
MIN
TYP
MAX
Driver in term mode (DUT_ = DTV_)
3
5
Driver in high-impedance mode
5
6
UNITS
pF
Low-Leakage Enable Time
(Notes 5, 6)
20
µs
Low-Leakage Disable Time
(Notes 6, 7)
0.1
µs
Low-Leakage Recovery
Time to return to the specified maximum
leakage after a 3V, 4V/ns step at DUT_
(Note 7)
4
µs
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_, COM_, LDH_, LDL_)
Input Bias Current
IBIAS
Settling Time
±25
MAX9969_RCCQ
To 0.1% of full scale change (Note 7)
1
µA
µs
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_, LDEN_, NLDEN_)
Input High Voltage
VIH
0
3.5
V
Input Low Voltage
VIL
-0.2
+3.1
V
±0.15
±1.00
Between differential inputs
Differential Input Voltage
VDIFF
Input Bias Current
Input Termination Voltage
VTDATA_
VTRCV_
VTLDEN_
Input Termination Resistor
V
Between a differential input and its
termination voltage (Note 7)
±1.9
MAX9969_DCCQ, MAX9969_RCCQ
±25
µA
MAX9969_GCCQ, MAX9969_LCCQ and
MAX9969_RCCQ
0
+3.5
V
MAX9969_GCCQ, MAX9969_LCCQ, and
MAX9969_RCCQ between signal and
corresponding termination voltage input
47.5
52.5
Ω
1.45
V
SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST)
Internal Threshold Reference
Internal Reference Output
Resistance
External Threshold Reference
VTHRINT
1.05
RO
1.25
20
kΩ
VTHR
0.43
1.73
V
Input High Voltage
VIH
VTHR +
0.2
3.5
V
Input Low Voltage
VIL
-0.1
VTHR 0.2
V
Input Bias Current
IB
±25
µA
50
MHz
SERIAL INTERFACE TIMING (Figure 5)
SCLK Frequency
fSCLK
SCLK Pulse-Width High
tCH
8
ns
SCLK Pulse-Width Low
tCL
8
ns
CS Low to SCLK High Setup
tCSS0
3.5
ns
CS High to SCLK High Setup
tCSS1
3.5
ns
_______________________________________________________________________________________
3
MAX9969
ELECTRICAL CHARACTERISTICS (continued)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SCLK High to CS High Hold
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tCSH1
3.5
ns
DIN to SCLK High Setup
tDS
3.5
ns
DIN to SCLK High Hold
tDH
3.5
ns
tCSWH
20
ns
CS Pulse Width High
TEMPERATURE MONITOR (TEMP)
TJ = +70°C, RL ≥ 10MΩ
Nominal Voltage
Temperature Coefficient
Output Resistance
3.33
V
+10
mV/°C
20
kΩ
DRIVERS (Note 8)
DC OUTPUT CHARACTERISTICS (RL ≥ 10MΩ)
DHV_, DLV_, DTV_,
Output Offset Voltage
VOS
At DUT_ with VDHV_,
VDTV_, VDLV_
independently tested
at +1.5V
MAX9969A
±15
MAX9969B
±100
mV
DHV_, DLV_, DTV_, Output Offset
Temperature Coefficient
DHV_, DLV_, DTV_, Gain
+200
AV
Measured with VDHV_, VDLV_,
and VDTV_ at 0 and 4.5V
0.960
DHV_, DLV_, DTV_, Gain
Temperature Coefficient
µV/°C
1.001
-50
V/V
ppm/°C
VDUT_ = 1.5V, 3V (Note 9)
±5
Full range (Notes 9, 10)
±15
DHV_ to DLV_ Crosstalk
VDLV_ = 0; VDHV_ = 200mV, 6.5V
±2
mV
DLV_ to DHV_ Crosstalk
VDHV_ = 5V; VDLV_ = -1.5V, +4.8V
±2
mV
DTV_ to DLV_ and DHV_
Crosstalk
VDHV_ = 3V; VDLV_ = 0;
VDTV_ = -1.5V, +6.5V
±2
mV
DHV_ to DTV_ Crosstalk
VDTV_ = 1.5V; VDLV_ = 0; VDHV_ = 1.6V, 3V
±2
mV
DLV_ to DTV_ Crosstalk
VDTV_ = 1.5V; VDHV_ = 3V; VDLV_ = 0, 1.4V
±2
mV
(Note 11)
±18
mV/V
Linearity Error
DHV_, DTV_, DLV_ DC
Power-Supply Rejection Ratio
PSRR
Maximum DC Drive Current
IDUT_
DC Output Resistance
RDUT_
DC Output Resistance Variation
_RDUT_
±40
mV
±80
mA
50
51
Ω
IDUT_ = ±1mA, ±8mA
0.5
1
IDUT_ = ±1mA, ±8mA, ±15mA, ±40mA
0.75
1.5
IDUT_ = ±30mA (Note 12)
49
Ω
DYNAMIC OUTPUT CHARACTERISTICS (ZL = 50Ω)
AC Drive Current
Drive-Mode Overshoot
4
±80
mA
VDLV_ = 0, VDHV_ = 0.1V
15
22
VDLV_ = 0, VDHV_ = 1V
110
130
VDLV_ = 0, VDHV_ = 3V
210
370
_______________________________________________________________________________________
mV
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Drive-Mode Undershoot
TYP
MAX
VDLV_ = 0, VDHV_ = 0.1V
CONDITIONS
MIN
4
11
VDLV_ = 0, VDHV_ = 1V
20
65
VDLV_ = 0, VDHV_ = 3V
30
185
60
150
VDUT_ = 1.0VP-P,
tR = tF = 250ps
10% to 90%
Term-Mode Overshoot
VDUT_ = 3.0VP-P,
tR = tF = 500ps
10% to 90%
High-Impedance Mode Spike
mV
mV
(Note 13)
Term-Mode Spike
UNITS
0
VDHV_ = VDTV_ = 1V, VDLV_ = 0
180
250
VDLV_ = VDTV_ = 0, VDHV_ = 1V
180
250
VDLV_ = -1.0V, VDHV_ = 0
100
VDLV_ = 0, VDHV_ = 1V
100
mV
mV
Settling Time to within 25mV
3V step (Note 14)
4
ns
Settling Time to within 5mV
3V step (Note 14)
40
ns
TIMING CHARACTERISTICS (ZL = 50Ω) (Note 15)
Prop Delay, Data to Output
tPDD
1.5
Prop Delay Match, tLH vs. tHL
3VP-P
Prop Delay Match, Drivers within
Package
(Note 16)
Prop Delay Temperature
Coefficient
Prop Delay Change vs.
Pulse Width
1.7
2.0
ns
±40
±80
ps
40
ps
+1.6
ps/°C
0.2VP-P, 40MHz,
0.6ns to 24.4ns pulse
width, relative to
12.5ns pulse width
MAX9969_DCCQ
±70
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
±25
1VP-P, 40MHz, 0.6ns
to 24.4ns pulse width,
relative to 12.5ns
pulse width
MAX9969_DCCQ
±70
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
±25
3VP-P, 40MHz, 0.9ns
to 24.1ns pulse width,
relative to 12.5ns
pulse width
MAX9969_DCCQ
±80
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
±35
5VP-P, ZL = 500Ω,
40MHz, 1.4ns to
23.6ns pulse width,
relative to 12.5ns
pulse width
MAX9969_DCCQ
±100
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
±100
±50
±50
ps
±60
_______________________________________________________________________________________
5
MAX9969
ELECTRICAL CHARACTERISTICS (continued)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Prop Delay Change vs.
Common-Mode Voltage
CONDITIONS
MIN
VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V
TYP
MAX
UNITS
50
75
ps
Prop Delay,
Drive to High Impedance
tPDDZ
VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0
2.0
2.3
2.6
ns
Prop Delay,
High Impedance to Drive
tPDZD
VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0
3.0
3.4
3.9
ns
-1.3
-1.1
-0.9
ns
0.4
0.6
0.8
ns
1.7
2.0
2.3
ns
Prop Delay Match,
tPDDZ vs. tPDZD
Prop Delay Match, tPDDZ vs. tLH
Prop Delay, Drive to Term
tPDDT
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V
Prop Delay, Term to Drive
tPDTD
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V
2.0
2.3
2.7
ns
Prop Delay Match, tPDDT vs. tPDTD
0.5
0.3
0.1
ns
Prop Delay Match, tPDDT vs. tLH
0.1
0.3
0.5
ns
0.2VP-P, 10% to 90%
300
350
400
1VP-P, 10% to 90%
330
390
450
3VP-P, 10% to 90%
500
650
750
5VP-P, ZL = 500Ω, 10% to 90%
800
1000
1200
DYNAMIC PERFORMANCE (ZL = 50Ω)
Rise and Fall Time
Rise and Fall Time Match
tR, tF
tR vs. tF
3VP-P, 10% to 90%
±50
ps
ps
SC1 = 0, SC0 = 1 Slew Rate
Percent of full speed (SC0 = SC1 = 0),
3VP-P, 20% to 80%
63
70
77
%
SC1 = 1, SC0 = 0 Slew Rate
Percent of full speed (SC0 = SC1 = 0),
3VP-P, 20% to 80%
40
47
55
%
SC1 = 1, SC0 = 1 Slew Rate
Percent of full speed (SC0 = SC1 = 0),
3VP-P, 20% to 80%
18
25
32
%
Minimum Pulse Width
(Note 17)
Data Rate
(Note 18)
Dynamic Crosstalk
(Note 19)
0.2VP-P
550
1VP-P
550
630
3VP-P
850
1000
5VP-P, ZL = 500Ω
1300
0.2VP-P
1800
1VP-P
1800
3VP-P
1200
5VP-P, ZL = 500Ω
800
ps
Mbps
12
mVP-P
Rise and Fall Time, Drive to Term
tDTR, tDTF
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V,
10% to 90%, Figure 1a (Note 20)
0.6
1.0
1.3
ns
Rise and Fall Time, Term to Drive
tTDR, tTDF
VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V,
10% to 90%, Figure 1b (Note 20)
0.6
1.0
1.3
ns
6
_______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+6.5
V
COMPARATORS (Note 8)
DC CHARACTERISTICS
Input Voltage Range
VIN
Differential Input Voltage
VDIFF
Hysteresis
VHYST
Input Offset Voltage
VOS
(Note 4)
-1.5
±8
0
VDUT_ = 1.5V
±20
MAX9969B
±100
±10
CMRR
Linearity Error
VDUT_ = -1.5V, +6.5V (Note 21)
(Note 10)
Power-Supply Rejection Ratio
mV
MAX9969A
Input Offset Voltage Temperature
Coefficient
Common-Mode Rejection Ratio
V
PSRR
±0.25
µV/°C
±2
VDUT_ = 1.5V, 3V
±3
VDUT_ = -1.5V, +6.5V
±10
VDUT_ = 1.5V (Note 11)
±0.035
mV
±2
mV/V
mV
mV/V
AC CHARACTERISTICS (Note 22)
Term mode, tR = tF = 150ps
Bandwidth
High-impedance mode
Minimum Pulse Width
Prop Delay
tPW(MIN)
2
3
0.65
0.75
MAX9969_LCCQ
and MAX9969_RCCQ
500
MAX9969_DCCQ
and MAX9969_GCCQ
600
GHz
650
(Note 23)
ps
tPDL
1.0
1.3
1.6
ns
Prop Delay Temperature
Coefficient
+1.7
Prop Delay Match, High/Low vs.
Low/High
±10
Prop Delay Match High vs. Low
Comparator
±50
ps
±80
ps
ps/°C
±50
Prop Delay Match, Comparators
within Package
(Note 16)
Prop Delay Dispersion vs.
Common-Mode Input
VCHV_ = VCLV_ = -1.4V to +6.4V
(Note 24)
40
60
VCHV_ = VCLV_ = 0.1V to 0.9V,
VDUT_ = 1VP-P, tR = tF = 250ps,
10% to 90% relative to timing at 50% point
±40
±60
Prop Delay Dispersion vs.
Overdrive
Prop Delay Dispersion vs.
Pulse Width
ps
ps
ps
VCHV_ = VCLV_ = 40mV to 160mV,
VDUT_ = 0.2VP-P, tR = tF = 150ps,
10% to 90% relative to timing at 50% point
±40
±60
0.6ns to 24.4ns pulse width, relative to
12.5ns pulse width
±30
±50
ps
_______________________________________________________________________________________
7
MAX9969
ELECTRICAL CHARACTERISTICS (continued)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Prop Delay Dispersion vs.
Slew Rate
Waveform Tracking 10% to 90%
DUT_ Slew-Rate Tracking
CONDITIONS
MIN
TYP
MAX
UNITS
0.5V/ns to 6V/ns slew rate,
relative to 4V/ns slew rate
±30
±60
ps
VDUT_ = 1.0VP-P, tR = tF = 250ps,
10% to 90% relative to timing at 50% point,
term mode
±40
±60
VDUT_ = 1.0VP-P, tR = tF = 250ps,
10% to 90% relative to timing at 50% point,
high-impedance mode
±190
±250
VDUT_ = 3VP-P, tR = tF = 500ps,
10% to 90% relative to timing at 50% point,
high-impedance mode
±150
±200
Term mode
6
High-impedance mode
5
ps
V/ns
LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_)
VCCO_ Voltage Range
VVCCO_
VCCO_ Current
IVCCO_
Output Low Voltage Compliance
0
Set by IOL, RTERM, and VCCO_
Output High Current
IOH
MAX9969_DCCQ, MAX9969_GCCQ
Output Low Current
IOL
MAX9969_DCCQ, MAX9969_GCCQ
Output Current Swing
VCCO_
- 0.05
VOH
ICH_ = INCH_ = ICL_ = INCL_ = 0,
MAX9969_LCCQ, MAX9969_RCCQ
Output Low Voltage
VOL
ICH_ = INCH_ = ICL_ = INCL_ = 0,
MAX9969_LCCQ, MAX9969_RCCQ
Output Voltage Swing
Output Termination Resistor
Differential Rise and Fall Times
RTERM
tR, tF
V
+0.3
mA
8.4
mA
VCCO_
- 0.005
VCCO_
+ 0.01
V
mA
VCCO_
- 0.4
ICH_ = INCH_ = ICL_ = INCL_ = 0,
MAX9969_LCCQ, MAX9969_RCCQ
380
Single-ended measurement from VCCO_ to
CH_, NCH_, CL_, NCL_, MAX9969_LCCQ,
MAX9969_RCCQ
48
20% to 80%
-0.5
8
7.6
V
mA
-0.1
MAX9969_DCCQ, MAX9969_GCCQ
Output High Voltage
3.5
32
400
MAX9969_DCCQ,
MAX9969_GCCQ,
RTERM = 50Ω at end of line
240
MAX9969_LCCQ,
MAX9969_RCCQ
190
V
420
mV
52
Ω
ps
230
CLAMPS
High Clamp Input Voltage Range
VCPH_
0
+7.5
V
Low Clamp Input Voltage Range
VCPL_
-2.5
+5.0
V
Clamp Offset Voltage
8
VOS
At DUT_ with IDUT_ = 1mA, VCPHV_ = 0
±100
At DUT_ with IDUT_ = -1mA, VCPLV_ = 0
±100
_______________________________________________________________________________________
mV
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
Offset-Voltage Temperature
Coefficient
Clamp Power-Supply
Rejection Ratio
Voltage Gain
PSRR
(Note 11)
IDUT_ = 1mA,
VCPHV_ = 0
±10
IDUT_ = -1mA,
VCPLV_ = 0
±10
µV/°C
0.960
1.005
-30
Clamp Linearity
ISCDUT_
ROUT
Clamp DC Impedance Variation
UNITS
mV/V
Voltage-Gain Temperature
Coefficient
Clamp DC Impedance
MAX
±250
AV
Short-Circuit Output Current
TYP
IDUT_ = 1mA, VCPLV_ = -1.5V,
VCPHV_ = 0 to 6.5V
±10
IDUT_ = -1mA, VCPHV_ = 6.5V,
VCPLV_ = -1.5V to +5V
±10
V/V
ppm/°C
mV
VCPHV_ = 0, VCPLV_ = -1.5V,
VDUT_ = 6.5V
40
80
VCPHV_ = 6.5V, VCPLV_ = 5V,
VDUT_ = -1.5V
-80
-40
VCPHV_ = 3V, VCPLV_ = 0,
IDUT_ = ±5mA and ±15mA
50
55
mA
VCPHV_ = 2.5V; VCPLV_ = -1.5V;
IDUT_ = 10mA, 20mA, 30mA
1.5
VCPHV_ = 6.5V; VCPLV_ = 2.5V;
IDUT_ = -10mA, -20mA, -30mA
1.5
Ω
Ω
ACTIVE LOAD (VCOM_ = 1.5V, RL > 1MΩ, driver in high-impedance mode unless otherwise noted)
COM_ Voltage Range
VCOM_
Differential Voltage Range
COM_ Offset Voltage
VDUT_ - VCOM_
Vos
-1
+6
V
-7.5
+7.5
V
±100
mV
ISOURCE = ISINK = 20mA
Offset-Voltage Temperature
Coefficient
COM_ Voltage Gain
+100
AV
VCOM_ = 0, 4.5V; ISOURCE = ISINK = 20mA
Voltage-Gain Temperature
Coefficient
1.00
VCOM_ = -1V, +6V;
ISOURCE = ISINK = 20mA
PSRR
VCOM_ = 2.5V,
ISOURCE = ISINK = 20mA
±3
V/V
ppm/°C
-10
COM_ Linearity Error
COM_ Output Voltage
Power-Supply Rejection Ratio
0.98
µV/°C
±15
mV
±10
mV/V
_______________________________________________________________________________________
9
MAX9969
ELECTRICAL CHARACTERISTICS (continued)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Output Resistance,
Sink or Source
Output Resistance,
Linear Region
Ro
Ro
Deadband
CONDITIONS
VDUT_ = 3V, 6.5V with ISOURCE =
ISINK = 35mA
VCOM_ = -1V and
VDUT_ = -1.5V, +2V
ISOURCE =
with VCOM_ = 6V
ISINK = 1mA
MIN
TYP
MAX
UNITS
30
kΩ
500
IDUT_ = ±33.25mA,
ISOURCE = ISINK = 35mA,
VCOM_ = 2.5V verfied by deadband test
11
15
Ω
VCOM_ = 2.5V, 95% ISOURCE to 95% ISINK
700
800
mV
40
mA
10
10.25
mA/V
0
µA
SOURCE CURRENT (VDUT_ = 4.5V)
Maximum Source Current
VLDL_ = 3.8V
36
Source Programming Gain
ATC
VLDL_ = 0.2V, 3V; VLDH_ = 0.1V
Source Current Offset (Combined
Offset of LDL_ and GS)
IOS
VLDL_ = 200mV
Source-Current Temperature
Coefficient
Source-Current Power-Supply
Rejection Ratio
9.75
-1000
ISOURCE = 35mA
PSRR
Source Current Linearity
-15
µA/°C
ISOURCE = 25mA
±60
ISOURCE = 35mA
±84
(Note 25)
VLDL_ = 100mV,
1V, 2.25V
±60
VLDL_ = 3V
±130
µA/V
µA
SINK CURRENT (VDUT_ = -1.5V)
Maximum Sink Current
VLDH_ = 3.8V
-40
Sink Programming Gain
ATC
VLDH_ = 0.2V, 3V; VLDL_ = 0.1V
Sink-Current Offset (Combined
Offset of LDH_ and GS)
IOS
VLDH_ = 200mV
Sink-Current Temperature
Coefficient
Sink-Current Power-Supply
Rejection Ratio
-10.25
0
ISINK = 35mA
PSRR
Sink-Current Linearity
-10
-36
mA
-9.75
mA/V
1000
µA
+8
µA/°C
ISINK = 25mA
±60
ISINK = 35mA
±84
(Note 25)
VLDH_ = 100mV,
1V, 2.25V
±60
VLDH_ = 3V
±130
µA/V
µA
GROUND SENSE
GS Voltage Range
GS Common-Mode Error
GS Input Bias Current
10
VGS
Verified by GS common-mode error test
±250
mV
VDUT_ = -1.5V, VGS = ±250mV,
VLDH_ - VGS = 0.2V
±20
VDUT_ = +4.5V, VGS = ±250mV,
VLDL_ - VGS = 0.2V
±20
VGS = 0
±25
______________________________________________________________________________________
µA
µA
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
ISOURCE = 10mA,
VCOM_ = -1V
3
3.5
4
ISINK = 10mA,
VCOM_ = 1V
3
3.5
4
ISOURCE = 10mA,
VCOM_ = 1V
1.7
2
2.3
ISINK = 10mA,
VCOM_ = -1V
1.7
UNITS
AC CHARACTERISTICS (ZL = 50Ω to GND)
Enable Time
tEN
Disable Time
tDIS
Current Settling Time on
Commutation
Spike During Enable/Disable
Transition
(Note 26)
(Note 26)
ISOURCE = ISINK =
1mA (Note 27)
ISOURCE = ISINK =
20mA (Note 27)
ns
ns
2
To 10%
15
To 1.5%
50
To 10%
3
To 1.5%
15
ISOURCE = ISINK = 35mA, VCOM_ = 0
200
2.3
5
300
ns
mV
Note 1: All minimum and maximum DC and driver 3V rise- and fall-time test limits are 100% production tested. All other test limits
are guaranteed by design. Tests are performed at nominal supply voltages, unless otherwise noted.
Note 2: Total for dual device at worst-case setting.
Note 3: Does not include above ground internal dissipation of the comparator outputs. Additional power dissipation is typically
(32mA x VVCCO_)
Note 4: Externally forced voltages may exceed this range provided that the Absolute Maximum Ratings are not exceeded.
Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 6: Based on simulation results only.
Note 7: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 8: With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 9: Specifications measured at the endpoints of the full range. Full range is -1.3V ≤ VDHV_ ≤ +6.5V, -1.5V ≤ VDLV_ ≤ +6.3V,
-1.5V ≤ VDTV_ ≤ +6.5V.
Note 10: Relative to straight line between 0 and 4.5V.
Note 11: Change in offset voltage with power supplies independently set to their minimum and maximum values.
Note 12: Nominal target value is 50Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range.
Note 13: VDTV_ = midpoint of voltage swing, RS = 50Ω. Measurement is made using the comparator.
Note 14: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
Note 15: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output
swing. Rise time of the differential inputs DATA_ and RCV_ are 250ps (10% to 90%).
Note 16: Rising edge to rising edge or falling edge to falling edge.
Note 17: Specified amplitude is programmed. At this pulse width, the output reaches at least 90% of its nominal (DC) amplitude. The
pulse width is measured at DATA_.
Note 18: Specified amplitude is programmed. Maximum data rate is specified in transitions per second. A square wave that reaches
at least 90% of its programmed amplitude may be generated at one-half of this frequency.
Note 19: Crosstalk from either driver to the other. Aggressor channel is driving 3VP-P into a 50Ω load. Victim channel is in term mode
with VDTV_ = +1.5V.
Note 20: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when VDLV_ < VDTV_ < VDHV_. If
VDTV_ < VDLV_ or VDTV_ > VDHV_, switching speed is degraded by a factor of approximately 3.
Note 21: Change in offset voltage over the input range.
______________________________________________________________________________________
11
MAX9969
ELECTRICAL CHARACTERISTICS (continued)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -4.75V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ =
+85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +60°C to +100°C, unless otherwise noted.) (Note 1)
Note 22: Unless otherwise noted, all propagation delays are measured at 40MHz, VDUT_ = 0 to +1V, VCHV_ = VCLV_ = +0.5V, tR = tF
= 250ps, ZS = 50Ω, driver in term mode with VDTV_ = +0.5V. Comparator outputs are terminated with 50Ω to 1.25V and
VCCO_ = 2.5V. Measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs.
Note 23: At this pulse width, the output reaches at least 90% of its DC voltage swing. The pulse width is measured at the crossing
points of the differential outputs.
Note 24: VDUT_ = 200mVP-P. Overdrive = 100mV.
Note 25: Relative to segmented interpolations between 200mV, 2V, 2.5V, and 3.5V.
Note 26: Measured from crossing of LDEN_ inputs to the 50% point of the output current change.
Note 27: VCOM = 1V, RS = 50Ω, driving voltage = 1.55V to 0.45V transition and 0.45V to 1.55V transition (at 1mA) or +2.5V to -0.5V
transition and -0.5V to +2.5V transition (at 20mA). Settling time is measured from VDUT_ = 1V to ISINK/ISOURCE settling within specified tolerance.
tDTF
90%
DHV_
10%
DTV_
90%
DLV_
10%
tDTR
(A) DRIVE-TO-TERM RISE AND FALL TIME
tTDR
90%
DHV_
10%
DTV_
90%
10%
DLV_
tTDF
(B) TERM-TO-DRIVE RISE AND FALL TIME
Figure 1. Drive-to-Term and Term-to-Drive Rise and Fall Times
12
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
VDHV_ = 200mV
VDHV_ = 100mV
VDHV_ = 3V
VDHV_ = 5V
VDHV_ = 3V
VDHV_ = 1V
VDHV_ = 1V
0
0
0
DRIVER 1V 600Mbps
SIGNAL RESPONSE
DRIVER 1V 1800Mbps
SIGNAL RESPONSE
DRIVER 3V 400Mbps
SIGNAL RESPONSE
VDUT_ = 100mV/div
0
0
VDLV_ = 0
VDLV_ = 3V
RL = 50Ω
VDUT_ = 250mV/div
VDUT_ = 100mV/div
VDLV_ = 0, VDHV_ = 1V, RL = 50Ω
MAX9969 toc06
t = 2.0ns/div
MAX9969 toc05
t = 2.0ns/div
MAX9969 toc04
t = 2.0ns/div
VDLV_ = 0, VDHV_ = 1V, RL = 50Ω
MAX9969 toc03
MAX9969 toc02
VDHV_ = 5V
VDLV_ = 0
RL = 500Ω
CL = 0.1pF
VDUT_ = 1V/div
VDUT_ = 500mV/div
VDHV_ = 500mV
VDLV_ = 0
RL = 50Ω
VDUT_ = 500mV/div
VDLV_ = 0
RL = 50Ω
DRIVER LARGE-SIGNAL RESPONSE
INTO 500Ω
DRIVER LARGE-SIGNAL RESPONSE
MAX9969 toc01
DRIVER SMALL-SIGNAL RESPONSE
0
t = 200ps/div
t = 1ns/div
DRIVER 3V 1200Mbps
SIGNAL RESPONSE
DRIVER DYNAMIC
CURRENT-LIMIT RESPONSE
DRIVER 3V TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH
IDUT_ = 40mA/div
0
DRIVER SINKING
MAX9969 toc09
POSITIVE PULSE
20
TIMING ERROR (ps)
DRIVER SOURCING
VDUT_ = 250mV/div
40
MAX9969 toc08
MAX9969 toc07
t = 500ps/div
0
-20
NEGATIVE PULSE
-40
-60
VDLV_ = 0
0 VDHV_ = 3V
RL = 50Ω
-80
RL = 10Ω
t = 250ps/div
t = 50ns/div
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns, VDHV_ = +3V, VDLV_ = 0
-100
0
5
10
15
20
25
PULSE WIDTH (ns)
______________________________________________________________________________________
13
MAX9969
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DRIVER 1V TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
0
-10
10
MAX9969 toc12
FALLING EDGE
DLV_ TO DTV_
-10
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns, VDHV_ = +1V, VDLV_ = 0
0
RL = 50Ω
NORMALIZED AT VCM = 1.5V
-30
-20
15
25
20
-1
0
1
2
3
4
DRIVE TO
HIGH-IMPEDANCE TRANSITION
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
8
0
8
4
2
0
-2
DUT_ = DLV_
VDLV_ = +6.5V
VDTV_ = 0
6
LINEARITY ERROR (mV)
LINEARITY ERROR (mV)
DHV_ TO HIGH IMPEDANCE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DUT_ = DHV_
VDLV_ = -1.5V
VDTV_ = 0
6
t = 2.0ns/div
6
5
COMMON-MODE VOLTAGE (V)
MAX9969 toc15
10
PULSE WIDTH (ns)
MAX9969 toc14
5
MAX9969 toc13
0
VDUT_ = 250mV/div
RISING EDGE
20
0
NEGATIVE PULSE
-20
DHV_ TO DTV_
30
VDUT_ = 250mV/div
POSITIVE PULSE
10
MAX9969 toc11
40
TIME DELAY (ps)
TIMING ERROR (ps)
20
DRIVE-TO-TERM TRANSITION
50
MAX9969 toc10
30
4
2
0
-2
-4
-4
-6
-6
DLV_ TO HIGH IMPEDANCE
-8
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
6
1.5
2.5
3.5
4.5
5.5
0
-2
VDHV_ = 5V
VDTV_ = 1.5V
-0.5
-6
-1.5
1.5
2.5
3.5
VDUT_ (V)
14
4.5
5.5
6.5
6.5
1.5
VDLV_ = 0
VDTV_ = 1.5V
0.5
0
-0.5
-1.0
-1.5
NORMALIZED AT VDHV_ = 5V
-2.0
-1.5 -0.5 0.5
5.5
2.0
NORMALIZED AT VDLV_ = 0
-8
4.5
1.0
0
-1.0
3.5
CROSSTALK TO DUT_ FROM
DHV_ WITH DUT_ = DLV_
0.5
-4
2.5
CROSSTALK TO DUT_ FROM
DLV_ WITH DUT_ = DHV_
VDUT_ ERROR (mV)
2
1.5
VDUT_ (V)
1.0
VDUT_ ERROR (mV)
4
-1.5 -0.5 0.5
VDUT_ (V)
2.0
1.5
6.5
MAX9969 toc17
DUT_ = DTV_
VDLV_ = -1.5V
VDHV_ = +6.5V
MAX9969 toc16
8
-8
-1.5 -0.5 0.5
t = 2.0ns/div
MAX9969 toc18
RL = 50Ω
LINEARITY ERROR (mV)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
-2.0
-1.5 -0.5 0.5
1.5
2.5
VDLV_ (V)
3.5
4.5
5.5
6.5
-1.5 -0.5 0.5
1.5
2.5
3.5
VDHV_ (V)
______________________________________________________________________________________
4.5
5.5
6.5
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
CROSSTALK TO DUT_ FROM
DTV_ WITH DUT_ = DLV_
0.6
0.4
0.2
0
-0.2
VDLV_ = 0
VDHV_ = 6.5V
0.8
0.6
VDUT_ ERROR (mV)
0.4
0.2
0
-0.2
0.4
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
NORMALIZED AT VDTV_ = 1.5V
3.5
4.5
5.5
6.5
-1.5 -0.5 0.5
1.5
CROSSTALK TO DUT_ FROM
DHV_ WITH DUT_ = DTV_
3.5
4.5
5.5
6.5
-1.5 -0.5 0.5
1.0010
0.4
-0.2
3
1.0000
0.9995
-0.4
-0.6
-4
NORMALIZED AT TJ = +85°C
1.5
2.5
3.5
4.5
5.5
6.5
60
65
70
75
80
85
90
95
VDHV_ (V)
TEMPERATURE (°C)
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
COMPARATOR TIMING VARIATION
vs. COMMON-MODE VOLTAGE
0.5
0
-0.5
-1.0
10
5
-5
1.5
2.5
3.5
4.5
COMMON-MODE VOLTAGE (V)
5.5
6.5
85
90
95
0
100
-10
RISING EDGE
-20
FALLING EDGE
-30
-40
NORMALIZED AT VCM = 1.5V
-1.5 -0.5 0.5
NORMALIZED AT 50% REFERENCE LEVEL
VDUT_ = 0 TO 1V PULSE
-60
RISING EDGE
-10
-1.5 -0.5 0.5
80
-50
NORMALIZED AT VCM = 1.5V
-2.0
75
10
MAX9969 toc26
FALLING EDGE
0
-1.5
70
COMPARATOR WAVEFORM TRACKING
20
15
65
TEMPERATURE (°C)
25
TIMING VARIATION (ps)
1.0
60
100
30
MAX9969 toc25
OTHER COMPARATOR REFERENCE = 2.5V
1.5
NORMALIZED AT TJ = +85°C
-5
0.9985
-1.5 -0.5 0.5
0
-1
-3
NORMALIZED AT VDHV_ = 3V
-1.0
1
-2
0.9990
-0.8
6.5
5.5
4
OFFSET (mV)
GAIN (V/V)
0
4.5
2
1.0005
0.2
3.5
5
MAX9969 toc23
0.6
2.5
DRIVER OFFSET vs. TEMPERATURE
1.0015
MAX9969 toc22
VDTV_ = 1.5V
VDLV_ = -1.5V
1.5
VDLV_ (V)
DRIVER GAIN vs. TEMPERATURE
1.0
2.0
2.5
VDTV_ (V)
MAX9969 toc24
2.5
MAX9969 toc27
1.5
NORMALIZED AT VDLV_ = 0
-1.0
VDTV_ (V)
0.8
-0.8
NORMALIZED AT VDTV_ = 1.5V
-1.0
-1.5 -0.5 0.5
VDUT_ ERROR (mV)
0.6
-0.6
-1.0
VDTV_ = 1.5V
VDHV_ = 6.5V
0.8
-0.4
-0.8
OFFSET (mV)
1.0
TIMING VARIATION (ps)
VDUT_ ERROR (mV)
1.0
VDUT_ ERROR (mV)
VDHV_ = 3V
VDLV_ = 0
MAX9969 toc20
0.8
MAX9969 toc19
1.0
CROSSTALK TO DUT_ FROM
DLV_ WITH DUT_ = DTV_
MAX9969 toc21
CROSSTALK TO DUT_ FROM
DTV_ WITH DUT_ = DHV_
1.5
2.5
3.5
4.5
COMMON-MODE VOLTAGE (V)
5.5
6.5
-70
0
20
40
60
80
100
REFERENCE LEVEL (%)
______________________________________________________________________________________
15
MAX9969
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
COMPARATOR TRAILING-EDGE TIMING
VARIATION vs. PULSE WIDTH
HIGH PULSE
-15
-20
-25
10
5
VDUT_ FALLING
0
-5
-10
MAX9969 toc30
15
VOUT = 100mV/div
-5
-10
MAX9969 toc29
0
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE
20
TIMING VARIATION (ps)
LOW PULSE
5
VDUT_ RISING
0
-15
-30
MAX9969_LCCQ
MAX9969_RCCQ
-20
NORMALIZED AT PW = 12.5ns
NORMALIZED AT SR = 4V/ns
-35
-25
5
10
15
20
25
0
1
2
3
4
5
PULSE WIDTH (ns)
SLEW RATE (V/ns)
COMPARATOR RESPONSE TO
HIGH SLEW RATE OVERDRIVE
COMPARATOR OFFSET
vs. TEMPERATURE
6
t = 2ns/div
7
VDUT_ = 0 TO 3V PULSE
VCHV_ = VCLV_ = 1.5V
EXTERNAL LOAD = 50Ω
CLAMP RESPONSE AT SOURCE
MAX9969 toc32
1.0
MAX9969 toc31
0
0.8
MAX9969 toc33
TIMING VARIATION (ps)
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE
MAX9969 toc28
10
0.4
200mV/div
OFFSET (mV)
VOUT_ = 150mV/div
0.6
0.2
0
-0.2
-0.4
0
NORMALIZED AT TJ = +85°C
-0.6
60
t = 2ns/div
65
70
INPUT SLEW RATE = 4V/ns
HIGH IMPEDANCE
85
90
95
100
t = 10ns/div
VDUT_ = 0 TO 1V SQUARE WAVE
RS = 10Ω
VCPLV_ = -0.1V, VCPHV_ = +1.1V
ACTIVE-LOAD CURRENT
vs. LOAD VOLTAGE
50
MAX9969 toc35
VLDH_ = 2V
VLDL_ = 2V
40
30
VCOM_ = 2.5V
VLDH_ = 3.5V
VLDL_ = 3.5V
20
ILDH_
IDUT_ (mA)
IDUT_ = 10mA/div
0
80
ACTIVE-LOAD ENABLE
SIGNAL RESPONSE
MAX9969 toc34
ACTIVE-LOAD COMMUTATION
SIGNAL RESPONSE
VLDH_ = 2V
VLDL_ = 2V
75
TEMPERATURE (°C)
MAX9969 toc36
0
IDUT_ = 10mA/div
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
0
ILDL_
10
0
-10
-20
-30
-40
-50
t = 5ns/div
t = 5ns/div
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
VDUT_ (V)
16
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
30
10
0
-10
-20
20
CALIBRATION POINTS AT
200mV, 2.0V, 2.5V, AND 3.5V
VCOM_ = 1.5V, VLDH_ = 0
VDUT = 3V
-0.30
-0.35
-0.40
-0.45
10
0
-10
-0.50
-0.55
-0.60
-20
-30
-30
-0.65
-40
-40
-0.70
-50
1
10
0.01
0.1
1
-1.5 -0.5 0.5
10
1.5
2.5
3.5
4.5
5.5
VLDH_ (V)
VLDL_ (V)
VDUT_ (V)
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
800
-2
-4
-6
-8
0
-100
700
-200
600
-300
500
400
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
-600
200
-700
100
-800
0
-900
6.5
-1000
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
VCPHV_ (V)
VCPLV_ (V)
LOW-LEAKAGE TO
DRIVE 1V TRANSITION
DRIVER REFERENCE CURRENT
vs. DRIVER REFERENCE VOLTAGE
0.930
MAX9969 toc44
MAX9969 toc43
DRIVE 1V TO
LOW-LEAKAGE TRANSITION
0.905
DHV_
INPUT CURRENT (μA)
IDUT_ = 2.5μA/div
IDUT_ = 2.5μA/div
0.880
0
VDUT_ = 0
VCPHV_ = 3V
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
VDUT_ (V)
RL = 100kΩ
CL = 10pF
-500
300
-100
-10
-400
RL = 100kΩ
CL = 10pF
0
MAX9969 toc45
IDUT_ (μA)
0
100
IDUT_ (μA)
2
VDUT_ = 3V
VCPLV = 0
900
6.5
MAX9969 toc42
1000
MAX9969 toc40
4
IDUT_ (nA)
-0.75
-50
0.1
0.01
MAX9969 toc39
40
IDUT_ (μA)
20
50
MAX9969 toc41
LINEARITY ERROR (μA)
30
CALIBRATION POINTS AT
200mV, 2.0V, 2.5V, AND 3.5V
VCOM_ = 1.5V, VLDL_ = 0
VDUT = 0
LINEARITY ERROR (μA)
40
MAX9969 toc37
50
HIGH-IMPEDANCE CURRENT
vs. DUT_ VOLTAGE
ACTIVE-LOAD LINEARITY
ERROR IDUT_ vs. VLDL_
MAX9969 toc38
ACTIVE-LOAD LINEARITY
ERROR IDUT_ vs. VLDH_
DLV_
0.855
DTV_
0.830
0.805
0.780
0.755
0.730
0
t = 2μs/div
0
t = 50ns/div
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
INPUT VOLTAGE (V)
______________________________________________________________________________________
17
MAX9969
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
CLV_
VCPLV_ = -2.2V
600
-500
VCPHV_ = 7.2V
-550
575
CHV_
-200
-300
-600
ICPLV_ (nA)
ICPHV_ (nA)
-100
-400
550
525
1.5
2.5
3.5
4.5
5.5
-750
475
-800
-850
0
6.5
1.5
3.0
4.5
6.0
-2.5
-1.0
0.5
2.0
VCPLV_ (V)
LOAD REFERENCE INPUT CURRENT
vs. INPUT VOLTAGE
INPUT CURRENT
vs. INPUT VOLTAGE, COM_
MAX9969 toc49
0.90
0.88
LDH_
0.86
-200
-300
-400
-500
-600
ICOM_ (μA)
INPUT CURRENT (nA)
7.5
VCPHV_ (V)
INPUT VOLTAGE (V)
200
100
0
-100
-700
MAX9969 toc50
-1.5 -0.5 0.5
-650
500
450
-500
0.84
0.82
0.80
-700
0.78
LDL_
-800
-900
-1000
0.76
0.74
0
0.5
1.0
1.5
2.0
2.5
INPUT VOLTAGE (V)
18
INPUT CURRENT
vs. INPUT VOLTAGE, CPLV_
MAX9969 toc47
VDUT_ = 6.5V
0
625
MAX9969 toc46
100
INPUT CURRENT
vs. INPUT VOLTAGE, CPHV_
MAX9969 toc48
COMPARATOR REFERENCE CURRENT
vs. INPUT VOLTAGE
INPUT CURRENT (nA)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
3.0
3.5
4.0
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
VCOM_ (V)
______________________________________________________________________________________
6.5
3.5
5.0
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
SUPPLY CURRENT ICC vs. VCC
SUPPLY CURRENT IEE vs. VEE
220
MAX9969 toc52
MAX9969 toc51
240
300
C
280
200
IEE (mA)
A
180
C
260
A
D
B
D
240
160
B
140
220
RL = 10kΩ, CL = 0.05pF, VEE = -4.75V
RL = 10kΩ, CL = 0.5pF, VCC = 9.75V
120
200
9.5
9.7
9.9
10.1
10.3
10.5
-5.25
-5.15
-5.05
VCC (V)
A: VDUT_ = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0
VCHV_ = VCLV_ = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V
VLDH_ = VLDL_ = 0, ISOURCE = ISINK = 0
B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z
AND LOAD ENABLED
C: SAME AS B EXCEPT ISOURCE = ISINK = 35mA,
VCOM_ = 1.5V, RL = 0
D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED
-4.75
IEE vs. TEMPERATURE
MAX9969 toc53
VDUT_ = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0
VCHV_ = VCLV_ = 0, VCHV_ = 7.2V, VCPLV_ = -2.2V
VLDH_ = VLDL_ = 0, VCC = 9.75, VEE = -5.25
234
233
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
164
-4.85
A: VDUT_ = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0
VCHV_ = VCLV_ = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V
VLDH_ = VLDL_ = 0, ISOURCE = ISINK = 0
B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z
AND LOAD ENABLED
C: SAME AS B EXCEPT ISOURCE = ISINK = 35mA,
VCOM_ = -1V, RL = 0
D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED
ICC vs. TEMPERATURE
165
-4.95
VEE (V)
163
162
161
VDUT_ = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0
VCHV_ = VCLV_ = 0, VCHV_ = 7.2V, VCPLV_ = -2.2V
VLDH_ = VLDL_ = 0, VCC = 9.75, VEE = -5.25
MAX9969 toc54
ICC (mA)
320
232
231
230
229
228
160
60
70
80
90
TEMPERATURE (°C)
100
110
60
70
80
90
100
110
TEMPERATURE (°C)
______________________________________________________________________________________
19
MAX9969
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Pin Description
PIN
NAME
1
TEMP
Temperature Monitor Output
2, 9, 12, 14,
17, 24, 35,
45, 46, 60,
80, 81, 91
VEE
Negative Power-Supply Input
3, 5, 10, 16,
21, 23, 25,
34, 43, 44,
82, 83, 92
GND
Ground Connection
4, 11, 15, 22,
33, 41, 42,
66, 84, 85, 93
VCC
Positive Power-Supply Input
6, 8, 18,
20, 50, 76
N.C.
No Connection. Do not connect.
20
FUNCTION
7
DUT1
13
GS
Channel 1 DUT Input/Output. Combined I/O for driver, comparator, clamp, and load.
19
DUT2
Channel 2 DUT Input/Output. Combined I/O for driver, comparator, clamp, and load.
26
CLV2
Channel 2 Low-Comparator Reference Input
27
CHV2
Channel 2 High-Comparator Reference Input
28
DLV2
Channel 2 Driver-Low Reference Input
29
DTV2
Channel 2 Driver-Termination Reference Input
30
DHV2
Channel 2 Driver-High Reference Input
31
CPLV2
Channel 2 Low-Clamp Reference Input
32
CPHV2
Channel 2 High-Clamp Reference Input
36
NCH2
37
CH2
38
VCCO2
39
NCL2
40
CL2
47
COM2
Ground Sense. GS is the ground reference for LDH_ and LDL_.
Channel 2 High-Comparator Output. Differential output of channel 2 high comparator.
Channel 2 Collector Voltage Input. Voltage input for channel 2 comparator output termination
resistors. Provides pullup voltage and current for the output termination resistors. Not internally
connected for versions without internal termination resistors.
Channel 2 Comparator Low Output. Differential output of channel 2 low comparator.
Channel 2 Active-Load Commutation-Voltage Reference Input
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
PIN
NAME
48
LDL2
Channel 2 Active-Load Source-Current Reference Input
FUNCTION
49
LDH2
Channel 2 Active-Load Sink-Current Reference Input
51
TDATA2
52
NDATA2
53
DATA2
54
TRCV2
55
NRCV2
56
RCV2
57
TLDEN2
58
NLDEN2
59
LDEN2
61
RST
Reset Input. Asynchronous reset input for the serial register. RST is active low.
62
CS
Chip-Select Input. Serial port activation input. CS is active low.
63
THR
Single-Ended Logic Threshold. Leave THR unconnected to set the threshold to +1.25V or force
THR to a desired threshold voltage.
64
SCLK
65
DIN
67
LDEN1
68
NLDEN1
69
TLDEN1
Channel 2 Data-Termination Voltage Input. Termination voltage input for the DATA2 and NDATA2
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2’s
input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above
DATA2 to select DLV2.
Channel 2 RCV Termination Voltage Input. Termination voltage input for the RCV2 and NRCV2
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 in
receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2
above RCV2 to place channel 2 into drive mode.
Channel 2 Load-Enable Termination Voltage Input. Termination voltage input for the LDEN2 and
NLDEN2 differential inputs. Not internally connected on versions without internal termination resistors.
Channel 2 Multiplexer Control Inputs. Differential controls LDEN2 and NLDEN2 enable/disable the
active load. Drive LDEN2 above NLDEN2 to enable the channel 2 active load. Drive NLDEN2
above LDEN2 to disable the channel 2 active load.
Serial Clock Input. Clock for serial port.
Data Input. Serial port data input.
Channel 1 Multiplexer Control Inputs. Differential controls LDEN1 and NLDEN1 enable/disable the
active load. Drive LDEN1 above NLDEN1 to enable the channel 1 active load. Drive NLDEN1
above LDEN1 to disable the channel 1 active load.
Channel 1 Load-Enable Termination Voltage Input. Termination voltage input for the LDEN1 and
NLDEN1 differential inputs. Not internally connected on versions without internal termination
resistors.
______________________________________________________________________________________
21
MAX9969
Pin Description (continued)
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
MAX9969
Pin Description (continued)
22
PIN
NAME
FUNCTION
70
RCV1
71
NRCV1
72
TRCV1
73
DATA1
74
NDATA1
75
TDATA1
77
LDH1
Channel 1 Active-Load Sink-Current Reference Input
78
LDL1
Channel 1 Active-Load Source-Current Reference Input
79
COM1
Channel 1 Active-Load Commutation-Voltage Reference Input
86
CL1
87
NCL1
88
VCCO1
Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 in
receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1
above RCV1 to place channel 1 into drive mode.
Channel 1 RCV Termination Voltage Input. Termination voltage input for the RCV1 and NRCV1
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1’s
input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above
DATA1 to select DLV1.
Channel 1 Data-Termination Voltage Input. Termination voltage input for the DATA1 and NDATA1
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 1 Low-Comparator Output. Differential output of channel 1 low comparator.
Channel 1 Collector Voltage Input. Voltage input for channel 1 comparator output-termination
resistors. Provides pullup voltage and current for the output-termination resistors. Not internally
connected for versions without internal termination resistors.
89
CH1
90
NCH1
94
CPHV1
Channel 1 High-Clamp Reference Input
95
CPLV1
Channel 1 Low-Clamp Reference Input
96
DHV1
Channel 1 Driver-High Reference Input
97
DTV1
Channel 1 Driver-Termination Reference Input
98
DLV1
Channel 1 Driver-Low Reference Input
99
CHV1
Channel 1 High-Comparator Reference Input
100
CLV1
Channel 1 Low-Comparator Reference Input
Channel 1 High-Comparator Output. Differential output of channel 1 high comparator.
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
CH_ MODE BITS
SC0
CS
SCLK
DIN
VCC
SERIAL INTERFACE
RST
THR
VEE
SERIAL INTERFACE IS COMMON
TO BOTH CHANNELS.
MODE BITS INDEPENDENTLY
LATCHED FOR EACH CHANNEL.
SC1
TMSEL
LLEAK
LDDIS
TEMP
GND
CDIFF
DLV_
DHV_
MULTIPLEXER
SLEW-RATE
CONTROL
BUFFER
0
50Ω
DUT_
0
DTV_
1
OPTIONAL RDATA
2 x 50Ω
SC0
LLEAK
SC1
TDATA_
DATA_
NDATA_
RCV_
NRCV_
MAX9969
HIGH IMPEDANCE
TMSEL
TRCV_
OPTIONAL RRCV
2 x 50Ω
CLAMPS
FROM DUT_
OTHER CHANNEL
CPHV_
CPLV_
0
CHV_
CH_
NCH_
1
CDIFF
OPTIONAL RCCO
4 x 50Ω
VCCO_
COMPARATORS
CL_
NCL_
VCC
SINK
(HIGH)
CURRENT
CLV_
LDH_
LLEAK
TLDEN_
OPTIONAL RLDEN
2 x 50Ω
LDDIS
1
ACTIVE
LOAD
CONTROL
ACTIVE
LOAD
LDEN_
NLDEN_
COM_
1
LDL_
SOURCE
(LOW)
CURRENT
GS
ONE OF TWO IDENTICAL CHANNELS SHOWN
VEE
______________________________________________________________________________________
23
MAX9969
Functional Diagram
Detailed Description
The MAX9969 dual, low-power, high-speed, pin electronics DCL IC includes, for each channel, a three-level
pin driver, a dual comparator, variable clamps, and an
active load. An additional differential comparator allows
comparisons between the two channels. The driver features a -1.5V to +6.5V operating range and high-speed
operation, includes high-impedance and active-termination (3rd-level drive) modes, and is highly linear even
at low-voltage swings. The dual comparator provides
low dispersion (timing variation) over a wide variety of
input conditions, and differential outputs. The clamps
provide damping of high-speed DUT waveforms when
the device is configured as a high-impedance receiver.
The programmable load supplies up to 35mA of source
and sink current. The load facilitates contact/continuity
testing, at-speed parametric test of IOH and IOL, and
pullup of high-output-impedance devices. The
MAX9969A features tighter matching of offset for the
drivers and the comparators.
Optional internal resistors at the high-speed inputs provide compatibility with LVPECL, LVDS, and GTL interfaces. Connect the termination voltage inputs (TDATA_,
TRCV_, TLDEN_) to the appropriate voltage for terminating LV_PECL, GTL, or other logic. Leave the inputs
HIGH-SPEED
INPUTS
unconnected for 100Ω differential LVDS termination. In
addition, flexible open-collector outputs with optional
internal pullup resistors are available for the comparators. These features significantly reduce the discrete
component count on the circuit board.
A 3-wire, low-voltage CMOS-compatible serial interface
programs the low-leakage, load-disable, slew-rate, differential/window comparator and tri-state/terminate
operational configurations of the MAX9969.
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_
and RCV_ and mode-control bit TMSEL (Table 1). A
slew-rate circuit controls the slew rate of the buffer
input. Select to one of four possible slew rates according to Table 2. The speed of the internal multiplexer
sets the 100% driver slew rate (see the Driver LargeSignal Response graph in the Typical Operating
Characteristics).
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
into low-leakage mode (Figure 2, Table 1). In highimpedance mode, the clamps are connected. Highspeed input RCV_ and mode-control bits TMSEL and
REFERENCE
INPUTS
0
DLV_
0
SLEW RATE
DHV_
1
BUFFER
MAX9969
0
50Ω
0
DUT_
1
DTV_
1
DATA_
HIGH-Z
RCV_
CPHV_
LLEAK
SC1
CPLV_
SC0
CLAMPS
TMSEL
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
COMPARATORS
AND
ACTIVE LOAD
4
MODE
Figure 2. Simplified Driver Channel
24
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Table 3a. Comparator Logic, CDIFF = 0
INTERNAL
CONTROL
REGISTER
EXTERNAL
CONNECTIONS
DUT_ > CHV_ DUT_ > CLV_
DRIVER
OUTPUT
CH_, NCH_
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
DATA
RCV
1
0
X
0
Drive to DHV_
0
0
X
0
Drive to DLV_
X
1
1
0
Drive to DTV_
(term mode)
CL_, NCL_
CH_, NCH_
0
High-impedance mode
(high-Z)
0
0
0
0
0
1
1
0
Low-leakage mode
1
0
0
1
1
1
1
1
X
TMSEL LLEAK
CL_, NCL_
0
1
X
0
X
X
1
Table 2. Slew-Rate Logic
SC1
SC0
DRIVER SLEW RATE (%)
0
0
100
0
1
75
1
0
50
1
1
25
Table 3b. Comparator Logic, CDIFF = 1
DUT1 > DUT2 DUT_ > CLV_
not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage range; overvoltage
protection remains active without loading DUT_.
Comparators
LLEAK control the switching. In high-impedance mode,
the bias current at DUT_ is less than 3µA over the 0 to
3V range, while the node maintains its ability to track
high-speed signals. In low-leakage mode, the bias current at DUT_ is further reduced to less than 15nA, and
signal tracking slows. See the Low-Leakage Mode,
LLEAK section for more details.
The nominal driver output resistance is 50Ω. Contact
the factory for different resistance values within the
45Ω to 51Ω range.
Clamps
Configure the voltage clamps (high and low) to limit the
voltage at DUT_ and to suppress reflections when the
channel is configured as a high-impedance receiver.
The clamps behave as diodes connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the
clamp voltages using the external connections CPHV_
and CPLV_. The clamps are enabled only when the driver is in high-impedance mode (Figure 2). For transient
suppression, set the clamp voltages to approximately
the minimum and maximum expected DUT_ voltage
range. The optimal clamp voltages are application specific and must be empirically determined. If clamping is
The MAX9969 provides two independent high-speed
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (see the
Functional Diagram). Comparator outputs are a logical
result of the input conditions, as indicated in Tables 3a
and 3b.
The comparator differential outputs are open-collector
outputs to ease interfacing with a wide variety of logic
families. Versions with and without internal termination
resistors switch an 8mA current source between the
two outputs (Figure 3). The optional termination resistors connect the outputs to voltage input VCCO_. For
versions without internal termination, leave V CCO _
unconnected and add the required external resistors.
These resistors are typically 50Ω to the pullup voltage
at the receiving end of the output trace. Alternate configurations can be used provided that the Absolute
Maximum Ratings are not exceeded. For versions with
internal termination, connect VCCO_ to the desired VOH
voltage. Each output provides a nominal 400mVP-P
swing and 50Ω source termination.
The upper comparators are configurable as differential
receivers for LVDS and other differential DUT_ signals.
When mode bit CDIFF is asserted, the upper comparator inputs are routed from the DUT_ outputs for both
channels.
______________________________________________________________________________________
25
MAX9969
Table 1. Driver Logic
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
MAX9969
Table 4. Active Load Programming
FROM DUT_
OTHER CHANNEL
CDIFF
EXTERNAL
CONNECTIONS
MAX9969
CH_
CHV_
INTERNAL
CONTROL
REGISTER
MODE
LDEN_
LDDIS
LLEAK
0
0
0
Normal operating mode,
load disabled
1
0
0
Normal operating mode,
load enabled
X
1
0
Load disabled
X
X
1
Low-leakage mode
DUT_
NCH_
1Ω
8mA
VCCO_
OPTIONAL
4 x 50Ω
8mA
1Ω
VEE
CL_
Low-Leakage Mode, LLEAK section for more detailed
information.
LDDIS
CLV_
NCL_
Figure 3. Open-Collector Comparator Outputs
In some tester configurations, the load enable is driven
with the complement of the driver high-impedance signal (RCV_), so disabling the driver enables the load
and vice versa. The LDDIS signal allows the load to be
disabled independent of the state of LDEN_ (Table 4).
GS Input
Active Load
The active load consists of linearly programmable,
class AB source and sink current sources, a commutation buffer, and a diode bridge (see the Functional
Diagram). Analog control inputs LDH_ and LDL_ program the sink and source currents, respectively, within
the 0 to 35mA range. Analog reference input COM_
sets the commutation buffer output voltage. The source
and sink naming convention is referenced to the DUT.
Current out of the MAX9969 constitutes sink current
and current into the MAX9969 constitutes source current. The class AB loads of the MAX9969 offer substantial efficiency improvement over conventional
active-load circuitry.
The programmed source (low) current loads the DUT
when VDUT_ > VCOM_. The programmed sink (high)
current loads the DUT when VDUT_ < VCOM_.
High-speed differential input LDEN_ and 2 bits of the
control word (LDDIS and LLEAK) control the load
(Table 4). When the load is enabled, the internal source
and sink current sources connect to the diode bridge.
When the load is disabled, the internal current sources
shunt to ground and the top and bottom of the bridge
float (see the Functional Diagram). LLEAK places the
load in low-leakage mode, and overrides LDEN_. See the
26
The GS input allows a single level-setting DAC, such as
the MAX5631 or MAX5734, to program the MAX9969’s
active load, driver, comparator, and clamps. Although
all the DAC levels are typically offset by VGS, the operation of the MAX9969’s ground-sense input nullifies this
offset with respect to the active-load current. Connect
GS to the ground reference used by the DAC. (VLDL_ VGS) sets the source current by +10mA/V. (V LDH_ VGS) sets the sink current by -10mA/V.
To maintain an 8V range in the presence of GS variations,
DHV_, DLV_, DTV_, CPHV_, CPLV_, and COM_ ranges
are offset by GS. Adequate supply headroom must be
maintained in the presence of GS variations. Ensure:
VCC ≥ 9.5V + Max(VGS)
VEE ≤ -4.5V + Min(VGS)
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST
places the MAX9969 into a very low-leakage state (see
the Electrical Characteristics). With LLEAK asserted, the
comparators function at a reduced speed, and the driver, clamps, and active load are disabled. This mode is
convenient for making IDDQ and PMU measurements
without the need for an output disconnect relay. LLEAK
is programmed independently for each channel.
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
SCLK
SHIFT REGISTER
DIN
0
1
2
3
4
5
6
Serial Interface and Device Control
7
A CMOS-compatible serial interface controls the
MAX9969 modes (Figure 4 and Table 5). Control data
flow into an 8-bit shift register (MSB first) and are
latched when CS is taken high, as shown in Figure 5.
Latches contain 6 control bits for each channel of the
dual pin driver. Data from the shift register are loaded
to either or both of the latches as determined by bits D6
and D7. When CDIFF = 1, its effect is independent of
bits D6 and D7. The control bits, in conjunction with
external inputs DATA_ and RCV_, manage the features
of each channel, as shown in Tables 1 and 2. RST sets
LLEAK = 1 for both channels, forcing them into lowleakage mode. All other bits are unaffected. At powerup, hold RST low until VCC and VEE have stabilized.
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5V to 3.3V logic.
CS
ENABLE
F/F
5
7
F/F
5
Q
D
D
6
ENABLE
Q
ENABLE
SET
SET
RST
F/F
0-4
7
D
F/F
0-4
Q
6
ENABLE
5
D
Q
ENABLE
1
5
1
20kΩ
VTHRINT = 1.25V
THR
LDDIS, LLEAK
TMSEL,
CDIFF,
SC0, SC1
LDDIS, LLEAK
TMSEL,
CDIFF,
SC0, SC1
CHANNEL 1 MODE BITS
CHANNEL 2 MODE BITS
MAX9967 Compatibility
MAX9969
The MAX9969 is pin compatible with the MAX9967 with
minor changes.
• No PMU force/sense connection on the MAX9969
Figure 4. Serial Interface
• Different common-mode ranges for control inputs
• MAX9967 comparator outputs additionally support
open emitter
• Different serial interface bit structures
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
tCH
SCLK
tCSS0
tCSS1
tCL
tCSH1
CS
tCSWH
tDH
tDS
D6
DIN
D5
D4
D3
D2
D1
D0
Figure 5. Serial-Interface Timing
______________________________________________________________________________________
27
MAX9969
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behavior under this condition.
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Table 5. Shift Register Functions
BIT
NAME
DESCRIPTION
D7
CH1
Channel 1 Write Enable. Set to 1 to update the
control byte for channel 1. Set to 0 to make no
changes to channel 1.
D6
CH2
Channel 2 Write Enable. Set to 1 to update the
control byte for channel 2. Set to 0 to make no
changes to channel 2.
D5
Low-Leakage Select. Set to 1 to put driver,
load, and clamps in low-leakage mode.
LLEAK Comparators remain active in low-leakage
mode, but at reduced speed. Set to 0 for
normal operation.
D4
Termination Select. Driver Termination Select
Bit. Set to 1 to force the driver output to the
TMSEL DTV_ voltage when RCV_ = 1 (term mode). Set
to 0 to place the driver into high-impedance
mode when RCV_ = 1 (high-Z). See Table 1.
D3
SC1
D2
SC0
Driver Slew Rate Select. SC1 and SC0 set the
driver slew rate. See Table 2.
D1
CDIFF
Differential Comparator Enable. Set to 1 to
enable the differential comparators and
disable the CH_ window comparators. Set to 0
to enable the CH_ window comparators and
disable the differential comparators. See
Tables 3a and 3b.
D0
LDDIS
Load Disable. Set LDDIS to 1 to disable the
load. Set to 0 for normal operation. See Table 4.
Temperature Monitor
The MAX9969 supplies a temperature output signal,
TEMP, that asserts a 3.33V nominal output voltage at a
+70°C (343K) die temperature. The output voltage
changes proportionally with temperature at 10mV/°C.
Heat Removal
Under normal circumstances, the MAX9969 requires
heat removal through the exposed pad by use of an
external heat sink. The exposed pad is electrically at
VEE potential, and must be either connected to VEE or
isolated.
Power dissipation is highly dependent upon the application. The Electrical Characteristics table indicates
power dissipation under the condition that the source
28
and sink currents are programmed to 0mA. Maximum
dissipation occurs when the source and sink currents
are both at 35mA, the VDUT_ is at an extreme of the
voltage range (-1.5V or +6.5V), and the diode bridge is
fully commutated. Under these conditions, the additional power dissipated (per channel) is:
If DUT_ is sourcing current:
PD = (VDUT_ - VEE) x ISOURCE
If DUT_ is sinking current:
PD = (VCC - VDUT_) x ISINK
DUT_ sources the programmed (low) current when
VDUT_ > VCOM_. The path of the current is from DUT_
through the outside of the diode bridge and the source
(low) current source to VEE. The programmed sink current is greatly reduced by the class AB load architecture.
DUT_ sinks the programmed (high) current when VDUT_
< VCOM_. The path of the current is from VCC through
the sink (high) current source and the outside of the
diode bridge to DUT_. The programmed source current
is greatly reduced by the class AB architecture.
θJC of the exposed-pad package is very low, approximately 1°C/W to 2°C/W. Die temperature is thus highly
dependent upon the heat removal techniques used in
the application. Maximum total power dissipation
occurs under the following conditions:
• VCC = +10.5V
• VEE = -5.25V
• ISOURCE = ISINK = 35mA for both channels
• Load enabled
• VDUT_ = -1.5V
• VCOM_ = +0.5V
Under these extreme conditions, the total power dissipation is 3.9W typical and 4.4W maximum. If the die
temperature cannot be maintained at an acceptable
level under these conditions, use software clamping to
limit the load output currents to lower values and/or
reduce the supply voltages.
Power-Supply Considerations
Bypass all VCC and VEE power input pins with 0.01µF
capacitors, and use bulk bypassing of at least 10µF on
each supply.
Chip Information
TRANSISTOR COUNT: 5284
PROCESS: Bipolar
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
HIGH-SPEED DIGITAL
INPUT TERMINATION (Ω)
PART
ACCURACY
GRADE
COMPARATOR
OUTPUT
TERMINATION
RCV_
DATA_
LDEN_
MAX9969ADCCQ
A
None
None
None
None
MAX9969AGCCQ
A
None
100
100
100
Top
MAX9969ALCCQ
A
50Ω to VCCO_
100
100
100
Top
MAX9969ARCCQ
A
50Ω to VCCO_
None
100
100
Top
Top
HEAT EXTRACTION
Top
MAX9969BDCCQ
B
None
None
None
None
MAX9969BGCCQ
B
None
100
100
100
Top
MAX9969BLCCQ
B
50Ω to VCCO_
100
100
100
Top
MAX9969BRCCQ
B
50Ω to VCCO_
None
100
100
Top
N.C.
LDH1
LDL1
COM1
VEE
VEE
GND
GND
VCC
VCC
CL1
NCL1
VCCO1
CH1
NCH1
VEE
GND
VCC
CPHV1
CPLV1
DHV1
DTV1
DLV1
CLV1
TOP VIEW
CHV1
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TEMP
1
75
TDATA1
VEE
2
74
NDATA1
GND
3
73
DATA1
VCC
4
72
TRCV1
GND
5
71
NRCV1
N.C.
6
70
RCV1
DUT1
7
69
TLDEN1
N.C.
8
68
NLDEN1
VEE
9
67
LDEN1
GND 10
66
VCC
VCC 11
65
DIN
VEE 12
64
SCLK
GS 13
63
THR
62
CS
MAX9969
VEE 14
VCC 15
61
RST
GND 16
60
VEE
VEE 17
59
LDEN2
N.C. 18
58
NLDEN2
DUT2 19
57
TLDEN2
N.C. 20
56
RCV2
GND 21
55
NRCV2
VCC 22
54
TRCV2
GND 23
53
DATA2
VEE 24
52
NDATA2
GND 25
51
TDATA2
N.C.
LDH2
LDL2
COM2
VEE
VEE
GND
GND
VCC
VCC
CL2
NCL2
VCCO2
CH2
NCH2
VEE
GND
VCC
CPHV2
CPLV2
DHV2
DTV2
DLV2
CLV2
CHV2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
______________________________________________________________________________________
29
MAX9969
Selector Guide
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TQFP 14x14.EPS
MAX9969
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
30
______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9969
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)