19-2155; Rev 0; 10/01 Single 500Mbps LVDS Line Receiver in SC70 Features ♦ Space-Saving SC70 Package (50% Smaller than SOT23) ♦ Guaranteed 500Mbps Data Rate ♦ Low 250ps (max) Pulse Skew ♦ High-Impedance LVDS Inputs When Powered Off Allow Hot Swapping ♦ Conforms to ANSI TIA/EIA-644 LVDS Standard ♦ Single +3.3V Supply ♦ Fail-Safe Circuit Sets Output High for Undriven Inputs (Open, Terminated, or Shorted) ♦ Low 150µA (typ) Supply Current in Fail-Safe Mode Ordering Information Applications Clock Distribution Cellular Phone Base Stations PART TEMP. RANGE MAX9130EXT-T -40°C to +85°C PINPACKAGE 6 SC70-6 TOP MARK ABB Digital Cross-Connects Network Switches/Routers DSLAMs Pin Configuration Typical Application Circuit CLOCK INPUT CLOCK INPUT MAX9130 MAX9130 Rx Rx CLOCK INPUT MAX9130 TOP VIEW VCC 1 6 OUT GND 2 5 GND 4 IN+ Rx IN- 3 CLOCK SOURCE 100Ω TERMINATION Tx MAX9130 SC70 LVDS SIGNALS REFERENCE CLOCK DISTRIBUTION USING MAX9130 IN A MULTIDROP CONFIGURATION ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9130 General Description The MAX9130 is a single low-voltage differential signaling (LVDS) line receiver ideal for applications requiring high data rates, low power, and low noise. The device is guaranteed to receive data at speeds up to 500Mbps (250MHz). The MAX9130 accepts an LVDS differential input and translates it to an LVTTL/LVCMOS output. The fail-safe feature sets the output high when the inputs are undriven and open, terminated, or shorted. The device supports a wide common-mode input range, allowing a ground potential difference and common-mode noise between the driver and the receiver. The MAX9130 conforms to the ANSI/TIA/EIA-644 LVDS standard. The MAX9130 operates from a single +3.3V supply, and is specified for operation from -40°C to +85°C. It is available in a space-saving 6-pin SC70 package. Refer to the MAX9110/MAX9112 data sheet for single/dual LVDS line drivers. Refer to the MAX9115 for a lower speed (200Mbps) single LVDS line receiver in SC70. MAX9130 Single 500Mbps LVDS Line Receiver in SC70 ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN+, IN- to GND.....................................................-0.3V to +4.0V OUT to GND ...............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 6-Pin SC70 (derate 3.1mW/°C above +70°C) .............245 mW Output Short to GND (OUT) (Note 1)........................................1s Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C ESD Protection Human Body Model (IN+, IN-) .........................................±6kV Lead Temperature (soldering, 10s) .................................+300°C Note 1: Package leads soldered to a PC board having copper ground and VCC planes. Do not exceed Maximum Junction Temperature. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.05V to 1.0V, input common voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values at VCC = +3.3V, TA = +25°C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS INPUTS (IN+, IN-) Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current Power-Off Input Current Input Resistance IIN+, IINIINO 50 -50 0.05V ≤VID≤ 0.6V -20 20 0.6V <VID≤ 1.0V -25 25 0.05V ≤VID≤ 0.6V, VCC = 0 -20 20 0.6V <VID≤ 1.0V, VCC = 0 -25 25 RIN1 VCC = +3.6V or 0, Figure 1 35 RIN2 VCC = +3.6V or 0, Figure 1 132 VOH IOH = -8.0mA mV mV µA µA kΩ LVTTL/LVCMOS OUTPUT (OUT) Output High Voltage Inputs open or undriven short or undriven 100Ω termination VCC - 0.3 VID = +50mV VCC - 0.3 V Output Low Voltage VOL IOL = +8.0mA, VID = -50mV 0.25 V Output Short-Circuit Current IOS VID = +50mV, VOUT = 0 -125 mA 300 µA 7 mA SUPPLY CURRENT Supply Current 2 ICC No load, inputs undriven (fail-safe) 150 No load, inputs driven _______________________________________________________________________________________ Single 500Mbps LVDS Line Receiver in SC70 (VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.0V, input common voltage VCM = |VID/2| to 2.4V - |VID /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 250MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C.) (Figures 2 and 3) (Notes 4 and 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD 1.2 1.8 3 ns Differential Propagation Delay Low to High tPLHD 1.2 1.8 3 ns Differential Pulse Skew |tPHLD - tPLHD| (Note 6) tSKD1 250 ps Differential Part-to-Part Skew (Note 7) tSKD2 1.3 ns Differential Part-to-Part Skew (Note 8) tSKD3 1.8 ns Rise Time tTLH 0.5 0.8 ns Fall Time tTHL 0.5 0.8 ns Maximum Operating Frequency (Note 9) fMAX 250 MHz Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes scope probe and test jig capacitance. Note 6: tSKD1 is the magnitude difference of differential propagation delays. tSKD1 = |tPHLD - tPLHD|. Note 7: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5°C of each other. Note 8: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 9: fMAX pulse generator output conditions: rise time = fall time = 1ns (0% to 100%), 50% duty cycle, VOH = +1.3V, VOL = +1.1V. MAX9130 output criteria: 60% to 40% duty cycle, VOL = 0.25V max, VOH = 2.7V min, load = 15pF. _______________________________________________________________________________________ 3 MAX9130 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC = +3.3V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 250MHz, 50% duty cycle, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. FREQUENCY OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 20 5.50 5.00 4.50 10 0 10 100 -40 1000 -15 -75 -70 -65 10 35 60 85 3.0 3.3 TEMPERATURE (°C) FREQUENCY (MHz) SUPPLY VOLTAGE (V) OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE 3.40 3.20 3.00 MAX9130 toc05 88.0 87.5 OUTPUT LOW VOLTAGE (mV) MAX9130 toc04 3.60 OUTPUT HIGH VOLTAGE (V) -80 -60 4.00 1 MAX9130 toc03 OUTPUT SHORT-CIRCUIT CURRENT (mA) SUPPLY CURRENT (mA) 30 -85 MAX9130 toc02 6.00 MAX9130 toc01 40 SUPPLY CURRENT (mA) 87.0 86.5 86.0 85.5 85.0 84.5 84.0 2.80 3.0 3.3 3.3 3.6 SUPPLY VOLTAGE (V) DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE tPHLD tPLHD 1.80 1.70 1.60 MAX9130 toc07 2.75 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9130 toc06 1.90 1.50 2.50 2.25 tPHLD tPLHD 2.00 1.75 1.50 3.0 3.3 SUPPLY VOLTAGE (V) 4 3.0 3.6 SUPPLY VOLTAGE (V) 2.00 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9130 Single 500Mbps LVDS Line Receiver in SC70 3.6 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 3.6 Single 500Mbps LVDS Line Receiver in SC70 DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE DIFFERENTIAL PULSE SKEW vs. TEMPERATURE 40 30 20 10 MAX9130 toc09 50 100 DIFFERENTIAL PULSE SKEW (ps) MAX9130 toc08 80 60 40 20 0 3.0 3.3 3.6 -40 -15 SUPPLY VOLTAGE (V) 85 tPLHD 2.0 1.9 tPHLD 1.7 1.6 MAX9130 toc11 2.2 1.9 tPHLD 1.8 tPLHD 1.7 1.6 1.5 0.1 1.2 0.1 2.3 TRANSITION TIME vs. LOAD CAPACITANCE 0.4 0.5 0.6 TRANSITION TIME vs. SUPPLY VOLTAGE TRANSITION TIME (ps) 1.800 0.3 580 MAX9130 toc12 2.100 0.2 DIFFERENTIAL INPUT VOLTAGE (V) COMMON-MODE VOLTAGE (V) TRANSITION TIME (ns) 60 2.0 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9130 toc10 DIFFERENTIAL PROPAGATION DELAY (ns) 2.3 1.8 35 DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE 2.1 10 TEMPERATURE (°C) 1.500 tTLH 1.200 tTHL 0.900 MAX9130 toc13 DIFFERENTIAL PULSE SKEW (ps) 60 tTHL 540 500 tTLH 460 0.600 0.300 420 5 15 25 35 LOAD CAPACITANCE (pF) 45 55 3.0 3.3 3.6 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX9130 Typical Operating Characteristics (continued) (VCC = +3.3V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 250MHz, 50% duty cycle, TA = +25°C, unless otherwise noted.) Single 500Mbps LVDS Line Receiver in SC70 MAX9130 Pin Description PIN NAME FUNCTION 1 VCC Power-Supply Input. Bypass VCC to GND with a 0.01µF ceramic capacitor. 2, 5 GND 3 IN- Inverting LVDS Differential Input 4 IN+ Noninverting LVDS Differential Input 6 OUT LVTTL/LVCMOS Output VCC RIN2 Ground VCC - 0.3V IN+ RIN1 OUT Detailed Description LVDS is intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9130 is a single LVDS line receiver ideal for applications requiring high data rates, low power, and low noise. The device accepts an LVDS input and translates it to an LVTTL/LVCMOS output. The receiver detects differential signals as low as 50mV and as high as 1V within an input voltage range of 0 to +2.4V. The 250mV to 450mV differential output of an LVDS driver is nominally centered around a +1.25V offset. This offset, coupled with the receiver’s 0 to +2.4V input voltage range, allows an approximate ±1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the driver and the receiver, the common-mode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to +2.4V referenced to receiver ground. Fail-Safe The fail-safe feature of the MAX9130 sets the output high and reduces supply current to 150µA when: • inputs are open • inputs are undriven and shorted • inputs are undriven and terminated A fail-safe circuit is important because under these conditions, noise at the input may switch the receiver and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when an LVDS driver output is in high impedance. A short condition can occur because of a cable failure. 6 RIN1 MAX9130 INGND Figure 1. Fail-Safe Input Network IN+ PULSE GENERATOR IN- Rx OUT CL MAX9130 *50Ω *50Ω *50Ω REQUIRED FOR PULSE GENERATOR. Figure 2. Propagation Delay and Transition Time Test Circuit The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC 0.3V, activating the fail-safe circuit and forcing the output high. Applications Information Power-Supply Bypassing Bypass V CC with a high-frequency surface-mount ceramic 0.01µF capacitor as close to the device as possible. _______________________________________________________________________________________ Single 500Mbps LVDS Line Receiver in SC70 MAX9130 Differential Traces Input trace characteristics affect the performance of the MAX9130. Use controlled-impedance PC board traces, typically 100Ω. Match the termination resistor to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Input differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. VINVID VID = 0 VID = 0 VIN+ tPHLD tPLHD 80% VOUT VOH 80% 50% 50% 20% 20% VOL tTHL tTLH COMMON-MODE VOLTAGE: VCM = (VIN+ + VIN-) / 2 DIFFERENTIAL INPUT VOLTAGE: VID = (VIN+) - (VIN-) Figure 3. Propagation Delay and Transition Time Waveforms Cables and Connectors Transmission media should typically have a controlled differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. (LVTTL/LVCMOS OUTPUT) U1 C1 0.01µF Termination The MAX9130 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance is typically 100Ω but may range between 90Ω to 132Ω, depending on the characteristic impedance of the transmission medium. When using the MAX9130, minimize the distance between the input termination resistor and the MAX9130 receiver inputs. Use 1% surface-mount resistors. Board Layout For LVDS applications, use a four-layer PC board that provides separate layers for power, ground, and input/output signals is recommended. Keep the LVDS input signals away from the output LVCMOS/LVTTL signal to prevent coupling (Figure 4). To minimize crosstalk, do not run the output in parallel with the inputs. VCC OUT GND GND IN- IN+ R1 (LVDS INPUTS) U1: MAX9130 R1, C1 ARE 0402 TYPE Figure 4. Board Layout Chip Information TRANSISTOR COUNT: 201 PROCESS: CMOS _______________________________________________________________________________________ 7 Single 500Mbps LVDS Line Receiver in SC70 SC70, 6L.EPS MAX9130 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.