DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver General Description Features The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE ® function that may be used to multiplex outputs. The receiver also supports open, shorted and terminated (100Ω) input Fail-safe. The receiver output will be HIGH for all fail-safe conditions. The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications. n n n n n n n n n n n n n Connection Diagram Functional Diagram > 400 Mbps (200 MHz) switching rates 0.1 ns channel-to-channel skew (typical) 0.1 ns differential skew (typical) 3.3 ns maximum propagation delay 3.3V power supply design Power down high impedance on LVDS inputs Low Power design (40mW 3.3V static) Interoperable with existing 5V LVDS networks Accepts small swing (350 mV typical) VID Supports open, short and terminated input fail-safe Compatible with ANSI/TIA/EIA-644 Industrial temp. operating range (-40˚C to +85˚C) Available in SOIC and TSSOP Packaging Dual-in-Line DS100067-1 Order Number DS90LV032ATM or DS90LV032ATMTC See NS Package Number M16A or MTC16 DS100067-2 INPUTS OUTPUT EN ENABLES EN* RIN+ − RIN− ROUT L H X Z VID ≥ 0.1V H VID ≤ −0.1V L All other combinations of ENABLE inputs Full Fail-safe OPEN/SHORT H or Terminated © 1999 National Semiconductor Corporation DS100067 www.national.com DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver July 1999 Absolute Maximum Ratings (Note 1) (Soldering 4 sec.) Maximum Junction Temperature ESD Rating (Note 10) (HBM 1.5 kΩ, 100 pF) (EIAJ 0 Ω, 200 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V −0.3V to +3.9V Input Voltage (RIN+, RIN−) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) Output Voltage (ROUT) Maximum Package Power Dissipation +25˚C M Package 1025 mW MTC Package 866 mW Derate M Package 8.2 mW/˚C above +25˚C Derate MTC Package 6.9 mW/˚C above +25˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature Range +260˚C +150˚C ≥ 4.5 kV ≥ 250 V Recommended Operating Conditions Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature (TA) Min +3.0 GND Typ +3.3 Max +3.6 +3.0 Units V V −40 25 +85 ˚C Min Typ Max Units +20 +100 mV Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2) Symbol Parameter Conditions Pin VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM = +1.2V (Note 13) RIN+, RIN− VCMR Common-Mode Voltage Range VID = 200 mV peak to peak (Note 5) 0.1 IIN Input Current VIN = +2.8V −10 VCC = 3.6V or 0V VIN = 0V VIN = +3.6V VOH Output High Voltage −10 VCC = 0V −20 ±1 ±1 -20 IOH = −0.4 mA, VID = +200 mV ROUT mV 2.3 V +10 µA +10 µA +20 µA 2.7 3.0 V IOH = −0.4 mA, Input terminated 2.7 3.0 V IOH = −0.4 mA, Input shorted 2.7 3.0 VOL Output Low Voltage IOL = 2 mA, VID = −200 mV IOS Output Short Circuit Current Enabled, VOUT = 0V (Note 11) IOZ Output TRI-STATE Current Disabled, VOUT = 0V or VCC VIH Input High Voltage VIL Input Low Voltage II Input Current VIN = 0V or VCC, Other Input = VCC or GND VCL Input Clamp Voltage ICL = −18 mA ICC No Load Supply Current EN, EN* = VCC or GND, Inputs Open Receivers Enabled No Load Supply Current Receivers Disabled ICCZ −100 V 0.1 0.25 V −15 −48 −120 mA −10 ±1 +10 µA 2.0 VCC V GND 0.8 V +10 µA 10 15 mA EN, EN* = 2.4V or 0.5V, Inputs Open 10 15 mA EN = GND, EN* = VCC, Inputs Open 3 5 mA Typ Max Units EN, EN* −10 ±1 −1.5 −0.8 VCC V Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 3, 4, 7, 8) Symbol Parameter Conditions Min tPHLD Differential Propagation Delay High to Low CL = 10 pF 1.8 3.3 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.8 3.3 ns (Figure 1 and Figure 2) tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (Note 6) tSKD2 Differential Channel-to-Channel Skew-same device (Note 7) 0 0.1 0.35 ns 0 0.1 0.5 ns tSKD3 Differential Part to Part Skew (Note 8) 1.0 ns tSKD4 Differential Part to Part Skew (Note 9) 1.5 ns tTLH Rise Time 0.35 1.2 ns tTHL Fall Time 0.35 1.2 ns www.national.com 2 Switching Characteristics (Continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 3, 4, 7, 8) Symbol Typ Max tPHZ Disable Time High to Z Parameter RL = 2 kΩ 8 12 ns tPLZ Disable Time Low to Z CL = 10 pF 6 12 ns (Figure 3 and Figure 4) 11 17 ns 11 17 tPZH Enable Time Z to High tPZL Enable Time Z to Low fMAX Maximum Operating Frequency (Note 14) Conditions All Channels Switching Min 200 250 Units ns MHz Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. Note 3: All typicals are given for: VCC = +3.3V, TA = +25˚C. Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN. Note 5: The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over a common-mode range of 0V to 2.3V. A VID up to VCC − 0V may be applied to the RIN+/ RIN− inputs with the Common-Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV ≤ VID ≤ 800mV over the common-mode range . Note 6: tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel Note 7: tSKD2, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Note 8: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC, and within 5˚C of each other within the operating temperature range. Note 9: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. Note 10: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 4.5kV EIAJ (0Ω, 200 pF) ≥ 250V Note 11: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Note 12: CL includes probe and jig capacitance. Note 13: VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range −0.2V to VCC − VID/2. However, to be compliant with AC specifications, the common voltage range is 0.1V to 2.3V Note 14: fMAX generator input conditions: tr = tf < 1ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output Criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), Load = 10 pF (stray plus probes) Parameter Measurement Information DS100067-3 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit DS100067-4 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms 3 www.national.com Parameter Measurement Information (Continued) DS100067-5 CL includes load and test jig capacitance. S1 = VCC for tPZL, and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. FIGURE 3. Receiver TRI-STATE Delay Test Circuit DS100067-6 FIGURE 4. Receiver TRI-STATE Delay Waveforms Typical Application Balanced System DS100067-7 FIGURE 5. Point-to-Point Application Applications Information the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN808, AN1035, AN977, AN971, AN916, AN805, AN903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the drivers . The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of www.national.com 4 Applications Information Termination: Use a resistor which best matches the differential impedance or your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. (Continued) The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ± 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ± 1V around this center point. The ± 1V shifting may be the result of a ground potential difference between the driver’s ground reference and the receiver’s ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins have a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX) Probing LVDS Transmission Lines: Always use high impedance ( > 100kΩ), low capacitance ( < 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. Power Decoupling Recommendations: Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes A 10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. PC Board considerations: Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. Differential Traces: Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Cables and Connectors, General Comments: When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. Fail-Safe Feature: The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or poweroff condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. 5 www.national.com Applications Information (Continued) Pin No. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. The footprint of the DS90LV032A is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. Name 2, 6, RIN+ Description 10, 14 1, 7, RIN− Inverting receiver input pin ROUT Receiver output pin 9, 15 3, 5, 11, 13 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +3.3V ± 0.3V 8 GND Ground pin Ordering Information Pin Descriptions Pin No. Name Operating Package Type/ Temperature Number −40˚C to +85˚C Description −40˚C to +85˚C SOP/M16A Order Number DS90LV032ATM TSSOP/MTC16 DS90LV032ATMTC Non-inverting receiver input pin DS100067-8 FIGURE 6. ICC vs Frequency, four channels switching DS100067-9 FIGURE 7. Typical Common-Mode Range variation with respect to amplitude of differential input www.national.com 6 Applications Information (Continued) DS100067-10 FIGURE 8. Typical Pulse Skew variation versus common-mode voltage DS100067-11 FIGURE 9. Variation in High to Low Propagation Delay versus VCM DS100067-12 FIGURE 10. Variation in Low to High Propagation Delay versus VCM 7 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90LV032ATM NS Package Number M16A www.national.com 8 DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90LV032ATMTC NS Package Number MTC16 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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