MAXIM MAX17000

19-4125; Rev 1; 2/11
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Complete DDR2 and DDR3 Memory
Power-Management Solution
MAX17000ETG+
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
24 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
LX
DH
TON
CSH
TOP VIEW
18
17
16
15
14
13
VDD 19
12
CSL
PGND1 20
11
FB
AGND 21
10
REFIN
9
VTTI
VCC 23
8
VTT
SHDN 24
7
PGND2
2
SSTL Memory Supplies
PGOOD1
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
3
4
5
6
VTTR
1
VTTS
DDR, DDR2, and DDR3 Memory Supplies
STDBY
MAX17000ETG+
SKIP 22
OVP
Notebook Computers
PART
PGOOD2
Applications
Ordering Information
BST
The VDDQ rail is supplied by a step-down converter
using Maxim’s proprietary Quick-PWM™ controller. The
high-efficiency, constant-on-time PWM controller handles wide input/output voltage ratios (low duty-cycle
applications) with ease and provides 100ns response
to load transients while maintaining a relatively constant
switching frequency. The Quick-PWM architecture circumvents the poor load-transient timing problems of
fixed-frequency current-mode PWMs while also avoiding the problems caused by widely varying switching
frequencies in conventional constant-on-time and constant-off-time PWM schemes. The controller senses the
current to achieve an accurate valley current-limit protection. It is also built in with overvoltage, undervoltage,
and thermal protections. The MAX17000 can be set to
run in three different modes: power-efficient SKIP
mode, low-noise forced-PWM mode, and standby
mode to support memory in notebook computer standby operation. The switching frequency is programmable from 200kHz to 600kHz to allow small components
and high efficiency. The VDDQ output voltage can be
set to a preset 1.8V or 1.5V, or be adjusted from 1.0V to
2.5V by an external resistor-divider. This output has 1%
accuracy over line-and-load operating range.
The MAX17000 includes a ±2A source/sink LDO regulator for the memory termination VTT rail. This VTT regulator has a ±5mV deadband that either sources or
sinks, ideal for the fast-changing load burst present in
memory termination applications. This feature also
reduces output capacitance requirements.
The VTTR reference buffer sources and sinks ±3mA,
providing the reference voltage needed by the memory
controller and devices on the memory bus.
The MAX17000 is available in a 24-pin, 4mm x 4mm,
TQFN package.
o SMPS Regulator (VDDQ)
Quick-PWM with 100ns Load-Step Response
Output Voltages—Preset 1.8V, 1.5V, or
Adjustable 1.0V to 2.5V
1% VOUT Accuracy Over Line and Load
26V Maximum Input Voltage Rating
Accurate Valley Current-Limit Protection
200kHz to 600kHz Switching Frequency
o Source/Sink Linear Regulator (VTT)
±2A Peak Source/Sink
Low-Output Capacitance Requirement
Output Voltages-Preset VDDQ/2 or REFIN
Adjustable from 0.5V to 1.5V
o Low Quiescent Current Standby State
o Soft-Start/Soft-Shutdown
o SMPS Power-Good Window Comparator
o VTT Power-Good Window Comparator
o Selectable Overvoltage Protection
o Undervoltage/Thermal Protections
o ±3mA Reference Buffer (VTTR)
DL
The MAX17000 pulse-width modulation (PWM) controller provides a complete power solution for notebook
DDR, DDR2, and DDR3 memory. It comprises a stepdown controller, a source/sink LDO regulator, and a reference buffer to generate the required VDDQ, VTT, and
VTTR rails.
Features
TQFN
4mm x 4mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX17000
General Description
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ABSOLUTE MAXIMUM RATINGS
VTTI to PGND2 .........................................................-0.3V to +6V
VTT to PGND2 ............................................-0.3V to (VTTI + 0.3V)
VTTS to AGND............................................-0.3V to (VCC + 0.3V)
VTTR to AGND ..........................................-0.3V to (VCSL + 0.3V)
PGND1, PGND2 to AGND.....................................-0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
24-Pin, 4mm x 4mm TQFN-EP
(derated 27.8mW/°C above +70°C) ..........................2222mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
TON to PGND1 .......................................................-0.3V to +28V
VDD to PGND1..........................................................-0.3V to +6V
VCC to VDD ............................................................-0.3V to +0.3V
OVP to AGND ...........................................................-0.3V to +6V
SHDN, STDBY, SKIP to AGND .................................-0.3V to +6V
REFIN, FB, PGOOD1,
PGOOD2 to AGND ................................-0.3V to (VCC + 0.3V)
CSH, CSL to AGND ....................................-0.3V to (VCC + 0.3V)
DL to PGND1..............................................-0.3V to (VDD + 0.3V)
BST to PGND1...........................................................-1V to +34V
BST to LX..................................................................-0.3V to +6V
DH to LX ....................................................-0.3V to (VBST + 0.3V)
BST to VDD .............................................................-0.3V to +26V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input Voltage Range
Output Voltage Accuracy
Output Voltage Range
VIN
3
26
VCC, VDD
4.5
5.5
VCSL
VIN = 4.5V to 26V,
SKIP = VCC
FB = AGND
1.485
1.500
1.515
FB = VCC
1.782
1.800
1.818
FB = Adj
0.99
1.000
1.01
VCSL
Load Regulation Error
Line Regulation Error
1
2.7
VCSH - VCSL = 0 to 18mV, SKIP = VCC
0.1
V
V
V
%
VDD = 4.5V to 5.5V, VIN = 4.5V to 26V
0.25
Soft-Start Ramp Time
t SSTART
Rising edge of SHDN
1.4
Soft-Stop Ramp Time
t SSTOP
Falling edge of SHDN
2.8
ms
25
mV
Soft-Stop Threshold
On-Time Accuracy (Note 2)
2
t ON
VIN = 12V,
VCSL = 1.2V
%
2.1
RTON = 96.75k
(600kHz), 167ns nominal
-15
+15
RTON = 200k (300kHz),
333ns nominal
-10
+10
RTON = 303.25k
(200kHz), 500ns nominal
-15
+15
_______________________________________________________________________________________
ms
%
Complete DDR2 and DDR3 Memory
Power-Management Solution
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Minimum Off-Time
SYMBOL
t OFF(MIN)
Quiescent Supply Current (VDD)
Quiescent Supply Current (VCC)
IDD
ICC
Shutdown Supply Current
(VDD + VCC)
ICC + IDD
TON Pin Shutdown Current
ITON
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 2)
250
350
ns
FB forced above 1.0V, STDBY = AGND or
VCC, TA = +25°C
0.01
1.00
µA
2
4
mA
FB forced above 1.0V (ultra-skip and VTTR
blocks); STDBY = AGND
275
475
µA
SHDN = AGND, TA = +25°C
0.01
5
µA
SHDN = AGND, VIN = 26V, VDD = 0 or 5V,
TA = +25°C
0.01
1.00
µA
FB forced above 1.0V (SMPS, VTT, and
VTTR blocks); STDBY = VCC
LINEAR REGULATOR (VTT)
VTTI Input Voltage Range
VTTI
VTTI Supply Current
IVTTI
1.0
VTTI Shutdown Current
VVTTI = 2.5V, VREFIN = 1.4V
SHDN = AGND, TA = +25°C
REFIN Input Bias Current
VVTTI = 2.5V, VREFIN = 1.4V
REFIN Range
VREFIN
VTT Output-Accuracy
Source Load
VTT Output-Accuracy
Sink Load
V
50
µA
10
µA
-50
+50
nA
0.5
1.5
V
V
High-side on-resistance
(source, I VTT = 0.1A)
0.12
0.25
Low-side on-resistance (sink, I VTT = 0.1A)
0.18
0.36
(VREFIN - 5mV) or
(VCSL/2 - 5mV) to
VTTS, VTT = VTTS
(VREFIN + 5mV) or
(VCSL/2 + 5mV) to
VTTS, VTT = VTTS
VREFIN = 1V,
I VTT = +50µA
-5
mV
VREFIN = 0.5V to 1.5V,
I VTT = +300mA
VREFIN = 1V,
I VTT = -50µA
+5
-5
-5
+5
mV
VREFIN = 0.5V to 1.5V,
I VTT = -300mA
+5
VTT Load Regulation
-50µA to -1A I VTT +50µA to +1A
13
VTT Line Regulation
1.0V VTTI 2.8V, I VTT = ±100mA
1
VTT Current Limit
2.8
VCC 0.3
REFIN Disable Threshold
VTT Internal MOSFET
10
17
mV
Source
2
4
Sink
-4
-2
VTT Current-Limit Soft-Start Time
With respect to internal VTT_EN signal
VTT Discharge MOSFET
OVP = VCC
16
VTTS Input Current
TA = +25°C
0.1
mV/A
160
A
µs
1.0
µA
_______________________________________________________________________________________
3
MAX17000
ELECTRICAL CHARACTERISTICS (continued)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE BUFFER (VTTR)
VTTR Output Accuracy (Adj)
REFIN to VTTR
VTTR Output Accuracy (Preset)
VCSL/2 to VTTR
VTTR Maximum
Recommended Current
Source/sink
I VTT = ±1mA
-10
+10
I VTT = ±3mA
-20
+20
I VTT = ±1mA
-10
+10
I VTT = ±3mA
-20
+20
5
mV
mA
FAULT DETECTION (SMPS)
SMPS OVP and PGOOD1
Upper Trip Threshold
12
SMPS OVP and PGOOD1
Upper Trip Threshold
Fault-Propagation Delay
t OVP
SMPS Output Undervoltage
Fault-Propagation Delay
tUVP
SMPS PGOOD1 Lower Trip
Threshold
PGOOD1 Lower Trip Threshold
Propagation Delay
FB forced 25mV above trip threshold
Measured at FB, hysteresis = 25mV
t PGOOD1
PGOOD1 Output Low Voltage
-12
FB forced 50mV below PGOOD1 trip
threshold
15
I PGOOD1
FB = 1V (PGOOD1 high impedance),
PGOOD1 forced to 5V, TA = +25°C
TON POR Threshold
VPOR(IN)
Rising edge, PWM disabled below this level;
hysteresis = 200mV
%
10
µs
200
µs
-15
-18
10
I SINK = 3mA
PGOOD1 Leakage Current
18
%
µs
0.4
V
1
µA
3.0
V
FAULT DETECTION (VTT)
PGOOD2 Upper Trip Threshold
Hysteresis = 25mV
8
10
13
%
PGOOD2 Lower Trip Threshold
Hysteresis = 25mV
-13
-10
-8
%
VTTS forced 50mV beyond PGOOD2
trip threshold
10
µs
PGOOD2 Fault Latch Delay
VTTS forced 50mV beyond PGOOD2
trip threshold
5
ms
PGOOD2 Output Low Voltage
I SINK = 3mA
PGOOD2 Propagation Delay
PGOOD2 Leakage Current
t PGOOD2
I PGOOD2
VTTS = VREFIN (PGOOD2 high impedance),
PGOOD2 forced to 5V, TA = +25°C
0.4
V
1
µA
FAULT DETECTION
Thermal-Shutdown Threshold
VCC Undervoltage Lockout
Threshold
CSL Discharge MOSFET
4
T SHDN
VUVLO(VCC)
Hysteresis = 15°C
Rising edge, IC disabled below this level
hysteresis = 200mV
OVP = VCC
°C
160
3.8
4.1
16
_______________________________________________________________________________________
4.4
V
Complete DDR2 and DDR3 Memory
Power-Management Solution
(VIN = 12V, VCC = VDD = V SHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
17
20
25
mV
CURRENT LIMIT
Valley Current-Limit Threshold
VLIMIT
VCSH - VCSL
Current-Limit Threshold
(Negative)
VNEG
VCSH - VCSL, SKIP = VCC
Current-Limit Threshold
(Zero Crossing)
VZX
VCSH - VCSL
RDH
BST - LX forced to 5V
1.5
5.0
DL high
1.5
5.0
DL low
0.6
3.0
-23
mV
1
mV
SMPS GATE DRIVERS
DH Gate Driver On-Resistance
DL Gate Driver On-Resistance
RDL
DH Gate Driver Source/
Sink Current
IDH
DL Gate Driver Source/
Sink Current
DH forced to 2.5V, BST - LX forced to 5V
1
IDL(SRC)
DL forced to 2.5V
1
IDL(SNK)
DL forced to 2.5V
3
Dead Time
tDEAD
Internal BST Switch
On-Resistance
RBST
LX, BST Leakage Current
DL rising, TA = +25°C
10
25
DL falling, TA = +25°C
15
35
IBST = 10mA,
VDD = 5V internal design target
A
A
ns
4.5
VBST = VLX = 26V, SHDN = AGND,
TA = +25°C
0.001
20
µA
1.65
2.00
V
+1
µA
INPUTS AND OUTPUTS
Logic Input Threshold
SHDN, STDBY, SKIP, OVP, rising edge
hysteresis = 300mV/600mV (min/max)
Logic Input Current
SKIP = AGND or VCC,
-1
Input Leakage Current
VCSH = 0V or VCC, TA = +25°C
-1
Input Bias Current
VCSL = 0V or VCC
1.30
55
+1
µA
100
µA
_______________________________________________________________________________________
5
MAX17000
ELECTRICAL CHARACTERISTICS (continued)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VCC = VDD = VSHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = -40°C to +85°C, unless otherwise noted.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
PWM CONTROLLER
Input Voltage Range
Output Voltage Accuracy
On-Time Accuracy (Note 2)
Minimum Off-Time
Quiescent Supply Current (VCC)
VIN
3
26
VCC, VDD
4.5
5.5
FB = AGND
1.485
1.520
FB = VCC
1.782
1.820
FB = Adj
0.990
1.020
RTON = 96.75k
(600kHz), 167ns
nominal
-15
+15
RTON = 200k
(300kHz), 333ns
nominal
-10
+10
RTON = 303.25k
(200kHz), 500ns
nominal
-15
+15
VCSL
t ON
t OFF(MIN)
ICC
VIN = 4.5V to 26V,
SKIP = VCC
VIN = 12V,
VCSL = 1.2V
(Note 2)
V
V
%
350
ns
FB forced above 1.0V (PWM, VTT, and
VTTR blocks); STDBY = VCC
4
mA
FB forced above 1.0V (ultra-skip and
VTTR blocks); STDBY = AGND
475
µA
LINEAR REGULATOR (VTT)
VTTI Input Voltage Range
VVTTI
VTTI Supply Current
IVTTI
REFIN Range
1.0
VVTTI = 2.5V, VREFIN = 1.4V
VREFIN
0.5
VTT Load Regulation
6
V
50
µA
1.5
V
VCC 0.3
REFIN Disable Threshold
VTT Internal MOSFET
2.8
V
High-side on-resistance (source, IVTT = 0.1A)
0.25
Low-side on-resistance (sink, I VTT = 0.1A)
0.36
-50µA to -1A I VTT +50µA to +1A
_______________________________________________________________________________________
17
mV/A
Complete DDR2 and DDR3 Memory
Power-Management Solution
(VIN = 12V, VCC = VDD = VSHDN = VREFIN = 5V, VCSL = 1.8V, STDBY = SKIP = AGND, TA = -40°C to +85°C, unless otherwise noted.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
I VTT = ±1mA
-10
+10
I VTT = ±3mA
-20
+20
I VTT = ±1mA
-10
+10
I VTT = ±3mA
-20
+20
UNITS
REFERENCE BUFFER (VTTR)
VTTR Output Accuracy (Adj)
REFIN to VTTR
VTTR Output Accuracy (Preset)
VCSL/2 to VTTR
mV
mV
FAULT DETECTION (SMPS)
PGOOD1 Output Low Voltage
I SINK = 3mA
0.4
V
I SINK = 3mA
0.4
V
FAULT DETECTION (VTT)
PGOOD2 Output Low Voltage
FAULT DETECTION
VCC Undervoltage-Lockout
Threshold
VUVLO(VCC)
Rising edge, IC disabled below this level;
hysteresis = 200mV
4.0
4.4
V
VCSH - VCSL
15
25
mV
BST - LX forced to 5V
5
DL high
5
DL low
3
CURRENT LIMIT
Valley Current-Limit Threshold
VLIMIT
SMPS GATE DRIVERS
DH Gate Driver On-Resistance
DL Gate Driver On-Resistance
Dead Time
RDH
RDL
tDEAD
DL rising
10
DL falling
15
SHDN, STDBY, SKIP, OVP, rising edge
hysteresis = 300mV/600mV (min/max)
1.3
ns
INPUTS AND OUTPUTS
Logic Input Threshold
2
V
Note 1: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design
and characterization.
Note 2: On-time and off-time specifications are measured from 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF
capacitor connected from DH to LX. Actual in-circuit times might differ due to MOSFET switching speeds.
_______________________________________________________________________________________
7
MAX17000
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(MAX17000 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25°C, unless otherwise noted.)
80
PWM MODE
SKIP MODE
50
40
70
60
50
30
20
20
VIN = 7V
0.1
0.01
1
70
60
50
SKIP MODE
PWM MODE
40
20
VIN = 12V
0.1
0.01
1
VIN = 20V
10
0.01
10
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
SMPS 1.8V OUTPUT VOLTAGE
vs. LOAD CURRENT
SMPS SWITCHING FREQUENCY
vs. LOAD CURRENT
SMPS VALLEY-CURRENT LIMIT
vs. INPUT VOLTAGE
PWM MODE
VIN = 12V
0.1
1
200
150
100
0
2
LOAD CURRENT (A)
4
6
8
4
8
12
10
PWM MODE, IIN
SKIP MODE, ICC + IDD
STANDBY MODE, ICC + IDD
SKIP MODE, IIN
0.1
50
SAMPLE SIZE = 150
SAMPLE PERCENTAGE (%)
PWM MODE, ICC + IDD
PRESET 1.5V OUTPUT
VOLTAGE DISTRIBUTION
MAX17000 toc07
NO LOAD
16
+85°C
+25°C
40
30
20
10
STANDBY MODE, IIN
0.01
0
4
8
12
16
20
INPUT VOLTAGE (V)
24
28
20
INPUT VOLTAGE (V)
LOAD CURRENT (A)
100
SUPPLY CURRENT (mA)
9.50
10
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
1
10.00
9.75
VIN = 12V
VOUT = 1.8V
0
10
RSENSE = 2mΩ
10.25
250
50
0.01
MAX17000 toc06
300
MAX17000 toc08
SKIP MODE
10.50
CURRENT LIMIT (A)
SWITCHING FREQUENCY (kHz)
MAX17000 toc04
350
1.79
8
10
LOAD CURRENT (A)
1.80
1.78
0.001
80
30
10
10
1.82
1.81
PWM MODE
40
30
10
SKIP MODE
STANDBY MODE
90
MAX17000 toc05
60
EFFICIENCY (%)
70
100
MAX17000 toc03
80
STANDBY MODE
90
EFFICIENCY (%)
STANDBY MODE
90
EFFICIENCY (%)
100
MAX17000 toc01
100
SMPS 1.8V EFFICIENCY
vs. LOAD CURRENT
SMPS 1.8V EFFICIENCY
vs. LOAD CURRENT
MAX17000 toc02
SMPS 1.8V EFFICIENCY
vs. LOAD CURRENT
OUTPUT VOLTAGE (V)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
1.490
1.495
1.500
1.505
1.510
OUTPUT VOLTAGE (V)
_______________________________________________________________________________________
24
28
Complete DDR2 and DDR3 Memory
Power-Management Solution
STARTUP WAVEFORM
(HEAVY LOAD)
SHUTDOWN WAVEFORM
(DISCHARGE MODE ENABLED)
MAX17000 toc09
VDDQ
MAX17000 toc11
VDDQ
VTTR
STBY
VDDQ
VTT
VTT
TON
DL
SHDN
STANDBY TRANSITION WAVEFORM
MAX17000 toc10
PGOOD2
VTT
PGOOD1
VTTR
PGOOD1
DL
SHDN
LX
ILX
ILX
DL
ILX
SHDN : 5V/div
VDDQ : 500mV/div
VTT : 500mV/div
VTTR : 500mV/div
200µs/div
PGOOD1 : 2V/div RLOAD = 0.25Ω
SKIP = GND
ILX : 5A/div
DL : 5V/div
2ms/div
400µs/div
DL : 5V/div
VDDQ : 2V/div
VTT : 1V/div
VTTR : 1V/div
MAX17000 toc14
MAX17000 toc13
MAX17000 toc12
STBY
VDDQ
VDDQ
VDDQ
SMPS LOAD-TRANSIENT RESPONSE
(SKIP MODE)
SMPS LOAD-TRANSIENT RESPONSE
(SKIP MODE)
STANDBY TRANSITION WAVEFORM
DL : 5V/div
LX : 10V/div
ILX : 2A/div
STBY : 5V/div
VDDQ : 1V/div
VTT : 1V/div
TON: 10V/div
PGOOD2 : 5V/div
PGOOD1 : 5V/div
SHDN : 10V/div
ILX : 2A/div
VTT
TON
LX
LX
ILOAD
ILOAD
ILX
ILX
LX
DL
ILX
20µs/div
20µs/div
200µs/div
STBY : 5V/div
VDDQ : 2V/div
VTT : 1V/div
TON: 10V/div
LX : 10V/div
ILX : 10A/div
DL : 5V/div
VDDQ : 50mV/div
LX : 10V/div
ILOAD : 5A/div
ILX : 5A/div
VDDQ : 50mV/div
LX : 10V/div
ILOAD : 5A/div
ILX : 5A/div
_______________________________________________________________________________________
9
MAX17000
Typical Operating Characteristics (continued)
(MAX17000 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(MAX17000 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25°C, unless otherwise noted.)
VTT OFFSET VOLTAGE DISTRIBUTION
AT 300mA LOAD
VTT VOLTAGE
vs. SOURCE/SINK LOAD CURRENT
DL
MAX17000 toc16
0.79
0.78
VTT VOLTAGE (V)
VDDQ
VTT
VTTR
PGOOD2
PGOOD1
0.77
0.76
0.75
0.74
SAMPLE SIZE = 150
+85°C
+25°C
40
30
20
10
ILX
0.73
VTTI = 18V
0
0.72
400µs/div
-2.0 -1.5 -1.0 -0.5
PGOOD2 : 2V/div
PGOOD1 : 2V/div
ILX : 10A/div
VTT SOURCE CURRENT LIMIT
+85°C
+25°C
40
30
20
0.5
1.0
1.5
-12.5
-10.0
-7.5
-5.0
LOAD CURRENT (A)
OFFSET VOLTAGE (mV)
VTT SINK CURRENT LIMIT
VTT OVERLOAD FAULT WAVEFORMS
(5ms TIMER)
MAX17000 toc20
SAMPLE SIZE = 150
+85°C
+25°C
40
DL
ILX
30
VDDQ
VTT
20
VTTR
10
10
-15.0
2.0
50
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 150
MAX17000 toc18
50
0
MAX17000 toc19
DL : 5V/div
VDDQ : 1V/div
VTT : 1V/div
VTTR : 1V/div
PGOOD1
PGOOD2
0
0
2.0
2.5
3.0
3.5
CURRENT LIMIT (A)
10
50
MAX17000 toc17
MAX17000 toc15
SAMPLE PERCENTAGE (%)
OUTPUT OVERLOAD WAVEFORM
SAMPLE PERCENTAGE (%)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
4.0
-4.0
-3.5
-3.0
-2.5
CURRENT LIMIT (A)
-2.0
1ms/div
DL : 5V/div
ILX : 2A/div
VDDQ : 2V/div
VTT : 1V/div
______________________________________________________________________________________
VTTR : 1V/div
PGOOD1 : 2V/div
PGOOD2 : 2V/div
Complete DDR2 and DDR3 Memory
Power-Management Solution
VTT LOAD-TRANSIENT RESPONSE
(SINK)
VTT LOAD-TRANSIENT RESPONSE (SOURCE)
IVTT BETWEEN 10mA AND 1.5A
MAX17000 toc22
MAX17000 toc21
IVTT
IVTT
VTT_ac
VTT_ac
VDDQ = 1.8V
VDDQ = 1.8V
20µs/div
20µs/div
IVTT : 1A/div
VTT : 20mV/div
IVTT : 1A/div
VTT : 20mV/div
VTT LOAD-TRANSIENT RESPONSE
(SOURCE/SINK)
VTTR OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17000 toc23
MAX17000 toc24
0.79
0.78
0.77
OUTPUT VOLTAGE (V)
IVTT
VTT_ac
0.76
0.75
0.74
0.73
0.72
VDDQ = 1.8V
0.71
0.70
20µs/div
IVTT : 1A/div
VTT : 20mV/div
-6
-4
-2
0
2
4
6
LOAD CURRENT (mA)
______________________________________________________________________________________
11
MAX17000
Typical Operating Characteristics (continued)
(MAX17000 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TA = +25°C, unless otherwise noted.)
Complete DDR2 and DDR3 Memory
Power-Management Solution
MAX17000
Pin Description
PIN
NAME
FUNCTION
OVP
OVP Mode Control. This input selectively enables/disables the SMPS OV protection feature and
output discharge mode. When enabled, the SMPS OV protection feature is enabled. Connect OVP to
the following voltage levels for the desired function:
High (> 2.4V) = Enable SMPS OV protection, and SMPS and VTT discharge FETs.
Low (AGND) = Disable SMPS OV protection, and SMPS and VTT discharge FETs.
PGOOD1
Open-Drain Power-Good Output. PGOOD1 is low when the SMPS output voltage is more than 15%
(typ) beyond the normal regulation point, during soft-start, and in shutdown.
After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the SMPS output is
in regulation.
PGOOD2
Open-Drain Power-Good Output. PGOOD2 is low when the VTT output voltage is more than 10%
(typ) beyond the normal regulation point, in shutdown, in standby, and during soft-start.
After the SMPS soft-start circuit has terminated, PGOOD2 becomes high impedance if the VTT
output is in regulation.
4
STDBY
Standby Control Input. When SHDN is high and STDBY is low, the MAX17000 enters a lowquiescent current mode, putting the SMPS in ultra-skip operation and turning off the VTT output
(high-Z). This mode helps save converter power loss in computer standby operation.
When STDBY is high, normal SMPS operation resumes and the VTT output is enabled.
5
VTTS
Sense Pin for Termination Supply Output. Normally connected to the VTT pin to allow accurate
regulation to VCSL/2 or the REFIN voltage.
6
VTTR
Termination Reference Buffer Output. VTTR tracks VCSL/2 when REFIN is connected to VCC. VTTR
tracks VREFIN when a voltage between 0.5V to 1.5V is set at REFIN. Decouple VTTR to AGND with a
0.33µF ceramic capacitor.
7
PGND2
8
VTT
Termination Power-Supply Output. Connect VTT to VTTS to regulate the VTT voltage to the VTTS
regulation setting.
9
VTTI
Termination Power-Supply Input. VTTI is the input power supply to the VTT linear regulator.
Normally connected to the output of the SMPS regulator for DDR applications.
1
2
3
12
10
REFIN
11
FB
Power Ground for VTT. Connect PGND2 externally to the underside of the exposed pad.
External Reference Input. REFIN sets the feedback regulation voltage (VTTR = VTTS = VREFIN) of
the MAX17000.
Connect REFIN to VCC to use the internal VCSL/2 divider.
Connect a 0.5V to 1.5V voltage input to set the adjustable output for VTT, VTTS, and VTTR.
Feedback Input for SMPS Output. Connect to VCC for a fixed +1.8V output or to AGND for a fixed
+1.5V output. For an adjustable output (1.0V to 2.7V), connect FB to a resistive divider from the
output voltage. FB regulates to +1.0V.
12
CSL
Negative Input of the PWM Output Current-Sense and Supply Input for VTTR. Connect CSL to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
CSL is also the path for the internal 16 discharge MOSFET when VCC UVLO occurs with OVP
enabled.
13
CSH
Positive Input of the PWM Output Current Sense. Connect CSH to the positive side of the output
current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
PIN
NAME
FUNCTION
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching frequency per phase according to the following equation:
14
TON
T SW = CTON x (RTON + 6.5k)
where CTON = 16.26pF.
TON is high impedance in shutdown.
15
DH
16
LX
High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.
Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1.
Boost Flying Capacitor Connection. Connect to an external 0.1µF, 6V capacitor as shown in Figure
1. The MAX17000 contains an internal boost switch.
17
BST
18
DL
Synchronous-Rectifier Gate-Driver Output. DL swings from VDD to PGND1.
19
VDD
Supply Voltage Input for the DL Gate Driver and 3.3V Reference/Analog Supply. Connect to the
system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1µF or greater
ceramic capacitor.
20
PGND1
Power Ground. Ground connection for the low-side MOSFET gate driver.
21
AGND
Analog Ground. Connect backside exposed pad to AGND.
22
SKIP
Pulse-skipping Control Input. This input determines the mode of operation under normal steadystate conditions and dynamic output voltage transitions:
High (> 2.4V) = Forced-PWM operation
Low (AGND) = Pulse-skipping mode
23
VCC
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass VCC to AGND with a 1µF or
greater ceramic capacitor.
Shutdown Control Input. Connect to VCC for normal operation. When SHDN is pulled low, the
MAX17000 slowly ramps down the output voltage to ground. When the internal target voltage
reaches 25mV, the controller forces DL low, and enters the low current (1µA) shutdown state.
24
SHDN
—
EP
When discharge mode is enabled by OVP (OVP = high), the CSL and VTT internal 16 discharge
MOSFETs are enabled in shutdown. When discharge mode is disabled by OVP (OVP = low), LX,
VTT, and VTTR are high impedance in shutdown.
A rising edge on SHDN clears the fault OV protection latch.
Exposed Pad. Connect backside exposed pad to AGND.
______________________________________________________________________________________
13
MAX17000
Pin Description (continued)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Standard Application Circuits
The MAX17000 standard application circuit (Figure 1)
generates the VDDQ, VTT, and VTTR rails for DDR,
DDR2, or DDR3 in a notebook computer. See Table 1 for
component selections. Table 2 lists the component manufacturers. Table 3 is the operating mode truth table.
Table 1. Component Selection for Standard Applications
COMPONENT
VOUT = 1.5V TO 1.8V AT 10A
VOUT = 1.5V TO 1.8V AT 6A
VIN = 7V TO 20V (300kHz)
VIN = 7V TO 16V (500kHz)
Input Capacitor
(2x) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
10µF, 25V
Taiyo Yuden TMK432BJ106KM
Output Capacitor
(2x) 330µF, 2.5V ,12m (C2 case)
SANYO 2R5TPE330MCC2
(2x) 220µF, 2.5V, 21m (B2 case)
SANYO 2R5TPE220MLB
Inductor
1.4µH, 12A, 3.4m (typ)
Sumida CDEP105(L)NP-1R4
1.4µH, 12A, 3.4m (typ)
Sumida CDEP105(L)NP-1R4
Current-Sensing Resistor
2m, 0.5W (2010)
Vishay WSL20102L000FEA
3m, 0.5W (2010)
Vishay WSL20103L000FEA
MOSFETs
30V, 20A n-channel MOSFET (high side)
Fairchild FDMS8690;
30V, 40A n-channel MOSFET (low side)
Fairchild FDMS8660S
30V 20A n-channel MOSFET (high side)
Fairchild FDMS8690;
30V 40A n-channel MOSFET (low side)
Fairchild FDMS8660S
Table 2. Component Suppliers
SUPPLIER
PHONE
WEBSITE
INDUCTORS
Dale (Vishay)
402-563-6866 (USA)
www.vishay.com
NEC/TOKIN America, Inc.
510-324-4110 (USA)
www.nec-tokinamerica.com
Panasonic Corp.
65-231-3226 (Singapore), 408-749-9714 (USA)
www.panasonic.com
Sumida Corp.
408-982-9660 (USA)
www.sumida.com
TOKO America, Inc.
858-675-8013 (USA)
www.tokoam.com
843-448-9411 (USA)
www.avxcorp.com
CAPACITORS
AVX Corp.
KEMET Corp.
408-986-0424 (USA)
www.kemet.com
Panasonic Corp.
65-231-3226 (Singapore), 408-749-9714 (USA)
www.panasonic.com
SANYO Electric Co., Ltd.
81-72-870-6310 (Japan), 619-661-6835 (USA)
www.sanyodevice.com
Taiyo Yuden
TDK Corp.
03-3667-3408 (Japan), 408-573-4150 (USA)
847-803-6100 (USA), 81-3-5201-7241 (Japan)
www.t-yuden.com
www.component.tdk.com
SENSING RESISTORS
Vishay
402-563-6866 (USA)
www.vishay.com
800-341-0392 (USA)
www.fairchildsemi.com
Central Semiconductor Corp.
631-435-1110
www.centralsemi.com
Nihon Inter Electronics Corp.
81-3-3343-84-3411 (Japan)
MOSFET
Fairchild Semiconductor
DIODES
14
www.niec.co.jp
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
SHDN
1
2
3
4
5
LH
LH
H
H
H
STDBY
LH
L
LH
H
H
SKIP
OPERATION
X
SMPS output ramps up in skip mode with a 1.4ms (typ) ramp time. PGOOD1 is held low until the
SMPS output is in regulation.
VTT and VTTR ramp up to the final voltage based on VCSL/2 or VREFIN. PGOOD2 is held low until
VTT is in regulation.
X
SMPS output ramps up in skip mode with a 1.4ms ramp time. PGOOD1 is held low until the SMPS
output is in regulation.
Once CSL or FB is in regulation, the PWM block turns off and enters standby mode.
VTT remains off throughout since STDBY is low. PGOOD2 stays low throughout. The VTT
discharge FET is enabled if OVP is high, but disabled if OVP is low.
VTTR ramps up to the final voltage based on VCSL/2 or VREFIN.
X
Ultra-skip and standby modes are exited and the full current capability of the MAX17000 is
available.
VTT ramps up after the internal SMPS block is ready. VTT ramps to the final voltage based on
VCSL/2 or VREFIN.
PGOOD2 goes high when VTT is in regulation.
H
SMPS output is in forced-PWM mode.
VTT and VTTR are enabled.
PGOOD1 is high when the SMPS output is in regulation.
PGOOD2 is high when VTT is in regulation.
L
SMPS output is in normal skip mode.
VTT and VTTR are enabled.
PGOOD1 is high when the SMPS output is in regulation.
PGOOD2 is high when VTT is in regulation.
6
H
L
X
SMPS output is in ultra-skip mode.
VTT is off and is high impedance.
PGOOD2 is forced low.
VTTR is active and regulates to VCSL/2 or VREFIN.
7
HL
H
X
Ultra-skip or skip mode is exited as the MAX17000 ramps the output down to zero.
VTTR tracks VCSL/2 or VREFIN during shutdown. After the SMPS output reaches 25mV, DL goes low.
8
HL
L
X
Ultra-skip or skip mode is exited as the MAX17000 ramps the output down to zero.
VTTR tracks VCSL/2 or VREFIN during shutdown. After the SMPS output reaches 25mV, DL goes
low. VTT is not enabled throughout soft-shutdown.
9
L
X
X
DL low. Internal16 discharge MOSFETs on CSL and VTT enabled if OVP is high, but disabled if
OVP is low.
______________________________________________________________________________________
15
MAX17000
Table 3. Operating Mode Truth Table
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
1
+5V
R3
100kΩ
R2
100kΩ
BST
2
3
+5V
19
CVDD
1µF
TON
OVP
DH
PGOOD1
PGOOD2
LX
VDD
DL
PGND1
R1
10Ω
PGND
23
5V VCC
CVCC
1µF
21
AGND
ON/OFF
24
22
10
PGND
CBST
0.1µF
16
L1
NL
18
RSENSE
VDDQ
+1.8V OR 1.5V
COUT
D1
20
PGND
PGND
11
RFBB
FB OPTIONS:
1. CONNECT FB TO 5V FOR FIXED +1.8V.
2. CONNECT FB TO GND FOR FIXED +1.5V.
3. USE FB RESISTOR-DIVIDER FOR ADJUSTABLE
OUTPUT VOLTAGES.
STDBY
AGND
SHDN
VTTI
SKIP
PGND2
VCC
NH
RFBA
FB
4
CIN
15
MAX17000
AGND
SLP_S3#
17
13
CSH
12
CSL
VCC
VIN
7V TO 20V
RTON
14
9
+1V TO + 2.5V
CVTTI
7
CVTT
PGND
REFIN
VTT
VTTS
VTTR
8
VTT = VDDQ/2
5
6
VTTR = VDDQ/2
CVTTR
0.33µF
EP
AGND
AGND
PGND
Figure 1. MAX17000 Standard Application Circuit
Detailed Description
The MAX17000 complete DDR solution comprises a
step-down controller, a source/sink LDO regulator, and a
reference buffer. Maxim’s proprietary Quick-PWM pulsewidth modulator in the MAX17000 is specifically
designed for handling fast load steps while maintaining a
relatively constant operating frequency and inductor
operating point over a wide range of input voltages. The
Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode
PWMs, while also avoiding the problems caused by
widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes.
Figure 1 is the MAX17000 standard application circuit
and Figure 2 is the MAX17000 functional diagram.
16
The MAX17000 includes a ±2A source/sink LDO regulator for the memory termination rail. The source/sink
regulator features a dead band that either sources or
sinks, ideal for the fast-changing short-period loads
presenting in memory termination applications. This
feature also reduces the VTT output capacitance
requirement down to 1µF, though load-transient
response can still require higher capacitance values
between 10µF and 20µF.
The reference buffer sources and sinks ±3mA, generating
a reference rail for use in the memory controller and
memory devices.
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
ON-TIME
COMPUTE
CSL
MAX17000
TON
tOFF(MIN)
Q
TON
TRIG
TRIG
1-SHOT
BST
Q
1-SHOT
RUN
STDBY
S
STDBY EA
ERROR
AMP
SMPS
RUN
DH
Q
R
LX
VDD
DL
S
R
Q
PGND1
STDBY
SKIP
1.2V
SMPS FAULT
DETECTION
OVF
SMPS
FAULT
ZERO CROSSING
INT_FB
OVP
VTT
FAULT
UVF
CSL
VALLEY CURRENT LIMIT
20mV
CSH
0.7V
10ms
TIMER
RUN
RUN
EA
PGOOD1
3mV
SMPS RUN
SMPS
FAULT
LATCH
SHDN
SOFT-START/STOP
1V REF
INT_FB
POWER-GOOD1
FB
DECODE
FB
VCC
OVF
1.15V
INT_REF
VTT FAULT
MAX17000
AGND
PGOOD2
POWER-GOOD2
1.4ms
VTT WINDOW
COMPARATOR
VTTS
VTTI
VTT
SMPS
FAULT
5ms
TIMER
VTT
FAULT
VTTI
VTT POS
CURRENT LIMIT
VDD
VTT SS
CURRENT LIMIT
5mV
SMPS RUNOK
VDD - 0.3V
STDBY
REFIN
VTT
VTT NEG
CURRENT LIMIT
PGND2
CSL
VTTR
16Ω
UVLO
RUN
OVP
PGND2
PGND2
CSL
VTT
VCC
R
VTT
VDD
5mV
VTT_EN
R
CSL
VTT_EN
16Ω
PGND2
PGND1
Figure 2. MAX17000 Functional Diagram
______________________________________________________________________________________
17
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
+5V Bias Supply (VDD, VCC)
The MAX17000 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator such as the MAX1615.
The 5V bias supply powers both the PWM controller
and internal gate-drive power, so the maximum current
drawn is:
IBIAS = IQ + fSWQG(MOSFETs) = 2mA to 20mA (typ)
where IQ is the current for the PWM control circuit, fSW
is the switching frequency, and QG(MOSFETs) is the
total gate-charge specification limits at VGS = 5V for the
internal MOSFETs.
Free-Running Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator
with voltage feed-forward. This architecture utilizes the
output filter capacitor’s ESR to act as a current-sense
resistor, so the output ripple voltage can provide the
PWM ramp signal. In addition to the general QuickPWM, the MAX17000 also senses the inductor current
through DCR method or with a sensing resistor.
Therefore, it is less dependent on the output capacitor
ESR for stability. The control algorithm is simple: the
high-side switch on-time is determined solely by a oneshot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage.
Another one-shot sets a minimum off-time (250ns typ).
The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley
current-limit threshold, and the minimum off-time oneshot has timed out.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltages. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the VIN input, and proportional
to the output voltage.
An external resistor between the input power source
and TON pin sets the switching frequency per phase
according to the following equation:
tON =
CTON × (RTON + 6.5kΩ) × (VCSL + 0.075V)
VIN
fSW =
1
CTON × (RTON + 6.5kΩ)
where CTON = 16.26pF, and 0.075V is an approximation to accommodate for the expected drop across the
low-side MOSFET switch. This algorithm results in a
nearly constant switching frequency despite the lack of
a fixed-frequency clock generator.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switching frequency is:
fSW =
VOUT + VDIS
tON × (VIN − VCHG + VDIS )
where VDIS is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous
rectifier, inductor, and PCB resistances; VCHG is the
sum of the parasitic voltage drops in the charging path,
including the high-side switch, inductor, and PCB resistances; and t ON is the on-time calculated by the
MAX17000.
Automatic Pulse-Skipping Mode
(SKIP = AGND)
In skip mode (SKIP = AGND), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing.
DC output-accuracy specifications refer to the threshold of the error comparator. When the inductor is in
continuous conduction, the MAX17000 regulates the
valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output
ripple voltage. In discontinuous conduction (SKIP =
AGND and IOUT < ILOAD(SKIP)), the output voltage has
a DC regulation level higher than the error-comparator
threshold by approximately 1.5% due to slope compensation. However, the internal integrator corrects for
most of it, resulting in very little load regulation.
STDBY = AGND overrides the SKIP pin setting, forcing
the MAX17000 into standby.
18
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
Forced-PWM Mode (SKIP = VCC)
The low-noise forced-PWM mode (SKIP = VCC) disables
the zero-crossing comparator, which controls the lowside switch on-time. This forces the low-side gate-drive
waveform to constantly be the complement of the highside gate-drive waveform, so the inductor current
reverses at light loads while DH maintains a duty factor
of VOUT/VIN. The benefit of forced-PWM mode is to keep
a fairly constant switching frequency. However, forcedPWM operation comes at a cost: the no-load 5V bias
VIN - VOUT
L
INDUCTOR CURRENT
∆I
=
∆t
IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
current remains between 2mA to 20mA, depending on
the switching frequency.
STDBY = AGND overrides the SKIP pin setting, forcing
the MAX17000 into standby.
The MAX17000 switches to forced-PWM mode during
shutdown, regardless of the state of SKIP and STDBY
levels.
Standby Mode (STDBY)
It should be noted that standby mode in the MAX17000
corresponds to computer system standby operation,
and is not referring to the MAX17000 shutdown status.
When standby mode is enabled (STDBY = AGND), the
MAX17000 switches over from the fast internal PWM
block to a low-quiescent current mode using a lowpower valley comparator to initiate an on-time pulse.
The zero-crossing comparator is enabled so that the
MAX17000 only operates in discontinuous mode,
reducing the maximum available output current by 1/6.
The system is NOT expected to have any fast load transients in such a state. While in standby, VTT is disabled
(high impedance) but VTTR remains active. SKIP is
ignored when standby mode is enabled.
When standby mode is disabled (STDBY = VCC), the
MAX17000 reenables its fast internal PWM block. Once
the internal SMPS block is ready, the VTT block is
enabled and the VTT output capacitor is charged. The
VTT soft-start current limit increases linearly from zero
to its maximum current limit in 160µs (typ), keeping the
input VTTI inrush low. See Figure 4.
STDBY
< 50µs
SMPS_RUNOK
SMPS OUTPUT
VTTR OUTPUT
VTT OUTPUT
VTT HIGH IMPEDANCE
VTT CURRENT LIMIT
160µs
PGOOD1
PGOOD2
Figure 4. MAX17000 Standby Mode Timing
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19
MAX17000
The MAX17000 always uses skip mode during startup,
regardless of the SKIP and STDBY setting. The SKIP
and STDBY controls take effect after soft-start is done.
See Figure 3.
Valley Current-Limit Protection
The MAX17000 uses the same valley current-limit protection employed on all Maxim Quick-PWM controllers. If
the current exceeds the valley current-limit threshold,
the PWM controller is not allowed to initiate a new cycle.
The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of
the inductor value and battery voltage. When combined
with the undervoltage-protection circuit, this current-limit
method is effective in almost every circumstance.
In forced-PWM mode, the MAX17000 also implements
a negative current limit to prevent excessive reverse
inductor currents when VOUT is sinking current. The
negative current-limit threshold is set to approximately
115% of the positive current limit. See Figure 5.
IPEAK
ILOAD
INDUCTOR CURRENT
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
ILIMIT
( LIR2 )
ILIM(VAL) = ILOAD(MAX) 1-
0
TIME
Figure 5. Valley Current-Limit Threshold Point
Power-Good Outputs
(PGOOD1 and PGOOD2)
The MAX17000 features two power-good outputs.
PGOOD1 is the open-drain output for a window comparator that continuously monitors the SMPS output.
PGOOD1 is actively held low in shutdown and during
soft-start and soft-shutdown. After the soft-start terminates, PGOOD1 becomes high impedance as long as
the SMPS output voltage is between 115% (typ) and
85% (typ) of the regulation voltage. When the SMPS
output voltage exceeds the 115%/85% regulation window, the MAX17000 pulls PGOOD1 low. Any fault condition on the SMPS output forces PGOOD1 and
PGOOD2 low and latches off until the fault latch is
cleared by toggling SHDN or cycling VCC power below
1V. Detection of an OVP event immediately pulls
PGOOD1 low, regardless of the OVP state (OVP
enabled or disabled).
20
PGOOD2 is the open-drain output for a window comparator that continuously monitors the VTT output.
PGOOD2 is actively held low in standby, shutdown,
and during soft-start. PGOOD2 becomes high impedance as long as the VTT output voltage is within ±10%
of the regulation voltage. When the VTT output exceeds
the ±10% threshold, the MAX17000 pulls PGOOD2 low.
If PGOOD2 remains low for 5ms (typ), the MAX17000
latches off with the soft-shutdown sequence.
For logic-level output voltages, connect an external 100kΩ
pullup resistor from PGOOD1 and PGOOD2 to VDD.
POR, UVLO
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and soft-start
circuit and preparing the controller for power-up. When
OVP is enabled, a rising edge on POR turns on the 16Ω
discharge MOSFET on CSL and VTT. When OVP is disabled, the internal 16Ω discharge MOSFETs on CSL
and VTT also remain off.
V CC undervoltage lockout (UVLO) circuitry inhibits
switching until VCC reaches 4.1V (typ). When VCC rises
above 4.1V, the controller activates the PWM controller
and initializes soft-start. When VCC drops below the
UVLO threshold (falling edge), the controller stops, DL
is pulled low, and the internal 16Ω discharge
MOSFETs on the CSL and VTT outputs are enabled, if
OVP is enabled.
Soft-Start and Soft-Shutdown
Soft-start and soft-shutdown for the MAX17000 PWM
block is voltage based. Soft-start begins when SHDN is
driven high. During soft-start, the PWM output is
ramped up from 0V to the final set voltage in 1.4ms.
This reduces inrush current and provides a predictable
ramp-up time for power sequencing. The MAX17000
always uses skip mode during startup, regardless of
the SKIP and STDBY setting. The SKIP and STDBY controls take effect after soft-start is done.
The MAX17000 VTT LDO regulator uses a current-limited
soft-start function. When the VTT block is enabled, the
internal source and sink current limits are linearly
increased from zero to the full-scale limit in 160µs. Fullscale current limit is available when the VTT output is in
regulation, or after 160µs, whichever is earlier. The VTTR
reference buffer does not have any soft-start control.
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
MAX17000
SHDN
STDBY
INT_REF
REFOK
SMPS_RUNOK
1.4ms
2.8ms
25mV
SMPS OUTPUT
VTT OUTPUT
VTTR OUTPUT
VTT CURRENT LIMIT
PGOOD1
160µs
PGOOD2
DL
SKIP
FPWM
VTT 16Ω FET
CSL 16Ω FET
Figure 6. MAX17000 Startup/Shutdown Timing when OVP Is Enabled
Soft-shutdown begins after SHDN goes low, an output
undervoltage fault occurs, or a thermal fault occurs. A
fault on the SMPS (UV fault for more than 200µs (typ)),
or fault on the VTT output that persists for more than
5ms (typ), triggers shutdown of the whole IC. During
soft-shutdown, the output is ramped down to 0V in
2.8ms, reducing negative inductor currents that can
cause negative voltages on the output. At the end of
soft-shutdown, DL is driven low.
When OVP is enabled (OVP = VCC), the internal 16Ω
discharging MOSFETs on CSL and VTT are enabled
until startup is triggered again by a rising edge of
SHDN. When OVP is disabled (OVP = AGND), the CSL
and VTT internal 16Ω discharging MOSFETs are not
enabled in shutdown.
Output Fault Protection
The MAX17000 provides overvoltage/undervoltage fault
protections for the PWM output. Drive OVP to enable
and disable fault protection as shown in Table 4.
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21
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Table 4. Fault Protection and Shutdown Setting Truth Table
OVP
OVP Disabled
Discharge Disabled
(OVP = Low)
MODE
REACTION/DRIVER STATE
COMMENT
Shutdown
(SHDN = low)
DL immediately pulled low.
VTTR tracks the SMPS output during soft-shutdown. CSL and VTT
are high impedance at the end of soft-shutdown (16 discharge
MOSFETs disabled).
Outputs highimpedance in
shutdown.
SMPS UVP
DL immediately pulled low.
VTTR tracks the SMPS output during soft-shutdown. CSL and VTT
are high impedance at the end of soft-shutdown (16 discharge
MOSFETs disabled).
SMPS latched fault
condition.
SMPS OVP
(disabled)
Controller remains active (normal operation).
Note: An OVP detection still pulls PGOOD1 low.
Only PGOOD1 pulled
low; fault not latched.
PGOOD2 immediately pulled low.
VTT < -90% or Soft-shutdown initiated if fault persists for more than 5ms (typ). DH
VTT > +110% not used in soft-shutdown. DL low after soft-shutdown completed.
VTTR tracks the SMPS output soft-shutdown.
VCC UVLO
falling edge
OVP Enabled
Discharge Enabled
(OVP = High)
22
DL and DH immediately pulled low.
PGOOD1 and PGOOD2 immediately forced low. VTT and VTTR
blocks immediately disabled (high impedance, no 16 discharge
on outputs).
—
Shutdown
(SHDN = low)
Soft-shutdown initiated.
DL high after soft-shutdown completed.
VTTR tracks the SMPS output during soft-shutdown. Internal 16
discharge MOSFETs on CSL and VTT enabled after soft-shutdown.
16 discharge
MOSFETs on CSL
and VTT enabled in
shutdown.
SMPS UVP
Soft-shutdown initiated. DH not used in soft-shutdown. DL low
after soft-shutdown completed.
VTTR tracks the SMPS output during soft-shutdown. Internal 16
discharge MOSFETs on CSL and VTT enabled after soft-shutdown.
SMPS latched fault
condition.
SMPS OVP
(enabled)
DL immediately latched high, DH forced low.
PGOOD1 and PGOOD2 immediately forced low.
VTT and VTTR blocks immediately shut down. Internal 16
discharge MOSFETs on CSL and VTT enabled.
SMPS latched fault
condition.
PGOOD2 immediately pulled low.
Soft-shutdown initiated if fault persists for more than 5ms (typ). DH
not used in soft-shutdown. DL low after soft-shutdown completed.
VTTR tracks the SMPS output during soft-shutdown. Internal 16
discharge MOSFETs on CSL and VTT enabled after soft-shutdown.
VTT latched fault
condition if fault
persists for more
than 5ms (typ).
VTT < 90% or
VTT > 110%
OVP Enabled
Discharge Enabled
(OVP = High)
VTT latched fault
condition if fault
persists for more
than 5ms (typ).
VCC UVLO
falling edge
DL and DH immediately pulled low.
PGOOD1 and PGOOD2 immediately forced low.
VTT and VTTR blocks immediately disabled.
Internal 16 discharge MOSFETs on CSL and VTT enabled
immediately.
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—
Complete DDR2 and DDR3 Memory
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OVP
MODE
Thermal fault
General Shutdown
and Fault
Conditions
REACTION/DRIVER STATE
COMMENT
DL and DH immediately pulled low.
PGOOD1 and PGOOD2 immediately forced low.
VTT and VTTR blocks immediately disabled (high impedance, no
16 discharge on outputs).
Active-fault condition.
VCC UVLO
rising edge
Activate INT_REF once VCC rises above UVLO, and SHDN = high.
Once REFOK is valid (high), initiate the soft-start sequence.
DL remains low until switching/soft-start begins.
—
VCC POR
rising edge
DL forced low.
—
VCC POR
falling edge
DL = Don’t care. VCC less than 2VT is not sufficient to turn on the
MOSFETs.
—
SMPS Overvoltage Protection (OVP)
If the output voltage of the SMPS rises 115% above its
nominal regulation voltage while OVP is enabled (OVP
= VCC), the controller sets its overvoltage fault latch,
pulls PGOOD1 and PGOOD2 low, and forces DL high.
The VTT and VTTR block shut down immediately, and
the internal 16Ω discharge MOSFETs on CSL and VTT
are turned on. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET),
the battery fuse blows. Cycle VCC below 1V or toggle
SHDN to clear the overvoltage fault latch and restart the
controller.
OVP is disabled when OVP is connected to AGND
(Table 4). PGOOD1 upper threshold remains active at
115% of nominal regulation voltage even when OVP is
disabled, and the 16Ω discharge MOSFETs on CSL
and VTT are not enabled in shutdown.
SMPS Undervoltage Protection (UVP)
If the output voltage of the SMPS falls below 85% of its
regulation voltage for more than 200µs (typ), the controller
sets its undervoltage fault latch, pulls PGOOD1 and
PGOOD2 low, and begins soft-shutdown pulsing DL. DH
remains off during the soft-shutdown sequence initiated
by an undervoltage fault. After soft-shutdown has completed, the MAX17000 forces DL and DH low, and
enables the internal 16Ω discharge MOSFETs on CSL
and VTT. Cycle VCC below 1V or toggle SHDN to clear
the undervoltage fault latch and restart the controller.
VTT Overvoltage and Undervoltage Protection
If the output voltage of the VTT regulator exceeds
±10% of its regulation voltage for more than 5ms (typ),
the controller sets its fault latch, pulls PGOOD1 and
PGOOD2 low, and begins soft-shutdown pulsing DL.
DH remains off during the soft-shutdown sequence initiated by an undervoltage fault. After soft-shutdown has
completed, the MAX17000 forces DL and DH low, and
enables the internal 16Ω discharge MOSFETs on CSL
and VTT. Cycle VCC below 1V or toggle SHDN to clear
the undervoltage fault latch and restart the controller.
Thermal-Fault Protection
The MAX17000 features a thermal-fault protection circuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
PGOOD1 and PGOOD2 low, and shuts down using the
shutdown sequence. Toggle SHDN or cycle VCC power
below VCC POR to reactivate the controller after the
junction temperature cools by 15°C.
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching
frequency and inductor operating point, and the following four factors dictate the rest of the design:
• Input Voltage Range: The maximum value
(VIN(MAX)) must accommodate the worst-case input
supply voltage allowed by the notebook’s AC
adapter voltage. The minimum value (V IN(MIN) )
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input
voltages result in better efficiency.
•
Maximum Load Current: There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and
filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal
______________________________________________________________________________________
23
MAX17000
Table 4. Fault Protection and Shutdown Setting Truth Table (continued)
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-contributing components. Most notebook loads generally exhibit ILOAD = ILOAD(MAX) x 80%.
•
•
Switching Frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
Inductor Operating Point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values provide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit. The optimum operating point is usually found
between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
⎛
⎞ ⎛ VOUT ⎞
VIN − VOUT
L=⎜
⎟ ×⎜
⎟
⎝ fSW × ILOAD(MAX) × LIR ⎠ ⎝ VIN ⎠
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
⎛ LIR ⎞
IPEAK = ILOAD(MAX) × ⎜ 1 +
⎟
⎝
2 ⎠
Setting the Valley Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half the ripple current; therefore:
⎛ LIR ⎞
ILIMIT(LOW) > ILOAD(MAX) × ⎜ 1 −
⎟
⎝
2 ⎠
where I LIMIT(LOW) equals the minimum current-limit
threshold voltage divided by the output sense element
(inductor DCR or sense resistor).
The valley current limit is fixed at 17mV (min) across the
CSH to CSL differential input.
Special attention must be made to the tolerance and
thermal variation of the on-resistance in the case of DCR
sensing. Use the worst-case maximum value for RDCR
from the inductor data sheet, and add some margin for
the rise in RDCR with temperature. A good general rule
is to allow 0.5% additional resistance for each °C of
temperature rise, which must be included in the design
margin unless the design includes an NTC thermistor in
the DCR network to thermally compensate the currentlimit threshold.
The current-sense method (Figure 7) and magnitude
determine the achievable current-limit accuracy and
power loss. The sense resistor can be determined by:
RSENSE = VLIMIT/ILIMIT
INPUT (VIN)
DH
NH
CIN
SENSE RESISTOR
L
LESL
RSENSE
CEQREQ =
LX
MAX17000 DL
NL
DL
REQ
CEQ
COUT
PGND1
CSH
CSL
A) OUTPUT SERIES RESISTOR SENSING
Figure 7a. Current-Sense Configurations (Sheet 1 of 2)
24
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LESL
RSENSE
Complete DDR2 and DDR3 Memory
Power-Management Solution
MAX17000
INPUT (VIN)
DH
NH
CIN
INDUCTOR
L
RDCR
RCS =
LX
MAX17000 DL
NL
DL
R1
PGND1
R2
CEQ
R2
RDCR
R1 + R2
COUT
L
RDCR = C
EQ
[ R11 + R21 ]
CSH
CSL
B) LOSSLESS INDUCTOR SENSING
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR.
Figure 7b. Current-Sense Configurations (Sheet 2 of 2)
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure 7a.
This configuration constantly monitors the inductor current, allowing accurate current-limit protection.
However, the parasitic inductance of the current-sense
resistor can cause current-limit inaccuracies, especially
when using low-value inductors and current-sense
resistors. This parasitic inductance (LESL) can be cancelled by adding an RC circuit across the sense resistor with an equivalent time constant:
CEQ × REQ =
LESL
RSENSE
Alternatively, low-cost applications that do not require
highly accurate current-limit protection could reduce
the overall power dissipation by connecting a series RC
circuit across the inductor (Figure 7b) with an equivalent time constant:
RCS =
R2
× RDCR
R1 + R2
and:
RDCR =
L
1 ⎤
⎡1
×⎢ +
CEQ ⎣ R1 R2 ⎥⎦
where RCS is the required current-sense resistance,
and RDCR is the inductor’s series DC resistance. Use
the worst-case inductance and RDCR values provided
by the inductor manufacturer, adding some margin for
the inductance drop over temperature and load.
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs.
This is consistent with the low duty factor seen in notebook applications, where a large VIN - VOUT differential
exists. The high-side gate driver (DH) sources and sinks
1.2A, and the low-side gate driver (DL) sources 1.0A and
sinks 2.4A. This ensures robust gate drive for high-current applications. The DH high-side MOSFET driver is
powered by an internal boost switch charge pump at
BST, while the DL synchronous-rectifier driver is powered directly by the 5V bias supply (VDD).
PWM Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
In core and chipset converters and other applications
where the output is subject to large-load transients, the
output capacitor’s size typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to finite
capacitance:
(RESR + RPCB ) ≤ ∆I
VSTEP
LOAD(MAX)
In low-power applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capacitor’s ESR.
______________________________________________________________________________________
25
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
The maximum ESR to meet ripple requirements is:
⎤
⎡
VIN × fSW × L
RESR ≤ ⎢
⎥ × VRIPPLE
⎢⎣ ( VIN − VOUT ) × VOUT ⎥⎦
where fSW is the switching frequency.
With most chemistries (polymer, tantalum, aluminum
electrolytic), the actual capacitance value required
relates to the physical size needed to achieve low ESR
and the chemistry limits of the selected capacitor technology. Ceramic capacitors provide low ESR, but the
capacitance and voltage rating (after derating) are
determined by the capacity needed to prevent VSAG
and VSOAR from causing problems during load transients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem. Thus, the output capacitor selection requires carefully balancing
capacitor chemistry limitations (capacitance vs. ESR
vs. voltage rating) and cost.
PWM Output Capacitor
Stability Considerations
For Quick-PWM controllers, stability is determined by the
in-phase feedback ripple relative to the switching frequency, which is typically dominated by the output ESR. The
boundary of instability is given by the following equation:
fSW
1
≥
π
2π × REFF × COUT
REFF = RESR + ACS × RSENSE
where COUT is the total output capacitance, RESR is the
total equivalent series resistance of the output capacitors, RSENSE is the effective current-sense resistance
(see Figure 7), and ACS is the current-sense gain of 2.
For a standard 300kHz application, the effective zero
frequency must be well below 95kHz, preferably below
50kHz. With these frequency requirements, standard
tantalum and polymer capacitors already commonly
used have typical ESR zero frequencies below 50kHz,
allowing the stability requirements to be achieved without any additional current-sense compensation. In the
standard application circuit (Figure 7), the ESR needed
to support a 15mV P-P ripple is 15mV/(10A x 0.3) =
5mΩ. Two 330µF, 9mΩ polymer capacitors in parallel
provide 4.5mΩ (max) ESR and 1/(2π x 330µF x 9mΩ) =
53kHz ESR zero frequency.
Ceramic capacitors have a high ESR zero frequency,
but applications with sufficient current-sense compensation can still take advantage of the small size, low
ESR, and high reliability of the ceramic chemistry. By
the inductor current DCR sensing, applications with
26
ceramic output capacitors can be compensated using
either a DC-compensation or AC-compensation
method. The DC-coupling requires fewer external compensation capacitors, but this also creates an output
load line that depends on the inductor’s DCR (parasitic
resistance). Alternatively, the current-sense information
can be AC-coupled, allowing stability to be dependent
only on the inductance value and compensation components and eliminating the DC load line.
When only using ceramic output capacitors, output
overshoot (VSOAR) typically determines the minimum
output capacitance requirement. Their relatively low
capacitance value can allow significant output overshoot when stepping from full-load to no-load conditions, unless a small inductor value and high switching
frequency are used to minimize the energy transferred
from inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related, but
distinctly different ways: double pulsing and feedback
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response undervoltage/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The IRMS requirements can be determined by the following equation:
⎛I
⎞
IRMS = ⎜ LOAD ⎟ VOUT × ( VIN − VOUT )
⎝ VIN ⎠
The worst-case RMS current requirement occurs when
operating with VIN = 2VOUT. At this point, the above
equation simplifies to:
IRMS = 0.5 x ILOAD
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both these sums.
Ideally, the losses at VIN(MIN) should be roughly equal to
losses at VIN(MAX), with lower losses in between. If the
losses at VIN(MIN) are significantly higher than the losses
at VIN(MAX), consider increasing the size of NH (reducing
RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at
VIN(MIN), consider reducing the size of NH (increasing
RDS(ON) to lower CGATE). If VIN does not vary over a
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized
package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),
and is reasonably priced. Make sure that the DL gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems can
occur (see the MOSFET Gate Drivers (DH, DL) section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
⎛V
⎞
2
PD (NH Resistive) = ⎜ OUT ⎟ × (ILOAD ) × RDS(ON)
⎝ VIN ⎠
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(NH) due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on NH:
⎛ QG(SW) ⎞
PD (NH Switching) = VIN(MAX) × ILOAD × fSW ⎜
⎟
⎝ IGATE ⎠
C
× VIN2 × fSW
+ OSS
2
where COSS is the NH MOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
x VIN2 x fSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
⎡ ⎛ V
⎞⎤
2
PD (NL Resistive) = ⎢1− ⎜ OUT ⎟ ⎥ × (ILOAD ) × RDS(ON)
⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
ILOAD(MAX), but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To protect against this possibility, the circuit can be “over
designed” to tolerate:
∆I
⎛
⎞
ILOAD = ⎜ IVALLEY(MAX) + INDUCTOR ⎟
⎝
⎠
2
⎛ ILOAD(MAX) × LIR ⎞
= IVALLEY(MAX) + ⎜
⎟
2
⎝
⎠
______________________________________________________________________________________
27
MAX17000
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a
mechanical switch or connector in series with the input.
If the Quick-PWM controller is operated as the second
stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit longevity.
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (DL) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if efficiency is not critical.
Setting the PWM Output Voltage
Preset Output Voltages
The MAX17000’s Dual Mode™ operation allows the
selection of common voltages without requiring external
components. Connect FB to AGND for a fixed 1.5V output, to V CC for a fixed 1.8V output, or connect FB
directly to OUT for a fixed 1.0V output.
Adjustable Output Voltage
The output voltage can be adjusted from 1.0V to 2.7V
using a resistive voltage-divider (Figure 8). The
MAX17000 regulates FB to a fixed reference voltage
(1.0V). The adjusted output voltage is:
VTTI Input Capacitor
Stability Considerations
The value of the VTTI bypass capacitor is chosen to
limit the amount of ripple/noise at VTTI, and the amount
of voltage dip during a load transient. Typically, VTTI is
connected to the output of the buck regulator, which
already has a large bulk capacitor. Nevertheless, a
ceramic capacitor of equivalent value to the VTT output
capacitor must be used and must be added and
placed as close as possible to the VTTI pin. This value
must be increased with larger load current, or if the
trace from the VTTI pin to the power source is long and
has significant impedance.
Setting VTT Output Voltage
The VTT output stage is powered from the VTTI input.
The output voltage is set by the REFIN input. REFIN sets
the feedback regulation voltage (VTTR = VTTS =
VREFIN) of the MAX17000. Connect a 0.1V to 2.0V voltage input to set the adjustable output for VTT, VTTS, and
VTTR. If REFIN is tied to VCC, the internal CSL/2 divider
is used to set VTT voltage; hence, VTT tracks the VCSL
voltage and is set to VCSL/2. This feature makes the
MAX17000 ideal for memory applications in which the
termination supply must track the supply voltage.
VTT Output Capacitor Selection
⎛ R
⎞
VOUT = VFB × ⎜ 1 + FBA ⎟
⎝ RFBB ⎠
A minimum value of 9µF is needed to stabilize a 300mA
VTT output. This value of capacitance limits the regulator’s unity-gain bandwidth frequency to approximately
1.2MHz (typ) to allow adequate phase margin for stability. To keep the capacitor acting as a capacitor within
the regulator’s bandwidth, it is important that ceramic
capacitors with low ESR and ESL be used.
where VFB is 1.0V.
L1
VOUT
LX
DL
NL
COUT
D1
PGND1
MAX17000
CSH
CSL
RFBA
FB
RFBB
Figure 8. Setting VOUT with a Resistive Voltage-Divider
Dual Mode is a trademark of Maxim Integrated Products, Inc.
28
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
COUT _ MIN = 20µF ×
ILOAD
1.5A
COUT needs to be increased by a factor of 2 for lowdropout operation:
RESR _ MAX = 5mΩ ×
ILOAD
1.5A
RESR value is measured at the unity-gain-bandwidth
frequency given by approximately:
fGBW =
36
COUT
×
ILOAD
1.5A
Once these conditions for stability are met, additional
capacitors, including those of electrolytic and tantalum
types, can be connected in parallel to the ceramic
capacitor (if desired) to further suppress noise or voltage ripple at the output.
VTTR Output Capacitor Selection
The VTTR buffer is a scaled-down version of the VTT
regulator, with much smaller output transconductance.
Its compensation capacitor can, therefore, be smaller
and its ESR larger than what is required for its larger
counterpart. For typical applications requiring load current up to ±4mA, a ceramic capacitor with a minimum
value of 0.33µF is recommended (R ESR < 0.3Ω).
Connect this capacitor between VTTR and the analog
ground plane.
Power Dissipation
Power loss in the MAX17000 is the sum of the losses of
the PWM block, the VTT LDO block, and the VTTR reference buffer:
PD(PWM) = IBIAS × 5V = 40mA × 5V = 0.2 W
PD(VTT) = 2 A × 0.9V = 1.8 W
PD(VTTR) = 3mA × 0.9V = 2.7mW
PD(Total) = 2 W
The 2W total power dissipation is within the 24-pin
TQFN multilayer board power dissipation spec of
2.22W. The typical application does not source or sink
continuous high currents. VTT current is typically
100mA to 200mA in the steady state. VTTR is down in
the µA range, though the Intel spec requires 3mA for
DDR1 and 1mA for DDR2. True worst-case power dissipation occurs on an output short-circuit condition with
worst-case current limit. The MAX17000 does not
employ any foldback current limiting, and relies on the
internal thermal shutdown for protection. Both the VTT
and VTTR output stages are powered from the same
VTTI input. Their output voltages are referenced to the
same REFIN input. The value of the VTTI bypass capacitor is chosen to limit the amount of ripple/noise at VTTI,
or the amount of voltage dip during a load transient.
Typically, VTTI is connected to the output of the buck
regulator, which already has a large bulk capacitor.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the highside MOSFETs’ gates:
CBST =
QGATE
200mV
where QGATE is the total gate charge specified in the
high-side MOSFET’s data sheet. For example, assume
the FDS6612A n-channel MOSFET is used on the high
side. According to the manufacturer’s data sheet, a single FDS6612A has a maximum gate charge of 13nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
CBST =
13nC
= 0.065µF
200mV
Selecting the closest standard value, this example
requires a 0.1µF ceramic capacitor.
______________________________________________________________________________________
29
MAX17000
Since the gain bandwidth is also determined by the
transconductance of the output FETs, which increases
with load current, the output capacitor might need to be
greater than 20µF if the load current exceeds 1.5A, but
can be smaller than 20µF if the maximum load current
is less than 1.5A. As a guideline, choose the minimum
capacitance and maximum ESR for the output capacitor using the following:
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the topside of the
board, with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
•
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing
PCB traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
•
Minimize current-sensing errors by connecting CSH
and CSL directly across the current-sense resistor
(RSENSE).
•
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor-charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
•
30
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN,
COUT, and anode of the low-side Schottky). If possible, make all these connections on the top layer
with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the backside opposite the
MOSFETs to keep LX, AGND, DH, and the DL gatedrive lines short and wide. The DL and DH gate
traces must be short and wide (50 mils to 100 mils
wide if the MOSFET is 1in from the controller IC) to
keep the driver impedance low and for proper
adaptive dead-time sensing.
3) Group the gate-drive components (BST diode and
capacitor, VDD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 9. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power components go; and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single
point directly at the IC.
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-to-DC converter circuit as close as is practical to the load.
Route high-speed switching nodes (BST, LX, DH,
and DL) away from sensitive analog areas (REFIN,
FB, CSH, and CSL).
______________________________________________________________________________________
Complete DDR2 and DDR3 Memory
Power-Management Solution
MAX17000
KELVIN SENSE VIAS
UNDER THE INDUCTOR
(SEE EVALUATION KIT)
POWER STAGE LAYOUT (TOP SIDE OF PCB)
OUTPUT
CEQ
COUT
CSL
CSH
COUT
INDUCTOR
L1
RNTC
R2
R1
POWER
GROUND
CIN1
KELVIN-SENSE VIAS TO
INDUCTOR PAD
INPUT
INDUCTOR DCR SENSING
SMPS
CONNECT AGND AND PGND1 TO
THE CONTROLLER AT THE
EXPOSED PAD
CONNECT THE
EXPOSED PAD TO
ANALOG GROUND
VDD BYPASS
CAPACITOR
VTTI BYPASS
CAPACITOR
VIA TO POWER GROUND
VCC BYPASS
CAPACITOR
VTT BYPASS
CAPACITOR
X-RAY VIEW.
IC MOUNTED
ON BOTTOM
SIDE OF PCB.
IC LAYOUT
Figure 9. PCB Layout Example
Package Information
Chip Information
PROCESS: BiCMOS
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 TQFN-EP
T2444+4
21-0139
90-0022
______________________________________________________________________________________
31
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Revision History
REVISION
NUMBER
REVISION
DATE
0
5/08
Initial release
—
1
2/11
Updated Package Information section.
31
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2011 Maxim Integrated Products
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