19-4590; Rev 1; 7/09 KIT ATION EVALU E L B AVAILA 1-Phase Quick-PWM GPU Controller Features o 1-Phase Quick-PWM Controller o ±6mV VOUT Accuracy Over Line, Load, and Temperature The MAX17409 is a 1-phase Quick-PWM™ step-down VID power-supply controller for high-performance graphics processors. The Quick-PWM control provides instantaneous response to fast-load current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX17409 is intended for two different notebook processor core applications: either bucking down the battery directly to create the core voltage, or bucking down the +5V system supply. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. The MAX17409 is available in a 28-pin, 4mm x 4mm TQFN package. o o o o o 6-Bit Graphics DAC (12.5mV LSB) Active Voltage Positioning with Adjustable Gain Accurate Droop and Current Limit Remote Output and Ground Sense Buffered 2V Reference Output for Offsets o o o o o Power-Good Window Comparator Temperature Comparator Drives Large Synchronous Rectifier FETs 2V to 26V Power Input Range Adjustable Switching Frequency (600kHz max) o Output Overvoltage and Undervoltage Protection o Soft-Startup and Soft-Shutdown o Internal Boost Diodes Ordering Information Applications PART Graphics Core (GPU) Power Supplies MAX17409GTI+ Voltage-Positioned Step-Down Converters TEMP RANGE PIN-PACKAGE -40°C to +105°C 28 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 2-to-4 Li+ Cells Battery to Processor Core Supply Converters Notebooks/Desktops/Servers BST VDD DL PGND G5 G4 TOP VIEW LX Pin Configuration 21 20 19 18 17 16 15 14 DH 22 G3 GND 23 13 G2 VRHOT 24 12 G1 11 G0 10 SHDN 9 PWRGD 8 TON MAX17409 REF 25 PAD GND ILIM 26 VCC 27 6 7 SKIP 5 THRM 4 CSP GNDS/OFSP 3 CSN 2 FB 1 IMON CCV 28 THIN QFN Quick-PWM is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX17409 General Description MAX17409 1-Phase Quick-PWM GPU Controller ABSOLUTE MAXIMUM RATINGS VCC, VDD to GND .....................................................-0.3V to +6V G0–G5 to GND .........................................................-0.3V to +6V CSP, CSN to GND ....................................................-0.3V to +6V ILIM, THRM, VRHOT, PWRGD to GND ....................-0.3V to +6V SKIP to GND.............................................................-0.3V to +6V CCV, FB, IMON, REF to GND .....................-0.3V to (VCC + 0.3V) SHDN to GND (Note 1)...........................................-0.3V to +30V TON to GND ...........................................................-0.3V to +30V GNDS/OFSP, PGND to GND (Note 2) ...................-0.3V to +0.3V Internal Driver (Note 2) DL to PGND .............................................-0.3V to (VDD + 0.3V) BST to GND .........................................................-0.3V to +36V Note 1: SHDN might be forced to 12V for the purpose of debugging ables fault protection. Note 2: Measurements valid using a 20MHz bandwidth limit. LX to BST...............................................................-6V to +0.3V BST to VDD ..........................................................-0.3V to +30V DH to LX .................................................-0.3V to (VBST + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin 4mm x 4mm TQFN (derate 21.3mW/°C above +70°C) ............................1702mW Operating Temperature Range .........................-40°C to +105°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10s) .................................+300°C prototype breadboards using the no-fault test mode, which dis- Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range VCC, VDD 4.5 5.5 V DC Output-Voltage Accuracy Measured at FB with respect to GNDS; includes load-regulation error (Note 4) -6 +6 mV Line Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V +200 mV 1.03 V/V +2 µA GNDS Input Range 0.1 -200 GNDS/OFSP Gain A GNDS GNDS/OFSP Input Bias Current I GNDS VOUT/VGNDS, -200mV VGNDS +200mV 0.97 1.00 -2 1.98 2.000 2.02 1.97 2.000 2.02 Dynamic VID Slew-Rate Accuracy 11.0 12.5 14.0 mV/µs Soft-Start/Soft-Shutdown Slew-Rate Accuracy 1.248 1.56 1.872 mV/µs RTON = 96.75k 142 167 192 RTON = 200k 300 333 366 RTON = 303.25k 425 REF Voltage On-Time (Note 5) Minimum Off-Time TON Shutdown Input Current 2 VREF t ON t OFF(MIN) VCC = 4.5V to 5.5V, IREF = 100µA IREF = 0 to 1mA % VIN = 12V, VFB = 1.2V V ns 500 575 Measured at DH (Note 5) 300 375 ns SHDN = GND, VIN = 26V, VCC = VDD = 0 or 5V 0.01 0.1 µA _______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, SKIP = 5V, FB forced above the regulation point 1.5 3 mA Quiescent Supply Current (VDD) IDD Measured at VDD, SKIP = 0V, FB forced above the regulation point, TA = +25°C 0.02 1 µA Shutdown Supply Current (VCC) Measured at VCC, SHDN = GND, TA = +25°C 0.01 1 µA Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND, TA = +25°C 0.01 1 µA mV FAULT PROTECTION Output Overvoltage Protection Threshold VOVP Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to unloaded output voltage 250 300 350 Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at FB 1.45 1.50 1.55 Minimum OVP threshold; measured at FB 0.8 10 Output Overvoltage Propagation Delay t OVP FB forced 25mV above trip threshold Output Undervoltage Protection Threshold VUVP Measured at FB with respect to unloaded output voltage Output Undervoltage Propagation Delay tUVP FB forced 25mV below trip threshold PWRGD Startup Delay Measured at startup from the time when SHDN goes high PWRGD Threshold Measured at FB with respect to unloaded output voltage, 15mV hysteresis (typ) Lower threshold, falling edge (undervoltage) PWRGD Output Low Voltage PWRGD Leakage Current High state, PWRGD forced to 5V tBLANK PWRGD Delay VCC Undervoltage-Lockout Threshold CSN Discharge Resistance in UVLO VUVLO(VCC) Rising edge, 50mV typical hysteresis, controller disabled below this level VCC = VDD = 4.0V -400 µs -350 10 mV µs 3 5 8 -350 -300 -250 ms mV Upper threshold, rising edge (overvoltage) Measured from the time when FB reaches the target voltage (Note 4) based on the slew rate FB forced 25mV outside the PWRGD trip thresholds I SINK = 3mA PWRGD Transition Blanking Time -450 V +150 4.05 +200 +250 20 µs 10 µs 4.25 8 0.4 V 1 µA 4.48 V _______________________________________________________________________________________ 3 MAX17409 ELECTRICAL CHARACTERISTICS (continued) MAX17409 1-Phase Quick-PWM GPU Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 29.2 30 30.8 % THERMAL COMPARATOR AND PROTECTION Measured at THRM with respect to VCC; falling edge; typical hysteresis = 100mV VRHOT Trip Threshold VRHOT Delay t VRHOT THRM forced 25mV below the VRHOT trip threshold; falling edge 10 VRHOT Output On-Resistance R VRHOT Low state 2 VRHOT Leakage Current I VRHOT High state, VRHOT forced to 5V, TA = +25°C THRM Input Leakage I THRM Thermal-Shutdown Threshold T SHDN VTHRM = 0 to 5V, TA = +25°C Typical hysteresis = 15°C -100 µs 8 1 µA +100 nA °C 160 VALLEY CURRENT LIMIT AND DROOP Current-Limit Threshold Voltage (Positive Adjustable) VLIMIT Current-Limit Threshold Voltage (Positive Default) Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) VCSP - VCSN VREF - VILIM = 100mV 7 10 13 VREF - VILIM = 500mV 45 50 55 20 22.5 25 mV +4 mV ILIM = VCC, VCSP - VCSN VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT VZERO -4 VPGND - VLX 1 CSP, CSN Common-Mode Input Range 0 mV mV 1.9 V CSP, CSN Input Current TA = +25°C -0.2 +0.2 µA ILIM Input Current TA = +25°C -100 +100 nA Droop Amplifier (GMD) Offset (VCSP - VCSN) at IFB = 0 -0.75 +0.75 mV Droop Amplifier (GMD) Transconductance IFB/(VCSP - VCSN); FB = CSN = 0.45V to 2.0V, and (VCSP - VCSN) = -15.0mV to +15.0mV 592 608 µS 600 GATE DRIVERS DH Gate-Driver On-Resistance R ON(DH) DL Gate-Driver On-Resistance R ON(DL) DH Gate-Driver Source Current DH Gate-Driver Sink Current DL Gate-Driver Source Current DL Gate-Driver Sink Current Internal BST Switch On-Resistance 4 BST - LX forced to 5V High state (pullup) 0.9 2.5 Low state (pulldown) 0.7 2.0 High state (pullup) 0.7 2.0 Low state (pulldown) 0.25 0.7 IDH(SOURCE) DH forced to 2.5V, BST - LX forced to 5V IDH(SINK) DH forced to 2.5V, BST - LX forced to 5V RBST A 2.7 A 2.7 A DL forced to 2.5V 8 A IBST = 10mA, VDD = 5V 10 IDL(SOURCE) DL forced to 2.5V IDL(SINK) 2.2 _______________________________________________________________________________________ 20 1-Phase Quick-PWM GPU Controller (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Gm(IMON) I IMON/(VCSP - VCSN), VCSN = 0.5V to 1.0V 4.9 5.0 51 mS I IMON = 0 -1.0 +1.0 mV I IMON = -1.0mA 1.05 1.15 V 2.3 CURRENT MONITOR Current-Monitor Transconductance Current-Monitor Offset Referred to V(CSP,CSN) IMON Clamp Voltage VIMON 1.10 LOGIC AND I/O Logic-Input High Voltage VIH SHDN, SKIP Logic-Input Low Voltage VIL SHDN, SKIP Low-Voltage Logic-Input High Voltage VIHLV G0–G5 Low-Voltage Logic-Input Low Voltage VILLV G0–G5 0.67 TA = +25°C, SHDN, SKIP, G0–G5 = 0 or 5V Logic-Input Current V 1.0 V V -1 0.33 V +1 µA ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = -40°C to +105°C, unless otherwise specified.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range VCC, VDD 4.5 5.5 V DC Output-Voltage Accuracy Measured at FB with respect to GNDS, includes load regulation error (Note 4) -10 +10 mV For positive offset and remote-sense errors -200 +200 mV VOUT/VGNDS, -200mV VGNDS +200mV 0.95 1.05 V/V VCC = 4.5V to 5.5V, IREF = 100µA IREF = 0 to 1mA 1.97 2.03 1.95 2.03 10 15 mV/µs 1.248 1.872 mV/µs RTON = 96.75k 142 192 RTON = 200k 300 366 RTON = 303.25k 425 575 GNDS Input Range GNDS/OFSP Gain A GNDS REF Voltage VREF Dynamic VID Slew-Rate Accuracy Soft-Start/Soft-Shutdown Slew-Rate Accuracy On-Time (Note 5) t ON Minimum Off-Time t OFF(MIN) VIN = 12V, VFB = 1.2V Measured at DH (Note 5) V ns 400 ns 3 mA BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, SKIP = 5V, FB forced above the regulation point _______________________________________________________________________________________ 5 MAX17409 ELECTRICAL CHARACTERISTICS (continued) MAX17409 1-Phase Quick-PWM GPU Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = -40°C to +105°C, unless otherwise specified.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FAULT PROTECTION Output Overvoltage-Protection Threshold Output Undervoltage-Protection Threshold VOVP VUVP Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to unloaded output voltage 250 350 mV Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage, measured at FB 1.45 1.55 V Measured at FB with respect to unloaded output voltage -450 -350 mV 3 8 ms Lower threshold, falling edge (undervoltage) -350 -250 mV Upper threshold, rising edge (overvoltage) +150 +250 mV 0.4 V 4.0 4.5 V 29.2 30.8 % 8 PWRGD Startup Delay Measured at startup from the time when SHDN goes high PWRGD Threshold Measured at FB with respect to unloaded output voltage; 15mV hysteresis (typ) PWRGD Output Low Voltage VCC Undervoltage-Lockout Threshold I SINK = 3mA Rising edge, 50mV typical hysteresis, VUVLO(VCC) controller disabled below this level THERMAL COMPARATOR AND PROTECTION Measured at THRM with respect to VCC; falling edge; typical hysteresis = 100mV VRHOT Trip Threshold VRHOT Output On-Resistance RVRHOT Low state VALLEY CURRENT LIMIT AND DROOP Current-Limit Threshold Voltage (Positive Adjustable) Current-Limit Threshold Voltage (Positive Default) Current-Limit Threshold Voltage (Negative) Accuracy VLIMIT VCSP - VCSN VREF - VILIM = 100mV 7 13 VREF - VILIM = 500mV 45 55 20 25 mV -5 +5 mV 0 1.9 V ILIM = VCC, VCSP - VCSN VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT CSP, CSN Common-Mode Input Range mV Droop Amplifier GMD) Offset (VCSP - VCSN) at IFB = 0 -1.0 +1.0 mV Droop Amplifier (GMD) Transconductance IFB/(VCSP - VCSN); FB = CSN = 0.45V to 2.0V, and (VCSP - VCSN) = -15.0mV to +15.0mV 588 612 µS 6 _______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller (Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V; G5–G0 set for 1.05V (G0–G5 = 100110); TA = -40°C to +105°C, unless otherwise specified.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GATE DRIVERS DH Gate-Driver On-Resistance R ON(DH) DL Gate-Driver On-Resistance R ON(DL) Internal BST Switch On-Resistance RBST BST - LX forced to 5V High state (pullup) 2.5 Low state (pulldown) 2.0 High state (pullup) 2.0 Low state (pulldown) 0.7 IBST = 10mA, VDD = 5V 20 CURRENT MONITOR Current-Monitor Transconductance Gm(IMON) Current-Monitor Offset Referred to V(CSP,CSN) IMON Clamp Voltage VIMON I IMON/(VCSP - VCSN) VCSN = 0.5V to 1.0V 4.9 5.1 mS I IMON = 0 -1.0 +1.0 mV I IMON = -1.0mA 1.05 1.15 V 2.3 1.0 V LOGIC AND I/O Logic-Input High Voltage VIH SHDN, SKIP Logic-Input Low Voltage VIL SHDN, SKIP Low-Voltage Logic-Input High Voltage VIHLV G0–G5 Low-Voltage Logic-Input Low Voltage VILLV G0–G5 V 0.67 V 0.33 V Note 3: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design and characterization. Note 4: The equation for the target voltage VTARGET is: VTARGET = the slew-rate-controlled version of VDAC, where VDAC = 0 for shutdown, VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 4). In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 5: On-time and minimum off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times might be different due to MOSFET switching speeds. _______________________________________________________________________________________ 7 MAX17409 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, G0–G5 set for 1.05V (G0–G5 = 100110), TA = +25°C, unless otherwise specified.) 0.9V OUTPUT VOLTAGE vs. LOAD CURRENT 0.9V OUTPUT EFFICIENCY vs. LOAD CURRENT OUTPUT VOLTAGE (V) EFFICIENCY (%) 12V 80 20V 70 60 MAX17409 toc02 7V 90 0.92 MAX17409 toc01 100 SKIP MODE 0.91 0.90 PWM MODE 0.89 50 SKIP MODE PWM MODE 40 0.88 0.1 1 100 10 6 8 10 12 200 150 100 50 100 MAX17409 toc04 MAX17409 toc03 250 16 14 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE 300 IIN 10 ICC + IDD ICC + IDD 1 0.1 IIN SKIP MODE PWM MODE SKIP MODE PWM MODE 0 0.01 1 100 10 5 6 7 8 9 10 11 12 13 LOAD CURRENT (A) INPUT VOLTAGE (V) 0.8125V OUTPUT VOLTAGE DISTRIBUTION Gm(FB) TRANSCONDUCTANCE DISTRIBUTION SAMPLE SIZE = 100 +85°C +25°C 70 60 50 40 30 20 50 45 SAMPLE PERCENTAGE (%) 90 14 SAMPLE SIZE = 100 +85°C +25°C 40 35 30 25 20 15 OUTPUT VOLTAGE (V) 610 608 606 604 602 600 598 596 594 592 0.8175 0.8165 0.8155 0.8145 0.8135 0.8125 0.8115 0.8105 0.8095 0.8085 0 0.8075 5 0 590 10 10 TRANSCONDUCTANCE (µS) _______________________________________________________________________________________ MAX17409 toc06 0.1 MAX17409 toc05 0.01 8 4 SWITCHING FREQUENCY vs. LOAD CURRENT VIN = 12V 80 2 LOAD CURRENT (A) 350 SWITCHING FREQUENCY (kHz) 0 LOAD CURRENT (A) SWITCHING FREQUENCY (kHz) 0.01 SAMPLE PERCENTAGE (%) MAX17409 1-Phase Quick-PWM GPU Controller 1-Phase Quick-PWM GPU Controller Gm(IMON) TRANSCONDUCTANCE DISTRIBUTION SOFT-START WAVEFORM 80 MAX17409 toc07 SAMPLE SIZE = 100 +85°C +25°C 5V 0 60 A 0.95V A 0 B 0 B 0.95V 50 C C 40 0 0 30 D D 0 0 20 10 E 5.10 5.08 5.06 5.04 5.02 5.00 4.98 4.96 4.94 0 4.92 0 MAX17409 toc09 5V 0 70 4.90 SAMPLE PERCENTAGE (%) 90 SOFT-SHUTDOWN WAVEFORM MAX17409 toc08 100 E 0 1ms/div A. SHDN, 5V/div B. ILX, 10A/div C. VOUT, 500mV/div TRANSCONDUCTANCE (mS) 100µs/div D. PWRGD, 5V/div E. DL, 5V/div IOUT = 0A, SKIP MODE LOAD-TRANSIENT RESPONSE (PWM MODE) A. SHDN, 5V/div B. ILX, 10A/div C. VOUT, 500mV/div D. PWRGD, 5V/div E. DL, 5V/div IOUT = 0A, SKIP MODE LOAD-TRANSIENT RESPONSE (SKIP MODE) MAX17409 toc10 MAX17409 toc11 0.95V A 0.95V A 1A B 1A B C 0 C 0 20µs/div A. VOUT, 50mV/div B. ILX, 20A/div 20µs/div C. LX, 10V/div IOUT = 1A - 11A A. VOUT, 50mV/div B. ILX, 20A/div C. LX, 10V/div IOUT = 1A - 11A _______________________________________________________________________________________ 9 MAX17409 Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, G0–G5 set for 1.05V (G0–G5 = 100110), TA = +25°C, unless otherwise specified.) 1-Phase Quick-PWM GPU Controller MAX17409 Pin Description PIN NAME FUNCTION Current Monitor Output. The MAX17409 IMON output sources a current that is directly proportional to the current-sense voltage as defined by: I IMON = Gm(IMON) x (VCSP - VCSN) where Gm(IMON) = 5mS (typ). The IMON current is unidirectional (sources current out of IMON only) for positive current-sense values. For negative current-sense voltages, the IMON current is zero. 1 IMON Connect an external resistor between IMON and GNDS to create the desired IMON gain based on the following equation: RIMON = 1.0V/(ILOAD(MAX) x R SENSE x Gm(IMON)) where ILOAD(MAX) is the maximum load current, and RSENSE is the current-sense voltage. The IMON voltage is internally clamped to 1.1V. The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot drive large external capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 1. 2 GNDS/OFSP Remote Ground-Sense Input/Positive Offset Input. Connect directly to the ground-sense pin or ground connection of the load. GNDS internally connects to a transconductance amplifier that adjusts the feedback voltage—compensating for voltage drops between the regulator’s ground and the processor’s ground. Remote-Sense Feedback Input and Voltage-Positioning Transconductance Amplifier Output. Connect resistor RFB between FB and the output remote-sense pin (or Kelvin-sensed to the supply pin of the load) for best accuracy and to set the steady-state droop based on the voltagepositioning gain requirement: RFB = RDROOP/(RSENSE x GMD) 3 FB where RDROOP_DC is the desired voltage-positioning slope, GMD = 600µS (typ), and RSENSE is the current-sense resistance with respect to CSP to CSN current-sense inputs. See the Current Sense section for details on designing with sense resistors or inductor DCR sensing. Shorting FB directly to the output effectively disables voltage positioning, but impacts the stability requirements. Designs that disable voltage positioning require a higher minimum output capacitance ESR to maintain stability (see the Output Capacitor Selection section). FB enters a high-impedance state in shutdown. 4 CSN 5 CSP 6 SKIP Negative Inductor Current-Sense Input. Connect CSN to the negative terminal of the inductor current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing method is used (see Figure 3). Positive Inductor Current-Sense Input. Connect CSP to the positive terminal of the inductor currentsensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless DCR sensing method is used (see Figure 3). Pulse-Skipping Control Input. The SKIP signal indicates the power usage and sets the operating mode of the MAX17409. When the system forces SKIP high, the MAX17409 immediately enters automatic pulse-skipping mode. The controller returns to continuous forced-PWM mode when SKIP is pulled low and the output is in regulation. SKIP determines the operating mode and outputvoltage transition slew rate as shown in the truth table below: SKIP 0 1 Functionality Normal slew rate, forced-PWM mode Normal slew rate, skip mode The SKIP state is ignored during soft-start and shutdown. The MAX17409 always uses pulseskipping mode during startup to ensure a monotonic power-up. During shutdown, the controller always uses forced-PWM mode so the output can be actively discharged. 10 ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller PIN 7 NAME THRM FUNCTION Comparator Input for Thermal Protection. THRM connects to the positive input of an internal comparator. The comparator’s negative input connects to an internal resistive voltage-divider that accurately sets the THRM threshold to 30% of the VCC voltage. Connect the output of a resistordivider and thermistor-divider (between VCC and GND) to THRM with the values selected so the voltage at THRM falls below 30% of VCC (1.5V when VCC = 5V) at the desired high temperature. Switching Frequency-Setting Input. An external resistor (RTON) between the input power source and TON sets the switching frequency (f SW = 1/t SW) according to the following equation used to determine the nominal switching period: 8 TON t SW = 16.3pF x (RTON + 6.5k) TON enters a high impedance in shutdown to reduce the input quiescent current. If the TON current is less than 10µA, the MAX17409 disables the controller, sets the TON OPEN fault latch, and pulls DH and DL low. Open-Drain Power-Good Output. The MAX17409 forces PWRGD low when SHDN is pulled low. After the controller is properly powered up, PWRGD becomes a high-impedance output as long as the feedback voltage is in regulation and the startup blanking time has expired. 9 PWRGD PWRGD becomes active 5ms after the MAX17409 reaches the VID target. The MAX17409 pulls PWRGD low when shutdown (SHDN = GND) is pulled low, during startup, and during shutdown transitions. The PWRGD upper threshold is blanked during any downward output-voltage transition that occurs when the MAX17409 is in skip mode (SKIP = VCC). PWRGD remains blanked until the transitionrelated PWRGD blanking period expires and the controller detects the output is in regulation (erroramplifier edge occurs). Note: The pullup resistance on PWRGD causes additional shutdown current. 10 SHDN 11–16 G0–G5 17 PGND Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the controller into the low-power 1µA (max) shutdown state. During startup, the controller ramps up the output voltage with a 1.56mV/µs slew rate to the selected target voltage. During the shutdown transition, the MAX17409 softly ramps down the output voltage with a 1.56mV/µs slew rate. Forcing SHDN to 11V ~ 13V disables overvoltage protection, undervoltage protection, and thermal shutdown, and clears the fault latches. Low-Voltage (1.0V Logic) VID DAC Code Inputs. The G0–G5 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the µP. The output voltage is set by the DAC code indicated by the logic-level voltages on G0–G5. Power Ground. Ground connection for the DL driver. 18 DL Low-Side Gate-Driver Output. DL swings from VDD to PGND. DL is forced low in shutdown. DL is also forced low when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL is forced low in skip mode after detecting an inductor current zero crossing. 19 VDD Driver-Supply Voltage Input. VDD supplies power to the low-side gate driver (DL) and to the internal BST switch used to refresh the BST capacitor. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to PGND with a 1µF or greater ceramic capacitor. 20 BST Boost Flying Capacitor Connection. BST provides the upper supply rail for the DH high-side gate driver. An internal switch between VDD and BST charges the flying capacitor while the low-side MOSFET is on (DL pulled high and LX pulled to ground). 21 LX Inductor Connection. LX serves as the lower supply rail for the DH high-side gate driver. The MAX17409 also uses LX as the input to the zero-crossing comparator. ______________________________________________________________________________________ 11 MAX17409 Pin Description (continued) 1-Phase Quick-PWM GPU Controller MAX17409 Pin Description (continued) 12 PIN NAME 22 DH FUNCTION 23 GND 24 VRHOT 25 REF Buffered 2V Reference Output. Bypass REF with a 100pF to 1000pF capacitor. Do not exceed 1000pF. 26 ILIM Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP to CSN equals precisely 1/10 of the differential REF to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). The negative current-limit threshold is nominally -125% of the corresponding valley current-limit threshold. Connect ILIM directly to VCC to set the default 22.5mV current-limit threshold setting. 27 VCC Analog Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1µF minimum capacitor. 28 CCV Integrator Capacitor Connection. Connect a capacitor (CCCV) from CCV to GND to set the integration time constant. Choose the capacitor value according to: 16 x [CCCV/Gm(CCV)] x f SW >> 1 where Gm(CCV) = 320S (max) is the integrator’s transconductance and fSW is the switching frequency set by the RTON resistance. The integrator is internally disabled during any downward output-voltage transition that occurs in pulse-skipping mode, and remains disabled until the transition blanking period expires and the output reaches regulation (error-amplifier transition detected). — EP Exposed Pad (Backside). Internally connected to the substrate. Connect to the ground plane through a thermally enhanced via. High-Side Gate-Driver Output. DH swings from LX to BST. The controller pulls DH low in shutdown. Analog Ground. Internally connected to GND. Thermal Comparator’s Open-Drain Output. The comparator pulls VRHOT low when the voltage at THRM drops below 30% of VCC (1.5V with 5V VCC). VRHOT is high impedance in shutdown. ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller 6 11 12 13 14 VID INPUTS 15 16 SHDN R3 R2 VDD G0 G1 G2 G3 G4 G5 TON DH LX ILIM REF PGND CSP 24 R6 7.87kΩ 7 VCC NLO THRM FB GNDS/OFSP C5 OPEN AGND 4 C6 OPEN AGND DCR THERMAL COMPENSATION LOAD LINE ADJUSTMENT: RFB = RDROOP/(RSENSE x 600µS) RFB 3 2 CCV AGND GND (EP) C8 1000pF AGND R13 10Ω C9 1000pF AGND R14 10Ω REMOTE-SENSE FILTERS CCCV 100pF RIMON PWR NTC1 C7 VREF IMON COUT PWR 5 R20 OPEN 1 CORE OUTPUT R10 R11 PWRGD VRHOT D1 17 AGND C4 0.1µF AGND L1 18 NTC2 100kΩ B = 4700 R8 10kΩ NHI 21 C3 9 PWR CBST 0.1µF R5 10kΩ R4 10kΩ INPUT 7V TO 24V CIN 22 CREF CSN PWR RBST 0Ω 100pF 3.3V C2 1.0µF RTON 8 MAX17409 BST 20 VREF AGND 19 SWITCHING FREQUENCY (fSW = 1/tSW): tSW = 16.3pF x (RTON + 6.5kΩ) DL 25 5V BIAS INPUT C1 1.0µF AGND SKIP VALLEY CURRENT LIMIT SET BY THE TIME TO ILIM VLIMIT = 0.2V x R2/(R2 + R3) SLEW RATE SET BY TIME BIAS CURRENT dV/dt = 12.5mV/µs x 71.5kΩ/(R2 + R3) 26 VCC R1 10Ω 27 MAX17409 ON OFF (VRON) 10 R15 10Ω OUTPUT SENSE GROUND SENSE R16 10Ω PWR CATCH RESISTORS REQUIRED WHEN CPU NOT POPULATED 28 23 AGND RGND 0Ω AGND PWR Figure 1. MAX17409 Application Circuit ______________________________________________________________________________________ 13 MAX17409 1-Phase Quick-PWM GPU Controller CSP IMON CSN ILIM MINIMUM OFF-TIME Q REF TRIG ONE-SHOT VCC ON-TIME ONE SHOT TON FB REF (2.0V) Q SLEW CONTROL GND G0–G5 TRIG BST R DAC Q DH S SHDN LX TARGET S Q PGND LX 1mV R VDD SKIP FAULT REF DL CCV PGND Gm(CCV) TARGET +200mV 7R BLANK R 5ms STARTUP DELAY TARGET -300mV FB SKIP PWRGD TARGET +300mV CSP FAULT Gm(FB) CSN THRM TARGET -400mV GNDS VRHOT Gm(GNDS) MAX17409 0.3 x VCC Figure 2. Functional Diagram 14 ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller MAX17409 Table 1. Component Selection for Standard Applications DESIGN PARAMETERS 14A DESIGN 9A DESIGN 5A DESIGN Input Voltage Range 8V to 20V 8V to 20V 8V to 20V Maximum Load Current 14A 9A 5A Transient Load Current 10A 7A 4A TON Resistance (RTON) 200k (fSW = 300kHz) 170k (fSW = 350kHz) 150k (fSW = 390kHz) Inductance (L1) 0.6µH, 17A, 2.3m NEC-TOKIN MPC0750LR60C 0.75µH, 10.7A, 6.2m TOKO FDVE0630-R75M 1.50µH, 8A, 12.1m TOKO FDVE0630-1R5M High-Side MOSFET (NHI) 9.4m/12.0m (typ/max) Fairchild FDS6298 11m/13.75m (typ/max) Vishay Si7392DP 14.5m/20.5m (typ/max) International Rectifier IRF7904 Low-Side MOSFET (NLO) 4.2m/5.0m (typ/max) Fairchild FDS8670 5m/6.5m (typ/max) International Rectifier IRF7822 10m/13m (typ/max) International Rectifier IRF7904 Output Capacitors (COUT) 1x 470µF, 6m, 2V SANYO 2TPE470M6 1x 330µF, 6m, 2V SANYO 2TPE330M6 1x 220µF, 6m, 2V SANYO 2TPE220M6 Input Capacitors (CIN) 2x 10µF, 25V ceramic (1210) 1x 10µF, 25V ceramic (1210) 1x 10µF, 25V ceramic (1210) REF/ILIM Resistance (R2) 10k 17.8k 20k ILIM/GND Resistance (R3) 63.4k 60.4k 54.9k FB Resistance (RFB) 100 100 100 Feedforward Capacitance (C3) 0.22µF 0.15µF 0.1µF LX/CSP Resistance (R10) 1.3k 1.3k 1.3k CSP/CSN Series Resistance (R11 + NTC1) 2k + 10k NTC (B = 3380) 2k + 10k NTC (B = 3380) 2k + 10 NTC (B = 3380) DCR Sense Capacitance (C7) 0.22µF, 6V ceramic (0603) 0.1µF, 6V ceramic (0603) 0.1µF, 6V ceramic (0603) IMON Resistance (RIMON) 6.81k 3.92k 3.24k COMPONENTS Table 2. Component Suppliers MANUFACTURER AVX Corporation WEBSITE MANUFACTURER WEBSITE www.avxcorp.com Taiyo Yuden www.t-yuden.com Fairchild Semiconductor www.fairchildsemi.com TDK Corp. www.component.tdk.com NEC-TOKIN America, Inc. www.nec-tokinamerica.com TOKO America, Inc. www.tokoam.com Panasonic Corp. www.panasonic.com SANYO Electric Co., Ltd. www.sanyodevice.com Toshiba America Electronic Components, Inc. www.toshiba.com/taec Vishay www.vishay.com ______________________________________________________________________________________ 15 MAX17409 1-Phase Quick-PWM GPU Controller Detailed Description Free-Running, Constant On-Time PWM Controller with Input Feed-Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to output voltage (see the On-Time One-Shot section). Another oneshot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current is below the valley current-limit threshold, and the minimum off-time one-shot times out. +5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook’s 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator. The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: ( IBIAS = I CC + fSW Q G(LOW) + Q G(HIGH) ) where ICC is provided in the Electrical Characteristics table, fSW is the switching frequency, and QG(LOW) and Q G(HIGH) are the MOSFET data sheet’s total gatecharge specification limits at VGS = 5V. VIN and VDD can be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Switching Frequency (TON) Connect a resistor (RTON) between TON and VIN to set the switching period (tSW = 1/fSW): tSW = 16.3pF x (RTON + 6.5kΩ) A 96.75kΩ to 303.25kΩ corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively. 16 High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. On-Time One-Shot The core contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFET’s on-time. The one-shot varies the on-time in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the RTON input, and proportional to the feedback voltage (VFB): t ( V + 0.075V ) t ON(MAIN) = SW FB VIN where the switching period (tSW = 1/fSW) is set by the resistor at the TON pin and 0.075V is an approximation to accommodate the expected drop across the lowside MOSFET switch. This algorithm results in a nearly constant switching frequency and balanced inductor currents despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output-voltage ripple. The on-time oneshots have good accuracy at the operating points specified in the Electrical Characteristics table. Ontimes at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PCB copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forced-PWM operation and dynamic output-voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller fSW = ( VOUT + VDROP1) t ON ( VIN + VDROP1 - VDROP2 ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VDROP2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time as determined above. Current Sense The output current is differentially sensed by the highimpedance current-sense inputs (CSP and CSN). Lowoffset amplifiers are used for voltage-positioning gain, current-limit protection, and power monitoring. Sensing the current at the output offers advantages, including less noise sensitivity and the flexibility to use either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor’s DCR must be accounted for in the output-voltage drooperror budget and power monitor. This current-sense method uses an RC filtering network to extract the current information from the inductor (see Figure 3). The resistive divider used should provide a current-sense resistance (RCS) low enough to meet the current-limit requirements, and the time constant of the RC network should match the inductor’s time constant (L/RCS): ⎛ R2 ⎞ R CS = ⎜ R ⎝ R1 + R2 ⎟⎠ DCR and: R CS = L ⎡1 1 ⎤ + C EQ ⎢⎣ R1 R2 ⎥⎦ where RCS is the required current-sense resistance, and RDCR is the inductor’s series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. To minimize the current-sense error due to the currentsense inputs’ bias current (I CSP and I CSN), choose R1//R2 to be less than 2kΩ and use the above equation to determine the sense capacitance (CEQ). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage Positioning and Loop Compensation section. When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (LESL) of the current-sense resistor (see Figure 3). The ESL-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. Similar to the inductor DCR sensing method above, the RC filter’s time constant should match the L/R time constant formed by the current-sense resistor’s parasitic inductance: L ESL = C EQR1 R SENSE where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is the current-sense resistance value, CEQ and R1 are the time-constant matching components. Current Limit The current-limit circuit employs a “valley” currentsensing algorithm that uses current-sense inputs (CSP to CSN) as the current-sensing elements. If the currentsense signal exceeds the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current drops below the valley current-limit threshold. Since only the valley current level is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. The positive current-limit threshold is fixed internally at 22.5mV (typ). There is also a negative current limit that prevents excessive reverse inductor currents when V OUT is sinking current. The negative current-limit threshold is 130% of the nominal valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately activates an on-time pulse—DL turns off and DH turns on— allowing the inductor current to remain above the negative current threshold. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP, CSN). ______________________________________________________________________________________ 17 MAX17409 on-time by a period equal to the DH rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: MAX17409 1-Phase Quick-PWM GPU Controller INPUT (VIN) DH NH CIN SENSE RESISTOR L LESL RSENSE R1 CEQ L CEQR1 = SENSE RSENSE LX MAX17409 DL NL DL COUT PGND CSP CSN A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) DH NH CIN INDUCTOR L RDCR RCS = LX MAX17409 DL NL DL R1 PGND R2 CEQ R2 RDCR R1 + R2 COUT L RDCR = C EQ [ R11 + R21 ] CSP CSN B) LOSSLESS INDUCTOR SENSING FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR. Figure 3. Current-Sense Methods Feedback Adjustment Amplifiers Voltage-Positioning Amplifier (Steady-State DC Droop) The MAX17409 includes a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier’s input is generated by the differential current-sense inputs, which sense the inductor current by measuring the voltage across either current-sense resistors or the inductor’s DCR. The amplifier’s output connects directly to the regulator’s voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltagepositioning gain: VOUT = VTARGET - R FBIFB where the target voltage (VTARGET) is defined in the Nominal Output-Voltage Selection section, and the FB amplifier’s output current (IFB) is determined by the current-sense voltages: IFB = Gm(FB) x (VCSP - VCSN) 18 where VCSP - VCSN is the differential current-sense voltage, and Gm(FB) is typically 600µS, as defined in the Electrical Characteristics table. Differential Remote Sense The MAX17409 includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor’s power pins. The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (R FB ) and ground-sense (GNDS) input directly to the processor’s remote-sense outputs as shown in Figure 1. Integrator Amplifier An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller where Gm(CCV) is the integrator’s maximum transconductance (320µs) and fSW is the switching frequency set by the TON resistance. The MAX17409 disables the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode (SKIP = high). The integrator remains disabled until 20µs after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). Nominal Output-Voltage Selection The nominal no-load output voltage (V TARGET ) is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VFB = VDAC + VGNDS where VDAC is the selected VID voltage. On startup, the MAX17409 slews the target voltage from ground to the selected VID voltage. DAC Inputs (G0–G5) The digital-to-analog converter (DAC) programs the output voltage using the G0–G5 inputs. G0–G5 are lowvoltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave G0–G5 unconnected. Changing G0–G5 initiates a transition to a new outputvoltage level. Change G0–G5 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect DAC readings could cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time (Table 4). Table 3. MAX17409 Operating Mode Truth Table SHDN SKIP OPERATING MODE GND X DISABLED Rising X Pulse-Skipping 1.56mV/µs Slew Rate Startup. When SHDN is pulled high, the MAX17409 begins the startup sequence. The controller enables the PWM controller and ramps the output voltage up to the selected VID voltage. High Low Forced-PWM 12.5mV/µs Slew Rate Full Power. The no-load output voltage is determined by the selected VID DAC code (G0–G5, Table 4). High Pulse-Skipping 12.5mV/µs Slew Rate Suspend Mode. The no-load output voltage is determined by the selected VID DAC code (G0–G5, Table 4). When SKIP is pulled high, the MAX17409 immediately enters pulse-skipping operation, allowing automatic PWM/PFM switchover under light loads. The PWRGD upper threshold is blanked during the transition. Falling X Forced-PWM 1.56mV/µs Slew Rate Shutdown. When SHDN is pulled low, the MAX17409 immediately pulls PWRGD low, and the output voltage is ramped down to ground. Once the output reaches 0V, the controller enters the low-power shutdown state. High X DISABLED Fault Mode. The fault latch has been set by the MAX17409 UVP or thermal-shutdown protection, or by the OVP protection. The controller remains in fault mode until VCC power is cycled or SHDN toggled. High DESCRIPTION Low-Power Shutdown Mode. DL forced low, and the controller is disabled. The supply current drops to 10µA (max). ______________________________________________________________________________________ 19 MAX17409 (Figure 2), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The integrator amplifier has the ability to shift the output voltage by ±80mV (typ). The differential input voltage range is at least ±60mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor between CCV and analog ground, with the minimum recommended CCV capacitor value determined by: G m(CCV) C CCV >> 16π × fSW MAX17409 1-Phase Quick-PWM GPU Controller Table 4. Output Voltage VID DAC Codes G5 G4 G3 G2 G1 G0 OUTPUT VOLTAGE (V) G5 G4 G3 G2 G1 G0 OUTPUT VOLTAGE (V) 1 0 0 0 0 0 1.1250 0 0 0 0 0 0 0.7250 1 0 0 0 0 1 1.1125 0 0 0 0 0 1 0.7125 1 0 0 0 1 0 1.1000 0 0 0 0 1 0 0.7000 1 0 0 0 1 1 1.0875 0 0 0 0 1 1 0.6875 1 0 0 1 0 0 1.0750 0 0 0 1 0 0 0.6750 1 0 0 1 0 1 1.0675 0 0 0 1 0 1 0.6625 1 0 0 1 1 0 1.0500 0 0 0 1 1 0 0.6500 1 0 0 1 1 1 1.0375 0 0 0 1 1 1 0.6275 1 0 1 0 0 0 1.0250 0 0 1 0 0 0 0.6250 1 0 1 0 0 1 1.0125 0 0 1 0 0 1 0.6125 1 0 1 0 1 0 1.0000 0 0 1 0 1 0 0.6000 1 0 1 0 1 1 0.9875 0 0 1 0 1 1 0.5875 1 0 1 1 0 0 0.9750 0 0 1 1 0 0 0.5750 1 0 1 1 0 1 0.9625 0 0 1 1 0 1 0.5625 1 0 1 1 1 0 0.9500 0 0 1 1 1 0 0.5500 1 0 1 1 1 1 0.9275 0 0 1 1 1 1 0.5275 1 1 0 0 0 0 0.9250 0 1 0 0 0 0 0.5250 1 1 0 0 0 1 0.9125 0 1 0 0 0 1 0.5125 1 1 0 0 1 0 0.9000 0 1 0 0 1 0 0.5000 1 1 0 0 1 1 0.8875 0 1 0 0 1 1 0.4875 1 1 0 1 0 0 0.8750 0 1 0 1 0 0 0.4750 1 1 0 1 0 1 0.8625 0 1 0 1 0 1 0.4625 1 1 0 1 1 0 0.8500 0 1 0 1 1 0 0.4500 1 1 0 1 1 1 0.8375 0 1 0 1 1 1 0.4275 1 1 1 0 0 0 0.8250 0 1 1 0 0 0 0.4250 1 1 1 0 0 1 0.8125 0 1 1 0 0 1 0.4125 1 1 1 0 1 0 0.8000 0 1 1 0 1 0 0.4000 1 1 1 0 1 1 0.7875 0 1 1 0 1 1 0.3875 1 1 1 1 0 0 0.7750 0 1 1 1 0 0 0.3750 1 1 1 1 0 1 0.7625 0 1 1 1 0 1 0.3625 1 1 1 1 1 0 0.7500 0 1 1 1 1 0 0.3500 1 1 1 1 1 1 0.7375 0 1 1 1 1 1 0.3375 20 ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller OVP LEVEL The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (tTRAN) is given by: t TRAN = VNEW - VOLD 12.5mVµs where VOLD is the original output voltage, and VNEW is the new target voltage. See Slew-Rate Accuracy in the Electrical Characteristics for slew-rate limits. For softstart and shutdown, the controller automatically reduces the slew rate to 1.56mV/µs (1/8 of the nominal slew rate). The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current required to make an output voltage transition is: IL ≅ C OUT × 12.5mVµs where COUT is the total output capacitance. OVP = 1.45V MIN OVP TRACKS INTERNAL TARGET HIGH VID NEW ACTIVE VID LOW VID ACTUAL VOUT CPU CORE VOLTAGE INTERNAL TARGET VID (G0–G5) SLEEP VID SKIP INTERNAL PWM CONTROL PULSE-SKIPPING MODE FORCED-PWM MODE NO PULSES: VOUT > VTARGET DH PWRGD LOW THRESHOLD ONLY BLANK HIGH-Z tBLANK 20µs TYP BLANK HIGH-Z tBLANK 20µs TYP Figure 4. VID Transition ______________________________________________________________________________________ 21 MAX17409 Output-Voltage Transition Timing The MAX17409 performs mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output-voltage transition, the MAX17409 blanks both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the PWRGD thresholds approximately 20µs after the slewrate controller reaches the target output voltage. The slew rate is set to 12.5mV/µs to ensure that the transition can be completed within a reasonable time period. The MAX17409 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal capacitor and current source to transition the target voltage. The total transition time depends on the 12.5mV/µs slew rate, the voltage difference, and the accuracy of the slew-rate controller, CSLEW, accuracy). Forced-PWM Operation (Normal Mode) During soft-shutdown and normal operation—when the CPU is actively running (SKIP = low, Table 3) — the MAX17409 operates with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gatedrive waveforms to constantly be the complement of the high-side gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative-output-voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the processor might switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. The MAX17409 automatically uses pulse-skipping operation during soft-start, regardless of the SKIP configuration. Light-Load Pulse-Skipping Operation During soft-start and sleep states—SKIP is pulled high—the MAX17409 operates in pulse-skipping mode. The pulse-skipping mode enables the driver’s zerocrossing comparator, so the controller pulls DL low when its current-sense inputs detect “zero” inductor current. This keeps the inductor from sinking current and discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. Upon entering pulse-skipping operation, the controller temporarily blanks the upper PWRGD thresholds, and sets the OVP threshold to 1.80V to prevent false OVP faults when the transition to pulse-skipping operation coincides with a VID DAC code. The MAX17409 automatically uses forced-PWM operation during soft-shutdown, regardless of the SKIP configuration. Automatic Pulse-Skipping Switchover In skip mode (SKIP = high), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs. 22 Once VLX drops below the zero-crossing comparator threshold (see the Electrical Characteristics table), the comparator forces DL low (Figure 2). This mechanism causes the threshold between pulse-skipping PFM and nonskipping-PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 5). For a 7V to 20V battery input range, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately: ILOAD(SKIP) = 1 ⎛ t SW VOUT ⎞ ⎛ VIN - VOUT ⎞ ⎟⎠ ⎜ ⎟⎠ L VIN 2 ⎜⎝ ⎝ The switching waveforms might appear noisy and asynchronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs between PFM noise and light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels. ∆I = ∆t VBATT - VOUT L INDUCTOR CURRENT MAX17409 1-Phase Quick-PWM GPU Controller IPEAK ILOAD = IPEAK/2 0 ON-TIME TIME Figure 5. Pulse-Skipping/Discontinuous Crossover Point ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller t TRAN(START) = VBOOT (1.56mV / µs) where VBOOT is the initial VID target. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. PWRGD becomes high impedance approximately 5ms after the target output voltage is reached. The MAX17409 automatically uses pulse-skipping mode during soft-start and uses forced-PWM mode during soft-shutdown, regardless of the SKIP configuration. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output (DL and DH pulled low). VCC SHDN G0–G5 INVALID VID OVP LEVEL INVALID VID CODE OVP = 1.45V MIN OVP TRACKS INTERNAL TARGET OVP = 1.45V MIN SOFT-START = 1.56mV/µs SLEW RATE SOFT-SHUTDOWN = 1.56mV/µs SLEW RATE INITIAL TARGET VCORE INTERNAL PWM CONTROL PULSE SKIPPING PWRGD tBLANK 60µs TYP FORCED-PWM tBLANK 5ms TYP tBLANK 20µs TYP tBLANK 20µs TYP Figure 6. Power-Up and Shutdown Sequence Timing Diagram ______________________________________________________________________________________ 23 MAX17409 Power-Up Sequence (POR, UVLO) The MAX17409 is enabled when SHDN is driven high (Figure 6). The reference powers up first. Once the reference exceeds its UVLO threshold, the internal analog blocks are turned on and masked by a 150µs one-shot delay. The PWM controller then begins switching. Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC is above 4.25V, and SHDN is driven high. With the reference in regulation, the controller ramps the output voltage to the selected VID voltage with a 1.56mV/µs slew rate: MAX17409 1-Phase Quick-PWM GPU Controller Shutdown When SHDN goes low, the MAX17409 enters low-power shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down with a 1.56mV/µs slew rate: t TRAN(SHDN) = VOUT (1.56mV / µs) Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX17409 shuts down completely— the drivers are disabled (DL driven high, DH pulled low)—the reference turns off, and the supply currents drop to approximately 1µA (max). When a fault condition—output UVLO or thermal shutdown—activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V typ. Temperature Comparator (VRHOT) The MAX17409 also features an independent comparator with an accurate threshold (VHOT) that tracks the analog supply voltage (VHOT = 0.3VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistor-divider between VCC and GND to generate a voltage-regulator overtemperature monitor. Place the thermistor as close to the MOSFETs and inductors as possible. Fault Protection (Latched) Output Overvoltage (OVP) Protection The OVP circuit is designed to protect the processor against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17409 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV, subject to a minimum OVP threshold of 0.8V. During pulse-skipping operation (SKIP = high), the controller initially sets the OVP threshold to a fixed 1.8V threshold. 24 Once the output is in regulation (the first on-time is triggered) and the PWRGD blanking time expires, the controller tightens the OVP threshold, tracking the OVP threshold by 300mV, subject to a minimum OVP threshold of 0.8V. The controller also uses the fixed 1.8V OVP threshold during soft-start and soft-shutdown. When the OVP circuit detects an overvoltage fault, the MAX17409 immediately forces DL high and pulls DH low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. OVP protection can be disabled through the no-fault test mode (see the No-Fault Test Mode section). Output Undervoltage Protection (UVP) The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX17409 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to zero, it forces the DL high, and pulls DH low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. UVP protection can be disabled through the no-fault test mode (see the No-Fault Test Mode section). Thermal-Fault Protection The MAX17409 features a thermal-fault protection circuit. When the junction temperature rises above +160°C, an internal thermal sensor sets the fault latch and forces the DL high and the DH low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C. Thermal shutdown can be disabled through the no-fault test mode (see the NoFault Test Mode section). No-Fault Test Mode The latched fault protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a “no-fault” test mode is provided to disable the fault protection—overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN. ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller The internal pulldown transistor that drives DL low is robust, with a 0.25Ω (typ) on-resistance. This helps DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces might require that rising LX edges do not pull up the low-side MOSFETs’ gate, causing shootthrough currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-to-drain capacitance (C RSS ), gate-to-source capacitance (C ISS C RSS ), and additional board parasitics should not exceed the following minimum threshold: ⎛C ⎞ VGS(TH) > VIN ⎜ RSS ⎟ ⎝ C ISS ⎠ Typically, adding a 4700pF between DL and power ground (C NL in Figure 7), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents could be caused by a combination of fast high-side MOSFETs and slow low-side MOSFETs. If the turn-off delay time of the lowside MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually MAX17409 BST DH (RBST)* INPUT (VIN) CBST NH L LX VDD MAX17409 MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead-time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17409 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). CBYP DL NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI, DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 7. Gate-Drive Circuit turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 7). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. Quick-PWM Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output ______________________________________________________________________________________ 25 MAX17409 1-Phase Quick-PWM GPU Controller capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. • • Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. The worst-case output sag voltage can be determined by: ⎡⎛ VOUT t SW ⎞ ⎤ + t OFF(M ⎢⎜ MIN) ⎥ ⎟ VIN ⎠ ⎣⎝ ⎦ VSAG = ⎡⎛ ( VIN - VOUT ) t SW ⎞ ⎤ 2C OUT VOUT ⎢⎜ - t OFF(MIN) ⎥ ⎟ VIN ⎠ ⎢⎣⎝ ⎥⎦ ( L ∆ILOAD(MAX) )2 where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics table). The amount of overshoot due to stored inductor energy can be calculated as: VSOAR 2 ∆ILOAD(MAX) ) L ( ≈ 2C OUT VOUT Current-Limit Control (ILIM) REF and ILIM are used to set the current limit. REF regulates to a fixed 2.0V and the REF-to-ILIM voltage determines the valley current-sense threshold. When ILIM = VCC, the controller uses the preset 22.5mV current-limit threshold. In an adjustable design, ILIM is connected to a resistive voltage-divider connected between REF and ground. The differential voltage between REF and ILIM sets the current-limit threshold (VLIMIT), so the valley current-sense threshold is: ⎛ ⎞ ⎛ VOUT ⎞ VIN - VOUT L=⎜ ⎟⎜ ⎟ ⎝ fSWILOAD(MAX)LIR ⎠ ⎝ VIN ⎠ V -V VLIMIT = REF ILIM 10 Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite and molded iron cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): This allows design flexibility since the DCR sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mV. Keeping VLIMIT between 20mV to 40mV leaves room for future current-limit adjustment. The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ⎛ LIR ⎞ IPEAK = ILOAD(MAX) ⎜ 1 + ⎟ ⎝ 2 ⎠ Transient Response The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of 26 ⎛ LIR ⎞ I VALLEY > ILOAD(MAX) ⎜ 1 ⎟ ⎝ 2 ⎠ ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller (RESR + RPCB ) ≤ ∆I VSTEP LOAD(MAX) V I VALLEY = LIMIT = R SENSE VLIMIT R DCR × CSP -CSN R LX -C CSN where RSENSE is the sensing resistor and RCSP-CSN/ RLX-CSN is the ratio of resistor-divider with DCR-sensing approach. In nonprocessor applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. The maximum ESR to meet ripple requirements is: ⎤ ⎡ VINfSWL R ESR ≤ ⎢ ⎥ VRIPPLE ⎢⎣ ( VIN - VOUT ) VOUT ⎥⎦ Voltage Positioning and Loop Compensation Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power dissipation requirements. The controller uses a transconductance amplifier to set the transient and DC output voltage droop (Figure 2) as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated. Steady-State Voltage Positioning Connect a resistor (RFB) between FB and VOUT to set the DC steady-state droop (load line) based on the required voltage positioning slope (RDROOP): R FB = R DROOP R SENSEG m(FB) where the effective current-sense resistance (RSENSE) depends on the current-sense method (see the Current Sense section), and the voltage-positioning amplifier’s transconductance (G m(FB) ) is typically 600µS as defined in the Electrical Characteristics table. When the inductors’ DCR is used as the current-sense element (R SENSE = R DCR), each current-sense input should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope. where f SW is the switching frequency. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR ≤ SW π where: fESR = Output Capacitor Selection The output filter capacitor must have low enough effective equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In processor core supplies and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: 1 2πR EFF C OUT and: R EFF = R ESR + R DROOP(AC) + R PCB where COUT is the total output capacitance, RESR is the total ESR, RSENSE is the current-sense resistance (RCM = RCS), RDROOP(AC) is the AC component of the droop, and RPCB is the parasitic board resistance between the output capacitors and sense resistors. ______________________________________________________________________________________ 27 MAX17409 where: MAX17409 1-Phase Quick-PWM GPU Controller In applications that require DC droop, RDROOP(AC) is the same as the DC droop setting (R DROOP(AC) = RDROOP(DC)). In applications that do not require DC droop, this AC signal is generated by capacitively coupling the inductor ripple current signal to the FB pin. In this case, RDROOP(AC) = RSENSE, where RSENSE is the effective sense resistance seen at the CSP-CSN pins. In Figure 1, C3 couples the inductor ripple current signal to the FB pin. C3 can be connected to the CSN pin or the CSP pin. Connecting to the CSN pin only couples the output capacitor ESR to the FB pin. Connecting to the CSP pin adds the RSENSE component to the effective resistance in addition to the output capacitor ESR. This is useful for applications using all ceramic output capacitors. Keep the C3 x RFB time constant between 3x and 5x of the switching period. Practical values for C3 range from 0.1µF to 1µF. Calculate RFB after selecting C3. Keeping RFB below 100Ω minimizes any residual DC droop. In the standard application circuit (Figure 1), the effective resistance for stability is the sum of the ~ 2mΩ DCR and the 6mΩ ESR of the 470µF output capacitor. The ESR zero frequency is 42kHz, well within the requirement of fSW/π. Ceramic capacitors have a high-ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PCB resistance to ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output-voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. 28 The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements can be determined by the following equation: ⎛I ⎞ IRMS = ⎜ LOAD ⎟ VOUT ( VIN - VOUT ) ⎝ VIN ⎠ The worst-case RMS current requirement occurs when operating with VIN = 2VOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity. Power-MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at V IN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller MOSFET Power Dissipation Worst-case conduction losses occur in the high-side MOSFET (NH) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage: ⎛V ⎞ PD (NH Resistive) = ⎜ OUT ⎟ ILOAD 2R DS(O ON) ⎝ VIN ⎠ Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the switching losses in a high-side MOSFET (NH) is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: ⎛ Q G(SW) ⎞ PD (NH Switching) = VINILOADfSW ⎜ ⎟ ⎝ IGATE ⎠ + C OSS VIN 2 fSW 2 where COSS is the NH MOSFET’s output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ). ⎡ ⎛ V ⎞⎤ 2 OUT PD (NL Resistive) = ⎢1- ⎜ ⎟ ⎥ (ILOAD ) R DS(ON) V ⎢⎣ ⎝ IN(MAX) ⎠ ⎥⎦ The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit can be overdesigned to tolerate: ∆I ⎛ ⎞ ILOAD = ⎜ I VALLEY(MAX) + INDUCTOR ⎟ ⎝ ⎠ 2 ⎛ ILOAD(MAX)LIR ⎞ = I VALLEY(MAX) + ⎜ ⎟ 2 ⎝ ⎠ where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. However, high-current applications driving large high-side MOSFETS require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: C BST = N × Q GATE 200mV Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: 2 × 24nC C BST = = 0.24µF 200mV For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor. ______________________________________________________________________________________ 29 MAX17409 driver can supply sufficient current to support the gate charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems could occur (see the MOSFET Gate Drivers section). MAX17409 1-Phase Quick-PWM GPU Controller Applications Information • When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. • Route high-speed switching nodes away from sensitive analog areas (CCV, FB, CSP, CSN, etc.). Positive Offset Some applications require a positive offset to shift the output voltage to a different level. This might be necessary to obtain a voltage not supported by the VID code, or to allow a shift in the VID code mapping. A positive offset is generated by raising the voltage at the GNDS/OFSP pin using a resistor-divider from REF. Refer to R14 and R20 in Figure 1. The voltage at the GNDS/OFSP pin relative to the analog ground of the IC sets the offset voltage that is added to the programmed VID voltage: ⎛ R14 ⎞ VGNDS = VOFFSET = ⎜ V ⎝ R20 + R14 ⎟⎠ REF and: VTARGET = VDAC + VOFFSET PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 8). If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow the MAX17409 Evaluation Kit layout and use the following guidelines for good PCB layout: • Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. • Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the V CC bypass capacitor, REF, GNDS bypass capacitors, and compensation (CCV) components. • Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. • CSP and CSN connections for current limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy. 30 Layout Procedures 1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50mils to 100mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST capacitors, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figure 1. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; the master’s analog ground plane where sensitive analog components go, the master’s GND pin and VCC bypass capacitor go; and the slave’s analog ground plane where the slave’s GND pin and VCC bypass capacitor go. The master’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical. ______________________________________________________________________________________ 1-Phase Quick-PWM GPU Controller MAX17409 KELVIN SENSE VIAS UNDER THE INDUCTOR (SEE MAX17409 EVALUATION KIT) POWER STAGE LAYOUT (TOP SIDE OF PCB) OUTPUT INDUCTOR L COUT COUT CSP CSN CEQ RNTC R2 R1 POWER GROUND CIN1 KELVIN SENSE VIAS TO INDUCTOR PAD INDUCTOR DCR SENSING INPUT SMPS Figure 8. PCB Layout Example Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 TQFN T2844-1 21-0139 ______________________________________________________________________________________ 31 MAX17409 1-Phase Quick-PWM GPU Controller Revision History REVISION NUMBER REVISION DATE 0 4/09 Initial release 1 7/09 Remove all NVIDIA references; change CPU to GPU DESCRIPTION PAGES CHANGED — 1–32 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.