19-0837; Rev 0; 6/07 KIT ATION EVALU E L B A AVAIL High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Dual Mode is a trademark of Maxim Integrated Products, Inc. TEMP RANGE PIN-PACKAGE MAX17003AETJ+ -40°C to +85°C 32 Thin QFN (5mm x 5mm) T3255-4 MAX17004AETJ+ -40°C to +85°C 32 Thin QFN (5mm x 5mm) T3255-4 +Denotes a lead-free package. DL3 IN LDO5 PGND DL5 LX5 24 PGDALL TOP VIEW LX3 Pin Configuration 23 22 21 20 19 18 17 DH3 25 16 DH5 BST3 26 15 BST5 DSCHG3 27 14 DSCHG5 CSL3 28 13 CSL5 12 CSH5 11 FB5 10 SKIP 9 FSEL MAX17003A MAX17004A CSH3 29 FB3 30 FBA 31 + 1 2 3 4 5 6 7 8 GND OUTA 32 REF PDAs and Mobile Communicators PKG CODE PART ON5 Notebook and Subnotebook Computers Ordering Information ON3 2 to 4 Li+ Cell Battery-Powered Devices o o SHDN Main Power Supplies o o o o o o ILIM Applications o Fixed-Frequency, Current-Mode Control 40/60 Optimal Interleaving Internal BST Switches Internal 5V, 100mA Linear Regulator Auxiliary Linear-Regulator Driver (12V or Adjustable Down to 1V) Dual Mode™ Feedback—3.3V/5V Fixed or Adjustable Output Voltages 200kHz/300kHz/500kHz Switching Frequency Undervoltage and Thermal-Fault Protection Overvoltage-Fault Protection (MAX17003A Only) 6V to 26V Input Range 2V ±0.75% Reference Output Independent Enable Inputs and Power-Good Outputs Soft-Start and Soft-Discharge (Voltage Ramp) 8µA (typ) Shutdown Current ONA The MAX17003A/MAX17004A are available in a 32-pin, 5mm x 5mm thin QFN package. The exposed backside pad improves thermal characteristics for demanding linear keep-alive applications. o o o o o DRVA The MAX17003A/MAX17004A are dual step-down, switch-mode, power-supply (SMPS) controllers with synchronous rectification, intended for main 5V/3.3V power generation in battery-powered systems. Fixedfrequency operation with optimal interleaving minimizes input ripple current from the lowest input voltages up to the 26V maximum input. Optimal 40/60 interleaving allows the input voltage to go down to 8.3V before dutycycle overlap occurs, compared to 180° out-of-phase regulators where the duty-cycle overlap occurs when the input drops below 10V. Output current sensing provides peak current-limit protection, using either an accurate sense resistor or using lossless inductor DCR current sensing. A low-noise mode maintains high light-load efficiency while keeping the switching frequency out of the audible range. An internal, fixed 5V, 100mA linear regulator powers up the MAX17003A/MAX17004A and their gate drivers, as well as external keep-alive loads. When the main PWM regulator is in regulation, an automatic bootstrap switch bypasses the internal linear regulator, providing current up to 200mA. An additional adjustable linear-regulator driver with an external pnp transistor can be used with a secondary winding to provide a 12V supply, or powered directly from the main outputs to generate low-voltage outputs as low as 1V. Independent enable controls and power-good signals allow flexible power sequencing. Voltage soft-start gradually ramps up the output voltage and reduces inrush current, while soft-discharge gradually decrease the output voltage, preventing negative voltage dips. The MAX17003A/MAX17004A feature output undervoltage and thermal-fault protection. The MAX17003A also includes output overvoltage-fault protection. Features THIN QFN 5mm x 5mm ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX17003A/MAX17004A General Description MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers ABSOLUTE MAXIMUM RATINGS IN, SHDN, DRVA, OUTA to GND............................-0.3V to +28V LDO5, ON3, ON5, ONA to GND ..............................-0.3V to +6V PGDALL, DSCHG3, DSCHG5 to GND .....................-0.3V to +6V CSL3, CSH3, CSL5, CSH5 to GND ..........................-0.3V to +6V REF, FB3, FB5, FBA to GND...................-0.3V to (VLDO5 + 0.3V) SKIP, FSEL, ILIM to GND........................-0.3V to (VLDO5 + 0.3V) DL3, DL5 to PGND..................................-0.3V to (VLDO5 + 0.3V) BST3, BST5 to PGND .............................................-0.3V to +34V BST3 to LX3..............................................................-0.3V to +6V DH3 to LX3 ..............................................-0.3V to (VBST3 + 0.3V) BST5 to LX5..............................................................-0.3V to +6V DH5 to LX5 ..............................................-0.3V to (VBST5 + 0.3V) GND to PGND .......................................................-0.3V to +0.3V BST3, BST5 to LDO5 .............................................-0.3V to +0.3V LDO Short Circuit to GND ..........................................Momentary REF Short Circuit to GND ...........................................Momentary DRVA Current (sinking).......................................................30mA OUTA Shunt Current ...........................................................30mA Continuous Power Dissipation (TA = +70°C) Multilayer PCB 32-Pin, 5mm x 5mm TQFN (derated 34.5mW/°C above +70°C) .........................2459mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, IREF = ILDO5 = IOUTA = no load, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUT SUPPLIES (Note 1) VIN Input Voltage Range VIN VIN Operating Supply Current IIN LDO5 in regulation 5.4 26.0 IN = LDO5, VCSL5 < 4.4V 4.5 5.5 V LDO5 switched over to CSL5, either SMPS on 20 36 µA VIN Standby Supply Current IIN(STBY) VIN = 6V to 26V, both SMPS off, includes ISHDN 65 120 µA VIN Shutdown Supply Current IIN(SHDN) VIN = 6V to 26V 8 20 µA 3.5 4.5 mW Quiescent Power Consumption PQ Both SMPS on, FB3 = FB5 = LDO5, SKIP = GND, VCSL3 = 3.5V, VCSL5 = 5.3V, VOUTA = 15V, PIN + PCSL3 + PCSL5 + POUTA MAIN SMPS CONTROLLERS 3.3V Output Voltage in Fixed Mode VOUT3 VIN = 6V to 26V, SKIP = FB3 = LDO5, 0 < VCSH3 - VCSL3 < 50mV (Note 2) 3.265 3.315 3.365 V 5V Output Voltage in Fixed Mode VOUT5 VIN = 6V to 26V, SKIP = FB5 = LDO5, 0 < VCSH5 - VCSL5 < 50mV (Note 2) 4.94 5.015 5.09 V VIN = 6V to 26V, FB3 or FB5 duty factor = 20% to 80% 1.980 2.010 2.040 VIN = 6V to 26V, FB3 or FB5 duty factor = 50% 1.990 2.010 2.030 Feedback Voltage in Adjustable Mode (Note 2) 2 VFB_ V _______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers (Circuit of Figure 1, VIN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, IREF = ILDO5 = IOUTA = no load, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Output Voltage Adjust Range CONDITIONS Either SMPS 3.0 Feedback Input Leakage Current VFB3 = VFB5 = 2.1V DC Load Regulation Either SMPS, SKIP = LDO5, 0 < VCSH_ - VCSL < 50mV Line Regulation Error Either SMPS, 6V < VIN < 26V Maximum Duty Factor DMAX Minimum On-Time tONMIN SMPS3-to-SMPS5 Phase Shift MAX UNITS 5.5 V VLOO5 - 1.0 VLOO5 - 0.4 V +0.1 µA -0.1 FSEL = GND fOSC TYP 2.0 FB3, FB5 Dual Mode Threshold Operating Frequency (Note 1) MIN -0.1 % 0.03 170 200 %/V 230 FSEL = REF 270 300 330 FSEL = LDO5 425 500 575 (Note 1) 97.5 SMPS5 starts after SMPS3 kHz 99 % 100 ns 40 % 144 Degrees CURRENT LIMIT ILIM Adjustment Range Current-Sense Input Leakage Current Current-Limit Threshold (Fixed) CSH3 = CSH5 = GND or LDO5 VLIMIT Current-Limit Threshold (Adjustable) VLIMIT Current-Limit Threshold (Negative) VNEG Current-Limit Threshold (Zero Crossing) VZX VCSH_ - VCSL _, ILIM = LDO5 VCSH_ - VCSL _ Soft-Start Ramp Time +1 µA mV 50 55 200 215 VILIM = 1.00V 94 100 106 -67 -60 -53 VCSH_ - VCSL _, SKIP = LDO5, adjustable mode, percent of current limit VCSH_ - VCSL _, SKIP = GND, ILIM = LDO5 VIDLE VCSH_ - VCSL _, SKIP = GND VIDLE VCSH_ - VCSL _, SKIP = REF -120 mV % 3 6 mV 6 10 14 mV 20 2.5 With respect to current-limit threshold (VLIMIT) Measured from the rising edge of ON_ to full scale mV 0 With respect to current-limit threshold (VLIMIT) ILIM = GND or REF tSSTART -1 45 VCSH_ - VCSL _, SKIP = ILIM = LDO5 ILIM Leakage Current V 185 ILIM = LDO5 Idle Mode Threshold (Low Audible-Noise Mode) VREF VILIM = 2.00V ILIM = LDO5 Idle Mode™ Threshold 0.5 5 % 7.5 10 -1 % +1 2 mV µA ms Idle Mode is a trademark of Maxim Integrated Products, Inc. _______________________________________________________________________________________ 3 MAX17003A/MAX17004A ELECTRICAL CHARACTERISTICS (continued) MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, IREF = ILDO5 = IOUTA = no load, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ON5 = GND, 6V < VIN < 26V, 0 < ILDO5 < 100mA 4.85 4.95 5.10 V LDO5 Undervoltage-Lockout Fault Rising edge, hysteresis = 1% 3.7 4.0 4.1 mA Short-Circuit Current (Switched over to CSL5) LDO5 = GND, VCSL5 > 4.7V 200 425 INTERNAL FIXED LINEAR REGULATORS LDO5 Output Voltage VLDO5 mA AUXILIARY LINEAR REGULATOR DRVA Voltage Range VDRVA DRVA Drive Current FBA Regulation Threshold 0.5 VFBA = 0.965V, VDRVA = 5V VFBA VDRVA = 5V, IDRVA = 1mA (sink) 0.4 10 0.98 FBA Load Regulation VDRA = 5V, IDRVA = 0.5mA to 5mA OUTA Shunt Trip Level Rising edge 25 FBA Leakage Current VFBA = 1.035V 0.1 Secondary Feedback-Regulation Threshold VDRVA - VOUTA DL5 Pulse Width OUTA Leakage Current 26.0 VFBA = 1.05V, VDRVA = 5V IOUTA VDRVA = VOUTA = 25V VREF LDO5 in regulation, IREF = 0 V mA 1.00 1.02 V -1.2 -2.2 % 26 27 V +0.1 µA 0 V 1/3/fOSC µs 50 µA 2.015 V +10 mV REFERENCE (REF) Reference Voltage Reference Load-Regulation Error REF Lockout Voltage ΔVREF VREF(UVLO) IREF = -5µA to +50µA 1.985 2.00 -10 Rising edge 1.8 V FAULT DETECTION Output Overvoltage Trip Threshold (MAX17003A Only) Output Overvoltage Fault Propagation Delay (MAX17003A Only) With respect to error-comparator threshold tOVP Output Undervoltage Protection Trip Threshold Output Undevoltage Fault Propagation Delay Output Undervoltage Protection Blanking Time 4 50mV overdrive With respect to error-comparator threshold tUVP tBLANK 8 14 10 65 50mV overdrive From rising edge of ON_ with respect to fSW 11 70 µs 75 10 5000 6144 _______________________________________________________________________________________ % % µs 7000 1/fOSC High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers (Circuit of Figure 1, VIN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, IREF = ILDO5 = IOUTA = no load, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL PGDALL Lower Trip Threshold PGDALL Propagation Delay tPGDALL PGDALL Output Low Voltage PGDALL Leakage Current Thermal-Shutdown Threshold CONDITIONS MIN TYP MAX UNITS With respect to either SMPS error-comparator threshold, hysteresis = 1% (typ) -12 -10 -8 % Falling edge, 50mV overdrive 10 Rising edge, 50mV overdrive 1 ISINK = 1mA IPGDALL tSHDN High state, PGDALL forced to 5.5V Hysteresis = 15°C µs 0.4 V 1 µA +160 °C GATE DRIVERS DH_ Gate-Driver On-Resistance RDH DL_ Gate-Driver On-Resistance RDL DH_ Gate-Driver Source/Sink Current IDH DL_ Gate-Driver Source Current IDL DL_ Gate-Driver Sink Current IDL (SINK) Dead Time tDEAD Internal BST_ Switch On-Resistance RBST BST_ Leakage Current BST_ - LX_ forced to 5V 1.3 5 DL_, high state 1.7 5 DL_, low state 0.6 3 DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V DL_ forced to 2.5V Ω Ω 2 A 1.7 A 3.3 A DH_ low to DL_ high 15 45 DL_ low to DH_ high 15 44 IBST = 10mA 5 VBST_ = 26V 2 ns Ω 20 µA INPUTS AND OUTPUTS SHDN Input Trip Level ONA Logic Input Voltage Rising trip level 1.1 1.6 2.2 Falling trip level 0.96 1 1.04 Hysteresis = 600mV (typ) High 2.4 Low 0.8 SMPS off level/clear fault level ON3, ON5 Input Voltage Delay start level 1.9 2.4 ISINK = 1mA DSCHG_ Leakage Current High state, DSCHG_ forced to 5.5V Tri-Level Input Logic SKIP, FSEL High VLDO5 - 0.4 REF 1.65 GND Input Leakage Current V 0.8 SMPS on level DSCHG_ Output Low Voltage V 2.1 V 0.4 V 1 µA 2.35 V 0.5 SKIP, FSEL forced to GND or LDO5 -1 +1 SHDN forced to GND or 26V -1 +1 µA _______________________________________________________________________________________ 5 MAX17003A/MAX17004A ELECTRICAL CHARACTERISTICS (continued) MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, IREF = ILDO5 = IOUTA = no load, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN MAX LDO5 in regulation 5.4 26.0 IN = LDO5, VCSL5 < 4.4V 4.5 5.5 UNITS INPUT SUPPLIES (Note 1) VIN Input Voltage Range VIN VIN Operating Supply Current I IN V LDO5 switched over to CSL5, either SMPS on 40 μA VIN Standby Supply Current I IN(STBY) VIN = 6V to 26V, both SMPS off, includes I SHDN 120 μA VIN Shutdown Supply Current I IN(SHDN) VIN = 6V to 26V 20 μA Both SMPS on, FB3 = FB5 = LDO5; SKIP = GND, VCSL3 = 3.5V, VCSL5 = 5.3V, VOUTA = 15V, PIN + PCSL3 + PCSL5 + P OUTA 4.5 mW Quiescent Power Consumption PQ MAIN SMPS CONTROLLERS 3.3V Output Voltage in Fixed Mode VOUT3 VIN = 6V to 26V, SKIP = FB3 = LDO5, 0 < VCSH3 - VCSL3 < 50mV (Note 2) 3.255 3.375 V 5V Output Voltage in Fixed Mode VOUT5 VIN = 6V to 26V, SKIP = FB5 = LDO5, 0 < VCSH5 - VCSL5 < 50mV (Note 2) 4.925 5.105 V VIN = 6V to 26V, FB3 or FB5 duty factor = 20% to 80% (Note 2) 1.974 2.046 V 2.0 5.5 V 3V VLDO5 0.4 V FSEL = GND 170 230 FSEL = REF 270 330 FSEL = LDO5 425 575 Feedback Voltage in Adjustable Mode VFB_ Output Voltage-Adjust Range Either SMPS FB3, FB5 Dual Mode Threshold Operating Frequency (Note 1) Maximum Duty Factor f OSC DMAX 97 kHz % CURRENT LIMIT ILIM Adjustment Range 0.5 VREF V 44 56 mV VILIM = 2.00V 185 215 VILIM = 1.00V 93 107 ON5 = GND, 6V < VIN < 26V, 0 < ILDO5 < 100mA 4.85 5.10 V Rising edge, hysteresis = 1% (typ) 3.7 4.1 V LDO5 Bootstrap Switch Rising edge of CSL5, hysteresis = 1% (typ) 4.30 4.75 V Short-Circuit Current LDO5 = GND, ON5 = GND 450 mA Short-Circuit Current (Switched over to CSL5) LDO5 = GND, VCSL5 > 4.7V Current-Limit Threshold (Fixed) VLIMIT VCSH_ - VCSL _, ILIM = LDO5 Current-Limit Threshold (Adjustable) VLIMIT VCSH_ - VCSL _ mV INTERNAL FIXED LINEAR REGULATORS LDO5 Output Voltage LDO5 Undervoltage-Lockout Fault Threshold 6 VLDO5 200 _______________________________________________________________________________________ mA High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers (Circuit of Figure 1, VIN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, IREF = ILDO5 = IOUTA = no load, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 0.5 26.0 V AUXILIARY LINEAR REGULATOR DRVA Voltage Range VDRVA VFBA = 1.05V, VDRVA = 5V DRVA Drive Current FBA Regulation Threshold VFBA VFBA = 0.965V, VDRVA = 5V VDRVA = 5V, IDRVA = 1mA (sink) OUTA Shunt Trip Level 0.4 10 mA 0.98 1.02 V 25 27 V 1.980 2.020 V REFERENCE (REF) Reference Voltage VREF LDO5 in regulation, IREF = 0 FAULT DETECTION Output Overvoltage Trip Threshold (MAX17003A Only) With respect to error comparator threshold 8 14 % Output Undervoltage Protection With respect to error comparator threshold 65 75 % PGDALL Lower Trip Threshold With respect to error comparator threshold, hysteresis = 1% -12 -8 % PGDALL Output Low Voltage I SINK = 1mA 0.4 V BST_ - LX_ forced to 5V 5 DL_, high state 5 DL_, low state 3 GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance RDH RDL INPUTS AND OUTPUTS SHDN Input Trip Level ONA Logic Input Voltage Rising trip level 1.0 2.3 Falling trip level 0.96 1.04 Hysteresis = 600mV High 2.4 Low 0.8 SMPS off level/clear fault level ON3, ON5 Input Voltage DSCHG_ Output Low Voltage Tri-Level Input Logic 1.9 SMPS on level 2.4 I SINK = 1mA High VLDO5 - 0.4 REF 1.65 GND V 0.8 Delay start level SKIP, FSEL V 2.1 V 0.4 V 2.35 V 0.5 Note 1: The MAX17003A/MAX17004A cannot operate over all combinations of frequency, input voltage (VIN), and output voltage. For large input-to-output differentials and high switching-frequency settings, the required on-time may be too short to maintain the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum ontime must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are measured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 2: When the inductor is in continuous conduction, the output voltage has a DC-regulation level lower than the error-comparator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1.1% due to slope compensation. Note 3: Specifications from -40°C to +85°C are guaranteed by design, not production tested. _______________________________________________________________________________________ 7 MAX17003A/MAX17004A ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 1, VIN = 12V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.) 5V OUTPUT EFFICIENCY vs. LOAD CURRENT 20V 60 70 LOW-NOISE MODE 60 SKIP MODE PWM MODE 0.1 1 LOAD CURRENT (A) 50 10 3.3V OUTPUT EFFICIENCY vs. LOAD CURRENT 0.01 20V 70 SKIP MODE 80 0.1 1 LOAD CURRENT (A) LOW-NOISE MODE PWM MODE 5.0V OUTPUT -1 MAX17003A/MAX17004A toc03 5 SKIP MODE LOW-NOISE MODE 3.33 3.30 PWM MODE 3.27 0.01 0.1 1 LOAD CURRENT (A) 0 10 100 PWM MODE SUPPLY CURRENT (mA) 0 4 3.36 1 2 3 LOAD CURRENT (A) 4 5 STANDBY AND SHUTDOWN INPUT CURRENT vs. INPUT VOLTAGE NO-LOAD INPUT SUPPLY CURRENT vs. INPUT VOLTAGE MAX17003A/MAX17004A toc07 1 2 3 LOAD CURRENT (A) 3.24 0.001 OUTPUT VOLTAGE DEVIATION vs. INPUT VOLTAGE 3.3V OUTPUT 1 3.39 50 10 2 0 3.3V OUTPUT VOLTAGE vs. LOAD CURRENT 70 60 SKIP MODE PWM MODE 3 PWM MODE 10 90 60 0.01 0.1 1 LOAD CURRENT (A) 100 EFFICIENCY (%) EFFICIENCY (%) 12V 80 MAX17003A/MAX17004A toc04 7V 90 0.001 5.00 3.3V OUTPUT EFFICIENCY vs. LOAD CURRENT 100 50 LOW-NOISE MODE 4.90 0.001 OUTPUT VOLTAGE (V) 0.01 10 LOW-NOISE MODE 100 STANDBY (ONx = GND) SUPPLY CURRENT (μA) 0.001 5.05 4.95 MAX17003A/MAX17004A toc05 50 PWM MODE SKIP MODE MAX17003A/MAX17004A toc06 70 80 5.10 MAX17003A/MAX17004A toc09 80 90 MAX17003A/MAX17004A toc08 EFFICIENCY (%) 12V SKIP MODE OUTPUT VOLTAGE (V) 90 100 5V OUTPUT VOLTAGE vs. LOAD CURRENT MAX17003A/MAX17004A toc02 7V EFFICIENCY (%) 100 MAX17003A/MAX17004A toc01 5V OUTPUT EFFICIENCY vs. LOAD CURRENT OUTPUT VOLTAGE DEVIATION (%) MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers SHUTDOWN (SHDN = GND) 10 -2 SKIP MODE 0 8 1 1 -3 4 8 12 INPUT VOLTAGE (V) 16 20 0 4 8 12 INPUT VOLTAGE (V) 16 20 0 4 8 12 INPUT VOLTAGE (V) _______________________________________________________________________________________ 16 20 High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers MAX17003A/MAX17004A Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.) 3.3V SWITCHING FREQUENCY vs. LOAD CURRENT 1 LOW-NOISE MODE SKIP = REF 0 0 4 8 12 INPUT VOLTAGE (V) 16 100 LOW-NOISE SKIP PULSE SKIPPING 10 30 20 0 0.01 0.1 1 10 -10 OUTA OUTPUT VOLTAGE vs. LOAD CURRENT 4.8 4.7 10 POWER-UP SEQUENCE MAX17003A/MAX17004A toc14 4.9 -6 -2 2 6 2V REF OFFSET VOLTAGE (mV) MAX17003A/MAX17004A toc15 12.2 OUTPUT VOLTAGE (V) MAX17003A/MAX17004A toc13 5.0 SAMPLE SIZE = 125 40 LOAD CURRENT (A) LDO5 OUTPUT VOLTAGE vs. LOAD CURRENT OUTPUT VOLTAGE (V) +85°C +25°C 10 1 0.001 20 50 MAX17003A/MAX17004A toc12 FORCED-PWM SAMPLE PERCENTAGE (%) 2 REFERENCE OFFSET VOLTAGE DISTRIBUTION MAX17003A/MAX17004A toc11 SKIP MODE SKIP = GND 1000 SWITCHING FREQUENCY (kHz) IDLE MODE CURRENT (mA) 3 MAX17003A/MAX17004A toc10 3.3V IDLE MODE CURRENT vs. INPUT VOLTAGE 12.1 A 12V B 0 C 0 12.0 0 5V D 0 E 4.6 0 11.9 4.5 0 20 40 60 LOAD CURRENT (mA) 80 100 0 50 100 LOAD CURRENT (mA) 150 400μs/div A. INPUT SUPPLY, 5V/div D. LDO5, 5V/div B. REF, 1V/div E. PGDALL, 5V/div C. 5V OUTPUT (VOUT5), 2V/div _______________________________________________________________________________________ 9 MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.) SMPS DELAYED STARTUP SEQUENCE (ON3 = REF) SOFT-START WAVEFORM SMPS DELAYED STARTUP SEQUENCE (ON5 = REF) MAX17003A/MAX17004A toc17 MAX17003A/MAX17004A toc16 MAX17003A/MAX17004A toc18 A B 5V 5V A A C 0 0 0 0 2V 0 0 5V D 3.3V F 0 5V 0 0 C 3.3V D 0 5V 1ms/div 400μs/div A. ON5, 5V/div B. 5V OUTPUT (VOUT5), 5V/div D. PGDALL, 5V/div A. AUX LDO OUTPUT ON3 = ON5, LDO5 (VOUTA), 5V/div B. 5V OUTPUT (VOUT5), 2V/div E. REF, 2V/div C. 3.3V OUTPUT (VOUT3), 2V/div F. DL5, 5V/div G. SHDN, 5V/div SMPS SHUTDOWN WAVEFORM B C D 0 G 0 5V 0 0 E 0 B 1ms/div C. 3.3V OUTPUT (VOUT3), 5V/div D. PGDALL, 5V/div A. ON3, 5V/div B. 5V OUTPUT (VOUT5), 5V/div OUT3 LOAD TRANSIENT OUT5 LOAD TRANSIENT MAX17003A/MAX17004A toc19 C. 3.3V OUTPUT (VOUT3), 5V/div D. PGDALL, 5V/div MAX17003A/MAX17004A toc21 MAX17003A/MAX17004A toc20 3A 5A 3.3V 5V A 1A 5.1V A 3.3V B 5.0V B C 4.9V 5A A 1A 3.35V 5V D 0 0 E C 12V 4ms/div C D 0 A. ON3, ON5, 5V/div D. PGDALL, 5V/div B. 5V OUTPUT (VOUT5), 2V/div E. DL5, 5V/div C. 3.3V OUTPUT (VOUT3), 2V/div F. DL3, 5V/div 3A 1A 12V F 0 10 3.25V 1A 0 5V B 3.30V D 0 20μs/div A. IOUT5 = 1A TO 5A, 5A/div B. VOUT5, 50mV/div 20μs/div C. INDUCTOR CURRENT, 5A/div D. LX5, 10V/div A. IOUT3 = 1A TO 3A, 5A/div B. VOUT3, 50mV/div ______________________________________________________________________________________ C. INDUCTOR CURRENT, 5A/div D. LX3, 10V/div High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers (Circuit of Figure 1, VIN = 12V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.) OUTPUT OVERVOLTAGE FAULT PROTECTION (MAX17003A ONLY) SKIP TRANSITION OUTPUT UNDERVOLTAGE (SHORT-CIRCUIT) FAULT PROTECTION MAX17003A/MAX17004A toc23 MAX17003A/MAX17004A toc22 MAX17003/MAX17004 toc24 3.3V 5V A 0 3.3V 3.3V A 0 B C A 3.35V B 3.25V 0 5V 2A 0 C 12V D 0 B 0 5V 5V D 0 5V E 0 40μs/div A. SKIP, 5V/div B. 3.3V OUTPUT (VOUT3), 100mV/div 0.5A LOAD 5V 0 5V C D 0 100μs/div C. INDUCTOR CURRENT, 2A/div D. LX3, 10V/div 4ms/div A. 5V OUTPUT (VOUT5), 2V/div D. DL5, 5V/div B. 3.3V OUTPUT (VOUT3), 2V/div E. PGDALL, 5V/div C. DL3, 5V/div RLOAD5 = 5Ω A. 3.3V OUTPUT (VOUT3), 2V/div C. PGDALL, 5V/div B. 5V OUTPUT (VOUT5), 2V/div D. DL3, 5V/div LDOA LOAD TRANSIENT LD05 LOAD TRANSIENT MAX17003A/MAX17004A toc26 MAX17003A/MAX17004A toc25 5V A 0 5.00V A 4.95V 15.0V B 14.5V 100mA B 12.0V C 11.9V 0 20μs/div A. LDO5 OUTPUT, 50mV/div B. LOAD CURRENT, 50mA/div 20μs/div A. LOAD FET GATE, 5V/div C. AUX LDO OUTPUT (VOUTA), B. AUX LDO INPUT, 0.5V/div 0.1V/div 0 TO 150mA LOAD TRANSIENT ______________________________________________________________________________________ 11 MAX17003A/MAX17004A Typical Operating Characteristics (continued) High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers MAX17003A/MAX17004A Pin Description PIN NAME FUNCTION 1 ONA Auxiliary LDO Enable Input. When ONA is pulled low, OUTA is high impedance and the secondary feedback control is disabled. When ONA is driven high, the controller enables the auxiliary LDO. 2 DRVA Auxiliary LDO Transistor Base Driver. Connect DRVA to the base of a pnp power transistor. Add a 680 pullup resistor between the base and emitter. 3 12 ILIM Peak Current-Limit Threshold Adjustment. The current-limit threshold defaults to 50mV if ILIM is pulled up to LDO5. In adjustable mode, the current-limit threshold across CSH_ and CSL_ is precisely 1/10 the voltage seen at ILIM over a 0.5V to 2.0V range. The logic threshold for switchover to the 50mV default value is approximately VLDO5 - 1V. 4 SHDN Shutdown Control Input. The device enters its 8μA supply-current shutdown mode if VSHDN is less than the SHDN input falling-edge trip level and does not restart until VSHDN is greater than the SHDN input rising-edge trip level. Connect SHDN to VIN for automatic startup. SHDN can be connected to VIN through a resistive voltage-divider to implement a programmable undervoltage lockout. 5 ON3 3.3V SMPS Enable Input. Driving ON3 high enables the 3.3V SMPS, while pulling ON3 low disables the 3.3V SMPS. If ON3 is connected to REF, the 3.3V SMPS starts after the 5V SMPS reaches regulation (delayed start). Drive ON3 below the clear fault level to reset the fault latch. 6 ON5 5V SMPS Enable Input. Driving ON5 high enables the 5V SMPS, while pulling ON5 low disables the 5V SMPS. If ON5 is connected to REF, the 5V SMPS starts after the 3.3V SMPS reaches regulation (delayed start). Drive ON5 below the clear fault level to reset the fault latch. 7 REF 2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1μF or greater ceramic capacitor. The reference sources up to 50μA for external loads. Loading REF degrades outputvoltage accuracy according to the REF load-regulation error. The reference shuts down when the system pulls SHDN low. 8 GND Analog Ground. Connect the exposed backside pad to GND. 9 FSEL Frequency Select Input. This three-level logic input sets the controllers’ switching frequency. Connect to LDO5, REF, or GND to select the following typical switching frequencies: LDO5 = 500kHz, REF = 300kHz, GND = 200kHz. 10 SKIP Pulse-SKIPping Control Input. Connect to LDO5 for low-noise, forced-PWM operation. Connect to REF for automatic, low-noise, pulse-SKIPping operation at light loads. Connect to GND for automatic, high-efficiency, pulse-SKIPping operation at light loads. Startup is always in the lownoise, pulse-SKIPping mode (i.e., same as SKIP = REF setting), regardless of the SKIP setting. The SKIP setting takes effect once the respective SMPS is in regulation. 11 FB5 Feedback Input for the 5V SMPS. Connect to LDO5 for the preset 5V output. In adjustable mode, FB5 regulates to 2V. 12 CSH5 Positive Current-Sense Input for the 5V SMPS. Connect to the positive terminal of the current-sense element. Figure 7 describes two different current-sensing options—using accurate sense resistors or lossless inductor DCR sensing. 13 CSL5 Output-Sense and Negative Current-Sense Input for the 5V SMPS. When using the internal preset 5V feedback-divider (FB5 = LDO5), the controller uses CSL5 to sense the output voltage. Connect to the negative terminal of the current-sense element. CSL5 also serves as the bootstrap input for LDO5. For the MAX17003A, place a Schottky diode from CSL5 to GND to prevent CSL5 from going below -7V. 14 DSCHG5 Open-Drain Discharge Input for the 5V SMPS. DSCHG5 is pulled low when ON5 is low, discharging the SMPS5 output. DSCHG5 is also low under fault conditions. Connect a 47 or larger resistor from DSCHG5 to the SMPS5 output. ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers PIN NAME FUNCTION 15 BST5 Boost Flying Capacitor Connection for the 5V SMPS. The MAX17003A/MAX17004A include an internal boost switch connected between LDO5 and BST5. Connect to an external capacitor as shown in Figure 1. 16 DH5 High-Side Gate-Driver Output for the 5V SMPS. DH5 swings from LX5 to BST5. 17 LX5 Inductor Connection for the 5V SMPS. Connect LX5 to the switched side of the inductor. LX5 serves as the lower supply rail for the DH5 high-side gate driver. 18 DL5 19 PGND Low-Side Gate-Driver Output for the 5V SMPS. DL5 swings from PGND to LDO5. 20 LDO5 21 IN 22 PGDALL 23 DL3 Low-Side Gate-Driver Output for the 3.3V SMPS. DL3 swings from PGND to LDO5. 24 LX3 Inductor Connection for the 3.3V SMPS. Connect LX3 to the switched side of the inductor. LX3 serves as the lower supply rail for the DH3 high-side gate driver. 25 DH3 High-Side Gate-Driver Output for the 3.3V SMPS. DH3 swings from LX3 to BST3. 26 BST3 Boost Flying Capacitor Connection for the 3.3V SMPS. The MAX17003A/MAX17004A include an internal boost switch connected between LDO5 and BST3. Connect to an external capacitor as shown in Figure 1. 27 DSCHG3 28 CSL3 Output Sense and Negative Current Sense for the 3.3V SMPS. When using the internal preset 3.3V feedback divider (FB3 = LDO5), the controller uses CSL3 to sense the output voltage. Connect to the negative terminal of the current-sense element. 29 CSH3 Positive Current-Sense Input for the 3.3V SMPS. Connect to the positive terminal of the currentsense element. Figure 7 describes two different current-sensing options—using accurate sense resistors or lossless inductor DCR sensing. 30 FB3 Power Ground 5V Internal Linear-Regulator Output. Bypass with 4.7μF minimum (1μF/25mA). Provides at least 100mA for the DL_ low-side gate drivers, the DH_ high-side drivers through the BST switches, the PWM controller, logic, reference, and external loads. If CSL5 is greater than 4.5V and soft-start is complete, the linear regulator shuts down, and LDO5 connects to CSL5 through a 1 switch rated for loads up to 200mA. Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to PGND with a 0.22μF or greater ceramic capacitor close to the IC. Open-Drain Power-Good Output for SMPS3 and SMPS5. PGDALL is pulled low if either SMPS3 or SMPS5 output drops more than 10% (typ) below the normal regulation point, or if either ON3 or ON5 is low. PGDALL becomes high impedance when both SMPS3 and SMPS5 are in regulation. Open-Drain Discharge Output for the 3.3V SMPS. DSCHG3 is pulled low when ON3 is low, discharging the SMPS3 output. DSCHG3 is also low under fault conditions. Connect a 47 or larger resistor from DSCHG3 to the SMPS3 output. Feedback Input for the 3.3V SMPS. Connect to LDO5 for fixed 3.3V output. In adjustable mode, FB3 regulates to 2V. ______________________________________________________________________________________ 13 MAX17003A/MAX17004A Pin Description (continued) MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Pin Description (continued) PIN NAME FUNCTION 31 FBA Auxiliary LDO Feedback Input. Connect a resistive voltage-divider from OUTA to analog ground to adjust the auxiliary linear-regulator output voltage. FBA regulates at 1V. 32 OUTA EP EP Adjustable Auxiliary Linear-Regulator Output. Bypass OUTA to GND with 1μF or greater capacitor (1μF/25mA). When DRVA < OUTA, the secondary feedback control triggers the DL5 for 1μs forcing the controller to recharge the auxiliary storage capacitor. When DRVA exceeds 25V, the MAX17003A/MAX17004A enable a 10mA shunt on OUTA, preventing the storage capacitor from rising to unsafe levels due to the transformer’s leakage inductance. Pulling ONA high enables the linear-regulator driver and the secondary feedback control. Exposed Pad. Connect the exposed backside pad to analog ground. Table 1. Component Selection for Standard Applications 300kHz 5V AT 5A 3.3V AT 5A COMPONENT 500kHz 5V AT 3A 3.3V AT 5A INPUT VOLTAGE VIN = 7V TO 24V VIN = 7V TO 24V CIN_, Input Capacitor (3) 10µF, 25V Taiyo Yuden TMK432BJ106KM (3) 10µF, 25V Taiyo Yuden TMK432BJ106KM COUT5, Output Capacitor 2x 100µF, 6V, 35mΩ SANYO 6TPE100MAZB 2x 100µF, 6V, 35mΩ SANYO 6TPE100MAZB L5/T5, Inductor/Transformer 6.8µH, 6.4A, 18mΩ (max) 1:2 Sumida 4749-T132 — NH5, High-Side MOSFET Fairchild Semiconductor FDS6612A International Rectifier IRF7807V Fairchild Semiconductor FDS6612A International Rectifier IRF7807V NL5, Low-Side MOSFET Fairchild Semiconductor FDS6670S International Rectifier IRF7807VD1 Fairchild Semiconductor FDS6670S International Rectifier IRF7807VD1 COUT3, Output Capacitor 2x 150µF, 4V, 35mΩ SANYO 4TPE150MAZB 2x 100µF, 6V, 35mΩ SANYO 6TPE100MAZB L3, Inductor 5.8µH, 8.6A, 16.2mΩ Sumida CORH127/LD-BR8NC 3.9µH, 6.5A, 15mΩ Sumida CDRH124-3R9NC NH3, High-Side MOSFET Fairchild Semiconductor FDS6612A International Rectifier IRF7807V Fairchild Semiconductor FDS6612A International Rectifier IRF7807V NL3, Low-Side MOSFET Fairchild Semiconductor FDS6670S International Rectifier IRF7807VD1 Fairchild Semiconductor FDS6670S International Rectifier IRF7807VD1 5V OUTPUT 3V OUTPUT 14 ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers INPUT (VIN) CIN IN 21 D1 NH1 25 26 CBST1 0.1μF L3 3.3V PWM OUTPUT COUT3 R1 6.96kΩ R2 3.48kΩ 24 23 DL1 DH3 DH5 BST3 BST5 LX3 LX5 DL3 DL5 NL1 28 CSH3 CSL3 CSH5 CSL5 C3 1000pF ILIM REF (300kHz) 9 7 FSEL FB5 REF FB3 CREF 0.22μF LDO5 SECONDARY OUTPUT 2 32 CLDOA 4.7μF CAUX 4.7μF 15 SECONDARY OUTPUT T5 CBST2 0.1μF 17 5V PWM OUTPUT 18 NL2 DL2 12 R3 10.5kΩ R4 4.02kΩ 13 C2 0.22μF 3 C4 1000pF COUT5 11 30 20 CLDO5 4.7μF 5V LDO OUTPUT MAX17003A MAX17004A R10 680Ω 12V LDO OUTPUT NH2 16 19 PGND 8 GND 29 C1 0.22μF MAX17003A/MAX17004A CIN DRVA SKIP 10 OUTA R5 110kΩ 31 CONNECT TO 5V OR 3.3V FBA R7 100kΩ R6 10kΩ PGDALL 4 5 ON OFF 6 1 DSCHG3 22 27 SMPS POWER-GOOD R8 47Ω 3.3V PWM OUTPUT SHDN ON3 ON5 DSCHG5 14 5V PWM OUTPUT R9 47Ω ONA POWER GROUND ANALOG GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. Figure 1. Standard Application Circuit ______________________________________________________________________________________ 15 MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Table 2. Component Suppliers SUPPLIER WEBSITE AVX www.avx.com Central Semiconductor Fairchild www.centralsemi.com International Rectifier www.irf.com KEMET www.kemet.com www.fairchildsemi.com NEC/Tokin www.nec-tokin.com Panasonic www.panasonic.com/industrial Philips www.philips.com Pulse www.pulseeng.com Renesas www.renesas.com SANYO www.edc.sanyo.com Sumida www.sumida.com Taiyo Yuden www.t-yuden.com TDK www.component.tdk.com TOKO www.tokoam.com Vishay (Dale, Siliconix) www.vishay.com Detailed Description The MAX17003A/MAX17004A standard application circuit (Figure 1) generates the 5V/5A and 3.3V/5A typical of the main supplies in a notebook computer. The input supply range is 7V to 24V. See Table 1 for component selections, while Table 2 lists the component manufacturers. The MAX17003A/MAX17004A contain two interleaved, fixed-frequency, step-down controllers designed for lowvoltage power supplies. The optimal interleaved architecture guarantees out-of-phase operation, reducing the input capacitor ripple. One internal LDO generates the keep-alive 5V power. The MAX17003A/MAX17004A have an auxiliary LDO with an adjustable output for generating either the 3.3V keep-alive supply or regulating the lowpower 12V system supply. Fixed 5V Linear Regulator (LDO5) An internal linear regulator produces a preset 5V lowcurrent output. LDO5 powers the gate drivers for the external MOSFETs, and provides the bias supply required for the SMPS analog controller, reference, and logic blocks. LDO5 supplies at least 100mA for external and internal loads, including the MOSFET gate drive, which typically varies from 5mA to 50mA, depending on the switching frequency and external MOSFETs selected. Bypass LDO5 with a 4.7µF or greater ceramic capacitor (1µF per 25mA of load) to guarantee stability under the full-load conditions. 16 The MAX17003A/MAX17004A SMPS require a 5V bias supply in addition to the high-power input supply (battery or AC adapter). This 5V bias supply is generated by the controller’s internal 5V linear regulator (LDO5). This bootstrapped LDO allows the controller to power up independently. The gate-driver input supply is connected to the fixed 5V linear-regulator output (LDO5). Therefore, the 5V LDO supply must provide LDO5 (PWM controller) and the gate-drive power, so the maximum supply current required is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 5mA to 50mA (typ) where ICC is 0.7mA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet’s total gate-charge specification limits at VGS = 5V. SMPS-to-LDO Bootstrap Switchover When the 5V main output voltage is above the LDO5 bootstrap-switchover threshold and has completed soft-start, an internal 1Ω (typ) p-channel MOSFET shorts CSL5 to LDO5, while simultaneously shutting down the LDO5 linear regulator. This bootstraps the device, powering the internal circuitry and external loads from the 5V SMPS output (CSL5), rather than through the linear regulator from the battery. Bootstrapping reduces power dissipation due to gate charge and quiescent losses by providing power from a 90%-efficient switch-mode source, rather than from a much-less-efficient linear regulator. The current capability increases from 100mA to 200mA when the LDO5 output is switched over to CSL5. When ON5 is pulled low, the controller immediately disables the bootstrap switch and reenables the 5V LDO. Reference (REF) The 2V reference is accurate to ±1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.1µF or greater ceramic capacitor. The reference sources up to 50µA and sinks 5µA to support external loads. If highly accurate specifications are required for the main SMPS output voltages, the reference should not be loaded. Loading the reference reduces the LDO5, CSL5 (OUT5), CSL3 (OUT3), and OUTA output voltages slightly because of the reference load-regulation error. System Enable/Shutdown (SHDN) Drive SHDN below the precise SHDN input falling-edge trip level to place the MAX17003A/MAX17004A in its low-power shutdown state. The controller consumes only 8µA of quiescent current while in shutdown mode. When shutdown mode activates, the reference turns off after the controller completes the shutdown sequence, ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers INPUTS* MODE Shutdown Mode OUTPUTS SHDN ON5 ON3 Low X X LDO5 5V SMPS OFF OFF 3V SMPS OFF Standby Mode High Low Low ON OFF, DSCHG5 LOW OFF, DSCHG3 LOW Normal Operation High High High ON ON ON 3.3V SMPS Active High Low High ON OFF, DSCHG5 LOW ON 5V SMPS Active High High Low OFF LDO5 to CSL5 bypass switch enabled ON OFF, DSCHG3 LOW Normal Operation (Delayed 5V SMPS Startup) High Ref High OFF LDO5 to CSL5 bypass switch enabled ON Power-up after 3.3V SMPS is in regulation ON Normal Operation (Delayed 3.3V SMPS Startup) High High Ref OFF LDO5 to CSL5 bypass switch enabled ON ON Power-up after 5V SMPS is in regulation *SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3 and ON5 are tri-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the middle-logic level is between 1.7V and 2.3V (see the Electrical Characteristics table). making the threshold to exit shutdown less accurate. To guarantee startup, drive SHDN above 2V (SHDN input rising-edge trip level). For automatic shutdown and startup, connect SHDN to VIN. The accurate 1V fallingedge threshold on SHDN can be used to detect a specific input voltage level and shut the device down. Once in shutdown, the 1.6V rising-edge threshold activates, providing sufficient hysteresis for most applications (see Table 3). The internal soft-start gradually increases the feedback voltage with a 1V/ms slew rate. Therefore, the outputs reach their nominal regulation voltage 2ms after the SMPS controllers are enabled (see the Soft-Start Waveform in the Typical Operating Characteristics). This gradual slew rate effectively reduces the input surge current by minimizing the current required to charge the output capacitors (IOUT = ILOAD + COUT x VOUT(NOM)/tSLEW). SMPS POR, UVLO, and Soft-Start SMPS Enable Controls (ON3, ON5) Power-on reset (POR) occurs when LDO5 rises above approximately 1V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. The POR circuit also ensures that the low-side drivers are pulled high until the SMPS controllers are activated. Figure 2 is the MAX17003A/MAX17004A block diagram. ON3 and ON5 control SMPS power-up sequencing. ON3 or ON5 rising above 2.4V enables the respective outputs. ON3 or ON5 falling below 1.6V disables the respective outputs. Driving ON_ below 0.8V clears the overvoltage, undervoltage, and thermal-fault latches. The LDO5 input undervoltage-lockout (UVLO) circuitry inhibits switching if the 5V bias supply (LDO5) is below its 4V UVLO threshold. Once the 5V bias supply (LDO5) rises above this input UVLO threshold and the SMPS controllers are enabled (ON_ driven high), the SMPS controllers start switching, and the output voltages begin to ramp up using soft-start. If the LDO5 voltage drops below the UVLO threshold, the controller stops switching and pulls the low-side gate drivers low until the LDO5 voltage recovers or drops below the POR threshold. SMPS Power-Up Sequencing Connecting ON3 or ON5 to REF forces the respective outputs off while the other output is below regulation and starts after that output regulates. The second SMPS remains on until the first SMPS turns off, the device shuts down, a fault occurs, or LDO5 goes into UVLO. Both supplies begin their power-down sequence immediately when the first supply turns off. ______________________________________________________________________________________ 17 MAX17003A/MAX17004A Table 3. Operating Mode Truth Table MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers IN FSEL SHDN 5V LINEAR REGULATOR OSC LDO5 LDO BYPASS CIRCUITRY ILIM SKIP CSH5 CSL5 CSH3 CSL3 LDO5 BST3 PWM5 CONTROLLER (FIGURE 3) PWM3 CONTROLLER (FIGURE 3) DH3 LX3 BST5 DH5 LX5 LDO5 DL5 LDO5 DL3 PGND FB3 ON5 FB DECODE (FIGURE 5) FB DECODE INTERNAL (FIGURE 5) FB FB5 ON3 REF PGDALL POWER-GOOD AND FAULT PROTECTION (FIGURE 6) R SECONDARY FEEDBACK DSCHG3 FAULT DSCHG5 2.0V REF GND R DRVA AUXILIARY LINEAR REGULATOR OUTA FBA ONA MAX17003A MAX17004A Figure 2. Functional Diagram 18 ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Fixed-Frequency, Current-Mode PWM Controller The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums two signals: the output-voltage error signal with respect to the reference voltage and the slope-compensation ramp (Figure 3). The MAX17003A/MAX17004A use a directsumming configuration, approaching ideal cycle-tocycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. FROM FB (SEE FIGURE 5) REF SOFT-START SLOPE COMP ON_ SKIP OSC GND FSEL TRI-LEVEL DECODE R Q DH DRIVER S 0.2 x VLIMIT 0.1 x VLIMIT IDLE MODE CURRENT ILIM A = 1/10 PEAK CURRENT LIMIT A = 1.2 NEG CURRENT LIMIT CSL_ S Q CSH_ R DL DRIVER ZERO CROSSING PGND DRVA ONE-SHOT OUTA 5V SMPS ONLY Figure 3. PWM Controller Functional Diagram ______________________________________________________________________________________ 19 MAX17003A/MAX17004A Output Discharge (Soft-Discharge) When the switching regulators are disabled—when ON_ or SHDN is pulled low, or when an output undervoltage fault occurs—the internal soft-discharge gradually decreases the output voltage by pulling DSCHG_ low (see the SMPS Shutdown Waveform in the Typical Operating Characteristics). This slowly discharges the output capacitance, eliminating the negative output voltages caused by quickly discharging the output through the inductor and low-side MOSFET. Both SMPS controllers contain separate soft-shutdown circuits. Table 4. FSEL Configuration Table FSEL SWITCHING FREQUENCY (kHz) LDO5 500 REF 300 GND 200 Frequency Selection (FSEL) The FSEL input selects the PWM mode switching frequency. Table 4 shows the switching frequency based on FSEL connection. High-frequency (500kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultraportable devices where the load currents are lower. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space. Forced-PWM Mode The low-noise forced-PWM mode (SKIP = LDO5) disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while DH_ maintains a duty factor of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forcedPWM operation comes at a cost: the no-load 5V supply current remains between 20mA and 50mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is most useful for avoiding audiofrequency noise and improving load-transient response. Since forced-PWM operation disables the zero-crossing comparator, the inductor current reverses under light loads. Idle-Mode Current-Sense Threshold When pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the currentsense voltage exceeds the idle-mode current-sense threshold. Under light load conditions, the on-time duration depends solely on the idle-mode current-sense threshold, which is 20% (SKIP = GND) of the full-load current-limit threshold set by ILIM, or the low-noise current-sense threshold, which is 10% (SKIP = REF) of the full-load current-limit threshold set by ILIM. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. Therefore, the controller regulates the valley of the output ripple under light load conditions. Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 4). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator senses the inductor current across CSH_ to CSL_. Once VCSH_ - VCSL_ drops below the 3mV zero-crossing, current-sense threshold, the comparator forces DL_ low (Figure 3). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous Light-Load Operation Control (SKIP) The MAX17003A/MAX17004A include a light-load operating mode control input (SKIP) used to enable or disable the zero-crossing comparator for both switching regulators. When the zero-crossing comparator is enabled, the regulator forces DL_ low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the regulator to skip pulses under lightload conditions to avoid overcharging the output. When the zero-crossing comparator is disabled, the regulator is forced to maintain PWM operation under light load conditions (forced PWM). tON(SKIP) = VOUT VINfOSC INDUCTOR CURRENT MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers IPK ILOAD = IPK/2 0 TIME ON-TIME Figure 4. Pulse-Skipping/Discontinuous Crossover Point 20 ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers ILOAD(SKIP) = (VIN − VOUT )VOUT 2VINfOSCL The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output-voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). Output Voltage DC output accuracy specifications in the Electrical Characteristics table refer to the error comparator’s threshold. When the inductor continuously conducts, the MAX17003A/MAX17004A regulate the peak of the output ripple, so the actual DC output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. For PWM operation (continuous conduction), the output voltage is accurately defined by the following equation: ⎛ A ⎞ ⎛V V ⎞ VOUT(PWM) = VNOM ⎜1− SLOPE RIPPLE ⎟ − ⎜ RIPPLE ⎟ ⎝ ⎠ V 2 ⎝ ⎠ IN where V NOM is the nominal output voltage, A SLOPE equals 1.1%, and VRIPPLE is the output ripple voltage (V RIPPLE = ESR x ΔI INDUCTOR, as described in the Output Capacitor Selection section). In discontinuous conduction (IOUT < ILOAD(SKIP)), the MAX17003A/MAX17004A regulate the valley of the output ripple, so the output voltage has a DC regulation level higher than the error-comparator threshold. For PFM operation (discontinuous conduction), the output voltage is approximately defined by the following equation: VOUT(PFM) = VNOM + 1 ⎛ fSW ⎞ IIDLEESR 2 ⎜⎝ fOSC ⎟⎠ where VNOM is the nominal output voltage, fOSC is the maximum switching frequency set by the internal oscillator, fSW is the actual switching frequency, and IIDLE is the idle-mode inductor current when pulse skipping. Connect FB3 and FB5 to LDO5 to enable the fixed SMPS output voltages (3.3V and 5V, respectively), set by a preset, internal resistive voltage-divider connected between the output (CSL_) and analog ground. Connect a resistive voltage-divider at FB_ between the output (CSL_) and GND to adjust the respective output voltage between 2V and 5.5V (Figure 5). Choose RFBLO (resistance from FB to GND) to be approximately 10kΩ and solve for RFBHI (resistance from the output to FB) using the equation: ⎛ VOUT _ ⎞ RFBHI = RFBLO ⎜ −1⎟ ⎝ VFB _ ⎠ where VFB_ = 2V nominal. When adjusting both output voltages, set the 3.3V SMPS lower than the 5V SMPS. LDO5 connects to the 5V output (CSL5) through an internal switch only when CSL5 is above the LDO5 bootstrap threshold (4.5V) and the soft-start sequence for the CSL5 side has completed. Bootstrapping works most effectively when the fixed output voltages are used. Once LDO5 is bootstrapped from CSL5, the internal 5V linear regulator turns off. This reduces the internal power dissipation and improves efficiency at higher input voltages. TO ERROR AMPLIFIER ADJUSTABLE OUTPUT FB LDO5 R 9R OUT FIXED OUTPUT FB = LDO5 Figure 5. Dual Mode Feedback Decoder Current-Limit Protection (ILIM) The current-limit circuit uses differential current-sense inputs (CSH_ and CSL_) to limit the peak inductor current. If the magnitude of the current-sense signal exceeds the current-limit threshold, the PWM controller ______________________________________________________________________________________ 21 MAX17003A/MAX17004A inductor-current operation (also known as the “critical conduction” point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is given by: MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers turns off the high-side MOSFET (Figure 3). The actual maximum load current is less than the peak currentlimit threshold by an amount equal to half of the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (VOUT/VIN). In forced-PWM mode, the MAX17003A/MAX17004A also implement a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when ILIM is adjusted. Connect ILIM to LDO5 for the 50mV default threshold, or adjust the current-limit threshold with an external resistor-divider at ILIM. Use a 2µA to 20µA divider current for accuracy and noise immunity. The current-limit threshold adjustment range is from 50mV to 200mV. In the adjustable mode, the current-limit threshold voltage equals precisely 1/10 the voltage seen at ILIM. The logic threshold for switchover to the default value is approximately VLDO5 - 1V. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSH_ and CSL_. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor. MOSFET Gate Drivers (DH_, DL_) The DH_ and DL_ drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN V OUT differential exists. The high-side gate drivers (DH_) source and sink 2A, and the low-side gate drivers (DL_) source 1.7A and sink 3.3A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by charge pumps at BST_ while the DL_ synchronous-rectifier drivers are powered directly by the fixed 5V linear regulator (LDO5). Adaptive dead-time circuits monitor the DL_ and DH_ drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17003A/MAX17004A interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL_ low is robust, with a 0.6Ω (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require additional gate-to-source capacitance to ensure fast-rising LX_ edges do not pull up the low-side MOSFET’s gate, causing shoot-through currents. The capacitive coupling between LX_ and DL_ created by the MOSFET’s gate-to-drain capacitance (CGD = CRSS), gate-to-source capacitance (CGS = CISS - C GD ), and additional board parasitics should not exceed the following minimum threshold: ⎛C ⎞ VGS(TH) > VIN ⎜ RSS ⎟ ⎝ CISS ⎠ Lot-to-lot variation of the threshold voltage may cause problems in marginal designs. Power-Good Output (PGDALL) PGDALL is the open-drain output of a comparator that continuously monitors both SMPS output voltages for undervoltage conditions. PGDALL is actively held low in shutdown (SHDN = GND), during soft-start, and soft discharge, and when either SMPS is disabled (either ON3 or ON5 low). Once the soft-start sequence terminates, FAULT PROTECTION POWER-GOOD 0.9 x INT REF_ 0.7 x INT REF_ 1.11 x INT REF_ INTERNAL FB ENABLE OVP ENABLE UVP 6144 CLK FAULT LATCH POWER-GOOD POR Figure 6. Power-Good and Fault Protection 22 FAULT ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers MODE CONDITION COMMENT Power-Up LDO5 < UVLO threshold Transitions to discharge mode after VIN POR and after REF becomes valid. LDO5, REF remain active. DL_ is low. Run SHDN = high, ON3 or ON5 enabled Normal operation. Output Overvoltage (OVP) Protection (MAX17003A) Either output > 111% of nominal level Exited by POR or cycling SHDN, ON3, or ON5. Output Undervoltage Protection (UVP) Either output < 70% of nominal level, UVP is enabled 6144 clock cycles (1/fOSC) after the output is enabled Exited by POR or cycling SHDN, ON3, or ON5. Standby ON5 and ON3 < startup threshold, SHDN = high DL_ stays low. LDO5 active. Shutdown SHDN = low All circuitry off. Thermal Shutdown TJ > +160°C Exited by POR or cycling SHDN, ON3, or ON5. DL3 and DL5 go low before LDO5 turns off. Switchover Fault Excessive current on LDO5 switchover Exited by POR or cycling SHDN, ON3, or ON5. transistors PGDALL becomes high impedance as long as both SMPS outputs are above 90% of the nominal regulation voltage set by FB_. PGDALL goes low once either the SMPS output drops 10% below its nominal regulation point, an SMPS output overvoltage fault occurs, or ON_ or SHDN is low. For a logic-level PGDALL output voltage, connect an external pullup resistor between PGDALL and LDO5. A 100kΩ pullup resistor works well in most applications (see Table 5). Fault Protection Output Overvoltage Protection (OVP)— MAX17003A Only If the output voltage of either SMPS rises above 111% of its nominal regulation voltage and the OVP protection is enabled, the controller sets the fault latch, pulls PGOOD low, shuts down the SMPS controllers that tripped the fault, and immediately pulls DH_ low and forces DL_ high. This turns on the synchronous-rectifier MOSFETs with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. However, immediately latching DL_ high typically causes slightly negative output voltages due to the energy stored in the output LC at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse-polarity clamp. If the condition that caused the overvoltage per- MAX17003A/MAX17004A Table 5. Operating Modes Truth Table sists (such as a shorted high-side MOSFET), the battery blows. The other output is shut down using the softdischarge feature with DL_ forced low. Cycle LDO5 below 1V or toggle either ON3, ON5, or SHDN to clear the fault latch and restart the SMPS controllers. Output Undervoltage Protection (UVP) Each SMPS controller includes an output UVP protection circuit that begins to monitor the output 6144 clock cycles (1/fOSC) after that output is enabled (ON_ pulled high). If either SMPS output voltage drops below 70% of its nominal regulation voltage and the UVP protection is enabled, the UVP circuit sets the fault latch, pulls PGOOD low, and shuts down both controllers using the soft-discharge feature with DL_ forced low. Cycle LDO5 below 1V or toggle either ON3, ON5, or SHDN to clear the fault latch and restart the SMPS controllers. Thermal-Fault Protection The MAX17003A/MAX17004A feature a thermal-faultprotection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch, pulls PGOOD low, and shuts down both SMPS controllers using the soft-discharge feature with DL_ forced low. Toggle either ON3, ON5, or SHDN to clear the fault latch and restart the controllers after the junction temperature cools by 15°C. ______________________________________________________________________________________ 23 MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Auxiliary LDO Detailed Description The MAX17003A/MAX17004A include an auxiliary linear regulator (OUTA) that can be configured for 12V, ideal for PCMCIA power requirements, and for biasing the gates of load switches in a portable device. OUTA can also be configured for outputs from 1V to 23V. The auxiliary regulator has an independent ON/OFF control, allowing it to be shut down when not needed, reducing power consumption when the system is in a low-power state. A flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the primary output is lightly loaded or when there is a low inputoutput differential voltage. If V DRVA < V OUTA , the low-side switch is turned on for a time equal to 33% of the switching period. This reverses the inductor (primary) current, pulling current from the output filter capacitor and causing the flyback transformer to operate in forward mode. The low impedance presented by the transformer secondary in forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing VINA - VOUTA back into regulation. The secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. In this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage. SMPS Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • 24 Maximum Load Current. There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. • Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor Operating Point. This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. Inductor Selection The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT (VIN − VOUT ) VINfOSCILOAD(MAX)LIR For example: ILOAD(MAX) = 5A, VIN = 12V, VOUT = 5V, fOSC = 300kHz, 30% ripple current or LIR = 0.3: L= 5V x (12V − 5V ) 12V x 300kHz x 5A x 0.3 = 6.50μH Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (ΔIINDUCTOR) is defined by: V (V − VOUT ) ΔIINDUCTOR = OUT IN VINfOSCL ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers I PEAK = I LOAD(MAX) + ΔIINDUCTOR 2 Transformer Design (for MAX17003A/MAX17004A Auxiliary Output) A coupled inductor or transformer can be substituted for the inductor in the 5V SMPS to create an auxiliary output (Figure 1). The MAX17003A/MAX17004A are particularly well suited for such applications because the secondary feedback threshold automatically triggers DL5 even if the 5V output is lightly loaded. The power requirements of the auxiliary supply must be considered in the design of the main output. The transformer must be designed to deliver the required current in both the primary and the secondary outputs with the proper turns ratio and inductance. The power ratings of the synchronous-rectifier MOSFETs and the current limit in the MAX17003A/MAX17004A must also be adjusted accordingly. Extremes of low input-output differentials, widely different output loading levels, and high turns ratios can further complicate the design due to parasitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. Power from the main and secondary outputs is combined to get an equivalent current referred to the main output. Use this total current to determine the current limit (see the Setting the Current Limit section): ITOTAL = PTOTAL/VOUT5 where ITOTAL is the equivalent output current referred to the main output, and PTOTAL is the sum of the output power from both the main output and the secondary output: VSEC + VFWD N= VOUT5 + VRECT + VSENSE where N is the transformer turns ratio, VSEC is the minimum required rectified secondary voltage, VFWD is the forward drop across the secondary rectifier, VOUT5(MIN) is the minimum value of the main output voltage, and VRECT is the on-state voltage drop across the synchronous-rectifier MOSFET. The transformer secondary return is often connected to the main output voltage instead of ground to reduce the necessary turns ratio. In this case, subtract VOUT5 from the secondary voltage (VSEC - VOUT5) in the transformer turns-ratio equation above. The secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60V. Common silicon rectifiers, such as the 1N4001, are also prohibited because they are too slow. Fast silicon rectifiers, such as the MURS120, are the only choice. The flyback voltage across the rectifier is related to the VIN - VOUT5 difference, according to the transformer turns ratio: VFLYBACK = VSEC + (VIN – VOUT5) x N where N is the transformer turns ratio (secondary windings/primary windings), and VSEC is the maximum secondary DC output voltage. If the secondary winding is returned to VOUT5 instead of ground, subtract VOUT5 from V FLYBACK in the equation above. The diode’s reverse breakdown voltage rating must also accommodate any ringing due to leakage inductance. The diode’s current rating should be at least twice the DC load current on the secondary output. Transient Response The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The total output-voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur: VSAG = ( L ΔILOAD(MAX) ( )2 2COUT VIN x DMAX − VOUT ΔILOAD(MAX) (t − Δt) ) + COUT where D MAX is the maximum duty factor (see the Electrical Characteristics table), t is the switching period (1/fOSC), and Δt equals VOUT/VIN x t when in PWM mode, or L x 0.2 x IMAX/(VIN - VOUT) when in skip mode. The amount of overshoot during a full-load to noload transient due to stored inductor energy can be calculated as: VSOAR 2 ΔILOAD(MAX) ) L ( ≈ 2COUT VOUT ______________________________________________________________________________________ 25 MAX17003A/MAX17004A Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers INPUT (VIN) CIN MAX17003A MAX17004A DH_ SENSE RESISTOR NH L LESL RSENSE LX_ DL_ NL DL R1 CEQ COUT L CEQR1 = SENSE RSENSE PGND CSH_ CSL_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) CIN MAX17003A MAX17004A DH_ INDUCTOR NH L RDCR RCS = LX_ DL_ NL PGND COUT DL R1 R2 RDCR = ( R1R2+ R2) R L CEQ [R11 + R21 ] CEQ CSH_ CSL_ B) LOSSLESS INDUCTOR SENSING Figure 7. Current-Sense Configurations 26 DCR ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers ILIMIT > ILOAD(MAX) + ⎛⎜ ΔIINDUCTOR ⎞⎟ ⎝ 2 ⎠ where ILIMIT_ equals the minimum current-limit threshold voltage divided by the current-sense resistance (RSENSE_). For the default setting, the minimum currentlimit threshold is 45mV. Connect ILIM to LDO5 for a default 50mV current-limit threshold. In adjustable mode, the current-limit threshold is precisely 1/10 the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM connected to the center tap. The external 0.5V to 2V adjustment range corresponds to a 50mV to 200mV current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10mA to prevent significant inaccuracy in the currentlimit tolerance. The current-sense method (Figure 7) and magnitude determines the achievable current-limit accuracy and power loss. Typically, higher current-sense limits provide tighter accuracy, but also dissipate more power. Most applications employ a current-limit threshold (VLIMIT) of 50mV to 100mV, so the sense resistor can be determined by: V VILIM RCS = LIMIT = 10 x ILIMIT ILIMIT For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 7A. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. However, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. This parasitic inductance (LESL) can be canceled by adding an RC circuit across the sense resistor with an equivalent time constant: CEQR1 = LESL RSENSE Alternatively, high-power applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 7B) with an equivalent time constant: ⎛ R2 ⎞ RCS = ⎜ ⎟ RDCR ⎝ R1 + R2 ⎠ and: RDCR = L CEQ 1⎤ ⎡1 ⎢ R1 + R2 ⎥ ⎣ ⎦ where RCS is the required current-sense resistance, and RDCR is the inductor’s series DC resistance. Use the typical inductance and RDCR values provided by the inductor manufacturer. Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors (see stability requirements), the filter capacitor’s ESR dominates the output voltage ripple. So the output capacitor’s size depends on the maximum ESR required to meet the output voltage ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P-P) = RESRILOAD(MAX)LIR In idle-mode, the inductor current becomes discontinuous, with peak currents set by the idle-mode current-sense threshold (VIDLE = 0.2VLIMIT). In idle-mode, the no-load output ripple can be determined as follows: V R VRIPPLE(P–P) = IDLE ESR RSENSE ______________________________________________________________________________________ 27 MAX17003A/MAX17004A Setting the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The peak inductor current occurs at ILOAD(MAX) plus half the ripple current; therefore: MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high ESR zeros that may affect the overall stability (see the OutputCapacitor Stability Considerations section). Output-Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR ≤ OSC π where: fESR = 1 2πRESR COUT For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OSCON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.5A = 16.7mΩ. One 220µF/4V SANYO polymer (TPE) capacitor provides 15mΩ (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. 28 For low-input-voltage applications where the duty cycle exceeds 50% (VOUT/VIN ≥ 50%), the output ripple voltage should not be greater than twice the internal slopecompensation voltage: VRIPPLE ≤ 0.02 x VOUT where VRIPPLE equals ΔIINDUCTOR x RESR. The worstcase ESR limit occurs when VIN = 2 x VOUT, so the above equation can be simplified to provide the following boundary condition: RESR ≤ 0.04 x L x fSW Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: short/long pulses and cycle skipping resulting in lower frequency operation. Instability occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering too early or into skipping a cycle. Cycle skipping is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It may help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than three cycles of ringing after the initial step-response under/overshoot. ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers MAX17003A/MAX17004A INPUT CAPACITOR RMS CURRENT vs. INPUT VOLTAGE 5.0 4.5 4.0 IN PHASE IRMS (A) 3.5 3.0 50/50 INTERLEAVING 2.5 2.0 1.5 40/60 OPTIMAL INTERLEAVING 1.0 0.5 0 6 8 10 12 14 16 18 20 VIN (V) INPUT RMS CURRENT FOR INTERLEAVED OPERATION: IRMS = (IOUT 5 − IIN )2 (DLX 5 − DOL ) + (IOUT3 − IIN )2 (DLX3 − DOL ) + (IOUT 5 + IOUT3 V V DLX 5 = OUT 5 DLX 3 = OUT3 VIN VIN VOUT 5IOUT 5 + VOUT3IOUT3 IIN = VIN − IIN )2 DOL + IIN2 (1 − DLX5 − DLX3 + DOL ) DOL = DUTY − CYCLE OVERLAP FRACTION INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION: ( ⎛ V OUT VIN − VOUT IRMS = ILOAD ⎜⎜ VIN ⎜⎝ ) ⎞⎟ ⎟ ⎟⎠ Figure 8. Input RMS Current Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. For an out-of-phase regulator, the total RMS current in the input capacitor is a function of the load currents, the input currents, the duty cycles, and the amount of overlap as defined in Figure 8. For most applications, nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. Choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime. The 40/60 optimal interleaved architecture of the MAX17003A/MAX17004A allows the input voltage to go as low as 8.3V before the duty cycles begin to overlap. This offers improved efficiency over a regular 180° outof-phase architecture where the duty cycles begin to overlap below 10V. Figure 8 shows the input-capacitor RMS current vs. input voltage for an application that requires 5V/5A and 3.3V/5A. This shows the improvement of the 40/60 optimal interleaving over 50/50 interleaving and in-phase operation. Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with Power-MOSFET Selection ______________________________________________________________________________________ 29 MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX17003A/MAX17004A DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology. Power-MOSFET Dissipation Worst-case conduction losses occur at the duty-factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: ⎛V ⎞ 2 PD (NH Re sistive) = ⎜ OUT ⎟ (ILOAD ) RDS(ON) V ⎝ IN ⎠ Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turnon and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH Re sistive) = COSS VIN(MAX) ⎞ ⎛ ILOADQG(SW ) + ⎜ ⎟ VIN(MAX)fSW IGATE 2 ⎝ ⎠ 30 where COSS is the output capacitance of NH, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (1A, typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage: PD (NL Re sistive) = ⎡ ⎛ VOUT ⎞ ⎤ 2 ⎢1 − ⎜ ⎟ ⎥(ILOAD ) RDS(ON) V ⎢⎣ ⎝ IN(MAX) ⎠ ⎥⎦ The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ⎛ ΔI ⎞ ILOAD = ILIMIT − ⎜ INDUCTOR ⎟ ⎝ ⎠ 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers where QGATE is the total gate charge specified in the high-side MOSFET’s data sheet. For example, assume the FDS6612A n-channel MOSFET is used on the high side. According to the manufacturer’s data sheet, a single FDS6612A has a maximum gate charge of 13nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 13nC = 0.065μF 200mV Selecting the closest standard value, this example requires a 0.1µF ceramic capacitor. LDOA Design Procedure Output Voltage Selection Adjust the auxiliary linear regulator’s output voltage by connecting a resistive divider between OUTA and analog ground with the center tap connected to FBA (Figure 1). Select R6 in the 10kΩ to 30kΩ range, and calculate R5 with the following equation: ⎛V ⎞ R5 = R6⎜ OUTA − 1⎟ ⎝ VFBA ⎠ where VFBA = 1.0V. Transistor Selection The pass transistor must meet specifications for current gain (β), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor’s current gain limits the guaranteed maximum output current to: ⎛ ILOAD(MAX) = ⎜IDRV − VBE R BE ⎝ ⎞ ⎟ βMIN ⎠ where IDRV is the minimum guaranteed base drive current, VBE is the base-to-emitter voltage of the transistor, and RBE is the pullup resistor connected between the transistor’s base and emitter. Furthermore, the transistor’s current gain increases the linear regulator’s DC loop gain (see the LDOA Stability Requirements section), so excessive gain destabilizes the output. Therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not recommended. The transistor’s input capacitance and input resistance also create a second pole, which could be low enough to make the output unstable when heavily loaded. The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports. Alternatively, the package’s power dissipation could limit the usable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor’s package and mounting must exceed the actual power dissipation in the device. The power dissipation equals the maximum load current times the maximum input-to-output differential: PWR = ILOAD(MAX) (VINA - VOUTA) PWR = ILOAD(MAX) VCE LDOA Stability Requirements The MAX17003A/MAX17004A linear-regulator controller uses an internal transconductance amplifier to drive an external pnp pass transistor. The transconductance amplifier, the pass transistor, the base-to-emitter resistor, and the output capacitor determine the loop stability. The transconductance amplifier regulates the output voltage by controlling the pass transistor’s base current. The total DC loop gain is approximately: ⎛ 5.5V ⎞ ⎛ IBIAShFE ⎞ A V(LDO) = ⎜ ⎟ ⎟ ⎜1 + I V ⎝ T ⎠⎝ LOAD ⎠ where VT is 26mV at room temperature, hFE is the pass transistor’s DC gain, and IBIAS is the current through the base-to-emitter resistor (RBE). The 680Ω base-toemitter resistor used in Figure 1 was chosen to provide a 1mA bias current (IBIAS). ______________________________________________________________________________________ 31 MAX17003A/MAX17004A Q CBST = GATE 200mV MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers The output capacitor and the load resistance create the dominant pole in the system. However, the internal amplifier delay, the pass transistor’s input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor’s ESR generates a zero. For proper operation, use the following steps to ensure the linear-regulator stability: 1) First, calculate the dominant pole set by the linear regulator’s output capacitor and the load resistor: fPOLE(LDO) = 1 2πCOUTARLOAD where COUTA is the output capacitance of the auxiliary LDO and RLOAD is the load resistance corresponding to the maximum load current. The unitygain crossover of the linear regulator is: fCROSSOVER = AV(LDO)fPOLE(LDO) 2) The pole caused by the internal amplifier delay is at approximately 1MHz: f POLE(AMP) ≈ 1MHz 3) Next, calculate the pole set by the transistor’s input capacitance, the transistor’s input resistance, and the base-to-emitter pullup resistor. Since the transistor’s input resistance (hFE/gm) is typically much greater than the base-to-emitter pullup resistance, the pole can be determined from the simplified equation: 1 fPOLE(CIN) ≈ 2πCINRIN gm CIN = 2πfT where gm is the transconductance of the pass transistor, and fT is the transition frequency. Both parameters can be found in the transistor’s data sheet. Therefore, the equation can be further reduced to: f f POLE(CIN) ≈ T hFE 4) Next, calculate the pole set by the linear regulator’s feedback resistance and the capacitance between FBA and ground (approximately 5pF including stray capacitance): f POLE(FBA) = 32 1 2πCFBA (R5 || R6) 5) Next, calculate the zero caused by the output capacitor’s ESR: fZERO(ESR) = 1 2πCOUTARESR where RESR is the equivalent series resistance of COUTA. 6) To ensure stability, choose COUTA large enough so that the crossover occurs well before the poles and zero calculated in steps 2 through 5. The poles in steps 3 and 4 generally occur at several MHz, and using ceramic output capacitors ensures the ESR zero occurs at several MHz as well. Placing the crossover frequency below 500kHz is typically sufficient to avoid the amplifier delay pole and generally works well, unless unusual component selection or extra capacitance moves the other poles or zero below 1MHz. A capacitor connected between the linear regulator’s output and the feedback node can improve the transient response and reduce the noise coupled into the feedback loop. If a low-dropout solution is required, an external pchannel MOSFET pass transistor could be used. However, a pMOS-based linear regulator requires higher output capacitance to stabilize the loop. The high gate capacitance of the p-channel MOSFET lowers the fPOLE(CIN) and can cause instability. A large output capacitance must be used to reduce the unity-gain bandwidth and ensure that the pole is well above the unity-gain crossover frequency. Applications Information Duty-Cycle Limits Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). Keep in mind that the transient performance gets worse as the stepdown regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Transient Response section of the SMPS Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). This results in a minimum operating voltage defined by the following equation: ⎛ 1 ⎞ VIN(MIN) = VOUT + VCHG + h⎜ − 1⎟ (VOUT + VDIS ) ⎝ DMAX ⎠ ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Maximum Input Voltage The MAX17003A/MAX17004A controllers include a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by SKIP. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): ⎛ ⎞ 1 VIN(SKIP) = VOUT ⎜ ⎟ ⎝ fOSCt ON(MIN) ⎠ where fOSC is the switching frequency selected by FSEL. PCB Layout Guidelines Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 9). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCB (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • Minimize current-sensing errors by connecting CSH_ and CSL_ directly across the current-sense resistor (RSENSE_). • When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. • Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSH_, CSL_). Layout Procedure Place the power components first, with ground terminals adjacent (N L _ source, C IN , C OUT _, and D L _ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, GND, and the DH_ and the DL_ gate-drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. Group the gate-drive components (BST_ capacitor, LDO5 bypass capacitor) together near the controller IC. Make the DC-DC controller ground connections as shown in Figures 1 and 9. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. ______________________________________________________________________________________ 33 MAX17003A/MAX17004A where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers MAX17003A/MAX17004A CONNECT THE EXPOSED PAD TO ANALOG GND VIA TO POWER GROUND REF BYPASS CAPACITOR SINGLE n-CHANNEL MOSFETS CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN DUAL n-CHANNEL MOSFET KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO THE EVALUATION KIT) INDUCTOR INDUCTOR DH LX DL CIN COUT CIN INPUT COUT INPUT COUT GROUND OUTPUT HIGH-POWER LAYOUT OUTPUT GROUND LOW-POWER LAYOUT Figure 9. PCB Layout Table 6. Functional Differences Between MAX8744/MAX8745 and MAX17003A/MAX17004A FEATURE MAX8744/MAX8745 MAX17003A/MAX17004A Startup Startup operating mode depends on the SKIP# setting. (e.g., SKIP is low, then startup occurs in skip mode). Startup is always in low-noise pulse-skipping mode (i.e., same as SKIP = REF setting). This allows for startup into prebiased outputs. The SKIP setting takes effect once the SMPS is in regulation. Actively discharges the output down to zero. Soft discharge of the output using the DSCHG3 and DSCHG5 pins. Shutdown DL3 and DL5 are high in shutdown. DL3 and DL5 DL3 and DL5 are latched high during an OV fault of States the respective output (MAX8744 only). Power-Good DL3 and DL5 are low in shutdown. DL3 and DL5 are latched high during an OV fault of the respective output (MAX17003A only). PGOOD3: Power-good indicator for SMPS3. PGDALL: Power-good indicator for SMPS3 and SMPS5. PGOOD5: Power-good indicator for SMPS5. PGOODA: Power-good indicator for the auxiliary LDO. Auxiliary LDO does not have power-good indicator. Chip Information TRANSISTOR COUNT: 6897 PROCESS: BiCMOS 34 ______________________________________________________________________________________ High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers QFN THIN.EPS ______________________________________________________________________________________ 35 MAX17003A/MAX17004A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX17003A/MAX17004A High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.