MAXIM MAX9960BCTM

19-3441; Rev 0; 10/04
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
♦ Dual Supervoltage Switch Arrays
♦ 3Ω, 8pF, 600MHz Bandwidth Pin Electronics Paths
♦ 13V Flash Programming Paths
♦ On-Chip 1x and 2x Selectable Gains
♦ 2 Kelvin PMU Paths
♦ Fast Switching: 350ns (typ)
♦ Monotonic Slew Rate When Switching Between
PE_ and FVHH_
Ordering Information
TEMP
PIN-PACKAGE*
RANGE
PART
MAX9960BCTM
0oC to
+70oC
PKG
CODE
48 Thin QFN-EP**
(7mm x 7mm x 0.8mm)
T4877-6
*See full package information at the end of this data sheet.
**EP = Exposed pad.
VSS
PE1
N.C.
DUT1
VSS
PMUSB1
PMUSA1
PMUSBEN1
PMUSAEN1
TOP VIEW
PMUFBEN1
PE/FVHHEN1
Pin Configuration
PMUFAEN1
The MAX9960 dual-flash-pin electronics/supervoltage
switch matrix replaces most of the relays and switches
commonly needed to connect system resources to
each of two pins in a flash memory or SOC ATE system
(Figure 1). The device provides seven switches per
channel to select up to four independent sources: the
pin electronics (PE), two parametric measurement units
(PMUs) or other Kelvin analog resources, and a flash
memory programming supervoltage (FV HH _). The
force-and-sense PMU switches are independently controlled, enabling their use to connect two non-Kelvin
resources in place of each PMU or Kelvin resource.
Each MAX9960 contains two complete seven-switch
channels with fully independent controls.
The MAX9960 features signal path switches with wide
600MHz bandwidth, low 3Ω series resistance, and low
8pF shunt capacitance over a voltage range compatible with common pin electronics ICs. An on-chip voltage-doubling buffer with selectable 1x or 2x gain
generates the flash supervoltage, allowing a 6.5V DAC
reference input to generate up to a maximum of 13V for
flash-memory programming levels.
When switching from the FVHH_ to PE_ or from PE_ to
FVHH_, the device-under-test (DUT_) voltage behaves
monotonically. Switching transitions between the PE_
and FVHH_ inputs are typically less than 350ns.
The MAX9960 operates over a commercial 0°C to
+70°C temperature range, and is available in the 48-pin
thin QFN package (7mm x 7mm x 0.8mm) with an
exposed pad on the bottom for heat removal.
Features
48 47 46 45 44 43 42 41 40 39 38 37
PE/FVHHSEL1
1
36
PMUFA1
GND
2
35
PMUFB1
Flash Memory Automatic Test Equipment
VL
3
34
VSS
SOC Automatic Test Equipment
V+
4
33
FVHHIN1
VSS
5
32
FVHHREF1
N.C.
6
31
VDD
VDD
7
30
VDD
VSS
8
29
FVHHREF2
V+
9
28
FVHHIN2
VL 10
27
VSS
GND 11
26
PMUFB2
PE/FVHHSEL2 12
25
PMUFA2
Applications
MAX9960
VSS
PE2
N.C.
DUT2
VSS
PMUSB2
PMUSA2
PMUSBEN2
PMUFBEN2
PMUSAEN2
PMUFAEN2
PE/FVHHEN2
13 14 15 16 17 18 19 20 21 22 23 24
QFN THIN
7mm x 7mm 0.8mm
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9960
General Description
MAX9960
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +26V
VDD to GND .........................................................-0.3V to +16.5V
VSS to GND............................................................-6.5V to +0.3V
VL to GND.................................................................-0.3V to +6V
V+ to VSS .............................................................................+32V
Digital Inputs.....................................(GND - 0.3V) to (VL + 0.3V)
FVHHIN_ ....................................................(the higher of -4V and
(VSS - 0.3V)) to (the lower of +10V and (VDD + 0.3V))
All Other Pins ...................................(VSS - 0.3V) to (VDD + 0.3V)
Continuous Current, PE_ ................................................±120mA
Continuous Current, PMUS_ _ ..........................................±10mA
Continuous Current, PMUFA_ + PMUFB_ +
(FVHH_ Path) ................................................................±45mA
Peak Current (100ns), PE_ .............................................±300mA
Peak Current (100ns), PMUS__ ........................................±20mA
Peak Current (100ns), PMUFA_ + PMUFB_ +
(FVHH_ Path) ................................................................±70mA
Package Continuous Power Dissipation (TA = +70°C)
48-Pin QFN-EP, on Single-Layer Board
(derate 27.8mW/°C above +70°C) .............................2222mW
48-Pin QFN-EP, on Multilayer Board
(derate 40.0mW/°C above +70°C) .............................3200mW
Operating Temperature Range...............................0°C to +70°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted. Specifications at TA = 0°C and TA = +70°C
are guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDUT_ = +2.5V, ISW = -40mA to +40mA,
TA = 0°C to +30°C (Note 1)
2.5
3.0
3.5
VDUT_ = +2.5V, ISW = -40mA to +40mA,
TA = +30°C to +70°C (Note 1)
2.5
4.2
VDUT_ = 0 to +5V (Note 1)
-0.6
+0.6
Ω
VDUT_ = +2.5V, ISW = -40mA to +40mA
Ω
DC CHARACTERISTICS
PE_ PATH
On-Resistance
On-Resistance Flatness
Ch1 to Ch2 Resistance Match
RON
RFLAT(ON)
RMATCH
Ω
-0.5
+0.5
Signal Voltage Range
VPE
-3.5
+8.0
V
Operating DC Current Range
ISW
-40
+40
mA
32
100
Ω
FVHH_
-1.5
VDD 1.5
V
ISW
-10
+10
mA
70
Ω
FVHH_ PATH
On-Resistance
Operating Voltage Range
Operating DC Current Range
RON
FVHH_ = -1.5V to (VDD - 1.5V),
IHH_ = -10mA to +10mA (Notes 1, 2)
FORCE PATHS
On-Resistance
Operating Voltage Range
Operating DC Current Range
RON
VPMUF_ _ = -4.25V to +14.5V,
IPMUF_ _ = -25mA to +25mA (Note 1)
VPMUF
-4.25
+14.5
V
ISW
-25
+25
mA
1250
Ω
SENSE PATHS
On-Resistance
2
RON
VPMUS_ _ = -4.25V to +14.5V,
IPMUS_ _ = -1mA to +1mA (Note 1)
_______________________________________________________________________________________
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted. Specifications at TA = 0°C and TA = +70°C
are guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) (Figure 1)
PARAMETER
Operating Voltage Range
Operating DC Current Range
SYMBOL
MAX
UNITS
VPMUS
CONDITIONS
-4.25
MIN
TYP
+14.5
V
ISW
-1
+1
mA
FVHH_ BUFFERS
DC Output Current
IODC
Current Limit
ILIM
Operating Voltage Range
Linearity Error
FVHH
LER_FVHH
Gain
Output Offset Temperature
Coefficient
Input Bias Current
Gain Resistor Current
+15
+25
DUT_ sinking current
-25
-15
FVHHREF_ = 0 (Note 2)
-1.5
VDD 1.5V
V
-2
+2
mV
2.02
V/V
+50
mV
FVHHREF_ = 0; no load; relative to 2-point
line between VDUT_ = 0 and +13V;
measured at VDUT_ = +3.25V, +6.5V, and
+9.75V
VOS_FVHH FVHHREF_ = 0, VDUT_ = +12V, no load
-50
TC_VOS
mA
DUT_ sourcing current
1.98
VDUT_ = 0 to +13V, FVHHREF_ = 0,
TCASE = +30°C to +50°C
2.00
±0.2
mA
mV/°C
FVHHIN_ = -1.5V to +7.5V,
FVHHREF_ = open
-25
+25
µA
FVHHREF
(Note 4)
-1.5
+0.5
V
IVHHREF
Measured with FVHHIN_ = +5V,
FVHHREF_ = 0
IFVHH
Gain Resistor Ground
10
FVHHREF_ = 0, no load,
VDUT_ = 0 to +13V (Note 3)
GFVHH
Output Offset
FVHH = -1.5V to (VDD - 1.5V)
0.4
mA
LEAKAGE (Notes 5, 6)
DUT_ Leakage, Disabled
ILEAK_OFF
Switches S1, S2, S6, S7 open;
VDUT_ = -4.25V to +14.5V
-1
+1
nA
PE_ Leakage
ILEAK_PE
S1 closed; S2, S6, S7 open;
VDUT_ = -3.5V to +8V
-1
+1
nA
S2, S4, S6 closed; S1, S3, S5, S7 open;
VDUT_ = -4.25V to +14.5V
-1
+1
nA
S2, S5, S7 closed; S1, S3, S4, S6 open;
VDUT_ = -4.25V to +14.5V
-1
+1
nA
S4, S6 open; VPMUFA_ = -4.25V to +14.5V;
measured at PMUFA_ with PMUSA_
externally connected to PMUFA_
-1
+1
nA
S5, S7 open; VPMUFB_ = -4.25V to +14.5V;
measured at PMUFB_ with PMUSB_
externally connected to PMUFB_
-1
+1
nA
PMUA_ Path Leakage, Enabled
ILEAK_PMU
A_ON
PMUB_ Path Leakage, Enabled
ILEAK_PMU
B_ON
PMUA_ Path Leakage, Disabled
PMUB_ Path Leakage, Disabled
ILEAK_PMU
A_OFF
ILEAK_PMU
B_OFF
DIGITAL INPUTS (PMUF_EN_, PMUS_EN_, PE/FVHHEN_, PE/FVHHSEL_)
Input High Voltage
VIH
Input Low Voltage
VIL
+2.3
V
+0.4
V
_______________________________________________________________________________________
3
MAX9960
ELECTRICAL CHARACTERISTICS (continued)
MAX9960
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted. Specifications at TA = 0°C and TA = +70°C
are guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) (Figure 1)
PARAMETER
Input Voltage Range
Input Current
SYMBOL
CONDITIONS
MAX
UNITS
-0.2
VL
V
-10
+10
µA
15
16.0
V
-6.00
-5
-4.25
V
23
24
25
V
3.0
3.3
3.6
V
∑ (IDD, I+)
V+ = +24V, VDD = +15V,
VSS = -5V, VL = +3.3V,
FVHHIN_ = +6.5V, FVHHREF_ = 0,
all digital inputs = +2.3V, no loads
10
mA
ISS
V+ = +24V, VDD = +15V,
VSS = -5V, VL = +3.3V,
FVHHIN_ = +6.5V, FVHHREF_ = 0,
all digital inputs = +2.3V, no loads
8.5
mA
IVL
V+ = +24V, VDD = +15V,
VSS = -5V, VL = +3.3V,
FVHHIN_ = +6.5V, FVHHREF_ = 0,
all digital inputs = +2.3V, no loads
2
mA
PDQ
V+ = +24V, VDD = +15V,
VSS = -5V, VL = +3.3V,
FVHHIN_ = +6.5V, FVHHREF_ = 0,
all digital inputs = +2.3V, no loads
200
mW
VIN
IIH, IIL
VIN = -0.2V to VL
MIN
TYP
POWER SUPPLIES
Positive Supply
VDD
Negative Supply
VSS
High Voltage Supply
V+
Logic Supply
VL
Quiescent Positive Supply
Current
Quiescent Negative Supply
Current
Quiescent Logic Supply Current
Quiescent Power Dissipation
14.5
(Note 1)
AC CHARACTERISTICS
SWITCHING TIMES BETWEEN PE_ AND FVHH_ PATHS (Note 7) (Figure 3)
Switch PE_ to FVHH_
tON_FVHH
FVHH_ Settling Time
tS_FVHH
Switch FVHH_ to PE_
tON_PE
PE_ Settling Time
tS_PE
+5V to +7V transition
275
425
0 to +13V transition
350
500
Settling to within larger of 1% step voltage
or 50mV of final value
500
300
Settling to within larger of 1% step voltage
or 50mV of final value
PE_ TO FVHH_
Overshoot/Undershoot
SRMIN
ns
425
ns
500
ns
±100
mV
±150
mV
±10
V/µs
VPE_ = +5V from 47Ω source
150
ns
FVHHIN_ = +2.5V, FVHHREF_ = 0
350
ns
PE_ to FVHH_ Preshoot
Minimum Switching Slew Rate
ns
Over 20% to 80% region
SWITCHING TIMES, SAME PATH (Note 8) (Figure 2)
PE_ Switch On-Time
FVHH_ Switch On-Time
4
tON_1
tON_2,3
_______________________________________________________________________________________
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted. Specifications at TA = 0°C and TA = +70°C
are guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PMUF_ _ Switch On-Time
tON_2,4
tON_2,5
VPMUF_ _ = +5V
150
ns
PMUS_ _ Switch On-Time
tON_6
tON_7
VPMUS_ _ = +5V
300
ns
PE_, FVHH_, PMUF_ _, PMUS_ _
Switch Off-Times
tOFF
700
ns
All switches disconnected, for frequencies
greater than 2MHz (Note 9)
20
pF
Switch S1 closed, all others open, for
frequencies greater than 2MHz
8
CAPACITANCE AND BANDWIDTH (Note 5)
Capacitance, All Paths
Disconnected
Capacitance, PE_ Path
Connected (Note 9)
Unit-to-Unit Variation, PE_ Path
Connected
CDUT_OFF
CDUT_PE
∆CDUT_PE
pF
Switch S1 closed, all others open, for
frequencies less than 1kHz
50
Switch S1 closed, all others open, for
frequencies greater than 2MHz (Note 9)
±2
pF
Capacitance, PMUFA_ and
PMUSA_ Path Connected
CDUT_PMUA
S2, S4, and S6 closed; all others open
(Note 9)
35
pF
Capacitance, PMUFB_ and
PMUSB_ Path Connected
CDUT_PMUB
S2, S5, and S7 closed; all others open
(Note 9)
35
pF
Capacitance, PMUFA_ Path
Disconnected
CPMUFA_OFF S4 open, measured at PMUFA_ (Note 9)
10
pF
Capacitance, PMUFB_ Path
Disconnected
CPMUFB_OFF S5 open, measured at PMUFB_ (Note 9)
10
pF
Capacitance, PMUSA_ Path
Connected
CPMUSA_ON
S6 closed, all others open, measured at
PMUSA_ (Note 9)
10
pF
Capacitance, PMUSB_ Path
Connected
CPMUSB_ON
S7 closed, all others open, measured at
PMUSB_ (Note 9)
10
pF
Capacitance, PMUSA_ Path
Disconnected
CPMUSA_OFF S6 open, measured at PMUSA_ (Note 9)
5
pF
Capacitance, PMUSB_ Path
Disconnected
CPMUSB_OFF S7 open, measured at PMUSB_ (Note 9)
5
pF
Only PE_ path enabled (Note 10)
600
MHz
FVHHREF_ = 0, (gain = 2), FVHHIN_
stepped from 0 to +5V and +5V to 0
±5
V/µs
CDUT_ = 200pF to within 0.1% of step
voltage, after FVHHIN_ changes
25
CDUT_ = 4000pF to within 0.1% of step
voltage, after FVHHIN_ Changes (Note 11)
50
PE_ Signal Bandwidth
f3DB
FVHH_ BUFFER
Slew Rate
Settling
SRFVHH
tS
µs
_______________________________________________________________________________________
5
MAX9960
ELECTRICAL CHARACTERISTICS (continued)
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted. Specifications at TA = 0°C and TA = +70°C
are guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) (Figure 1)
V+ should be at least 8V above VDD to guarantee specified path resistance values.
When the FVHH_ buffer is configured for a gain of +1 (FVHHREF_ open), the output voltage range is limited to -1.5V to
+7.5V.
Note 3: FVHH_ buffer gain is typically +1, when FVHHREF_ is open.
Note 4: FVHHREF_ is tested by repeating the FVHH_ path resistance tests over the variation of FVHHREF_. For each value of
FVHHREF_, FVHHIN_ is adjusted to FVHHIN_ = (FVHH_ + FVHHREF_) / 2.
Note 5: All measurements taken at DUT_, except where noted.
Note 6: These specifications are guaranteed by design and characterization. In addition, these specifications will be production
tested with min/max test limits of ±10nA.
Note 7: Voltage source driving PE_ has 47Ω source resistance. PE_ = 0 to +5.0V, FVHH_ = +7 to +13V. Measured from 50% point
of input logic to 90% of analog swing.
Note 8: All unused switches open, unless otherwise noted. Measured from 50% point of input logic to 90% of analog swing.
Note 9: Unless otherwise noted, measured at DUT_. No external connections to any of the switched analog pins—PE_, DUT_,
PMUFA_, PMUFB_, PMUSA_, or PMUSB_—except as needed to make measurement.
Note 10: ZDUT_ = 50Ω; equivalent bandwidth calculated from measured DUT_ rise and fall time with PE_ stimulated by a 3V step
with 1ns 10% to 90% rise/fall time.
Note 11: The maximum load for FVHH buffer is 4000pF.
Note 1:
Note 2:
Typical Operating Characteristics
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted.)
FORCE PATH RESISTANCE vs. VOLTAGE
IPATH = 25mA
70
5
4
3
60
IPATH = 1mA
900
PATH RESISTANCE (Ω)
PATH RESISTANCE (Ω)
6
SENSE PATH RESISTANCE vs. VOLTAGE
1000
MAX9960 toc02
MAX9960 toc01
IPATH = 40mA
7
50
40
30
800
700
600
500
2
20
400
1
10
300
0
0
-3.50 -2.35 -1.20 -0.05 1.10 2.25 3.40 4.55 5.70 6.85 8.00
VOLTAGE (V)
6
80
MAX9960 toc03
PE PATH RESISTANCE vs. VOLTAGE
8
PATH RESISTANCE (Ω)
MAX9960
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
200
-5.0 -2.5
0
2.5
5.0
7.5 10.0 12.5 15.0
VOLTAGE (V)
-5.0 -2.5
0
2.5
5.0
7.5 10.0 12.5 15.0
VOLTAGE (V)
_______________________________________________________________________________________
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
70
60
50
40
6
4
3
2
20
1
5.0
7.5 10.0 12.5 15.0
PE, VDUT_ = +8V
-0.2
0
10
VOLTAGE (V)
20
30
40
50
60
70
0
10
20
TEMPERATURE (°C)
40
50
60
70
PE_ TO FVHH_ TRANSITIONS
MAX9960 toc07
PE_ TO FVHH_ TRANSITIONS
DUT_
V = 2V/div
DUT_
30
TEMPERATURE (°C)
MAX9960 toc08
2.5
PE/VHHSEL_
PE/VHHSEL_
0
0
t = 250ns/div
VPE_ = +5V, FVHH_ = +7V
t = 250ns/div
VPE_ = 0V, FVHH_ = +13V
FVHH BUFFER OUTPUT OFFSET
vs. TEMPERATURE
FVHH_ SLEW
NO LOAD
FVHHREF_ = 0
1.5
DUT_
1.0
OFFSET (mV)
FVHHIN_
MAX9960 toc10
2.0
MAX9960 toc09
0
0.1
-0.1
V = 1V/div
-5.0 -2.5
0.2
0
0
10
PMUB
VDUT_ = +14.5V
0.3
5
30
PMUA
VDUT_ = +14.5V
0.4
LEAKAGE (nA)
PATH RESISTANCE (Ω)
80
IPATH = 40mA
VPE_ = +2.25V
7
LEAKAGE CURRENT vs. TEMPERATURE
0.5
MAX9960 toc06
MAX9960 toc04
IPATH = 10mA
V = 2V/div
PATH RESISTANCE (Ω)
90
PE PATH RESISTANCE vs. TEMPERATURE
8
MAX9960 toc05
FVHH_ PATH RESISTANCE vs. VOLTAGE
100
0.5
0
-0.5
-1.0
0
-1.5
FVHHIN_ = 0
FVHHREF_ = 0
-2.0
t = 500ns/div
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX9960
Typical Operating Characteristics (continued)
(V+ = +24V, VDD = +15V, VSS = -5V, VL = +3.3V, TA = +25°C, unless otherwise noted.)
MAX9960
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
Pin Description
8
PIN
NAME
1
PE/FVHHSEL1
2, 11
GND
FUNCTION
PE1 or FVHH1 Select. Selects either PE1 or FVHH1 to be connected to DUT1. Force low to select PE1,
force high to select FVHH1.
Ground
3, 10
VL
Logic Power Supply. Nominally 3.3V.
4, 9
V+
Analog Positive Gate-Drive Power Supply. Nominally 24V.
5, 8, 20,
24, 27, 34,
37, 41
VSS
Analog Negative Power Supply. Nominally -5V.
6, 22, 39
N.C.
No Connection. Make no connection to this pin.
7, 30, 31
VDD
Analog Positive Power Supply. Nominally 15V.
12
PE/FVHHSEL2
PE2 or FVHH2 Select. Selects either PE2 or FVHH2 to be connected to DUT2. Force low to select PE2,
force high to select FVHH2.
13
PE/FVHHEN2
PE2 and FVHH2 Enable. Enables PE2 and FVHH2 to be connected to DUT2, as determined by
PE/FVHHSEL2. Force low to enable signal path, force high to disable the signal path.
14
PMUFAEN2
PMUFA2 Enable. Controls the connection of PMUFA2 to DUT2. Force low to connect PMUFA2 to
DUT2, force high to disconnect PMUFA2 from DUT2.
15
PMUSAEN2
PMUSA2 Enable. Controls the connection of PMUSA2 to DUT2. Force low to connect PMUSA2 to
DUT2, force high to disconnect PMUSA2 from DUT2.
16
PMUFBEN2
PMUFB2 Enable. Controls the connection of PMUFB2 to DUT2. Force low to connect PMUFB2 to
DUT2, force high to disconnect PMUFB2 from DUT2.
17
PMUSBEN2
PMUSB2 Enable. Controls the connection of PMUSB2 to DUT2. Force low to connect PMUSB2 to
DUT2, force high to disconnect PMUSB2 from DUT2.
18
PMUSA2
Sense A Analog Output for Channel 2. Kelvin feedback output for the channel 2 force A path.
19
PMUSB2
Sense B Analog Output for Channel 2. Kelvin feedback output for the channel 2 force B path.
21
DUT2
23
PE2
25
PMUFA2
26
PMUFB2
Analog Input Force B for Channel 2. Connects to an external DC resource such as a PMU.
28
FVHHIN2
Analog Supervoltage Input for Channel 2. The voltage applied to FVHHIN2 is amplified as determined
by FVHHREF2 (see the Functional Block Diagram).
29
FVHHREF2
Analog Gain-Setting Input for Channel 2. Sets the gain of the FVHH2 buffer.
32
FVHHREF1
Analog Gain-Setting Input for Channel 1. Sets the gain of the FVHH1 buffer.
33
FVHHIN1
Analog Supervoltage Input for Channel 1. The voltage applied to FVHHIN1 is amplified as determined
by FVHHREF1 (see the Functional Block Diagram).
35
PMUFB1
Analog Input Force B for Channel 1. Connects to an external DC resource such as a PMU.
36
PMUFA1
38
PE1
40
DUT1
42
PMUSB1
Sense B Analog Output for Channel 1. Kelvin feedback output for the channel 1 force B path.
43
PMUSA1
Sense A Analog Output for Channel 1. Kelvin feedback output for the channel 1 force A path.
Analog I/O for Channel 2. Connects to the DUT.
Analog I/O for Channel 2. Connects to the pin electronics I/O.
Analog Input Force A for Channel 2. Connects to an external DC resource such as a PMU.
Analog Input Force A for Channel 1. Connects to an external DC resource such as a PMU.
Analog I/O for Channel 1. Connects to the pin electronics I/O.
Analog I/O for Channel 1. Connects to the DUT.
_______________________________________________________________________________________
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
PIN
NAME
FUNCTION
44
PMUSBEN1
PMUSB1 Enable. Controls the connection of PMUSB1 to DUT1. Force low to connect PMUSB1 to
DUT1, force high to disconnect PMUSB1 from DUT1.
45
PMUFBEN1
PMUFB1 Enable. Controls the connection of PMUFB1 to DUT1. Force low to connect PMUFB1 to
DUT1, force high to disconnect PMUFB1 from DUT1.
46
PMUSAEN1
PMUSA1 Enable. Controls the connection of PMUSA1 to DUT1. Force low to connect PMUSA1 to
DUT1, force high to disconnect PMUSA1 from DUT1.
47
PMUFAEN1
PMUFA1 Enable. Controls the connection of PMUFA1 to DUT1. Force low to connect PMUFA1 to
DUT1, force high to disconnect PMUFA1 from DUT1.
48
PE/FVHHEN1
PE1 and FVHH1 Enable. Enables PE1 and FVHH1 to be connected to DUT1, as determined by
PE/FVHHSEL1. Force low to enable signal path, force high to disable the signal path.
—
EP
Exposed Pad for Heat Removal. Internally biased to VSS. Connect to VSS or leave floating.
Detailed Description
S1
MAX9960
PE_
FVHHIN_
DUT_
FVHH_ S3
R
R
FVHHREF_
S4
S2
PMUFA_
PMUFAEN_
S5
PMUFB_
PMUFBEN_
PE/FVHHEN_
PE/FVHHSEL_
S6
PMUSA_
The MAX9960 is a dual analog switch matrix featuring
two Kelvin PMU paths, a PE path, and a flash programming supervoltage circuit that allows testing of flash
memory using standard PE devices. It makes possible,
without the use of relays, a fully functional pin with both
AC and DC capabilities.
The signal path switches feature 600MHz bandwidth,
3Ω series resistance, and 8pF shunt capacitance over
a voltage range compatible with common pin-electronics ICs. The voltage-doubling buffer, with selectable 1x
or 2x gain, generates the 13V flash memory programming level from a 6.5V input. Configure the switches
using digital inputs PMUFAEN_, PMUSAEN_,
PMUFBEN_, PMUSBEN_, PE/FVHHEN_, and PE/FVHHSEL_ as indicated in Tables 1 and 2.
The switching speed between PE_ and FVHH_ paths is
less than 350ns typical (Figure 3), and during switching, DUT_ behaves monotonically.
FVHH Buffer Load Capacitance
PMUSAEN_
S7
PMUSB_
PMUSBEN_
ONE OF TWO CHANNELS SHOWN.
LOGIC ZERO AT SWITCH = SWITCH CLOSED.
Figure 1. Functional Block Diagram
The maximum load capacitance for the FVHH buffer is
4000pF. While this amount of load capacitance is not
expected during normal operation, an application may
call for the buffer to be connected to a highly capacitive PMU path occasionally for calibration purposes. No
damage to the MAX9960 will result as a consequence
of this condition.
Supervoltage FVHH Buffer Gain
The FV HH buffer gain can be selected using
FVHHREF_. If FVHHREF_ is grounded, the gain of the
buffer is +2. If FVHHREF_ is left floating, the buffer gain
is +1.
_______________________________________________________________________________________
9
MAX9960
Pin Description (continued)
MAX9960
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
Table 1. Switch Control, All Possible Combinations
PMUFAEN_
PMUFBEN_
PMUSAEN_
PMUSBEN_
PE/FVHHEN_
PE/FVHHSEL_
0
X
X
X
X
X
PMUFA_ path connected
X
0
X
X
X
X
PMUFB_ path connected
X
X
0
X
X
X
PMUSA_ path connected
X
X
X
0
X
X
PMUSB_ path connected
X
X
X
X
0
1
FVHH_ path connected
X
X
X
X
0
0
All other combinations
DUT_
PE_ path connected
Every path is disconnected
Table 2. Switch Control, Use Cases
PMUFAEN_
PMUFBEN_
PMUSAEN_
PMUSBEN_
PE/FVHHEN_
PE/FVHHSEL_
1
1
1
1
0
0
PE_
1
1
1
1
0
1
FVHH_
0
1
0
1
1
X
PMUFA_ + PMUSA_
1
0
1
0
1
X
PMUFB_ + PMUSB_
0
1
0
1
0
0
PE_ + PMUFA_ + PMUSA_
1
0
1
0
0
0
PE_ + PMUFB_ + PMUSB_
0
1
0
1
0
1
FVHH_ + PMUFA_ + PMUSA_
1
0
1
0
0
1
FVHH_ + PMUFB_ + PMUSB_
0
0
0
0
0
0
PE_ + PMUFA_ + PMUSA_ +
PMUFB_ + PMUSB_
DUT_
Power-Supply Considerations
The MAX9960 requires four power-supply voltages,
typically V+ = +24V, VDD = +15V, VSS = -5V, and VL =
+3.3V. Use a 0.1µF bypass capacitor close to each
supply pin, and provide bulk bypassing where power
enters the circuit board. The MAX9960 does not require
any special power-up sequencing.
MAX9960
PMUS_ _
PMUF_ _
Chip Information
TRANSISTOR COUNT: 2020
PROCESS: BiCMOS
FVHHIN_
FVHH_
47Ω PE_
DUT_
1kΩ
Figure 2. Switching Time Test Circuit
10
______________________________________________________________________________________
200pF
Dual-Flash-Pin Electronics/Supervoltage
Switch Matrix
MAX9960
PE _ TO FVHH_
TRANSITION
MINIMUM
SWITCHING
SLEW RATE
OVERSHOOT
SETTLING
PRESHOOT
VFVHH_
90%
OVERSHOOT
SETTLING
10%
VPE_
PRESHOOT
tON_PE
tON_FVHH
tS_PE
tS_FVHH
PE/FVHHSEL_
Figure 3. PE_ - FVHH_ and FVHH_ - PE_ Transition and Settling Timing
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.