SC2616 Complete DDR Power Solution POWER MANAGEMENT Description Features The SC2616 is a fully integrated DDR power solution providing power for the VDDQ and the VTT rails. The SC2616 also completely adheres to the ACPI sleep state power requirements. A synchronous buck controller provides the high current of the VDDQ at high efficiency, while a linear sink/source regulator provides the termination voltage with 2 Amp Source/Sink capability. This approach makes the best trade-off between cost and performance. Additional logic and UVLOs complete the functionality of this single chip DDR power solution in compliance with S3 and S5 motherboard signals. High efficiency (90%) switcher for VDDQ supplies 20 Amps High current gate drives Single chip solution complies fully with ACPI power sequencing specifications Internal S3 state LDO supplies high standby VDDQ current (0.65Amp Min.) The SC2616 is capable of sourcing up to 20A at the switcher output, and 2A source/sink at the VTT output. The MLP package provides excellent thermal impedance while keeping small footprint. VDDQ current limit as well as 3 independent thermal shutdown circuits assure safe operation under all fault conditions. ACPI sleep state controlled 2 Amp VTT source/sink capability UVLO on 5V and 12V Independent thermal shutdown for VDDQ and VTT Fast transient response 18 pin MLP package Applications Power solution for DDR memory per ACPI motherboard specification High speed data line termination Memory cards Typical Application Circuit 5V 12V Cin 0.1uF 5V STBY 16 0.1uF Suspend to RAM Suspend to disk 4 S3 S5 11 10 18 17 0.1uF 1uF 10k 10k 12 3 12VCC 5VCC 5VSBY TG SLP_S3 BG SLP_S5 PGND SS/EN VDDQSTBY COMP VDDQIN AGND FB LGND VTTSNS VTT VTT 9 L Revision 3, March 2003 VDDQ 15 0.1uF 14 Cout 13 7 8 1 6 5 VTT 0.1uF 19 2 U4 SC2616 HSINKPAD 10uF 1 www.semtech.com SC2616 POWER MANAGEMENT Dual 5V Typical Application Schematic 5V Ins tantly Available ACPI Controller 5V Cin 5VSTBY (SC1549) 12V 5V Dual 0.1uF Cin 1uF 1uF 16 0.1uF Suspend to RAM Suspend to disk 10k 4 S3 S5 11 10 18 17 0.1uF 12 3 12VCC 5VCC 5VSBY TG SLP_S3 BG SLP_S5 PGND SS/EN VDDQSTBY COMP VDDQIN AGND FB LGND VTTSNS VTT VTT 9 L VDDQ 15 14 Cout 0.1uF 13 7 8 1 6 2 AMP 5 VTT 0.1uF 19 2 U4 SC2616 HSINKPAD 10k 5V STBY Figure 1: ACPI controller supplies “always on” 5V supply, eliminating the need for back to back MOSFETs. (see applications section) 2003 Semtech Corp. 2 www.semtech.com SC2616 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage, 5VCC to AGND V 5V C C 7 V Supply Voltage, 12VCC to AGND V 12V C C 15 V Standby Input Voltage V 5V S B Y 7 V I/O 5VSTBY +0.3, AGND -0.3 V 0.3 V IO(VTT) ±2 A Operating Ambient Temperature Range TA 0 to 70 °C Operating Junction Temperature TJ 125 °C Thermal Resistance Junction to Ambient * θJA 25 °C/W Thermal Resistance Junction to Case * θJC 4 °C/W Storage Temperature TSTG -65 to 150 °C Lead Temperature (Soldering) 10seconds TLEAD 300 °C TG/BG DC Voltage 12Vcc + 0.3, AGND -0.5 V TG/BG AC Voltage 12Vcc + 1.0, AGND -1.0 V 2 kV Inputs AGND to PGND or LGND VTT Output Current ESD Rating (Human Body Model) ESD Electrical Characteristics * See Mounting Considerations. Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions Min Typ Max Units 5V Supply Voltage V 5V C C 4.5 5 5.5 V 12V Supply Voltage V 12V C C 10.8 12 13.2 V 5V Standby Voltage V 5V S B Y 4.5 5 5.5 V Quiescent Current IQ(5VSBY) S 0, S 5 1.8 2.5 S3 3.5 5.0 S3/S5 Threshold TTL mA V 12VCC Under Voltage Lockout UVLO12VCC 7 8.2 10 V 5VCC Under Voltage Lockout UVLO5VCC 3.5 3.7 4 V Feedback Reference Feedback Current 1.25 VREF VFB = 1.25V IFB V 2 µA SS/EN Shutdown Threshold VEN(TH) 0.3 V Thermal Shutdown TJ-SHDN 150 °C Thermal Shutdown Hysteresis TJ-HYST 10 °C 2003 Semtech Corp. 3 www.semtech.com SC2616 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions Min Typ Max Units Sw itcher Load Regulation IVDDQ = 0A to 10A; S0; Fig 2: Oscillator Frequency fOSC Soft Start Current ISS 0.2 225 250 % 275 25 Duty Cycle 0 KHz µA 80 % 70 % Overcurrent Trip Voltage VTRIP % of VDDQ Setpoint Top Gate Rise Time TGR Gate capacitance = 4000pF 25 nS Top Gate Fall Time TGF Gate capacitance = 4000pF 25 nS Bottom Gate Rise Time BGR Gate capacitance = 4000pF 35 nS Bottom Gate Fall Time BGF Gate capacitance = 4000pF 35 nS 50 nS 0.8 mS 38 dB 5 MHz ± 60 µA VIN = 5V 19 dB IPWRGD = 1mA, sink 50 400 mV VPWRGD = 5V; S0 0.1 2 µA Dead Time td Error Amplifier Transconductance gm Error Amplifier Gain @ DC A EA Error Amplifier Bandwidth GBW 50 20 RCOMP = open Error Amplifier Source/Sink Current Modulator Gain AM Power Good Low Power Good High Leakage 60 S TB Y LD O Output Current IVDDQSTBY DC current ∆V/∆I IVDDQ = 0A to 750mA; S3; Fig1: 0.5 % ILIM S3 = 0, VTT floating 1 A Output Voltage VTT VVDDQSTBY = 2.500V Source and Sink Currents IVTT Load Regulation Current Limit 750 mA V TT LD O Load Regulation AEA_VTT Current Limit VTTILIM 2003 Semtech Corp. 1.250 1.265 ±1.8 ∆VTT/ ∆I Error Amplifier Gain 1.235 A IVTT =+1.8A to -1.8A S3 = high 4 V ±1 % 75 dB 3 A www.semtech.com SC2616 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW FB 1 18 SS/EN VTTSNS 2 17 COMP LGND 3 16 12VCC 5VSBY 4 15 TG VTT 5 14 BG VTT 6 13 PGND VDDQSTBY 7 12 AGND VDDQIN 8 11 SLP_S3 5VCC 9 10 SLP_S5 Part Numbers P ackag e SC2616MLTR(1) MLP-18 Note: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (18 Pin MLP) Note: Pin 19 is the thermal Pad on the bottom of the device Pin Descriptions Pin # Pin Name 1 FB 2 VTTSNS 3 LGND VTT return. Connect to point of load return. The trace connecting to this pin must be able to carry 2 Amps. 4 5V S B Y Bias supply for the chip. Connect to 5V standby. 5, 6 VTT 7 Pin Function Feedback for the STBY LDO and the switcher for VDDQ. VTT LDO feedback and remote sense input. VTT return. Connect to point of load return. The trace connecting to this pin must be able to carry 2 Amps. VDDQSTBY S3 VDDQ output. Provision must be made to prevent the VDDQSTBY supply from back feeding the input supply (see typical application schematic). Traces connecting to this pin must be capable of carring 1 Amp. 8 VDDQIN 9 5V C C 10 S LP _S 5 Connect to S5 signal from motherboard. 11 S LP _S 3 Connect to S3 signal from motherboard. 12 AGND Analog ground. 13 PGND Gate drive return. Keep this pin close to bottom FET source. 14 BG Bottom gate drive. 15 TG Top gate drive. 16 12V C C Supply to the upper and lower gate drives. 17 COMP Compensation pin for the PWM transconductance amplifier. 18 SS/EN Soft start capacitor to GND. Pull low to less than 0.3V to disable controller. 19 TH_PAD 2003 Semtech Corp. VDDQ power input to VTT LDO. The trace connecting to this pin must be able to carry 2 Amps. Supply to the lower gate drive. Copper pad on bottom of chip used for heatsinking. This pin is internally connected to AGND. 5 www.semtech.com SC2616 POWER MANAGEMENT Timing Diagram 5V, 12V Rails S3 S5 1.25V 1.0V 0.3V SS/EN PGOOD TG BG STBY VDDQ VTT Vssqsb Vddqsw VDDQ S0 S3 S0 S5 S0 Block Diagram 2003 Semtech Corp. 6 www.semtech.com SC2616 POWER MANAGEMENT Typical Characteristics 100% 40 35 80% DUTY CYCLE (%) Gain (dB) 30 25 20 15 10 60% 40% 20% 5 0% 0 1E+3 10E+3 100E+3 1.2 1E+6 1.3 1.4 1.5 1.6 1.7 VCOMP (V) Frequency (Hz) VCOMP vs Duty Cycle Switching Section Error Amplifier Gain Vo Error (%) 0.0% -0.1% -0.2% 0.0 2.0 4.0 6.0 8.0 10.0 12.0 Io (A) VDDQ Load Regulation 1.0% VTT Error (%) 0.5% 0.0% -0.5% -1.0% -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 Io (A) VTT Load Regulation, Source and Sink 2003 Semtech Corp. 7 www.semtech.com SC2616 POWER MANAGEMENT Evaluation Board Schematic +12V J1 12V C14 Place Jumper JP2 to have Silver Box on at all times C15 100uF 0.1uF J3 5V J2 GND 1500uF 1500uF 1500uF 1500uF 1500uF C1 C2 C4 J5 5V STBY 10uF C5 J4 GND C16 R12 10k R13 10k * * * 5V C18 C3 R4 2.2 R3 2.2 Q1 1uF SOURCE TO SOURCE CONFIGURATION Q2 R9 10k J6 GND L1 2.8uH U4 SC2616 5VSBY 4 J7 BF_CUT/S3 11 J11 10 PWR GD/S5 18 J12 SS/EN 17 C10 12 R6 33K 3 2 TBD 0.1uF C12 1nF 5VCC 5VSBY TG SLP_S3 BG SLP_S5 PGND SS/EN VDDQSTBY COMP VDDQIN AGND FB LGND VTTSNS 19 C11 12VCC HSINKPAD 16 VTT VTT 9 15 Q3 R11 2.2 14 J8 13 J9 VDDQ J10 7 8 R5 10.0k/1% 1 6 5 VTT C17 J13 VTT R7 10.0k/1% C13 0.1uF 330uF J14 GND J15 J18 GND R10 J20 PWR_OK 1500uF 1500uF 1500uF VDDQ C7 C9 C6 C8 0.1uF 5VSBY * J16 GND J17 Q4 2N2222 20K R8 +12V * 10k JP2 5V 1 2 3.3V 3.3V COM 5V COM 5V COM PWR_OK 5VSB 12V 3.3V -12V COM PS_ON COM COM COM -5V 5V 5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MAN PS_ON J19 ATX M/B MOLEX 39-29-9202 Figure 2 2003 Semtech Corp. 8 www.semtech.com SC2616 POWER MANAGEMENT Evaluation Board Bill of Materials Item Quantity Reference 1 8 C1,C2,C4,C5,C6,C7,C8,C18 2 1 C3 3 5 4 Part 1500uF Manufacturer Sanyo MX_CX 1uF any C9,C11,C15,C16,C17 0.1uF any 1 C 10 TBD 5 1 C 12 1nf 6 1 C 13 330uF any 7 1 C 14 100uF any 8 1 JP 2 MAN PS_ON 9 19 10 J1,J2,J3,J4,J5,J6,J7,J8,J9,J10,J11, J12,J13,J14,J15,J16,J17,J18,J20 E D 5052 1 J1 9 ATX M/B 11 1 L1 2.8uH 12 3 Q1,Q2,Q3 13 1 Q4 14 3 R3,R4,R11 15 2 R5,R7 16 1 17 F D B 7030B L MOLEX P/N: 39-29-9202 FALCO P/N: T50168 (www.falco.com) Fairchild P/N: FDB7030BL 2N2222 any 2.2 any 10.0k, 1% any R6 33k any 4 R8,R9,R12,R13 10k any 18 1 R10 20k any 19 1 U4 S C 2616 2003 Semtech Corp. 9 Semtech www.semtech.com SC2616 POWER MANAGEMENT Typical Characteristics (Cont.) Figure 3: S3 to S0 state transition with 600mA load on VDDQ Ch1: TG drive, Ch2: VDDQ w/2.5V offset, Ch3, S3, Ch4: SS/EN Note: VDDQ changes 16mV between S0 and S3 states (see cursor). Figure 4: S3 to S0 state transition with 800mA load on VDDQ Ch1: TG drive, Ch12 VDDQ w/2.5V offset, Ch3, S3, Ch4: SS/EN Note: VDDQ changes 22mV between S0 and S3 states (see cursor). 2003 Semtech Corp. 10 www.semtech.com SC2616 POWER MANAGEMENT Applications Information Description The Semtech SC2616 DDR power supply controller is the latest and most complete switching and linear regulator combination, providing the necessary functions to comply with S3 and S5 sleep state signals generated by the Desktop Computer Motherboards. VDDQ supply, and VTT termination voltage are supplied to the Memory bus during S0 (normal operation) state. During S0, VDDQ is supplied via the Switching regulator, sourcing high output currents to the VDD bus as well as supplying the termination supply current. The SC2616 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability allows 15-20A DC load on the VDDQ supply. The VTT termination voltage is an internal sink/ source linear regulator, which during S0 state receives its power from the VDDQ bus. It is capable of sourcing and sinking 2 Amps (max). The current limit on this pin is set to 3 Amps (typical). Output Current and PCB layout The current handling capacity of SC2616 depends upon the amount of heat the PC board can sink from the SC2616 thermal pad. (See mounting instructions). The PC board layout must take into consideration the high current paths, and ground returns for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ, 5VCC and PGND traces must also be routed using wide traces to minimize power loss and heat in these traces, based on the current handling requirements. S3 and S5 States During S3 and S5 sleep states, the operation of the VDDQ and VTT supplies is governed by the internal sequencing logic in strict adherence with motherboard specifications. The timing diagram demonstrates the state of the controller, and each of the VDDQ and VTT supplies during S3 and S5 transitions. When S3 is low, the VDDQ supplies the “Suspend To RAM” current of 650 mA (min) to maintain the information in memory while in standby mode. The VTT termination voltage is not needed during this state, and is thus tri-stated during S3. Once S3 goes high, the VDDQ switcher recovers and takes control of the VDDQ supply voltage. When S5 and S3 are pulled low, all supplies shut down. The SS/EN pin must be pulled low (<0.3V) and high again to restart the SC2616. This can be achieved by cycling the input supplies, 5V and 2003 Semtech Corp. 12V since both supplies have to be higher than their UVLO thresholds for proper start-up. Initial Conditions and Event Sequencing The main switcher will start-up in Asynchronous Mode when the voltage on SS/EN pin is greater than ~0.3V. The SS/EN will go high only after the 5Vcc and 12Vcc are higher than their respective UVLO thresholds. The switcher achieves maximum duty cycle when SS/EN reaches 0.8V. When the SS/EN equals 1.25V, the synchronous FET will also be activated. When the S5 and S3 go high for the first time, the VDDQ is supplied by the switcher, thus removing the burden of charging the output capacitors via the linear regulator. An internal latch guarantees that the supply goes through S0 state for the first time. During a transition from S3 to S0, where the 5V and 12V rails and subsequently the SS/EN pin go high, the internal VDDQ standby supply will remain ”on” until SS/EN has reached 1V, at which point only the switcher is supplying VDDQ , andthe internal “power good” indicator goes high. The “Memory” activity should be slaved off the “Power OK” signal from the Silver Box supply, and since the “Power OK” is asserted after all supplies are within close tolerance of their final values, the VDDQ switcher should have been running for some time before the memory is activated. This is true for typical SS/EN capacitor values (10nf to 220nf). Thus during transitions from S3 to S0, the concern that the VDDQ Standby supply may have to provide high currents before the switcher is activated is alleviated. The logic inputs to S3 and S5 pins must be defined before application of power to the SC2616. This can be guaranteed by pulling up the S3 and S5 inputs to 5VStandby. If the chipset that asserts these signals is powered after the SC2616 powers up, and S3 and S5 are not pulled up, erroneous startup and operation can result. Care must be taken not to exceed the maximum voltage/ current specifications on to the interface supplying these signals. The pullup voltage and resistor must be chosen such that when high, the S3 and S5 do not “back drive” 11 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) the interface chipset (Southbridge, etc.) and the maximum voltage applied to these pins do not exceed the chipsets specifications. A separate lower pullup supply may be necessary to avoid damage to the chipset. “Back Feeding” the Input Supply When in S3 state, VDDQ is supplied by the linear regulator and current can flow back from the VDDQ supply through the body diode of the Top switching MOSFET to the 5V supply of the Silver Box, which is off during the S3 state. This in turn shorts out the VDDQ supply and is not desirable. Thermal Shutdown There are three independent Thermal Shutdown protection circuits in the SC2616: the VDDQ linear regulator, the VTT source regulator, and the VTT sink regulator. If any of the three regulators’ temperature rises above the threshold, that regulator will turn off independently, until the temperature falls below the thermal shutdown limit. There are two approaches to avoiding this reverse current flow. One method is to place a MOSFET in series with the top switching MOSFET, but with the source and drain reversed. (see typical application circuit). The MOSFETs should be connected with sources connected to each other, to prevent Gate Source (Vgs) break-down in the even the inductor current flows in the negative direction, which subsequenstly can give rise to the switching (Phase) node voltage flying up to voltages higher than VGS_Breakdown. The connection of the MOSFETs in this manner places the body diodes back to back, thus removing a current path from VDDQ supply back into the input power source. Another way is to use the Instantly available ACPI controllers (such as Semtech SC1549). Such controllers serve to provide a 5V bus to the user, irrespective of the Status of S3 and S5 signals. Thus the 5V supply and the 5V Standby are multiplexed to provide an “always On” 5V to the VDDQ supply. Since the 5V supply is always greater than VDDQ, the back to back MOSFET connection is no longer necessary. Current Limit Current limit is implemented by sensing the VDDQ voltage If it falls to 60% off its nominal voltage, as sensed by the FB pin, the TG and BG pins are latched off and the switcher and the linear converters are shut down. To recover from the current limit condition, either the power rails, 5VCC or 12VCC have to be recycled, or the SS/EN pin must be pulled low and released to restart switcher operation. 2003 Semtech Corp. 12 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) Compensation Components Calculate the filter double pole frequency (Fp(lc)) Once the filter components have been determined, the compensation components can be calculated. The goal of compensation is to modify the frequency response characteristics of the error amplifier to ensure that the closed loop feedback system has the highest gain and bandwidth possible while maintaining stability. A simplified stability criteria states that the open loop gain of the converter should fall through 0dB at 20dB/ decade at a frequency no higher than 20-25% of the switching frequency. This objective is most simply met by generating asymptotic bode plots of the small signal response of the various sections of the converter. Fp(lc ) = 1 2π LCo and calculate ESR Zero frequency (Fz(esr)) Fz( esr ) = 1 2π ⋅ Co ⋅ Re sr Choose an open loop crossover frequency (Fco) no higher than 20% of the switching frequency (Fs). The proximity of Fz(esr) to the crossover frequency Fco determines the type of compensation required, if Fz(esr)>Fco/4, use type 3 compensation, otherwise use type 2. Type 1 compensation is not appropriate and is not discussed here. It is convenient to split the converter into two sections, the Error amp and compensation components being one section and the Modulator, output filter and divider being the other. Type 2 Example First calculate the DC Filter + Modulator + Divider gain. The DC filter gain is always 0dB, the Modulator gain is 19dB at 5V in and is proportional to Vin, so modulator gain at any input voltage is. The total Filter+Modulator+Divider DC Gain is: V GMOD = 19 + 20 ⋅ Log IN 5 As an example of type 2 compensation, we will use the Evaluation board schematic. 8.06 5 GFMD = 19 + 20 ⋅ Log + 20 ⋅ Log = 13.6dB 5 6.98 + 8.06 This is drawn as the line A-B in Figure 5. the divider gain is given by RB G DIV = 20 ⋅ Log R A + RB Fp(lc ) = 1 1 = ≈ 1.6kHz −6 2π LCo 2π 3.3 ⋅ 10 ⋅ 3000 ⋅ 10−6 So the total Filter + Modulator + Divider DC Gain is Vin=5V SC2616 AND FETS RB V G FMD = 19 + 20 ⋅ Log IN + 20 ⋅ Log 5 R A + RB REF FB MODULATOR + EA - 3.3uH OUT VOUT 6.98k COMP SC2610 AND FETS 3000uF REF Cs MODULATOR + 22mOhm EA FB Cp - Rs L OUT 8.06k VOUT Ra COMP Zf Co Zs Zp 2003 Semtech Corp. Resr Rb 13 www.semtech.com SC2616 POWER MANAGEMENT Applications Information (Cont.) This is point B in Figure 5. Fz( esr ) = 100 1 = 2.4kHz 2π ⋅ 3000 ⋅ 10 − 6 ⋅ 22 ⋅ 10 − 3 80 This is point C in Figure 5., the line joining B-C slopes at 40dB/decade, the line joining C-D slopes at -20dB/decade. E 60 Compensated Error Amp gain Gain (dB) 40 For 600kHz switching frequency, crossover is designed for 100kHz. G F H 20 A Fz1 B Fp1 C 0 Total open loop gain Fp(lc) Fz(esr) -20 Filter+modulator +divider gain Since Fz(esr)<<Fco/4 Type 2 compensation is appropriate. Having plotted the line ABCD, and confirmed the type of compensation necessary, compensation component values can be determined. At Fco, the line ABCD shows a gain of -27.5dB and a slope of -20dB/decade. In order for the total open loop gain to be 0dB with a -20dB/decade slope at this frequency, the compensated error amp gain at Fco must be +27.5dB with a 0dB slope. This is the line FG on the plot below. Since open loop DC gain should be as high as possible to minimize errors, a zero is placed at F and to minimize high frequency gain and switching interference a pole is placed at G. Fco -40 -60 100.0E+0 1.0E+3 10.0E+3 100.0E+3 D 1.0E+6 Frequency (Hz) Figure 5: Type 2 Error Amplifier Compensation The zero at F should be no higher than Fco/4 and the pole at G no lower than 4*Fco. The equations to set the gain and the pole and zero locations allow Shutdown: A Rs = 10 20 where A = gain at Fco (in dB) gm Cs = 1 2 π ⋅ Fz1 ⋅ Rs Cp = 1 2π ⋅ Fp1 ⋅ Rs For this example, this results in the following values. 27.5 Rs = 10 20 = 29.6kΩ ≈ 30kΩ 0.8 Cs ≈ 1 = 0.22nF 6 ⋅ 25 ⋅ 10 3 ⋅ 30 ⋅ 10 3 Cp ≈ 1 = 14pF (unecessar y due to EA rolloff ) 6 ⋅ 400 ⋅ 10 3 ⋅ 30 ⋅ 10 3 2003 Semtech Corp. 14 www.semtech.com SC2616 POWER MANAGEMENT Mounting Considerations Description The MLP18 is a leadless package whose electrical connections are made by lands on the bottom surface of the component. These lands are soldered directly to the PC board. The MLP has an exposed die attach pad, which enhances the thermal and electrical characteristics enabling high power applications. Power handling capability of the MLP package is typically >2x the power of other common SMT packages, such as the TSSOP and SOIC packages. In order to take full advantage of this feature the exposed pad must be physically connected to the PCB substrate with solder. Thermal Pad Via Design Thermal data for the MLP18 is based on a 4 layer PCB incorporating vias which act as the thermal path to other layers. (Ref: Jedec Specification JESD 51-5). Based on thermal performance, four-layer PCB’s with vias are recommended to effectively remove heat from the device. Vias should be 0.3mm diameter on a 1.2mm pitch, and should be plugged to prevent voids being formed between the exposed pad and PCB thermal pad due to solder escaping by capillary action. Plugging can be accomplished by “tenting” the via during the solder mask process. The via solder mask diameter should be 100µm larger than the via diameter. 2003 Semtech Corp. Two layer boards have less copper and thus typically require an increase in the PC board area for effective heatsinking. The copper area immdiately surrounding the thermal pad connection must not be interupted by routing traces. Exposed Pad Stencil Design It is good practice to minimize the presence of voids within the exposed pad inter-connection. Total elimination is difficult but the design of the exposed pad stencil is important, a single slotted rectangular pattern is recommended. (If large exposed pads are screened with excessive solder, the device may “float”, thus causing a gap between the MLP terminal and the PCB land metalization.) The proposed stencil designs enables outgassing of the solder paste during reflow as well as controlling the finished solder thickness. 15 www.semtech.com SC2616 POWER MANAGEMENT Outline Drawing - MLP-18 TERMINAL 1 IDENTIFIER TOP VIEW TERMINAL 1 BOTTOM VIEW 1 CONTROLLING DIMENSIONS: MILLIMETERS 2003 Semtech Corp. 16 www.semtech.com SC2616 POWER MANAGEMENT Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2003 Semtech Corp. 17 www.semtech.com