LTC6990 TimerBlox: Voltage Controlled Silicon Oscillator FEATURES DESCRIPTION n The LTC®6990 is a precision silicon oscillator with a programmable frequency range of 488Hz to 2MHz. It can be used as a fixed-frequency or voltage-controlled oscillator (VCO). The LTC6990 is part of the TimerBlox™ family of versatile silicon timing devices. n n n n n n n n n n Fixed-Frequency or Voltage-Controlled Operation – Fixed: Single Resistor Programs Frequency with <2.2% Max Error – VCO: Two Resistors Set VCO Center Frequency and Tuning Range Frequency Range: 488Hz to 2MHz 2.25V to 5.5V Single Supply Operation 72μA Supply Current at 100kHz 500μs Start-Up Time VCO Bandwidth >300kHz at 1MHz CMOS Logic Output Sources/Sinks 20mA 50% Duty Cycle Square Wave Output Output Enable (Selectable Low or Hi-Z When Disabled) –40°C to 125°C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN Package APPLICATIONS n n n n n Low Cost Precision Programmable Oscillator Voltage-Controlled Oscillator High Vibration, High Acceleration Environments Replacement for Fixed Crystal and Ceramic Oscillators Portable and Battery-Powered Equipment L, LT, LTC and LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6342817, 6614313. A single resistor, RSET, programs the LTC6990’s internal master oscillator frequency. The output frequency is determined by this master oscillator and an internal frequency divider, NDIV, programmable to eight settings from 1 to 128. fOUT = 1MHz 50kΩ • , N = 1, 2, 4 …128 NDIV RSET DIV Optionally, a second resistor at the SET input provides linear voltage control of the output frequency and can be used for frequency modulation. A narrow or wide VCO tuning range can be configured by the appropriate selection of the two resistors. The LTC6990 includes an enable function that is synchronized with the master oscillator to ensure clean, glitch-free output pulses. The disabled output can be configured to be high impedance or forced low. The LTC6990 is available in the 6-lead SOT-23 (ThinSOT) package or a 6-lead 2mm × 3mm DFN. TYPICAL APPLICATION Voltage Controlled Oscillator with 16:1 Frequency Range VCO Transfer Function 1000 f OUT 1MHz VCTRL • 0.5 V+ LTC6990 GND VCTRL V+ V+ C1 0.1μF RVCO 100k SET RSET 100k 750 OUT DIV fOUT (kHz) OE MHz V 500 250 6990 TA01a 0 0 0.5 1 VCTRL (V) 1.5 2 6990 TA01b 6990f 1 LTC6990 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (V+) to GND ........................................6V Maximum Voltage on Any Pin ............................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6990C ............................................–40°C to 85°C LTC6990I .............................................–40°C to 85°C LTC6990H .......................................... –40°C to 125°C Specified Temperature Range (Note 3) LTC6990C ................................................ 0°C to 70°C LTC6990I .............................................–40°C to 85°C LTC6990H .......................................... –40°C to 125°C Junction Temperature ........................................... 150°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10sec) ................... 300°C PIN CONFIGURATION TOP VIEW V+ 1 DIV 2 TOP VIEW 6 OUT 7 SET 3 OE 1 5 GND 4 OE 6 OUT GND 2 5 V+ SET 3 4 DIV DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 64°C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL TJMAX = 150°C, θJA = 230°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6990CDCB#PBF LTC6990CDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6990IDCB#PBF LTC6990IDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6990HDCB#PBF LTC6990HDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6990CS6#PBF LTC6990CS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 0°C to 70°C LTC6990IS6#PBF LTC6990IS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6990HS6#PBF LTC6990HS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 6990f 2 LTC6990 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15 (NDIV = 1 to 128), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN fOUT Output Frequency Recommended Range: RSET = 50k to 800k Extended Range: RSET = 25k to 800k 0.488 0.488 ΔfOUT Frequency Accuracy (Note 4) Recommended Range RSET = 50k to 800k l Extended Range RSET = 25k to 800k l ΔfOUT/ΔT ΔfOUT/ΔV+ Frequency Drift Over Temperature TYP ±0.8 l ±0.005 l l 0.23 0.06 MAX UNITS 1000 2000 kHz kHz ±1.5 ±2.2 % % ±2.4 ±3.2 % % %/°C Frequency Drift Over Supply V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V Period Jitter (Note 10) NDIV = 1 0.38 %P-P NDIV = 2 0.22 0.027 %P-P %RMS NDIV = 128 0.022 0.004 %P-P %RMS Duty Cycle BW Frequency Modulation Bandwidth tS Frequency Change Settling Time (Note 9) l l NDIV = 1, RSET = 25k to 800k NDIV > 1, RSET = 25k to 800k 47 48 tMASTER = tOUT /NDIV 50 50 0.55 0.16 53 52 %/V %/V % % 0.4•fOUT kHz 6•tMASTER μs Analog Inputs Voltage at SET Pin l ΔVSET /ΔT VSET Drift Over Temperature l ΔVSET VSET Drift Over Supply VSET /ΔV+ ΔVSET /ΔISET VSET Droop with ISET Frequency-Setting Resistor RSET ΔVDIV /V+ 1.00 1.03 V ±75 μV/°C –150 μV/V –7 Ω l l 50 25 800 800 kΩ kΩ l 0 V+ V l ±1.5 % DIV Pin Input Current l ±10 nA Operating Supply Voltage Range l Recommended Range Extended Range DIV Pin Voltage VDIV 0.97 DIV Pin Valid Code Range (Note 5) Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 Power Supply V+ IS 2.25 5.5 V 1.95 V 235 145 283 183 μA μA l l 71 59 105 92 μA μA V+ = 5.5V V+ = 2.25V l l 137 106 180 145 μA μA V+ = 5.5V V+ = 2.25V l l 66 56 100 90 μA μA l Power-On Reset Voltage RSET = 25k to 800k Supply Current RL = ∞, NDIV = 1, RSET = 50k V+ = 5.5V V+ = 2.25V l l RL = ∞, NDIV = 1 RSET = 800k V+ = 5.5V V+ = 2.25V RL = ∞, NDIV = 128, RSET = 50k RL = ∞, NDIV = 128, RSET = 800k 6990f 3 LTC6990 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15 (NDIV = 1 to 128), RSET = 25k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ±10 nA Digital I/O OE Pin Input Capacitance 2.5 OE Pin Input Current OE = 0V to V+ l VIH High Level OE Pin Input Voltage (Note 6) l VIL Low Level OE Pin Input Voltage (Note 6) l OUT Pin Hi-Z Leakage OE = 0V, DIVCODE ≥ 8, OUT = 0V to V+ IOUT(MAX) Maximum Output Current VOH High Level Output Voltage (Note 7) VOL Low Level Output Voltage (Note 7) pF 0.7•V+ V 0.3•V+ V ±10 μA ±20 mA V+ = 5.5V IOH = –1mA IOH = –16mA l l 5.45 4.84 5.48 5.15 V V V+ = 3.3V IOH = –1mA IOH = –10mA l l 3.24 2.75 3.27 2.99 V V V+ = 2.25V IOH = –1mA IOH = –8mA l l 2.17 1.58 2.21 1.88 V V V+ = 5.5V IOL = 1mA IOL = 16mA l l 0.02 0.26 0.04 0.54 V V V+ = 3.3V IOL = 1mA IOL = 10mA l l 0.03 0.22 0.05 0.46 V V V+ = 2.25V IOL = 1mA IOL = 8mA l l 0.03 0.26 0.07 0.54 V V tPD Output Disable Propagation Delay V+ = 5.5V V+ = 3.3V V+ = 2.25V tENABLE Output Enable Time NDIV ≤ 2, tOUT = 1/fOUT NDIV ≥ 4, tMASTER = tOUT/NDIV tr Output Rise Time (Note 8) tf Output Fall Time (Note 8) 17 26 44 ns ns ns tPD to tOUT tPD to 2•tMASTER μs μs V+ = 5.5V V+ = 3.3V V+ = 2.25V 1.1 1.7 2.7 ns ns ns V+ = 5.5V V+ = 3.3V V+ = 2.25V 1.0 1.6 2.4 ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6990C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: The LTC6990C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6990C is designed, characterized and expected to meet specified performance from –40°C to 85°C but it is not tested or QA sampled at these temperatures. The LTC6990I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6990H is guaranteed to meet specified performance from –40°C to 125°C. Note 4: Frequency accuracy is defined as the deviation from the fOUT equation, assuming RSET is used to program the frequency. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. Note 6: The OE pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using VOE(RISING) ≈ 0.55 • V+ + 185mV and VOE(FALLING) ≈ 0.48 • V+ – 155mV. Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within ±1% of the final frequency after a 0.5x or 2x change in ISET. Note 10: Jitter is the ratio of the deviation of the period to the mean of the period. This specification is based on characterization and is not 100% tested. 6990f 4 LTC6990 TYPICAL PERFORMANCE CHARACTERISTICS Frequency Error vs Supply Voltage Frequency Error vs RSET 0.5 TA = 25°C 2 1 TYPICAL MAX 0 90% OF UNITS –1 TYPICAL MIN –2 –4 10 100 RSET (kΩ) RSET = 800k 0.2 0.5 0.1 0 RSET = 200k –0.1 –0.2 RSET = 50k 0.0 RSET = 800k –0.5 RSET = 50k RSET = 267k –1.0 –0.4 –0.5 1000 2 3 4 5 SUPPLY VOLTAGE (V) 6990 G01 –1.5 –50 6 –25 0 25 50 75 TEMPERATURE (°C) 100 6990 G02 VSET vs ISET 1.003 V+ = 3.3V DIVCODE = 4 1.0 0.3 –0.3 GUARANTEED MIN OVER TEMPERATURE –3 TA = 25°C 0.4 GUARANTEED MAX OVER TEMPERATURE FREQUENCY ERROR (%) FREQUENCY ERROR (%) 3 Frequency Error vs Temperature 1.5 ERROR (%) 4 V+ = 3.3V, unless otherwise noted. 6990 G03 VSET vs Supply Voltage 1.003 V+ = 3.3V VSET vs Temperature 1.020 RSET = 200k 1.015 3 TYPICAL PARTS RSET = 200k TA = 25°C TA = 25°C 125 1.010 1.002 VSET (V) VSET (V) VSET (V) 1.002 1.001 1.005 1.000 0.995 1.001 0.990 0.985 0 10 20 ISET (μA) 30 1.000 40 2 3 4 5 SUPPLY VOLTAGE (V) 6990 G04 150 100 50 0 250 POWER SUPPLY CURRENT (μA) NUMBER OF UNITS 200 0.994 1.002 1.010 VSET (V) 1.018 6990 G07 0 25 50 75 TEMPERATURE (°C) 100 TA = 25°C Supply Current vs Temperature RSET = 50k, ÷1 5.5V, RSET = 50k, ÷1 RSET = 50k, ÷2 150 RSET = 50k, ÷128 100 RSET = 800k, ÷1 50 RSET = 800k, ÷128 2 125 250 200 0 0.986 –25 6990 G06 Supply Current vs Supply Voltage TA = 25°C 2 LOTS DFN AND SOT-23 1416 UNITS 250 0.980 –50 6990 G05 Typical VSET Distribution 300 6 POWER SUPPLY CURRENT (μA) 1.000 3 4 5 SUPPLY VOLTAGE (V) 6 6990 G05 200 2.25V, RSET = 50k, ÷1 150 5.5V, RSET = 50k, ÷128 100 5.5V, RSET = 800k, ÷1 50 0 –50 2.25V, RSET = 800k, ÷128 –25 0 25 50 75 TEMPERATURE (°C) 100 125 6990 G09 6990f 5 LTC6990 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Frequency, 5V 400 300 ÷2 250 200 ÷128 150 ÷1 100 V+ = 5V TA = 25°C 50 0 0.1 1 RECOMMENDED RANGE EXTENDED RANGE 350 POWER SUPPLY CURRNET (μA) POWER SUPPLY CURRNET (μA) Supply Current vs Frequency, 2.5V 400 RECOMMENDED RANGE EXTENDED RANGE 350 V+ = 3V, unless otherwise noted. 10 100 1000 FREQUENCY (kHz) 300 ÷1 250 ÷2 200 150 ÷128 100 V+ = 2.5V TA = 25°C 50 0 0.1 10000 1 10 100 1000 FREQUENCY (kHz) 6990 G10 Peak-to-Peak Jitter vs Frequency Supply Current vs OE Pin Voltage 0.50 TA = 25°C RSET = 800k 175 DIVCODE = 7 TA = 25°C 0.45 V+ = 5V PEAK-TO-PEAK PERIOD 0.40 DEVIATION MEASURED 0.35 OVER 30sec INTERVALS 5V, OE RISING 5V, OE FALLING 3.3V, OE RISING 3.3V, OE FALLING 125 JITTER (%P-P) POWER SUPPLY CURRENT (μA) 200 150 100 0.25 ÷2 0.20 ÷4 0.10 ÷128 0.05 0 20 40 60 VOE /V+ (%) 80 0 0.1 100 1 10 100 FREQUENCY (kHz) OE Threshold Voltage vs Supply Voltage 3.5 1000 6990 G13 6990 G12 Output Resistance vs Supply Voltage 50 TA = 25°C TA = 25°C 45 3.0 OUTPUT RESISTANCE (Ω) POSITIVE-GOING OE PIN VOLTAGE (V) ÷1 0.30 0.15 75 50 10000 6990 G11 2.5 2.0 NEGATIVE-GOING 1.5 1.0 40 35 OUTPUT SOURCING CURRENT 30 25 20 OUTPUT SINKING CURRENT 15 10 0.5 0 5 2 3 4 5 SUPPLY VOLTAGE (V) 6 6990 G14 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 6990 G16 6990f 6 LTC6990 TYPICAL PERFORMANCE CHARACTERISTICS Rise and Fall Time vs Supply Voltage 3.0 Output Disable Propagation Delay (tPD) vs Supply Voltage 50 TA = 25°C CLOAD = 5pF TA = 25°C CLOAD = 5pF 45 PROPAGATION DELAY (ns) 2.5 RISE/FALL TIME (ns) V+ = 3V, unless otherwise noted. 2.0 tRISE 1.5 tFALL 1.0 40 35 30 25 20 15 10 0.5 5 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 0 2 3 4 5 SUPPLY VOLTAGE (V) 6990 G16 6990 G17 Typical ISET Current Limit vs V+ 1000 Typical Output Waveform V+ = 3.3V DIVCODE = 2 RSET = 200k TA = 25°C SET PIN SHORTED TO GND 800 ISET (μA) 6 600 OE 2V/DIV 400 OUT 2V/DIV 200 0 2 3 4 5 SUPPLY VOLTAGE (V) 20μs/DIV 6 6990 G19 6990 G18 Frequency Modulation Frequency Modulation VCTRL 2V/DIV VCTRL 2V/DIV OUT 2V/DIV OUT 2V/DIV fOUT 50kHz/DIV fOUT 50kHz/DIV 20μs/DIV V+ = 3.3V, DIVCODE = 0 RSET = 200k, RVCO = 464k fOUT = 175kHz to 350kHz 6990 G20 20μs/DIV V+ = 3.3V, DIVCODE = 0 RSET = 200k, RVCO = 464k fOUT = 175kHz to 350kHz 6990 G21 6990f 7 LTC6990 PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1μF capacitor. DIV (Pin 2/Pin 4): Programmable Divider and Hi-Z Mode Input. A V+ referenced A/D converter monitors the DIV pin voltage (VDIV) to determine a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (Hi-Z) determines the behavior of the output when OE is driven low. If Hi-Z = 0 the output is pulled low when disabled. If Hi-Z = 1 the output is placed in a high impedance condition when disabled. SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25μA to 40μA. The output oscillation will stop if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to set the frequency. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. V+ OE OUT LTC6990 RSET V+ GND V+ SET DIV 6990 PF C1 0.1μF R1 R2 OE (Pin 4/Pin 1): Output Enable. Drive high to enable the output driver (Pin 6). Driving OE low disables the output asynchronously, so that the output is immediately forced low (Hi-Z = 0) or floated (Hi-Z = 1). When enabled, the output may temporarily remain low to synchronize with the internal oscillator in order to eliminate pulse slivers. GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30Ω. When driving an LED or other low-impedance load a series output resistor should be used to limit source/sink current to 20mA. 6990f 8 LTC6990 BLOCK DIAGRAM (S6 Package Pin Numbers Shown) V+ OE 1 5 R1 DIV 4 4-BIT A/D CONVERTER Hi-Z BIT DIGITAL FILTER R2 Hi-Z WHEN DISABLED MASTER OSCILLATOR tMASTER 1μs VSET • 50k7 ISET MCLK PROGRAMMABLE DIVIDER ÷1, 2, 4, 8, 16, 32, 64, 128 OUT 6 tOUT Hi-Z OUTPUT UNTIL SETTLED HALT OSCILLATOR IF ISET < 500nA ISET + – POR + – 1V 2 VSET = 1V 3 GND SET 6990 BD RSET 6990f 9 LTC6990 OPERATION The LTC6990 is built around a master oscillator with a 1MHz maximum frequency. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1MHz • 50k conversion factor that is accurate to ±0.8% under typical conditions. I 1 f MASTER = = 1MHz • 50k • SET tMASTER VSET A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the output frequency. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET. The master oscillator equation reduces to: f MASTER = 1 tMASTER = DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that monitors the DIV pin voltage (VDIV) to determine the DIVCODE value. DIVCODE programs two settings on the LTC6990: 1. DIVCODE determines the output frequency divider setting, NDIV. 2. DIVCODE determines the state of the output when disabled, via the Hi-Z bit. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1. 1MHz • 50k RSET From this equation it is clear that VSET drift will not affect the output frequency when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ΔfOUT of the LTC6990. RSET values between 50k and 800k (equivalent to ISET between 1.25μA and 20μA) produce the best results, although RSET may be reduced to 25k (ISET = 40μA) with reduced accuracy. 2.25V TO 5.5V V+ LTC6990 R1 DIV R2 GND 6990 F01 Figure 1. Simple Technique for Setting DIVCODE The LTC6990 includes a programmable frequency divider which can further divide the frequency by 1, 2, 4, 8, 16, 32, 64 or 128 before driving the OUT pin. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. fOUT = 1 tOUT = 1MHz • 50k ISET • NDIV VSET With RSET in place of VSET /ISET the equation reduces to: fOUT = 1 tOUT = 1MHz • 50k NDIV • RSET 6990f 10 LTC6990 OPERATION Table 1. DIVCODE Programming DIVCODE Hi-Z NDIV Recommended fOUT R1 (k) R2 (k) VDIV /V+ 0 0 1 62.5kHz to 1MHz Open Short ≤ 0.03125 ±0.015 1 0 2 31.25kHz to 500kHz 976 102 0.09375 ±0.015 2 0 4 15.63kHz to 250kHz 976 182 0.15625 ±0.015 3 0 8 7.813kHz to 125kHz 1000 280 0.21875 ±0.015 4 0 16 3.906kHz to 62.5kHz 1000 392 0.28125 ±0.015 5 0 32 1.953kHz to 31.25kHz 1000 523 0.34375 ±0.015 6 0 64 976.6Hz to 15.63kHz 1000 681 0.40625 ±0.015 7 0 128 488.3Hz to 7.813kHz 1000 887 0.46875 ±0.015 8 1 128 488.3Hz to 7.813kHz 887 1000 0.53125 ±0.015 9 1 64 976.6Hz to 15.63kHz 681 1000 0.59375 ±0.015 10 1 32 1.953kHz to 31.25kHz 523 1000 0.65625 ±0.015 11 1 16 3.906kHz to 62.5kHz 392 1000 0.71875 ±0.015 12 1 8 7.813kHz to 125kHz 280 1000 0.78125 ±0.015 13 1 4 15.63kHz to 250kHz 182 976 0.84375 ±0.015 14 1 2 31.25kHz to 500kHz 102 976 0.90625 ±0.015 15 1 1 62.5kHz to 1MHz Short Open ≥ 0.96875 ±0.015 Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and Hi-Z values for the recommended resistor pairs. Other values may be used as long as: column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V+ 1. The VDIV /V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects) = DIVCODE + 0.5 ± 1.5% 16 For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. 2. The driving impedance (R1||R2) does not exceed 500kΩ. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. If the voltage is generated by other means (i.e. the output of a DAC) it must track the V+ supply voltage. The last Hi-Z BIT = 0 Hi-Z BIT = 1 1000 fOUT (kHz) 0 15 1 100 14 13 2 3 12 11 4 10 5 10 6 9 7 8 1 0.1 RECOMMENDED RANGE EXTENDED RANGE 0V 0.5•V+ V+ INCREASING VDIV 6990 F02 Figure 2. Frequency Range and Hi-Z Bit vs DIVCODE 6990f 11 LTC6990 OPERATION On start-up, the DIV pin A/D converter must determine the correct DIVCODE before the output is enabled. If VDIV is not stable, it will increase the start-up time as the converter waits for a stable result. Therefore, capacitance on the DIV pin should be minimized so it will settle quickly. Less than 100pF will not affect performance. Output Enable The OE pin controls the state of the LTC6990’s output as seen on the OUT pin. Pulling the OE pin high enables the oscillator output. Pulling it low disables the output. When the output is disabled, it is either held low or placed in a high impedance state as dictated by the Hi-Z bit value (determined by the DIVCODE as described earlier). Table 2 summarizes the output control states. Table 2. Output States OE Pin Hi-Z OUT 1 X Enabled, Output is Active 0 1 Disabled, Output is Hi-Z 0 0 Disabled, Output is Held Low Figure 3 illustrates the timing for the OE function when Hi-Z = 0. When OE is low, the output is disabled and OUT is held low. Bringing OE high enables the output after a delay, tENABLE, which synchronizes the enable to eliminate sliver pulses and guarantee the correct width for the first pulse. If NDIV = 1 or 2 this delay will be no longer than the output period, tOUT. If NDIV > 2 the delay is limited to twice the internal master oscillator period (or 2 • tMASTER). Forcing OE low will bring OUT low after a propagation delay, tPD. If the output is high when OE falls, the output pulse will be truncated. As shown in Figure 4, setting Hi-Z = 1 places the output in a high-impedance state when OE = 0. This feature allows for “wired-OR” connections of multiple devices. Driving OE high enables the output. The output will usually be forced low during this time, although it is possible for OUT to transition directly from high-impedance to a high output, depending on the timing of the OE transition relative to the internal oscillator. Once high, the first output pulse will have the correct width (unless truncated by bringing OE low again). OE tPD tPD OUT tENABLE tOUT tENABLE 6990 F03 Figure 3. OE Timing Diagram (Hi-Z = 0) OE tPD OUT tPD tPD tPD Hi-Z tENABLE tOUT tENABLE 6990 F04 Figure 4. OE Timing Diagram (Hi-Z = 1) 6990f 12 LTC6990 OPERATION Changing DIVCODE After Start-Up Start-Up Time Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6990 places a priority on eliminating any “wandering” in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. When power is first applied to the LTC6990 the power-on reset (POR) circuit will initiate the start-up time, tSTART. The OUT pin is floated (high-impedance) during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tDIVCODE = 16 • (ΔDIVCODE + 6) • tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. Then the output will make a clean (glitchless) transition to the new divider setting. t START(TYP) = 500 • tMASTER The start-up time may be longer if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. 576μs DIV 1V/DIV V+ 1V/DIV 470μs OUT 1V/DIV OUT 1V/DIV V+ = 3.3V RSET = 200k 100μs/DIV OUTPUT CONNECTED TO 1.25V THROUGH 25k TO SHOW Hi-Z 6990 F05 Figure 5. DIVCODE Change from 5 to 2 V+ = 2.5V DIVCODE = 4 RSET = 50k 100μs/DIV 6990 F06 Figure 6. Typical Start-Up 6990f 13 LTC6990 APPLICATIONS INFORMATION OE Hi-Z OUT tSTART 1/2 tOUT tOUT 6990 F07 Figure 7. Start-Up Timing Diagram (OE = 1, NDIV = 1 or 2, Hi-Z = 0 or 1) OE Hi-Z OUT tSTART tMASTER tOUT 6990 F08 Figure 8. Start-Up Timing Diagram (OE = 1, NDIV ≥ 4, Hi-Z = 0 or 1) OE OUT Hi-Z tSTART tENABLE tOUT 6990 F09 Figure 9. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 0) OE tPD OUT Hi-Z tSTART REMAINS Hi-Z tENABLE UNTIL OE = 1 tOUT 6990 F10 Figure 10. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 1) 6990f 14 LTC6990 APPLICATIONS INFORMATION Start-Up Behavior When first powered up, the output is high impedance. If the output is enabled (OE = 1) at the end of the start-up time, the output will go low for one tMASTER cycle (or half a tOUT cycle if NDIV < 4) before the first rising edge. If the output is disabled (OE = 0) at the end of the start-up time, the output will drop to a low output if the Hi-Z bit = 0, or simply remain floating if Hi-Z = 1. Basic Fixed Frequency Operation The simplest and most accurate method to program the LTC6990 for fixed frequency operation is to use a single resistor, RSET, between the SET and GND pins. The design procedure is a simple two step process. First select the NDIV value and then calculate the value for the RSET resistor. Step 1: Selecting the NDIV Frequency Divider Value As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the Hi-Z bit and the NDIV value. For a given output frequency, NDIV should be selected to be within the following range. 1MHz 62.5kHz ≤ NDIV ≤ fOUT fOUT (1a) To minimize supply current, choose the lowest NDIV value (generally recommended). For faster start-up or decreased jitter, choose a higher NDIV setting. Alternatively, use Table 1 as a guide to select the best NDIV value for the given application. After choosing the value for NDIV, use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. Example: Design a 20kHz Oscillator with Minimum Power Consumption Step 1: Selecting the NDIV Frequency Divider Value First, choose an NDIV value that meets the requirements of Equation (1a). 3.125 ≤ NDIV ≤ 50 Potential settings for NDIV include 4, 8, 16, and 32. NDIV = 4 is the best choice, as it minimizes supply current by using a large RSET resistor. Using Table 1, choose the R1 and R2 values to program DIVCODE to either 2 or 13, depending on the desired behavior when the output is disabled. Step 2: Select RSET Calculate the correct value for RSET using Equation (1b). RSET = Since 625k is not available as a standard 1% resistor, substitute 619k if a 0.97% frequency shift is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. Frequency Modulated Operation (Voltage-Controlled Oscillator) Operating the LTC6990 as a voltage-controlled oscillator in its simplest form is achieved with one additional resistor. As shown in Figure 11, voltage VCTRL sources/sinks a current through RVCO to vary the ISET current, which in turn modulates the output frequency as described in Equation (2). fOUT = Step 2: Calculate and Select RSET The final step is to calculate the correct value for RSET using the following equation. RSET = 1MHz • 50k NDIV • fOUT 1MHz • 50k = 625k 4 • 20kHz 1MHz • 50k NDIV • R VCO ⎛ R ⎞ V • ⎜ 1+ VCO − CTRL ⎟ ⎝ RSET VSET ⎠ V+ OE OUT V+ LTC6990 (1b) Select the standard resistor value closest to the calculated value. (2) GND VCTRL V+ RVCO SET RSET C1 0.1μF R1 DIV 6990 F08 R2 Figure 11. Voltage Controlled Oscillator 6990f 15 LTC6990 APPLICATIONS INFORMATION Equation (2) can be re-written as shown below, where f(0V) is the output frequency when VCTRL = 0V, and KVCO is the frequency gain. Note that the gain is negative (the output frequency decreases as VCTRL increases). fOUT = f(0V) – K VCO • VCTRL f(0V) = 1MHz • 50k NDIV • (RSET PR VCO ) K VCO = 1MHz • 50k NDIV • VSET • R VCO With KVCO and f(0V) determined, the RVCO and RSET values can now be calculated. The design procedure for a VCO is a simple four step process. First select the NDIV value. Then calculate the intermediate values KVCO and f(0V). Next, calculate and select the RVCO resistor. Finally calculate and select the RSET resistor. Step 1: Select the NDIV Frequency Divider Value For best accuracy, the master oscillator frequency should fall between 62.5kHz and 1MHz. Since fMASTER = NDIV • fOUT, choose a value for NDIV that meets the following conditions 1MHz 62.5kHz ≤ NDIV ≤ fOUT(MAX) fOUT(MIN) (3a) The 16:1 frequency range of the master oscillator and the 2:1 divider step-size provides several overlapping frequency spans to guarantee that any 8:1 modulation range can be covered by a single NDIV setting. RVCO allows the gain to be tailored to the application, mapping the VCTRL voltage range to the modulation range. Step 2: Calculate KVCO and f(0V) KVCO and f(0V) define the VCO’s transfer function and simplify the calculation of the the RVCO and RSET resistors. Calculate these parameters using the following equations. fOUT(MAX) − fOUT(MIN) K VCO = (3b) V −V CTRL(MAX) CTRL(MIN) f(0V) = fOUT(MAX) + KVCO • VCTRL(MIN) KVCO and f(0V) are not device settings or resistor values themselves. However, beyond their utility for the resistor calculations, these parameters provide a useful and intuitive way to look at the VCO application. The f(0V) parameter is the output frequency when VCTRL is at 0V. Viewed another way, it is the fixed output frequency when the RVCO and RSET resistors are in parallel. KVCO is actually the frequency gain of the circuit. (3c) Step 3: Calculate and Select RVCO The next step is to calculate the correct value for RVCO using the following equation. R VCO = 1MHz • 50k NDIV • VSET • K VCO (3d) Select the standard resistor value closest to the calculated value. Step 4: Calculate and Select RSET The final step is to calculate the correct value for RSET using the following equation: RSET = ( 1MHz • 50k NDIV • f(0V) − VSET • K VCO ) (3e) Select the standard resistor value closest to the calculated value. Some applications require combinations of fOUT(MIN), fOUT(MAX), VCTRL(MIN) and VCTRL(MAX) that are not achievable. These applications result in unrealistic or unrealizable (e.g. negative value) resistors. These applications will require preconditioning of the VCTRL signal via range scaling and/or level shifting to place the VCTRL into a range that yields realistic resistor values. Frequency Error in VCO Applications Due to VSET Error As stated earlier, f(0V) represents the frequency for VCTRL = 0V, which is the same value as would be generated by a single resistor between SET and GND with a value of RSET || RVCO . Therefore, f(0V) is not affected by error or drift in VSET (i.e. ΔVSET adds no frequency error when VCTRL = 0V). 6990f 16 LTC6990 APPLICATIONS INFORMATION The accuracy of KVCO does depend on VSET because the output frequency is controlled by the ratio of VCTRL to VSET. The frequency error (in Hertz) due to ΔVSET is approximated by: ΔV ΔfOUT ≅ K VCO • VCTRL • SET VSET As the equation indicates, the potential for error in output frequency due to VSET error increases with KVCO and is at its largest when VCTRL is at its maximum. Recall that when VCTRL is at its maximum, the output frequency is at its minimum. With the maximum absolute frequency error (in Hertz) occurring at the lowest output frequency, the relative frequency error (in percent) can be significant. VSET is nominally 1.0V with a maximum error of ±30mV for at most a ±3% error term. However, this ±3% potential error term is multiplied by both VCTRL and KVCO. Wide frequency range applications (high KVCO) can have frequency errors greater than ±50% at the highest VCTRL voltage (lowest fOUT). For this reason the simple, two resistor VCO circuit must be used with caution for applications where the frequency range is greater than 4:1. Restricting the range to 4:1 typically keeps the frequency error due to VSET variation below 10%. For wide frequency range applications, the non-inverting VCO circuit shown in Figure 13 is preferred because the maximum frequency error occurs when the frequency is highest, keeping the relative error (in percent) much smaller. fOUT(MIN) = 10kHz at VCTRL(MAX) = 4V Step 1: Select the NDIV Value First, choose an NDIV that meets the requirements of Equation (3a). 6.25 ≤ NDIV ≤ 10 The application’s desired frequency range is 10:1, which isn’t always possible. However, in this case NDIV = 8 meets both requirements of Equation (3). Step 2: Calculate KVCO and f(0V) Next, calculate the intermediate values KVCO and f(0V) using Equations (3b) and (3c). 100kHz − 10kHz = 30kHz/V 4V − 1V f(0V) = 100kHz + 30kHz/V • 1V = 130kHz K VCO = Step 3: Calculate and Select RVCO The next step is to use Equation (3d) to calculate the correct value for RVCO. R VCO = 1MHz • 50k = 208.333k 8 • 1V • 30kHz/V Select RVCO = 210k. The final step is to calculate the correct value for RSET using Equation (3e). 1MHz • 50k RSET = = 62.5k 8 • (130kHz − 1V • 30kHz/V ) 80 fOUT (kHz) fOUT(MAX) = 100kHz at VCTRL(MIN) = 1V Step 4: Calculate and Select RSET 100 60 40 Select RSET = 61.9k 20 0 Example: Design a VCO with the Following Parameters 1 2 3 4 VCTRL (V) 6990 F12 Figure 12. VCO Transfer Function In this design example, with its wide 10:1 frequency range, the potential output frequency error due to VSET error alone ranges from less than ±1% when VCTRL is at its minimum up to ±36% when VCTRL is at its maximum. This error must be accounted for in the system design. 6990f 17 LTC6990 APPLICATIONS INFORMATION Depending on the application’s requirements, the noninverting VCO circuit in Figure 13 may be preferred for this wide of a frequency variation as its maximum inaccuracy due to VSET error is only ±9% and can be reduced to only ±3% with a small change to the voltage tuning range specification. Reducing VSET Error Effects in VCO Applications Figure 13 shows a VCO that reduces the effect of ΔVSET by adding an op-amp to make VCTRL dependent on VSET. This circuit also has a positive transfer function (the output frequency increases as VIN increases). Furthermore, for positive VIN voltages, this circuit places the greatest absolute frequency error at the highest output frequency. Compared to the simple VCO circuit of Figure 11, the absolute frequency error is unchanged. However, with the maximum absolute frequency error (in Hertz) now occurring at the highest output frequency, the relative frequency error (in percent) is greatly improved. Additionally, by choosing the VCO’s specifications shrewdly, the frequency error (in percent) due to VSET variation is reduced to ΔVSET/VSET = ±3%. To realize this improvement, the design must abide by three conditions. First, the VIN voltage must be positive throughout the range. Second, choose VMAX /VMIN ≥ fMAX /fMIN. Last, choose RVCO /RSET ≥ R4/R3. Figure 13 shows a design similar to the previous design example where the VMIN voltage is now specified to be 0.4V. This satisfies the VMAX /VMIN ≥ fMAX /fMIN condition and the design assures that the output frequency error due to VSET variation is only ±3%. 10kHz TO 100kHz fOUT 3V OE OUT LTC6990 3V V+ GND C1 0.1μF VSET SET + 0.4V TO 4V VIN R3 100k 1/2 LTC6078 6990 F13 VCTRL R4 30.1k R2 280k RVCO 75k RSET 249k – C4 33pF DIVCODE = 3 (NDIV = 8, Hi-Z = 0) DIV 3V f OUT IF R1 1M 1MHz • 50k7 NDIV • R VCO ¨R ¥ V ´ R4 · ¸ • © VCO ¦ IN 1µ • ¶ R3 ¸¹ ©ª RSET § VSET R4 R VCO , THE EQUATION REDUCES TO: R3 RSET f OUT = 1MHz • 50k7 VIN • VIN • 25kHz/V NDIV • RSET VSET Figure 13. VCO with Reduced ΔVSET Sensitivity 6990f 18 LTC6990 APPLICATIONS INFORMATION Eliminating VSET Error Effects with DAC Frequency Control Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET error is eliminated by buffering VSET and using it as the DAC’s reference voltage, as shown in Figure 14. The DAC’s output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC’s REF input would affect the frequency. ISET Extremes (Master Oscillator Frequency Extremes) Pushing ISET outside of the recommended 1.25μA to 20μA range forces the master oscillator to operate outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator will still function with reduced accuracy in its extended range (see the Electrical Characteristics section). The LTC6990 is designed to function normally for ISET as low as 1.25μA. At approximately 500nA, the oscillator output will be frozen in its current state. For NDIV = 1 or 2, OUT will halt in a low state. But for larger divider ratios, it could halt in a high or low state. This avoids introducing short pulses while modulating a very low frequency output. Note that the output will not be disabled as when OE is low (e.g. the output will not enter a high impedance state if Hi-Z = 1). At the other extreme, the master oscillator frequency can reach 2MHz for ISET = 40μA (RSET = 25k). It is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. OE OUT V+ LTC6990 GND V+ V+ + SET 1/2 LTC6078 C1 0.1μF R1 DIV 6990 F14 R2 – V+ DIN μP CLK CS/LD VCC f OUT REF LTC1659 GND D ´ 1MHz • 50k7 ¥ R VCO • 1 IN NDIV • R VCO ¦§ RSET 4096 µ¶ DIN = 0 to 4095 VOUT RVCO RSET Figure 14. Digitally Controlled Oscillator with VSET Variation Eliminated 6990f 19 LTC6990 APPLICATIONS INFORMATION Modulation Bandwidth and Settling Time Power Supply Current The LTC6990 will respond to changes in ISET up to a –3dB bandwidth of 0.4 • fOUT (see Figure 15). This makes it easy to stabilize a feedback loop around the LTC6990, since it does not introduce a low-frequency pole. The power supply current varies with frequency, supply voltage and output loading. It can be estimated under any condition using the following equation: Settling time depends on the master oscillator frequency. Following a 2x or 0.5x step change in ISET, the output frequency takes approximately six master clock cycles (6 • tMASTER) to settle to within 1% of the final value. An example is shown in Figure 16. $fOUT (fMOD)/$fOUT(DC) (dB) 0 VCTRL = 0.536V + 0.278V • SIN(2π•fMOD •t) fOUT =18.75kHz ±10% –10 IS(TYP) ≈ V + • fMASTER • 7pF + V + • f OUT • (13pF + CLOAD ) V+ V+ + + 1.75 •ISET + 50µA + 480kΩ 2 • RLOAD The equation is also valid for OE = 0 (output disabled), with fOUT = 0Hz. VCTRL 2V/DIV OUT 2V/DIV –3dB AT 0.4•fOUT –20 fOUT 50kHz/DIV –30 RSET = 200k RVCO = 464k DIVCODE = 4(÷16) –40 0.1 1 10 fMOD /fOUT (Hz/Hz) 6990 F15 Figure 15. Modulation Frequency Response 10μs/DIV V+ = 3.3V, DIVCODE = 0 RSET = 200k, RVCO = 464k fOUT = 175kHz AND 350kHz 6990 F16 Figure 16. Settling Time 6990f 20 LTC6990 APPLICATIONS INFORMATION SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES The LTC6990 is a 2.2% accurate silicon oscillator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. The most important use issues involve adequate supply bypassing and proper PCB layout. Figure 17 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6990. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1’s connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the OE C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1μF ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the operating frequency. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but the direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. OUT LTC6990 GND SET V+ V+ C1 0.1μF R1 DIV RSET R2 V+ R1 R2 V+ C1 C1 V+ OUT OE OUT DIV GND GND V+ SET OE SET DIV R1 RSET RSET DCB PACKAGE R2 TSOT-23 PACKAGE 6990 F17 Figure 17. Supply Bypassing and PCB Layout 6990f 21 LTC6990 TYPICAL APPLICATIONS Programming NDIV Using an 8-Bit DAC OE DIVCODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OUT LTC6990 2.25V TO 5.5V GND V+ SET DIV C1 0.1μF C2 0.1μF RSET 619k VCC SDI VOUT LTC2630-LZ8 SCK GND μP CS/LD DAC CODE 0 24 40 56 72 88 104 120 136 152 168 184 200 216 232 255 6990 TA02 Full Range VCO with Any NDIV Setting (fMAX to fMIN for VIN = 0V to VSET) 5V RVCO2 26.1k OE OUT LTC6990 VIN 0V TO 1V RVCO1 26.1k 5V – V+ GND D1 IN4148 LT1490 SET + C1 0.1μF 5V R1 DIV 6990 TA03 R2 RSET 826k Full Range VCO with Any NDIV Setting (Positive Frequency Control, fMIN to fMAX for VIN = 0V to VSET 5V R4 10k OE OUT LTC6990 VIN 0V TO 1V R3 10k 5V – GND V+ RVCO 53.6k LT1490 SET + 5V R1 DIV 6990 TA04 RSET1 412k C1 0.1μF R2 RSET2 412k 6990f 22 LTC6990 TYPICAL APPLICATIONS Speaker Alarm. Modulate Tone with RVCO within 500Hz to 8kHz Span 5V 8Ω IN4004 5V 20k OE 2N2222 OUT LTC6990 50k V+ GND RVCO STEP SET RAMP 5V 1M DIV 6990 TA05 97.6k 887k Overvoltage Detector/Alarm. Direct Drive of Piezo Alarm 24V 5V RA 787k + RB 10.7k 400mV 100k LT6703-3 OE – OUT LTC6990 + GND 5V V 1M ¥ R ´ V ALARM 400mV ¦ 1 A µ 30V § RB ¶ SET DIV 6990 TA06 392k PIEZO ALARM 4kHz MURATA PKM29-3A0 523k Direct Piezo Alarm Driver. Adjust Frequency for Maximum Alarm Sound Pressure (Maximum Annoyance for Best Effect) 5V ON 10k OE OFF OUT LTC6990 GND V+ 5V 1M SET 392k PIEZO ALARM MURATA PKM29-340 f = 4kHz DIV 6990 TA07 523k 6990f 23 LTC6990 TYPICAL APPLICATIONS Isolated V → F Converter. VIN Provided by Isolated Measurement Circuit. 5μs Rise/Fall Time of Isolator Limits fMAX to 60kHz 3.3V 5V 365Ω OE MOC207M OUT LTC6990 GND V+ SET DIV 5V 1M 75k VIN 0V TO 5V 412Ω 6990 TA08 157k fOUT 523k Quadrature Sine Wave Oscillator. Voltage Controlled Frequency Range from 2Hz to 18kHz with 1VP-P Constant Output Amplitude SINE 2.5V COSINE 51.1k 5.11k N 124k – S1A BP LP 5V LTC1059 OR 1/2 LTC1060 – + + – CLOCK 5V SA/B AGND 50/100 OUT 2.5V 10k LT1004 –2.5V 2k 1M V+ 5V GND R1 1M VCC OUT R2 280k LTC1440 REF RVCO 267k DIV – V+ 5V OE LTC6990 SET 6990 TA09 RSET 49.9k FREQ ADJ + HYST 1.18V 4.12k 0.1μF 1M 6990f 24 LTC6990 TYPICAL APPLICATIONS Temperature to Frequency Converter. 3% Linearity from –20°C (fOUT ≈ 20kHz) to 75°C (fOUT ≈ 25kHz) 5V OE fOUT OUT LTC6990 GND V+ SET DIV 5V 1M 60.4k 22k AT 25°C B = 3964 6990 TA10 21.5k 523k + THERMISTOR: VISHAY NTHS120601N2202J Full Range Temperature to Frequency Converter. 16kHz to 1kHz from –20°C to 80°C 5V OE 10k OUT V+ GND 5V – 100k 10k SET + DIV 6990 TA11 + 5V 1M LT1490 22k AT 25°C B = 3964 fOUT LTC6990 681k 26k 26k THERMISTOR: VISHAY NTHS120601N2202J Light to Frequency Converter. fOUT ≈ –1.4kHz per Microampere of Photo Diode Current, IPD 1000pF 5V OE 24.9k IPD – OUT GND 5V V+ LT1677 + 5V 187k 222k SFH213 fOUT LTC6990 SET 619k DIV 6990 TA12 1M 6990f 25 LTC6990 PACKAGE DESCRIPTION DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715) 0.70 p0.05 3.55 p0.05 1.65 p0.05 (2 SIDES) 2.15 p0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 1.35 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 2.00 p0.10 (2 SIDES) R = 0.05 TYP 3.00 p0.10 (2 SIDES) 0.40 p 0.10 4 6 1.65 p 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 s 45o CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 p0.05 1 (DCB6) DFN 0405 0.25 p 0.05 0.50 BSC 1.35 p0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6990f 26 LTC6990 PACKAGE DESCRIPTION S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.90 BSC NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 S6 TSOT-23 0302 REV B 6990f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC6990 TYPICAL APPLICATION Ultrasonic Frequency Sweep Generator fOUT = 500kHz TO 31.25kHz OE OE OUT LTC6990 GND SET 74HC125 CSET 0.022μF RSET1 49.9k V+ C1 0.1μF 2.25V TO 5.5V R1 976k DIV 6990 TA13 R2 102k RSET2 750k SWEEPS FROM 500kHz to 31.25kHz IN A FEW MILLISECONDS (CONTROLLED BY CSET). RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35μA at 400kHz LTC6930 0.09% Accuracy, 110μs Start-Up Time, 105μA at 32kHz Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 6990f 28 Linear Technology Corporation LT 0710 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010