LTC6995-1/LTC6995-2 TimerBlox: Long Timer, Low Frequency Oscillator Description Features Period Range: 1ms to 9.5 Hours Timing Reset by Power-On or Reset Input n Configured with 1 to 3 Resistors n<1.5% Maximum Frequency Error n Programmable Output Polarity n2.25V to 5.5V Single Supply Operation n55µA to 80µA Supply Current (2ms to 9.5hr Clock Period) n500µs Start-Up Time n CMOS Output Driver Sources/Sinks 20mA n–55°C to 125°C Operating Temperature Range n Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN Packages The LTC®6995 is a silicon oscillator with a programmable period range of 1.024ms to 9.54 hours (29.1µHz to 977Hz), specifically intended for long duration timing events. The LTC6995 is part of the TimerBlox® family of versatile silicon timing devices. n n A single resistor, RSET , programs the LTC6995’s internal master oscillator frequency. The output clock period is determined by this master oscillator and an internal frequency divider, NDIV , programmable to eight settings from 1 to 221. tOUT = NDIV • RSET • 1.024ms, NDIV = 1,8,64,...,221 50kΩ When oscillating, the LTC6995 generates a 50% duty cycle square wave output. A reset function is provided to stop the master oscillator and clear internal dividers. Removing reset initiates a full output clock cycle which is useful for programmable power on reset and watchdog timer applications. Applications Power-On Reset Timer Long Time One Shot n“Heartbeat” Timers n Watchdog Timers n Periodic “Wake-Up” Call n High Vibration, High Acceleration Environments n n The LTC6995 has two versions of reset functionality. The reset input is active high for the LTC6995-1 and active low for the LTC6995-2. The polarity of the output when reset is selectable for both versions. L, LT, LTC, LTM, Linear Technology, TimerBlox and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. OUTPUT (OSCILLATOR START STATE) Typical Application RST RST/RST POLARITY LTC6995-1 LTC6995-2 0 0 Oscillating (Low) 0 (Reset) 1 0 0 (Reset) Oscillating (Low) 0 1 Oscillating (High) 1 (Reset) 1 1 1 (Reset) Oscillating (High) Active Low Power-On Reset Timer OUT V+ LTC6995-1 GND V+ V+ 1M 118k SET DIV 392k 0.1µF OUT 5 SECONDS 1/2 tOUT TIMER STOPPED POWER-ON RESET (1ms TO 4.8 HOURS) 699512 TA01 699512f For more information www.linear.com/6995 1 LTC6995-1/LTC6995-2 Absolute Maximum Ratings (Note 1) Supply Voltage (V+) to GND.........................................6V Maximum Voltage on Any Pin................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6995C.............................................–40°C to 85°C LTC6995I..............................................–40°C to 85°C LTC6995H........................................... –40°C to 125°C LTC6995MP........................................ –55°C to 125°C Specified Temperature Range (Note 3) LTC6995C................................................. 0°C to 70°C LTC6995I..............................................–40°C to 85°C LTC6995H........................................... –40°C to 125°C LTC6995MP........................................ –55°C to 125°C Junction Temperature............................................ 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) S6 Package............................................................ 300°C Pin Configuration LTC6995-1/LTC6995-2 LTC6995-1/LTC6995-2 TOP VIEW V+ 1 DIV 2 TOP VIEW 6 OUT 7 GND RST/RST 1 5 GND 4 RST/RST SET 3 DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 64°C/W, θJC = 9.6°C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL 6 OUT GND 2 5 V+ SET 3 4 DIV S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W Order Information Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LGJM 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6995IDCB-1#TRMPBF LGJM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LGJM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LGJP 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6995IDCB-2#TRMPBF LGJP 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LGJP 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 0°C to 70°C LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –55°C to 125°C LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 0°C to 70°C LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 125°C LTGJQ 6-Lead Plastic TSOT-23 –55°C to 125°C LTC6995IDCB-1#TRPBF LTC6995IDCB-2#TRPBF LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 For more information www.linear.com/6995 699512f LTC6995-1/LTC6995-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1, RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER tOUT Output Clock Period fOUT Output Frequency ∆fOUT Frequency Accuracy (Note 4) CONDITIONS MIN TYP ∆fOUT/∆V+ 34,360 29.1µ 977 Hz ±1.5 ±2.2 % % 29.1µHz ≤ fOUT ≤ 977Hz ±0.8 Frequency Drift Over Temperature UNITS 1.024m l ∆fOUT/∆T MAX l ±0.005 l l 0.23 0.06 Seconds %/°C Frequency Drift Over Supply V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V Long-Term Frequency Stability (Note 11) 90 ppm/√kHr Period Jitter (Note 10) NDIV = 1 NDIV = 8 15 7 ppmRMS ppmRMS BW Frequency Modulation Bandwidth tS Frequency Change Settling Time (Note 9) 0.55 0.16 0.4 • fOUT %/V %/V Hz 1 Cycle Analog Inputs VSET Voltage at SET Pin l ∆VSET/∆T VSET Drift Over Temperature l 0.97 1.00 1.03 ±75 V µV/°C RSET Frequency-Setting Resistor l 50 800 kΩ VDIV DIV Pin Voltage l 0 V+ V ∆VDIV/∆V+ DIV Pin Valid Code Range (Note 5) l ±1.5 % DIV Pin Input Current l ±10 nA V+ Operating Supply Voltage Range l 5.5 V IS Supply Current Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 Power Supply 2.25 1.95 V RL = ∞, RSET = 50k V+ = 5.5V V+ = 2.25V l l 135 105 170 135 µA µA RL = ∞, RSET = 100k V+ = 5.5V V+ = 2.25V l l 100 80 130 105 µA µA RL = ∞, RSET = 800k V+ = 5.5V V+ = 2.25V l l 65 55 100 85 µA µA RL = ∞, ISET = 0µA V+ = 5.5V V+ = 2.25V Power-On Reset Voltage l 60 52 µA µA 699512f For more information www.linear.com/6995 3 LTC6995-1/LTC6995-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1, RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted. SYMBOL Digital I/O VIH VIL IOUT(MAX) VOH VOL PARAMETER RST Pin Input Capacitance RST Pin Input Current High Level RST Pin Input Voltage Low Level RST Pin Input Voltage Output Output Current High Level Output Voltage (Note 7) Low Level Output Voltage (Note 7) tRST Reset Propagation Delay tWIDTH tr Minimum Input Pulse Width Output Rise Time (Note 8) tf Output Fall Time (Note 8) CONDITIONS MIN TYP MAX 2.5 RST = 0V to V+ (Note 6) (Note 6) V+ = 2.7V to 5.5V V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 3.3V V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6995C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: The LTC6995C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6995C is designed, characterized and expected to meet specified performance from –40°C to 85°C but it is not tested or QA sampled at these temperatures. The LTC6995I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6995H is guaranteed to meet specified performance from –40°C to 125°C. The LTC6995MP is guaranteed to meet specified performance from –55°C to 125°C. Note 4: Frequency accuracy is defined as the deviation from the fOUT equation, assuming RSET is used to program the frequency. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. Note 6: The RST pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using VRST(RISING) ≈ 0.55 • V+ + 185mV and VRST(FALLING) ≈ 0.48 • V+ – 155mV. ±10 l 0.7 • V+ 0.3 • V+ l IOUT = –1mA IOUT = –16mA IOUT = –1mA IOUT = –10mA IOUT = –1mA IOUT = –8mA IOUT = 1mA IOUT = 16mA IOUT = 1mA IOUT = 10mA IOUT = 1mA IOUT = 8mA l l l l l l l l l l l l 5.45 4.84 3.24 2.75 2.17 1.58 ±20 5.48 5.15 3.27 2.99 2.21 1.88 0.02 0.26 0.03 0.22 0.03 0.26 16 24 40 5 1.1 1.7 2.7 1.0 1.6 2.4 0.04 0.54 0.05 0.46 0.07 0.54 UNITS pF nA V V mA V V V V V V V V V V V V ns ns ns ns ns ns ns ns ns ns Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within ±1% of the final frequency after a 0.5× or 2× change in ISET . Note 10: Jitter is the ratio of the deviation of the period to the mean of the period. This specification is based on characterization and is not 100% tested. Note 11: Long-term drift of silicon oscillators is primarily due to the movement of ions and impurities within the silicon and is tested at 30°C under otherwise nominal operating conditions. Long-term drift is specified as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate drift for a set time period, translate that time into thousands of hours, take the square root and multiply by the typical drift number. For instance, a year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift without power applied to the device may be approximated as 1/10th of the drift with power, or 9ppm/√kHr for a 90ppm/√kHr device. 699512f 4 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted. Frequency Error vs Temperature Frequency Error vs Temperature 3 GUARANTEED MAX OVER TEMPERATURE RSET = 50k 3 PARTS 0 –1 2 RSET = 200k 3 PARTS 1 ERROR (%) 1 0 GUARANTEED MIN OVER TEMPERATURE –2 –3 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 GUARANTEED MIN OVER TEMPERATURE –2 –3 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 100 699512 G01 Frequency Error vs RSET GUARANTEED MAX OVER TEMPERATURE DRIFT (%) ERROR (%) 200 0.2 –1 0.1 0 –0.1 –0.2 REFERENCED TO V+ = 4.5V RSET = 50k RSET = 200k RSET = 800k –0.3 GUARANTEED MIN OVER TEMPERATURE –0.4 200 400 RSET (kΩ) 600 –0.5 800 2 100 0 0.98 0.8 0.8 1.015 0.6 0.6 0.4 0.4 0.2 0.2 –0.6 –0.6 –1.0 0 5 10 ISET (µA) 15 20 699512 G07 VSET (V) 1.000 0.995 0.990 –0.8 –1.0 3 PARTS 1.005 –0.2 –0.4 1.02 1.012 1.010 0 –0.4 REFERENCED TO ISET = 10µA 0.996 1.004 VSET (V) VSET vs Temperature 1.020 –0.8 0.988 699512 G06 VSET Drift vs Supply DRIFT (mV) VSET (mV) 150 1.0 0 2 LOTS DFN AND SOT-23 1274 UNITS 699512 G05 VSET Drift vs ISET 125 50 6 4 3 5 SUPPLY VOLTAGE (V) 699512 G04 –0.2 100 Typical VSET Distribution 250 0.3 3 PARTS 0 50 25 75 0 TEMPERATURE (°C) 699512 G03 0.4 1 1.0 –3 –50 –25 125 Frequency Drift vs Supply Voltage 0 GUARANTEED MIN OVER TEMPERATURE –2 0.5 –2 0 699512 G02 3 2 RSET = 800k 3 PARTS –1 –1 NUMBER OF UNITS ERROR (%) 1 GUARANTEED MAX OVER TEMPERATURE GUARANTEED MAX OVER TEMPERATURE 2 ERROR (%) 2 –3 Frequency Error vs Temperature 3 3 0.985 REFERENCED TO V+ = 4V 2 3 4 SUPPLY (V) 6 5 699512 G08 0.980 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 699512 G09 699512f For more information www.linear.com/6995 5 LTC6995-1/LTC6995-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted. Supply Current vs Supply Voltage 150 125 100 RSET = 100k RSET = 200k 75 RSET = 800k 50 25 2 3 4 5 SUPPLY VOLTAGE (V) 250 125 5V, RSET = 100k 100 2.5V, RSET = 100k 75 5V, RSET = 800k 50 2.5V, RSET = 800k 25 0 –50 –25 6 50 25 75 0 TEMPERATURE (°C) 150 1000 V+ = 2.5V 0 200 400 RSET (kΩ) 600 600 400 0 800 2 3 4 5 SUPPLY VOLTAGE (V) 20 15 10 2 4 3 5 SUPPLY VOLTAGE (V) 6 NEGATIVE-GOING 1.5 1.0 2 3 4 5 SUPPLY VOLTAGE (V) 200 CLOAD = 5pF 65 UNITS SOT-23 AND DFN PARTS TA = 30°C 150 2.0 tRISE 1.5 tFALL 1.0 0 6 Typical Frequency Error vs Time (Long-Term Drift) 0.5 5 1.0 699512 G15 DELTA FREQUENCY (ppm) RISE/FALL TIME (ns) PROPAGATION DELAY (ns) 25 0 2.0 0 6 2.5 40 0.8 0.5 3.0 CLOAD = 5pF 30 0.6 0.4 VRST/V+ (V/V) 2.5 Rise and Fall Time vs Supply Voltage 35 0.2 699512 G14 Reset Propagation Delay (tRST) vs Supply Voltage 45 0 POSITIVE-GOING 699512 G13 50 50 3.0 200 25 0 100 3.5 SET PIN SHORTED TO GND RST PIN VOLTAGE (V) ISET (µA) V+ = 3.3V 3.3V RST RISING RST Threshold Voltage vs Supply Voltage 100 50 3.3V RST FALLING 699512 G12 800 V+ = 5V 75 5V RST RISING 150 0 125 5V RST FALLING 200 Typical ISET Current Limit vs V+ Supply Current vs RSET POWER SUPPLY CURRENT (µA) 100 RSET = 800k 699512 G11 699512 G10 125 POWER SUPPLY CURRENT (µA) RSET = 50k POWER SUPPLY CURRENT (µA) POWER SUPPLY CURRENT (µA) 150 0 Supply Current vs RST Pin Voltage Supply Current vs Temperature 100 50 0 –50 –100 –150 2 3 4 5 SUPPLY VOLTAGE (V) 6 699512 G17 –200 0 400 800 1200 1600 2000 2400 2800 TIME (h) 699512 G18 699512 G16 699512f 6 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted. Output Resistance vs Supply Current Typical LTC6995-1 Start-Up with POL = 1 50 OUTPUT RESISTANCE (Ω) 45 V+ 5V/DIV 40 35 RST 5V/DIV OUTPUT SOURCING CURRENT 30 OUT 5V/DIV 25 20 V+ = 5V DIVCODE = 15 RSET = 499k OUTPUT SINKING CURRENT 15 10 RESET RELEASED, 100Hz OUTPUT CLOCK OUTPUT RESET 4ms START-UP 5ms/DIV 699512 G20 5 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 699512 G19 Pin Functions (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1µF capacitor. 50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. An internal A/D converter (referenced to V+) monitors the DIV pin voltage (VDIV) to determine a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the OUT pin. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25µA to 20µA. The output oscillation will stop if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to set the frequency. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and RST OUT LTC6995-1/ LTC6995-2 GND V+ SET RSET V+ C1 0.1µF R1 DIV 699512 PF R2 RST or RST (Pin 4/Pin 1): Output Reset. The reset input is used to stop the output oscillator and to clear internal dividers. When reset is released the oscillator starts with a full half period time interval. The output logic state when reset is determined by the programmed DIVCODE. The LTC6995-1 has an active high RST input. The LTC6995-2 has an active low RST input. 699512f For more information www.linear.com/6995 7 LTC6995-1/LTC6995-2 Pin Functions (DCB/S6) GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. 30Ω. When driving an LED or other low impedance load a series output resistor should be used to limit source/ sink current to 20mA. OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings from GND to V+ with an output resistance of approximately Block Diagram (S6 package pin numbers shown) 5 V+ R1 4 DIV 4-BIT A/D CONVERTER POL BIT DIGITAL FILTER R2 MASTER OSCILLATOR 1µs V = SET 50kΩ ISET tMASTER = HALT OSCILLATOR OUTPUT IF ISET < 500nA MCLK FIXED DIVIDER ÷ 1024 PROGRAMMABLE DIVIDER ÷1, 8, 64, 512 4096, 215, 218, 221 OUTPUT POLARITY OUT 6 tOUT DIVIDER RESET ISET + – VSET = 1V POR + – SET LTC6995-2 ONLY 1V RST GND 3 2 1 699512 BD ISET RSET 699512f 8 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Operation The LTC6995 is built around a master oscillator with a 1MHz maximum frequency. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1MHz • 50k conversion factor that is accurate to ±0.8% under typical conditions. fMASTER = 1 tMASTER I = 1MHz • 50kΩ • SET VSET A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the output frequency. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: fMASTER = 1 tMASTER = DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6995: 1.DIVCODE determines the output frequency divider setting, NDIV . 2.DIVCODE determines the polarity of the RST and OUT pins, via the POL bit. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1. 2.25V TO 5.5V V+ 1MHz • 50kΩ RSET LTC6995 DIV R2 From this equation, it is clear that VSET drift will not affect the output frequency when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ∆fOUT of the LTC6995. RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). Before reaching the OUT pin, the oscillator frequency passes through a fixed ÷1024 divider. The LTC6995 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. fOUT = tOUT = 1MHz • 50kΩ ISET • , or 1024 • NDIV VSET 1 fOUT = NDIV VSET • • 1.024ms 50kΩ ISET NDIV • RSET • 1.024ms 50kΩ GND 699512 F01 Figure 1. Simple Technique for Setting DIVCODE Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1.The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects) 2.The driving impedance (R1||R2) does not exceed 500kΩ. If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: with RSET in place of VSET/ISET the equation reduces to: tOUT = R1 VDIV DIVCODE + 0.5 = ± 1.5% V+ 16 For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. 699512f For more information www.linear.com/6995 9 LTC6995-1/LTC6995-2 Operation Table 1. DIVCODE Programming DIVCODE POL NDIV RECOMMENDED tOUT R1 (kΩ) R2 (kΩ) VDIV/V+ 0 0 1 1.024ms to 16.384ms Open Short ≤0.03125 ±0.015 1 0 8 8.192ms to 131ms 976 102 0.09375 ±0.015 2 0 64 65.5ms to 1.05sec 976 182 0.15625 ±0.015 3 0 512 524ms to 8.39sec 1000 280 0.21875 ±0.015 4 0 4,096 4.19sec to 67.1sec 1000 392 0.28125 ±0.015 5 0 32,768 33.6sec to 537sec 1000 523 0.34375 ±0.015 6 0 262,144 268sec to 4,295sec 1000 681 0.40625 ±0.015 7 0 2,097,152 2,147sec to 34,360sec 1000 887 0.46875 ±0.015 8 1 2,097,152 2,147sec to 34,360sec 887 1000 0.53125 ±0.015 9 1 262,144 268sec to 4,295sec 681 1000 0.59375 ±0.015 10 1 32,768 33.6sec to 537sec 523 1000 0.65625 ±0.015 11 1 4,096 4.19sec to 67.1sec 392 1000 0.71875 ±0.015 12 1 512 524ms to 8.39sec 280 1000 0.78125 ±0.015 13 1 64 65.5ms to 1.05sec 182 976 0.84375 ±0.015 14 1 8 8.192ms to 131ms 102 976 0.90625 ±0.015 15 1 1 1.024ms to 16.384ms Short Open ≥0.96875 ±0.015 POL BIT = 0 POL BIT = 1 10000 7 6 1000 9 10 5 100 tOUT (SECONDS) 8 11 4 10 12 3 1 13 2 0.1 1 0.01 0.001 14 0 0V 15 0.5•V+ INCREASING VDIV V+ 699512 F02 Figure 2. Frequency Range and POL Bit vs DIVCODE 699512f 10 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Operation Reset and Polarity Bit Functions The Reset input, RST for the LTC6995-1 and RST for the LTC6995-2, forces the output to a fixed state and resets the internal clock dividers. The output state when reset is determined by the polarity bit as selected by through the DIVCODE setting. OUTPUT (OSCILLATOR START STATE) RST/RST POLARITY LTC6995-1 0 0 Oscillating (Low) LTC6995-2 0 (Reset) 1 0 0 (Reset) Oscillating (Low) 0 1 Oscillating (High) 1 (Reset) 1 1 1 (Reset) Oscillating (High) With the POL bit programmed to be 0, the output will be forced low when reset. When reset is released by changing state, the oscillator starts. The next rising edge at the output follows a precise half cycle delay. With the POL bit programmed to be 1, the output will be forced high when reset. When reset is released by changing state, the oscillator starts. The next falling edge at the output follows a precise half cycle delay. tWIDTH tWIDTH RST RST tRST tRST OUT REMAINS LOW WHILE RST IS HIGH OUT tOUT LTC6995-1 OUT REMAINS LOW WHILE RST IS LOW OUT 699512 F03 tOUT 1/2 tOUT LTC6995-2 1/2 tOUT Figure 3. Reset Timing Diagram (POL Bit = 0) tWIDTH tWIDTH RST RST tRST tRST OUT REMAINS HIGH WHILE RST IS HIGH OUT tOUT LTC6995-1 1/2 tOUT OUT REMAINS HIGH WHILE RST IS LOW OUT 699512 F04 tOUT LTC6995-2 1/2 tOUT Figure 4. Reset Timing Diagram (POL Bit = 1) 699512f For more information www.linear.com/6995 11 LTC6995-1/LTC6995-2 Operation Changing DIVCODE After Start-Up Following start-up, the A/D converter will continue monitoring VDIV for changes. The LTC6995 will respond to DIVCODE changes in less than one cycle. tDIVCODE < 500 • tMASTER < tOUT The output may have an inaccurate pulse width during the frequency transition. But the transition will be glitch-free and no high or low pulse can be shorter than the master clock period. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. Start-Up Time When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . A supply voltage of typically 1.4V (1.2V to 1.5V over temperature) initiates the start-up sequence. The OUT pin is held low during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tSTART(TYP) = 500 • tMASTER During start-up, the DIV pin A/D converter must determine the correct DIVCODE before the output is enabled. The start-up time may increase if the supply or DIV pin DIV 200mV/DIV voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not affect performance. Start-Up Behavior When first powered up, the output is held low. If the polarity is set for non-inversion (POL = 0) and the output is enabled at the end of the start-up time, OUT will begin oscillating. If the output is being reset (RST = 1 for LTC6995-1 and RST = 0 for LTC6995-2) at the end of the start-up time, it will remain low due to the POL bit = 0. When reset is released the oscillator starts and the output remains low for precisely one half cycle of the programmed period. In inverted operation (POL = 1), the start-up sequence is similar. However, the LTC6995 does not know the correct DIVCODE setting when first powered up, so the output defaults low. At the end of tSTART , the value of DIVCODE is recognized and OUT goes high (inactive) because POL = 1. If the output is being reset (RST = 1 for LTC6995-1 and RST = 0 for LTC6995-2) at the end of the start-up time, it will remain high due to the POL bit = 1. When reset is released the oscillator starts and the output remains high for precisely one half cycle of the programmed period. Figures 7 to 10 detail the possible start-up sequences. V+ 1V/DIV OUT 1V/DIV 500µs OUT 1V/DIV V+ = 3.3V RSET = 200k 10ms/DIV 699512 F05 Figure 5. DIVCODE Change from 1 to 0 V+ = 2.5V DIVCODE = 15 RSET = 50k 250µs/DIV 699512 F06 Figure 6. Typical Start-Up LTC6995-1 with RST = 0V 699512f 12 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Operation RST RST OUT OUT tSTART tOUT 1/2 tOUT tSTART tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F07 Figure 7. Start-Up Timing Diagram (Reset = 0, POL Bit = 0) RST RST OUT OUT tSTART tOUT 1/2 tOUT tSTART tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F08 Figure 8. Start-Up Timing Diagram (Reset = 1, POL Bit = 0) RST RST OUT OUT tSTART tOUT 1/2 tOUT tSTART tOUT 1/2 tOUT LTC6995-1 LTC6995-2 699512 F09 Figure 9. Start-Up Timing Diagram (Reset = 0, POL Bit = 1) RST RST OUT OUT tSTART 1/2 tOUT tOUT tSTART LTC6995-1 tOUT 1/2 tOUT LTC6995-2 699512 F10 Figure 10. Start-Up Timing Diagram (Reset = 1, POL Bit = 1) 699512f For more information www.linear.com/6995 13 LTC6995-1/LTC6995-2 Applications Information Basic Operation The simplest and most accurate method to program the LTC6995 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a 3-step process. First select the POL bit setting and NDIV value, then calculate the value for the RSET resistor. Step 1: Select the LTC6995 Version and POL Bit Setting Determine if the application requires an active-high, LTC6995-1 or active-low, LTC6995-2 reset function. Otherwise the two versions share identical functionality. The OUT pin polarity depends on the setting of the POL bit. To force OUT = 0 during reset, choose POL bit = 0. To force OUT = 1 during reset, choose POL bit = 1. Step 2: Select the NDIV Frequency Divider Value As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given output clock period, NDIV should be selected to be within the following range. tOUT t ≤ NDIV ≤ OUT 1.024ms 16.384ms (1) Example: Design a 1Hz oscillator with minimum power consumption, an active-high reset input, and the OUT pin low during reset. Step 1: Select the LTC6995 Version and POL Bit Setting For active-high reset select the LTC6995-1. For OUT low during reset choose POL bit = 0. Step 2: Select the NDIV Frequency Divider Value Choose an NDIV value that meets the requirements of Equation (1), using tOUT = 1000ms: 61.04 ≤ NDIV ≤ 976.6 Potential settings for NDIV include 64 and 512. NDIV = 64 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 0 and NDIV = 64 requires DIVCODE = 2. Using Table 1, choose R1 = 976k and R2 = 182k values to program DIVCODE = 2. Step 3: Select RSET Calculate the correct value for RSET using Equation (2). RSET = 50k 1000ms • = 763k 1.024ms 64 To minimize supply current, choose the lowest NDIV value (generally recommended). Alternatively, use Table 1 as a guide to select the best NDIV value for the given application. Since 763k is not available as a standard 1% resistor, substitute 768k if a –0.7% frequency shift is acceptable. Otherwise, select a parallel or series pair of resistors such as 576k + 187k to attain a more precise resistance. With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. The completed design is shown in Figure 11. Step 3: Calculate and Select RSET RST 50k t • OUT 1.024ms NDIV (2) OUT LTC6995-1 The final step is to calculate the correct value for RSET using the following equation. RSET = RST GND 2.25V TO 5.5V V+ R1 976k SET RSET 763k DIV DIVCODE = 2 R2 182k 699512 F11 Select the standard resistor value closest to the calculated value. Figure 11. 1Hz Oscillator 699512f 14 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Applications Information Power-On Reset (POR) Function When power is applied to the LTC6995 the output is held low for tSTART, then takes on the value of the POL bit as the clock cycle begins. If POL = 0 (DIVCODE < 8) the output will remain low for a programmable interval of tSTART + 1/2 tOUT, assuming the RST pin is inactive. This makes the LTC6995 useful as a programmable long-time power-on reset (POR), with the low output used to hold a system in reset for a fixed period after power is applied. Timing begins when the V+ supply exceeds approximately 1.4V. RST POR OUT LTC6995-1 GND RSET 191k V+ R1 1M SET RST = V+ FOR LTC6995-2 2.25V TO 5.5V 0.1µF DIV R2 280k tPOR = 1 SECOND FOR VALUES SHOWN POL = 0 DIVCODE = 3 NDIV = 512 To prevent additional output transitions after the initial POR time, the oscillator can be disabled by removing the SET pin current. This prevents the internal master oscillator output from clocking the frequency dividers or output, while keeping it biased so it can resume operation quickly. The easiest way to implement this feature is to connect RSET between the SET and OUT pins. V+ tSTART ~1.4V STARTS TIMER tDELAY (1/2 tOUT) OUT POL = 0 POWER-ON RESET TIMER STOPPED 699512 F12 Figure 12. Active Low Power-On Reset (1 Second Interval Example) Figure 12 shows the basic power-on reset function. When the half cycle times out, the output goes high, eliminates the SET pin current, and stops additional OUT pin transitions. The output remains high until the device is reset by driving the RST input or power is cycled off then back on. The POR interval is only one half of an oscillator period so component selection is slightly different. Table 2 provides the component values required for one half cycle time intervals. Timing starts after a short startup delay time following the application of the V+ supply. Table 2. Power-On Reset (POR). One Shot, One Half Cycle Delay Programming Output Low During Time Interval, POL = 0 DIVCODE tDELAY TIME INTERVAL (1/2 tOUT) R1 (kΩ) R2 (kΩ) ~RSET (kΩ) 0 512µs to 8.2ms Open Short tDELAY(MS) • 97.6 1 4.1ms to 65.5ms 976 102 tDELAY(MS) • 12.2 2 32.8ms to 524.3ms 976 182 tDELAY(MS) • 1.5 3 262.1ms to 4.2sec 1000 280 tDELAY(SEC) • 190.7 4 2.1sec to 33.6sec 1000 392 tDELAY(SEC) • 23.8 5 16.8sec to 4.5min 1000 523 tDELAY(MIN) • 178.6 6 2.2min to 35.8min 1000 681 tDELAY(MIN) • 22.7 7 17.9min to 4.8hrs 1000 887 tDELAY(HR) • 167.6 Note: Power-On Reset Time = tDELAY + tSTART 699512f For more information www.linear.com/6995 15 LTC6995-1/LTC6995-2 Applications Information For shorter power on reset times (1ms to 73ms) the timer startup delay becomes a significant part of the total POR time. To take this delay into account the value for RSET can be modified from the values shown in Table 2. For a POR time in the range from 1ms to 16ms (DIVCODE = 0), RSET should be tPOR(ms) • 49.5. For a POR time in the range from 4.5ms to 73ms (DIVCODE = 1), RSET is tPOR(ms) • 10.9. For longer POR times (DIVCODE 2 through 7) the startup time is insignificant. After power on, the delay following a reset condition will be in the same range as shown for tDELAY in Table 2 for these two DIVCODE selections. For short POR times, a more precise estimation of the startup time can be found from the following: tSTART (µs) = ( 256 + 16 • (12 – DIVCODE)) RSET (kΩ) 50 +80 Supply bounce resets the internal timer so the POR circuit automatically debounces supply noise. POR timing starts from the time that the V+ supply has reached approximately 1.4 volts. Long Timer One Shots and Delay Generators The POR circuit of Figure 12 is also useful when the reset inputs are driven. This creates edge triggered timing events that are active low and can either be re-triggered or can stop after one programmed interval. The programmed time interval can range from only 500µs to over 4 hours with just resistor value changes. The circuits in Figure 13 show how a POR or active low interval can be re-started to provide a full system reset time. The Figure 14 circuit requires an indication from the system being reset that it is ready before timing out. The LTC6995-2 can accommodate an active high OK signal. By forcing a reset condition at power on the LTC6995 can be used to create a long time delayed rising edge triggered by either a falling edge signal (LTC6995-1) or a rising edge signal (LTC6995-2) as show in Figure 15. V+ V+ 100k RST OUT RST POR LTC6995-1 100k RSET GND V+ SET DIV V+ 0.1µF R1 ACTIVE HIGH RESET V+ RSET R2 GND V+ SET DIV POR R1 ACTIVE LOW RESET V+ 0.1µF R2 V+ RESET RESET RST OUT POL = 0 OUT LTC6995-2 RST tSTART + 1/2 tOUT POR 1/2 tOUT TIMER STOPPED TIMER STOPPED OUT POL = 0 POR tSTART + 1/2 tOUT POR 1/2 tOUT TIMER STOPPED TIMER STOPPED POR 699512 F13 Figure 13. System Resets On Command with Full POR Time Interval. Reset Pulse Is Debounced Automatically 699512f 16 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Applications Information SYSTEM OK RST V+ POR OUT SYSTEM LTC6995-1 RSET RST GND V+ SET DIV R1 SYSTEM OK V+ 0.1µF tSTART + 1/2 tOUT OUT POL = 0 R2 POR 1/2 tOUT POR EXTENDED TIMER STOPPED POR 699512 F14 Figure 14. Extended POR. Timer Reset During Initial POR Interval. Full POR Interval Provided Once System Signals the OK TRIGGER RST OUTPUT OUT TRIGGER LTC6995-1 GND RSET FALLING EDGE TRIGGERED POL = 0 V+ V+ 0.1µF GND RSET DIV R2 V+ TRIGGER TRIGGER 1/2 tOUT V+ R1 SET 1/2 tOUT OUTPUT V+ 0.1µF DIV RISING EDGE TRIGGERED POL = 0 V+ OUTPUT OUTPUT OUT LTC6995-2 R1 SET RST 1/2 tOUT R2 1/2 tOUT 699512 F15 Figure 15. Long Time Delayed Rising Edge. Delay Time Can Range from 500µs to 4.8 Hours 699512f For more information www.linear.com/6995 17 LTC6995-1/LTC6995-2 Applications Information Watchdog Timers Using the same circuits as shown in Figure 15 with periodic pulsing of the reset input can create an effective watchdog timer. A watchdog pulse is required from a system within each timing interval. The watchdog timeout interval can be programmed from 500µs to 4.8 hours. If a pulse is missed the output goes high to indicate that the system software may be caught in an infinite loop. This high level can be used to initiate software diagnostic or restart procedures. The LTC6995 internal clock stops and the output remains high until the software recovers and returns to issuing watchdog pulses. Figure 16 shows the timing for this application. Watchdog timers are used to detect if a system operating software is diverted from the designed program sequence for any reason. It is always a possibility that the software could get stuck in a way that keeps the watchdog pulse in the state that holds the timer in the reset so it can never time out. In this condition the watchdog timer is ineffective and will never force corrective action. To help to prevent this a second one shot can be used to reset the watchdog timer as shown in Figure 17. V+ MISSED PULSE RST (LTC6995-1) WATCHDOG PULSES RST (LTC6995-2) OUTPUT SERVICE WATCHDOG TIMER RESTARTS TIMEOUT RESUME 699512 F16 Figure 16. Watchdog Timer. Same Circuits as Shown in Figure 15 100µs ONE SHOT SYSTEM POSITIVE WATCHDOG PULSE TRG OUT RST LTC6993-1 GND RSET 619k 50ms WATCHDOG TIMER SET V+ DIV OUT OUTPUT LTC6995-1 V+ V+ GND RSET 604k R1 976k SET V+ 0.1µF DIV R2 102k RISING EDGE TRIGGERED POSITIVE OUTPUT PULSE DIVCODE = 1 FALLING EDGE TRIGGERED POL = 0 DIVCODE = 1 699512 F17 Figure 17. Extra-Reliable Watchdog Timer. Allows Timeout if System Watchdog Pulse Gets Stuck in the Timer Reset State. Both Timer Devices Can Share the Same DIVCODE Setting 699512f 18 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Applications Information Gated Oscillators The reset input (RST) clears all internal dividers so that, when released, the output will start clocking with a full programmed period. This edge can be used to gate the output ON and OFF at a known starting point for the clock. Circuits which count clock cycles for further timing purposes will always have an accurate count of full cycles until reset. The output clock is always at 50% duty cycle and the period of each cycle can range from 1ms to 9.5 hours. Depending on the polarity bit selection the output clock can start high or low as shown in Figure 18. Self-Resetting Circuits The RST pin has hysteresis to accommodate slow-changing input voltages. Furthermore, the trip points are proportional to the supply voltage (see Note 6 and the RST Threshold Voltage vs Supply Voltage curve in Typical Performance Characteristics). This allows an RC time constant at the RST input to generate a delay that is nearly independent of the supply voltage. A simple application of this technique allows the LTC6995 output to reset itself, producing a well-controlled pulse once each cycle. Figures 19a and 19b show circuits that produce approximately 1µs pulses once a minute. The only difference is the version of LTC6995 used and the POL bit setting, which controls whether the pulse is positive or negative. Voltage Controlled Frequency With one additional resistor, the LTC6995 output frequency can be manipulated by an external voltage. As shown in Figure 20, voltage VCTRL sources/sinks a current through RVCO to vary the ISET current, which in turn modulates the output frequency as described in Equation (3). fOUT = R V 1MHz • 50kΩ • 1+ VCO – CTRL 1024 • NDIV • R VCO RSET VSET LTC6995-1 ACTIVE HIGH RESET RST FALLING EDGE STARTS THE CLOCK RST OUT POL = 0 OUT POL = 1 (3) LTC6995-2 ACTIVE LOW RESET RST RISING EDGE STARTS THE CLOCK RST 1/2 tOUT 1/2 tOUT OUT POL = 0 OUT POL = 1 1/2 tOUT 1/2 tOUT 699512 F18 Figure 18. Gated Oscillators. First One-Half Cycle Time Always Accurate 699512f For more information www.linear.com/6995 19 LTC6995-1/LTC6995-2 Applications Information OUT RPW 2.26k RST RST CPW 470pF OUT LTC6995-1 GND SET GND 2.25V TO 5.5V V+ 0.1µF R1 1M RSET 178k VCTRL RVCO DIV SET ( VRST(RISING) V+ tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61) tPULSE ≈ 1µs ) Figure 19a. Self-Resetting Circuit (DIVCODE = 4) OUT RPW 2.26k RSET 178k OUT 0.1µF DIV R2 1M ( VRST(FALLING) V+ tPULSE ≈ –2.26kΩ • 470pF • In(0.43) tPULSE ≈ 0.9µs tPULSE = –RPW • CPW • In DIV R2 The control voltage can be generated by a DAC (digitalto-analog converter), resulting in a digitally-controlled frequency. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC’s reference voltage, as shown in Figure 21. The DAC’s output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC’s REF input would affect the frequency. 2.25V TO 5.5V V+ R1 523k SET R1 Digital Frequency Control 699512 F19a GND C1 0.1µF Figure 20. Voltage-Controlled Oscillator 1µs PULSE WIDTH 60 SECONDS LTC6995-2 V+ 699512 F20 tPULSE = –RPW • CPW • In 1– RST V+ RSET R2 523k CPW 470pF OUT LTC6995-1 ) ISET Extremes (Master Oscillator Frequency Extremes) When operating with ISET outside of the recommended 1.25µA to 20µA range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator can still function with reduced accuracy for ISET < 1.25µA. At approximately 500nA, the oscillator output will be frozen in its current state. The output could halt in a high or low state. This avoids introducing short pulses when frequency modulating a very low frequency output. 0.9µs PULSE WIDTH 60 SECONDS 699512 F19b Figure 19b. Self-Resetting Circuit (DIVCODE = 11) At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. 699512f 20 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Applications Information RST OUT V+ LTC6995 0.1µF V+ GND + SET 1/2 LTC6078 V+ C1 0.1µF R1 DIV R2 – V+ 0.1µF VCC DIN µP CLK LTC1659 VOUT RVCO CS/LD GND ( R D 1MHz • 50kΩ • 1 + VCO – IN RSET 4096 1024 • NDIV • RVCO DIN = 0 TO 4095 fOUT = REF ) RSET 699512 F21 Figure 21. Digitally-Controlled Oscillator Frequency Modulation and Settling Time The LTC6995 will respond to changes in ISET up to a –3dB bandwidth of 0.4 • fOUT . Following a 2× or 0.5× step change in ISET , the output frequency takes less than one cycle to settle to within 1% of the final value. Power Supply Current The power supply current varies with frequency, supply voltage and output loading. It can be estimated under any condition using the following equation. This equation ignores CLOAD (valid for CLOAD < 1nF) and assumes the output has 50% duty cycle. IS(TYP) ≈ V+ • fMASTER • 7.8pF + V+ V+ + 420kΩ 2 • RLOAD + 1.8 •ISET + 50µA Supply Bypassing and PCB Layout Guidelines The LTC6995 is a 2.2% accurate silicon oscillator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 22 shows example PCB layouts for both the TSOT-23 and DFN packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6995. These layouts are a guide and need not be followed exactly. 1.Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DFN package, C1’s connection to GND is also simply done on the top layer. For the TSOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1µF ceramic capacitor. 699512f For more information www.linear.com/6995 21 LTC6995-1/LTC6995-2 Applications Information RST OUT LTC6995 GND SET V+ V+ C1 0.1µF R1 DIV RSET R2 V+ R1 R2 V+ C1 C1 V+ OUT RST OUT DIV GND GND V+ SET RST SET DIV R1 RSET RSET R2 699512 F22 DFN PACKAGE TSOT-23 PACKAGE Figure 22. Supply Bypassing and PCB Layout 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the operating frequency. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. 699512f 22 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Typical Applications Timed Power Switches, Auto Shutoff After One Hour P-CHANNEL MOSFET * TO LOAD COUT CURRENT DEPENDS ON PMOS SELECTION 3V TO 36V 5V LTC4412HV VIN SENSE 0.1µF PUSH TO ACTIVATE RST LOW = ON HIGH = OFF OUT GND GATE CTL STAT *DRAIN-SOURCE DIODE OF MOSFET LTC6995-1 100k GND RSET 169k V+ 5V 0.1µF R1 1M SET 2.6V TO 5.5V DIV ACTIVE HIGH RESET 1/2 tOUT = 1 HOUR IN OUT LTC4411 GND 1µF R2 887k CTL STAT COUT 4.7µF TO LOAD UP TO 2.6A 699512 TA08 5 Second On/Off Timed Relay Driver 12V 0.1µF L D1 1N4148 RESET RUN RELAY ENABLE RST OUT LTC6995-1 GND R4 15k R3 118k Q1 2N2219A 1 COTO 1022 RELAY 9001-12-01 5V V+ R1 1M SET C NO C2 0.1µF DIV R2 392k 699512 TA02 699512f For more information www.linear.com/6995 23 LTC6995-1/LTC6995-2 Typical Applications 1.5ms Radio Control Servo Reference Pulse Generator 5V R7 10k RESET = OPEN RUN = GND 20ms FRAME RATE GENERATOR RST 20ms PERIOD OUT LTC6995-1 TRIG 5V SET 5V V+ GND C1 0.01µF R4 976k 1.5ms PULSE OUT LTC6993-1 V+ GND R6 121k 1.5ms REFERENCE PULSE C2 0.1µF R1 1M DIV SET R3 146k R5 102k DIV R2 280k 699512 TA03 Cycling (10 Seconds On/Off) Symmetrical Power Supplies M2 Si4435DY 15VIN RST R2 1k M3 Si9410 R11 5k OUT LTC6995-1 V+ GND 5V C1 0.1µF R8 1M SET M4 Si4435DY DIV R9 392k R10 237k 15VOUT R6 20k –15VIN R1 100k R3 50k –15VOUT M1 Si9410 699512 TA04 Isolated AC Load Flasher 5V OPEN = OFF GND = ON R3 10k 0.1µF 5 1 RST V+ OUT LTC6995-1 3 RSET 237k SET GND DIV R4 215Ω 6 4 2 R1 1M R2 392k 1 U2 MOC3041M 6 R5 5.94k 2 5V ZERO CROSSING U3 NTE5642 4 10 SECONDS ON/OFF 40W LAMP R6 10k HOT 117V AC R7 100Ω C2 0.022µF 699512 TA05 NEUTRAL AC ISOLATION BARRIER = 7500V 699512f 24 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Typical Applications Interval (Wiper) Timer 5s 15s 30s 5V 2s V+ 1m 2m 4m OFF RST 24.9k OUT TRIG LTC6995-1 178k 5s 15s 30s 59k 2s GND 29.4k V+ V+ 0.1µF SET 1m 2m 4m OFF OUTPUT OUT 2s LTC6993-1 V+ V+ GND 0.1µF 1M DIV 2 SECONDS TO 4 MINUTES DIV SET 383k tINTERVAL 1M 681k 2s 699512 TA06 90.9k 280k 5s 15s 30s 113k 1m 2m 4m 133k 2s OFF 154k Adjustable Time Lapse Photography Intervalometer SHUTTER OPEN TIME LAPSE TIME LAPSE RST OUT TRG LTC6995-1 GND V+ V+ GND V+ 0.1µF 66.5k SHORT 1M LONG 2M SET 3s TO 30s DIV LONG TIMER 3s TO 3Hrs OUTPUT OUT LTC6993-3 392k 30s TO 3m 523k 56.2k 30m TO 3Hrs 3m TO 30m SHORT 967k 1M LONG 681k 1M TIME LAPSE 2M V+ 1M SET DIV NON-RETRIGGERABLE ONE SHOT TIMER 0.3s TO 30s 0.3s TO 3s 681k EXPOSURE TIME 3s TO 30s 887k 699512 TA09 699512f For more information www.linear.com/6995 25 LTC6995-1/LTC6995-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 (2 SIDES) 2.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 1.35 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP R = 0.05 TYP 2.00 ±0.10 (2 SIDES) 3.00 ±0.10 (2 SIDES) 0.40 ±0.10 4 6 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 × 45° CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 ±0.05 1 (DCB6) DFN 0405 0.25 ±0.05 0.50 BSC 1.35 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 699512f 26 For more information www.linear.com/6995 LTC6995-1/LTC6995-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.90 BSC NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 S6 TSOT-23 0302 699512f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaForofmore information www.linear.com/6995 tion that the interconnection its circuits as described herein will not infringe on existing patent rights. 27 LTC6995-1/LTC6995-2 Typical Application Sentry Timer V+ Q V+ CLK FF Q 100k D V+ CLR PUSH BUTTON EVERY 4 HOURS OR ALARM SOUNDS RST OUT LTC6995-2 GND V+ V+ 15Ω 4 HOUR TIMER DIVCODE = 7 R1 887k SET 800Hz ALARM TONE DIVCODE = 0 DIV R2 49.9k 75k 32Ω 60.4k 332k 699512 TA07 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators Micropower, ISUPPLY = 35µA at 400kHz LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation LTC6991 TimerBlox: Very Low Frequency Oscillator with Reset Cycle Time from 1ms to 9.5 Hours, No Capacitors, 2.2% Accurate LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range LTC6993 TimerBlox: Monostable Pulse Generator (One Shot) Resistor Programmable Pulse Width of 1µs to 34sec LTC6994 TimerBlox: Delay Block/Debouncer Delays Rising, Falling or Both Edges 1µs to 34sec 699512f 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/6995 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/6995 LT 0213 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013