CYIS1SM0250-AA
CYIS1SM0250-AA STAR250 250K Pixel
Radiation Hard CMOS Image Sensor
Features
Key Features (continued)
The STAR250 sensor is a CMOS Active Pixel Sensor,
designed for application in Optical Inter-Satellite Link beam
trackers. The STAR250 is part of broader range of applications
such as space-borne systems like sun sensing and star
tracking. It features 512 by 512 pixels on a 25 µm pitch, on chip
Fixed Pattern Noise (FPN) correction, a programmable gain
amplifier, and a 10bit ADC. Flexible operating (multiple
windowing, subsampling) is possible by direct addressable Xand Y- register.
The sensor has an outstanding radiation tolerance that is
observed by using proprietary technology modifications and
design techniques. Two versions of sensors are available,
STAR250 and STAR250BK7. STAR250 has a quartz glass lid
and air in the cavity. The STAR250BK7 has a BK7G18 glass
lid with anti reflective coating. The cavity is filled with N2
increasing the temperature operating range.
Key Features
Parameter
Power Consumption
84 pin JLCC
< 350 mW
Applications
• Satellites
• Spacecraft monitoring
• Nuclear inspection
Electronic
8 MHz
Up to 30 full frames/s
10 bit
Sensitivity
3340 V.m2/W.s
Dynamic Range
74dB (5000:1)
76 e-
kTC Noise
4750 e-/s at RT
Supply Voltage
Operating Temperature
Packaging
Mono
25 µm
ADC Resolution
Dark Current
Color Filter Array
> 80 MeV cm3 mg-1
512 x 512
Maximum Data Rate /
Master Clock
Frame Rate
SEL Threshold
1% of pixels has an increase in
dark current > 1 nA/cm2 after
3*10^10 protons at 11.7 MeV
1 Inch
Pixel Size
Shutter Type
Proton Radiation
Tolerance
Typical Value
Typical Value
Optical Format
Active Pixels
Parameter
5V
0°C - +65°C (STAR250)
-40°C - +85°C (STAR250BK7)
Gamma Total Dose
Radiation tolerance
Increase in average dark current
< 1 nA/cm2 after 3 MRad
Image operation with dark signal
< 1V/s after 10 Mrad
demonstrated (Co60)
Cypress Semiconductor Corporation
Document Number: 38-05713 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 12, 2006
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CYIS1SM0250-AA
Specifications
General Specifications
Table 1. General Specifications
Parameter
Specification
Pixel Architecture
3-transistor active pixel
4 diodes per pixel
Pixel Size
25 x 25 µm2
Resolution
512 by 512 pixels
Pixel Rate
8 Mps
Shutter Type
Electronic
Frame Rate
29 full frames/second
Extended dynamic range
Remarks
Radiation-tolerant pixel design
4 photodiodes for improved MTF
Integration time is variable in time, steps equal to the row
readout time
Double slope
Programmable gain
Programmable between x1, x2, x4, x8
Supply voltage VDD
5V
Operational temperature
range
0°C - +65°C
-40°C - +85°C
Package
Selectable through pins G0 and G1
STAR250 (Quartz glass lid, air in cavity)
STAR250BK7 (BK7G18 glass lid, N2 in cavity)
84 pins JLCC
Electro-optical Specifications
Overview
Table 2. Electro-optical Specifications
Parameter
Detector Technology
Pixel Structure
Photodiode
Specification (all typical)
Comment
CMOS Active Pixel Sensor
3-transistor active pixel
4 diodes per pixel
Radiation-tolerant pixel design
4 Photodiodes for improved MTF
High fill factor photodiode
Sensitive Area Format
Pixel Size
Spectral Range
Quantum Efficiency x Fill
Factor
512 by 512 pixels
25 x 25 µm2
200 - 1000 nm
Max. 35%
See curves
Above 20% between 450 and 750 nm
(Note: Metal FillFactor (MFF) is 63%)
Full Well Capacity
311K electrons
When output amplifier gain = 1
Linear Range within + 1%
128K electrons
When output amplifier gain = 1
1.68 V
When output amplifier gain = 1
Output Signal Swing
Conversion Gain
5.7 µV/e
Temporal Noise
76 e-
Dynamic Range
74 dB (5000:1)
Document Number: 38-05713 Rev. *B
-
When output amplifier gain = 1 near dark
Dominated by kTC
At the analog output
Page 2 of 24
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CYIS1SM0250-AA
Table 2. Electro-optical Specifications (continued)
Parameter
Specification (all typical)
Comment
FPN (Fixed Pattern Noise)
1 < 0.1% of full well
(typical)
Measured local, on central image area 50% of pixels, in
the dark
Local: 1 = 0.39% of response
Global: 1 = 1.3% of response
Measured in central image area 50% of pixels, at Qsat/2
PRNU (Photo Response
Non-uniformity)
4750 e-/s
Average Dark Current
Signal
At RT
DSNU (Dark Signal Non
Uniformity)
3805 e-/s RMS
At RT, scale linearly with integration time
MTF
Horizontal: 0.36
Vertical: 0.39
at 600 nm.
Optical Cross Talk
5% (TBC) to nearest neighbor if central
pixel is homogeneously illuminated
Anti-blooming Capacity
x 1000 to x 100 000
Output Amplifier Gain
Windowing
1, 2, 4 or 8
X and Y 9-bit programmable shift
registers
Electronic Shutter Range
1: 512
ADC
10 bit
ADC Linearity
± 3.5 counts
Missing Codes
none
ADC Setup Time
310 ns
ADC Delay Time
125 ns
Power Dissipation
< 350 mW
Document Number: 38-05713 Rev. *B
Controlled by 2 bits
Indicate upper left pixel of each window
Integration time is variable in time steps equal to the row
readout time
INL
To reach 99% of final value
Average at 8 MHz pixel rate
Page 3 of 24
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CYIS1SM0250-AA
Spectral Response Curve
Figure 1. Spectral Response Curve
0.2
QE 0.4
QE 0.3
QE 0.2
Spectral respnse [A/W]
0.15
0.1
QE 0.1
QE 0.05
0.05
QE 0.01
0
400
500
600
700
800
900
1000
1100
Wavelength [nm]
Figure 2. UV Region Spectral Response Curve
STAR250
UV-m easurem ent
1,00E+00
200
250
300
350
400
450
500
FF * Spectral Response [A/W]
QE 100%
1,00E-01
QE 10%
1,00E-02
QE 1%
1,00E-03
1,00E-04
WaveLength [nm ]
Document Number: 38-05713 Rev. *B
Page 4 of 24
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CYIS1SM0250-AA
Pixel Profile
Figure 3. Pixel Profile
horizontal pixel profile
Vertica pixel profile
Relative profile
Imaginary pixel boundaries
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
Scan distance [mm]
The pixel profile is measured using the 'knife edge' method:
the image of a target containing a black to white transition is
scanned over a certain pixel with subpixel resolution steps.
Document Number: 38-05713 Rev. *B
The image sensors settings and the illumination conditions are
adjusted such that the transition covers 50% of the output
range. The scan is performed both horizontal and vertical.
Page 5 of 24
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CYIS1SM0250-AA
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings STAR250
Characteristics
Limits
Units
Remarks
Min
Max
Any Supply Voltage
-0.5
+7
V
Voltage on any Input Terminal
-0.5
Vdd + 0.5
V
0
+60
°C
Storage Temperature
-10
+60
°C
Sensor soldering Temperature
NA
125
°C
Hand soldering only. The
sensor’s temperature
during soldering should not
exceed this limit.
Units
Remarks
Operating Temperature
Table 4. Absolute Maximum Ratings STAR250BK7
Characteristics
Limits
Min
Max
Any Supply Voltage
-0.5
+7
V
Voltage on any Input Terminal
-0.5
Vdd + 0.5
V
Operating Temperature
-40
+85
°C
Storage Temperature
-40
+85
°C
-40
+120
°C
Maximum 1 hour
NA
125
°C
Hand soldering only. The
sensor’s temperature
during soldering should not
exceed this limit.
Sensor soldering Temperature
Radiation Tolerance
Table 5. Radiation Tolerance
Parameter
Gamma Total Dose Radiation
tolerance
Proton Radiation Tolerance
SEL Threshold
Criterion
Increase in average dark current
< 1 nA/cm2 after 3 MRad
See graph
Image operation with dark signal
< 1V/s
10 Mrad demonstrated (Co60)
Single (test) pixel operation with
dark signal < 1V/s
24 Mrad demonstrated (Co60)
1% of pixels has an increase in
dark current > 1 nA/cm2 after
3*10^10 protons at 11.7 MeV
see graph
> 80 MeV cm3 mg-1
Figure 4. shows the increase in dark current under total dose
irradiation. This curve is measured when the radiation is at
Document Number: 38-05713 Rev. *B
Qualification level
To be confirmed
high dose rate. Annealing results in a significant dark current
decrease.
Page 6 of 24
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CYIS1SM0250-AA
1,4
Dark current increase [nA/cm
2
]
Figure 4. Dark Current Increase
1,2
1
0,8
0,6
0,4
0,2
0
0
2
4
6
8
10
12
Total Ionizing Dose [Mrad(Si)]
Figure 5. shows the percentage of pixels with a dark current
increase under 11.7 Mev radiation with protons.
Absolute Ratings are those values beyond that damage to the
device may occur.
Figure 5. Percentage of Pixels with Dark Current Increase
Notes
1. All parameters are characterized for DC conditions after establishing thermal equilibrium.
2. Unused inputs must always be tied to an appropriate logic level, e.g. either VDD or GND.
3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. Take, normal precautions to avoid applying any
voltages higher than the maximum rated voltages to this high-impedance circuit.
Document Number: 38-05713 Rev. *B
Page 7 of 24
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CYIS1SM0250-AA
DC Operating Conditions
Table 6. DC operating conditions
Symbol
Parameter
Min
Typ
Max
Units
VDD_ANA
Analogue supply voltage to imager part
5
V
VDD_DIG
Digital supply voltage to imager part
5
V
VDD_ADC_ANA
Analogue supply voltage to ADC
5
V
VDD_ADC_DIG
Digital supply voltage to ADC
5
V
Supply voltage of ADC output stage
3.3 to 5
V
VDD_ADC_DIG_3.3/5
VIH
Logical '1' input voltage
2.3
Vdd
V
VIL
Logical '0' input voltage
0
1
V
VOH
Logical '1' output voltage
4.25
VOL
Logical '0' output voltage
0.1
Pixel array power supply (default 5V, the device is
then in "soft reset". In order to avoid the image lag
associated with soft reset, reduce this voltage to
3…3.5V "hard reset")
5
V
Reset power supply
5
V
VDD_PIX
VDD_RESL
Document Number: 38-05713 Rev. *B
4.5
V
1
V
Page 8 of 24
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CYIS1SM0250-AA
Sensor Architecture
Figure 6. STAR250 Schematic
Clk_YR
SyncYR
Sync_YL
9
Clk_YL
A8...A0
Col
Sel
Rst
D9...D0
10-bit ADC
9
512
Pixel Array
512 by 512 Pixels
Y Address
Decoder / Shift Register
9
512
Y Address
Decoder / Shift Register
Ld_Y
Y-Start Registeer-Decoder
10
Clk_ADC
Ain
512
S
R
Column Amplifiers
1024
512
Rst
1024
Sig
9
Progr. Gain
Amplifier
Aout
X-Start Register
X Address
Decoder / Shift Register
The base line of the STAR250 sensor design consists of an
imager with a 512 by 512 array of active pixels at 25 µm pitch.
The detector contains on-chip correction for Fixed Pattern
Noise (FPN) in the column amplifiers, a programmable gain
output amplifier and a 10-bit Analog-to-Digital Converter
(ADC). Through additional preset registers the start position of
a window can be programmed to enable fast read out of only
part of the detector array.
The image sensor consists of several building blocks as
outlined in Figure 6. The central element is a 512 by 512 pixel
array with square pixels at 25 µm pitch. Unlike classical
designs, the pixels of this sensor contain four photodiodes.
This configuration enhances the MTF and reduces the PRNU.
Figure 7. shows an electrical diagram of the pixel structure.
The four photodiodes are connected in parallel to the reset
transistor (T1). Transistor T2 converts the charge, collected on
the photo diode node, to a voltage signal that is connected to
G0
G1
the column bus by T3. The Reset and the Read entrance of
the pixel are connected to one of the Y shift registers.
Figure 7. STAR250 Pixel Structure
T1
Read
Reset
T2
Column Bus
Pixel Structure
Document Number: 38-05713 Rev. *B
Blackref
Cal
Sync_X
CLKX
Ld_X
T3
Page 9 of 24
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CYIS1SM0250-AA
Shift Registers
The shift registers are located next to the pixel array and
contain as many outputs as the number of rows in the pixel
array. They are designed as "1-hot" registers, (YL and YR shift
register) each allowing selection of one row of pixels at a time.
A clock pulse moves the pointer one position down the register
resulting in the selection of every individual row for either reset
or for readout. The spatial offset between the two selected
rows determines the integration time. A synchronization pulse
to the shift registers loads the value from a preset register into
the shift register forcing the pointer to a predetermined
position. Windowing in the vertical (Y) direction is achieved by
presetting the registers to a row that is not the first row and by
clocking out only the required number of rows.
Column Amplifiers
All outputs from the pixels in a column are connected in parallel
to a column amplifier. This amplifier samples the output
voltage and the reset level of the pixel whose row is selected
at that moment and presents these voltage levels to the output
amplifier. As a result, the pixels are always reset immediately
after readout as part of the sample procedure and the
maximum integration time of a pixel is the time between two
read cycles.
Electronic Shutter
The first process resets lines in a progressive scan. At line
reset, all the pixels in a line are drained from any photo
charges collected since their last reset or readout. After reset,
a new exposure cycle starts for that particular line.
The second process is the actual readout, which also happens
in an equally fast linewise progressive scan.
During readout, the photo charges collected since the
previous reset are converted into an output voltage. This is
then passed on pixel by pixel to the imager's pixel serial output
and ADC. Readout is destructive, meaning the accumulation
of charges from successive exposure phases is not possible
in the present architecture.
The STAR250 has two Y- shift registers; YL and YR. One is
used for readout of a line (YL) and the other is used to reset a
line (YR). The integration time is equal to the time between the
last reset and the readout of that line, see Figure 8. The
integration time is thus equal to:
Integration time = (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with:
• Nr. Lines: Number of Lines between readout and reset (Y).
• Nr. Pixels: Number of pixels read out each line (X).
• RBT: Row Blanking Time = 3.2 µs (typical).
• Pixel period: 1/8 MHz = 125 ns (typical).
In a linescan integrating imager with electronic shutter, there
are two continuous processes of image gathering.
Figure 8. Electronic Shutter
x
Reset line
Read line
y
x
y
Reset sequence
Line number
Time axis
Frame time
Document Number: 38-05713 Rev. *B
Integration time
Page 10 of 24
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CYIS1SM0250-AA
Programmable Gain Amplifier
Image Readout
The signal from the column amplifiers is fed to an output
amplifier with four presettable gains (adjustable with pins G0
and G1). The offset correction of this amplifier is done through
a black reference procedure. The signal from the output
amplifier is externally available on the analog output
terminator of the device.
In an infinite uninterrupted loop, follow these steps line-by-line:
1. Synchronize the read (YL) and/or reset (YR) registers, in
this cases:
• SYNC_YL - to reinitiate the readout sequence to row
position Y1
• SYNC_YR - to reinitiate the reset pointer to row position
Y1
For all other lines do not pulse one of these SYNC_Y signals.
2. Operate the double sampling column amplifiers with two
RESETs. Apply one to reset the line that is currently
selected to produce the reset reference level for the double
sampling column amplifiers. Apply the other reset to
another line depending on the required integration time
reduction.
3. Perform a Line Readout:
Analog-to-Digital Converter
The on-chip 10-bit ADC is electrically separated from the other
circuits of the device. The ADC conversion range is set by the
voltages on VLOW_ADC (pin 47) and VHIGH_ADC (pin 70).
Make voltages on these pins equal to about 2V on
VLOW_ADC and 4V on VHIGH_ADC. The voltages are set by
connecting VLOW with 1.2kΩ to GND and VHIGH_ADC with
560Ω to VDD. This way, a resistor ladder is created as shown
in Figure 9.
Figure 9. ADC Resistor Ladder
RADC_VHIGH
Pin 70: VHIGH_ADC
External
Internal
RADC
RADC_VLOW
The internal ADC resistance varies according to temperature.
The resistance value increases approximately 4.4 Ω/°C with
increasing temperature. If the ADC range is set externally with
resistors, the conversion range may vary with temperature.
This effect is cancelled out by not making use of resistors but
directly applying voltages on VLOW_ADC and VHIGH_ADC.
Timing and Readout of the Image Sensor
Image Readout Procedure
A preamble or initialization phase is irrelevant. The sensor is
read out continuously. The first frame is generally saturated
and useless because there is no preceding reset of each pixel.
Document Number: 38-05713 Rev. *B
Perform a pixel readout operation, operating the track/hold
and the ADC.
Shift the X read address shift register one position further.
Shift the Y read and reset address shift registers one position
further. If either of Y read or reset address shift register comes
to the end of the pixel array (or the ROI), wrap it around to the
start position by pulsing SYNC_YL.
Readout Timing
External
Pin 47: VLOW_ADC
Reset the X read address shift register to the value in its
shadow register (X1).
The actual line readout process starts with addressing the line
to read. This is done either by initializing the YL pointer with a
new value, or by shifting it one position beyond its previous
value. (Addressing the line has reset, YR is done in an
analogous fashion). During the "blanking time", after the new
line is addressed on the sensor, the built-in column-parallel
double sampling amplifiers are operated. This renders
offset-corrected values of the line under readout.
After the blanking time the pixels of the row addressed by YL
are read by multiplexing all the pixels one by one to the serial
output chain. The pixel is selected by the X pointer, and that
pointer is either initialized with a new value or an increment of
the previous position.
The time between row resets and their corresponding row
readouts is the effective exposure time (or integration time).
This time is proportional to the number of lines (DelayLines)
between the line currently under reset and the line currently
under readout: DelayLines = (YR - YL+1). This time is also
equal to the delay between the SYNC_YR pulse and the
subsequent SYNC_YR.
The effective integration time tint is calculated as delaylines *
line time. The line time itself is a function of four terms: the time
to output the desired number of pixels in the line (Wframe), and
the overhead ("blanking") time that is needed to select an new
line and perform the double sampling and reset operations.
Page 11 of 24
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CYIS1SM0250-AA
Figure 10. Basic Readout Timing
Once per frame
SYNC_YL
T13
SYNC_YR
T10
May occur at any moment,
persumably once per
sequence of frames
CAL
T2
T9
T16
Row Start
Address
T15
T17
LD_Y
CLK_YL
T14
T12
CLK_YR
T1
S
T3
T7
RESET
T4
T4
T6
R
T11
T5
L/R
T8
Row
Y-1
Row Blanking Time
SYNC_YR is not identical to as SYNC_YL. SYNC_YR is used
in case of electronic shutter operation. The CLK_YR is driven
identically as CLK_YL, but the SYNC_YR pulse leads the
SYNC_YL pulse by a certain number of rows. This lead time
is the effective integration (electronic shutter ~) time. Relative
to the row timing, both SYNC pulses are given at the same
time position, once for each frame, but during different rows.
SYNC_YL is pulsed when the first row is read out and
SYNC_YR is pulsed for the electronic shutter to start for this
Time Available for Read Out of Row Y
first row. CAL is pulsed on the first row too, 2 µs later than
SYNC_YL.
The minimal idle time is 1.4 µs (before starting reading pixels).
However, do not read out pixels during the complete row initialization process (in between the rising edge on S and the falling
edge on L/R). In this case, the total idle time is minimal. This
timing assumes that the Y start register was loaded in
advance, which can occur at any time but before the pulse on
SYNC_YL or SYNC_YR.
Table 7. Readout Timing Specifications
Symbol
Min
Typ
T1
1.8 µs
Delay between selection of new row by falling edge on CLK_YL and falling edge on S.
Minimal value. Normally, CLK_YR is low already at the end of the previous sequence.
T2
1.8 µs
Delay between selection of new a row by SYNC_YL and falling edge on S.
T3
0.4 µs
Duration of S and R pulse.
T4
0.1 µs
Duration of RESET pulse.
T5
T4 + 40 ns
0.3 µs
Document Number: 38-05713 Rev. *B
Description
L/R pulse must overlap second RESET pulse at both sides.
Page 12 of 24
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CYIS1SM0250-AA
Table 7. Readout Timing Specifications (continued)
Symbol
Min
Typ
Description
T6
0.8 µs
T7
20 ns
0.1 µs
T8
0
1 µs
Delay between falling edge on L/R and falling edge on CLK_Y.
T9
100 ns
1 µs
Duration of cal pulse. The CAL pulse is given once each frame.
T10
0
2 µs
Delay between falling edge of SYNC_YL and rising edge of CAL pulse.
T11
40 ns
0.1 µs
T12
0.1 µs
1 µs
Delay between falling edge on RESET and falling edge on R.
Delay between falling edge on S and rising edge on RESET.
Delay between falling edge on R and rising edge on L/R.
Delay between rising edge of CLK_Y and falling edge on S.
T13
0.5 µs
Pulse width SYNC_YL / YR
T14
0.5 µs
Pulse width CLK_YL / YR
T15
10 ns
Address set-up time
T16
20 ns
Load X / Y start register value
T17
10 ns
Address stable after load
T18
10 ns
T19
20 ns
T20
10 ns
SYNC_X pulse width. SYNC_X while CLK_X is high.
T21
40 ns
Analogue output is stable during CLK_X low.
T22
40 ns
CLK_X pulse width: During this clock phase the analogue output ramps to the next
pixel level.
T23
125 ns
ADC digital output stable after falling edge of CLK_ADC
Loading the X- and Y- Start Positions
The following timing constraints apply:
The start positions (start addresses) for "ROI" (Region Of
Interest) are preloaded in the X or Y start register. They
become effective by the application of the SYNC_X,
SYNC_YL and/or SYNC_YR. The start X- or Y address must
be applied to their common address bus, and the
corresponding LD_X or LD_Y pin must be pulsed.
Load the X or Y start addresses in advance, before the X or Y
shift registers are preset by a SYNC pulse. However, if
necessary, they can be load just before the SYNC_X or
SYNC_Y pulse as shown in the Figure 11.
On each falling edge of CLK_X, a new pixel of the same row
(line) is accessed. The output stage is in hold when CLK_X is
low and starts generating a new output after a rising edge on
CLK_X.
Document Number: 38-05713 Rev. *B
E.g. the X start register can be loaded during the row idle time.
The Y start register can be loaded during readout of the last
row of the previous frame.
If the X or Y start address does not change for later frames, it
does not need to be reloaded in the register.
Page 13 of 24
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CYIS1SM0250-AA
Figure 11. Timing for Loading the X- and Y- Register
May Occur at any
Moment in Time
Row Blanking Time
Time Available for Read Out of Row Y
Column Start
Address
T15
LD_X
T17
T16
T19
SYNC_X
CLK_X
T18
Analog
Output
T20
T21
T22
Pixel 1
Pixel 2
Pixel 3
CLK ADC
T23
ADC Out
Other Signals
Tie SELECT signal to VDD for normal operation. This signal
was added for diagnostic reasons and inhibits the pixel array
operation when held low.
The CAL signal sets the output amplifier DC offset level. When
this signal is active (high) the pixel array is internally
disconnected from the output amplifier, its gain is set to unity
and its input signal is connected to the BLACK_REF input.
Perform this action at least once for each frame.
EOS_X, EOS_YL and EOS_YR produce a pulse when the
respective shift register comes at its end. These outputs are
Document Number: 38-05713 Rev. *B
Pixel 1
Pixel 2
used mainly during testing to verify proper operation of the shift
registers.
TEST DIODE and TESTPIXEL ARRAY are connections to
optical test structures that are used for electro optical
evaluation. TESTDIODE is a plain photodiode with an area of
14x5 pixels. TESTPIXEL_ARRAY is an array (14x5) of pixels
where the photodiodes are connected in parallel. These
structures measure the photocurrent of the diodes directly.
TESTPIXEL_RESET and TESTPIXEL-OUT are connections
to a single pixel that are used for testing.
Page 14 of 24
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CYIS1SM0250-AA
Pinlist
Table 8. Power Supply Connections
Pin
Pin Name
Pin Description
10
VDD_ANA
Analog power supply 5V.
11
VDD_DIG
Digital power supply 5V.
31
VDD_AMP
Power supply of output amplifier 5V.
33
VDD_DIG
Digital power supply 5V.
34
VDD_ANA
Analogue power supply 5V.
49
VDD_RESR
Reset power supply 5V.
50
VDD_DIG
Digital power supply 5V.
53
VDD_ADC_ANA
ADC analogue power supply 5V.
66
VDD_ADC_ANA
ADC analogue power supply 5V.
67
VDD_ADC_DIG
ADC digital power supply 5V.
69
VDD_ADC_DIG_3.3/5
52
76
VDD_PIX
Pixel array power supply [default: 5V, the device is then in "soft reset". In order to avoid
the image lag associated with soft reset, reduce this voltage to 3…3.5 V "hard reset"].
78
VDD_DIG
Digital power supply 5V.
79
VDD_RESL
Reset power supply 5V.
ADC 3.3V power supply for digital output of ADC.
For interface with 5V external system: connect to VDD_ADC_DIG.
For interface with 3.3 V external system: connect to 3.3V power supply.
Table 9. Ground Connections
Pin
Pin Name
Pin Description
9
GND_ANA
Analog ground.
12
GND_DIG
Digital ground.
30
GND_AMP
Ground of output amplifier.
32
GND_DIG
Digital ground.
35
GND_ANA
Analog ground.
51
GND_DIG
Digital ground.
54
GND_ADC_ANA
ADC analog ground.
65
GND_ADC_ANA
ADC analog ground.
68
GND_ADC_DIG
ADC digital ground.
77
GND_DIG
Digital ground.
Table 10. Digital Input Signals
Pin
Pin Name
1
S
Control signal for column amplifier.
Apply pulse pattern - see sensor timing diagram.
2
R
Control signal for column amplifier.
Apply pulse pattern - see sensor timing diagram.
Document Number: 38-05713 Rev. *B
Pin Description
Page 15 of 24
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CYIS1SM0250-AA
Table 10. Digital Input Signals (continued)
Pin
Pin Name
3
RESET
Resets row indicated by left/right shift register.
high active (1= reset row).
Apply pulse pattern - see sensor timing diagram.
4
SELECT
Selects row indicated by left/right shift register.
high active (1=select row).
Apply 5 V DC for normal operation.
5
L/R
Use left or right shift register for SELECT and RESET.
1 = left / 0 = right - see sensor timing diagram.
6
A0
Start address for X- and Y- pointers (LSB).
7
A1
Start address for X- and Y- pointers.
8
A2
Start address for X- and Y- pointers.
13
A3
Start address for X- and Y- pointers.
14
A4
Start address for X- and Y- pointers.
15
A5
Start address for X- and Y- pointers.
16
A6
Start address for X- and Y- pointers.
17
A7
Start address for X- and Y- pointers.
18
A8
Start address for X- and Y- pointers (MSB).
19
LD_Y
Latch address (A0…A8) to Y start register (0 = track, 1 = hold).
20
LD_X
Latch address (A0…A8) to X start register(0 = track, 1 = hold).
21
CLK_YL
22
SYNC_YL
24
CLK_X
25
SYNC_X
Sets X shift register to location preloaded in X start register.
Low active (0=sync).
Apply SYNC_X when CLK_X is high.
After SYNC_X, apply falling edge on CLK_X, and rising edge on CLK_X.
27
CLK_YR
Clock YR shift register (shifts on falling edge).
28
SYNC_YR
36
CAL
37
G0
Select output amplifier gain value: G0 = LSB; G1 = MSB.
00 = unity gain; 01 = x2; 10= x4; 11=x8.
38
G1
idem.
71
CLK_ADC
ADC clock.
ADC converts on falling edge.
75
BITINVERT
1 = invert output bits.
0 = no inversion of output bits.
Document Number: 38-05713 Rev. *B
Pin Description
Clock YL shift register (shifts on falling edge).
Sets YL shift register to location preloaded in Y start register.
Low active (0=sync).
Apply SYNC_YL when CLK_YL is high.
Clock X shift register (output valid & s when CLK_X is low).
Sets YR shift register to location preloaded in Y start register.
Low active (0=sync).
Apply SYNC_YR when CLK_YR is high.
Initialize output amplifier.
Output amplifier will output BLACKREF in unity gain mode when CAL is high (1).
Apply pulse pattern (one pulse per frame) - see sensor timing diagram.
Page 16 of 24
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CYIS1SM0250-AA
Table 10. Digital Input Signals (continued)
Pin
Pin Name
80
TRI_ADC
Pin Description
Tri-state control of digital ADC outputs
1 = tri-state; 0 = output
Table 11. Digital Output Signals
Pin
Pin Name
Pin Description
23
EOS_YL
End-of-scan of YL shift register.
Low first clock period after last row (low active).
26
EOS_X
End-of-scan of X shift register.
Low first clock period after last active column (low active).
29
EOS_YR
55
D0
ADC output bit (LSB).
56
D1
ADC output bit.
57
D2
ADC output bit.
58
D3
ADC output bit.
59
D4
ADC output bit.
60
D5
ADC output bit.
61
D6
ADC output bit.
62
D7
ADC output bit.
63
D8
ADC output bit.
64
D9
ADC output bit (MSB).
End-of-scan of YR shift register.
Low first clock period after last row (low active).
Table 12. Analog Input Signals
Pin
Pin Name
39
NBIASARR
40
PBIAS
Connect with 39 k to ground and decouple to Vdd with a 100 nF capacitor for 8 MHz
pixel rate. (Lower resistor values yield higher maximal pixel rates at the cost of extra
power dissipation).
41
NBIAS_AMP
Output amplifier speed/power control.
Connect with 51kΩ to VDD and decouple with 100 nF to GND for 8 MHz output rate
(Lower resistor values yield higher maximal pixel rates at the cost of extra power
dissipation).
42
BLACKREF
Control voltage for output signal offset level.
Buffered on-chip, the reference level can be generated by a 100kΩ resistive divider.
Connect to +/- 2 V DC for use with on-chip ADC.
44
IN_ADC
45
NBIASANA2
Connect with 100 k to VDD and decouple to GND.
46
NBIASANA
Connect with 100 k to VDD and decouple to GND.
47
70
VLOW_ADC
VHIGH_ADC
Document Number: 38-05713 Rev. *B
Pin Description
Connect with 470 k to Vdd and decouple to ground with a 100 nF capacitor.
Input, connect to sensor's output.
Input range is between 2 & 4 V (VLOW_ADC & VHIGH_ADC).
Low reference and high reference voltages of ADC should be about 2 and 4V.
The required voltage settings on VLOW_ADC and VHIGH_ADC can be approximated
by tying VLOW_ADC with 1.2kΩ to GND and VHIGH_ADC with 560Ω to VDD.
Page 17 of 24
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CYIS1SM0250-AA
Table 12. Analog Input Signals (continued)
Pin
Pin Name
Pin Description
48
G_AB
72
PBIASDIG2
Connect with 100K to GND and decouple to VDD.
73
PBIASENCLOAD
Connect with 100K to GND and decouple to VDD.
74
PBIASDIG1
Connect with 47K to GND and decouple to VDD.
Anti-blooming drain control voltage:
Default: connect to ground. The anti-blooming is operational but not maximal.
Apply 1V DC for improved anti-blooming.
Table 13. Analog Output Signals
Pin
Pin Name
43
OUT
Pin Description
Analogue output signal are connected to the analogue input of the ADC.
Table 14. Test Structures
Pin
Pin Name
81
TESTDIODE
82
TESTPIX
ARRAY
83
TESTPIXEL_RESET
84
TESTPIXEL_OUT
Document Number: 38-05713 Rev. *B
Pin Description
Plain photo diode, size: 14 x 25 pixels.
Must be left open for normal operation.
Array of test pixels, connected in parallel (14 x 25 pixels).
Must be left open for normal operation.
Reset input of single test pixel.
Must be tied to GND for normal operation.
Output of single test pixel.
Must be left open for normal operation.
Page 18 of 24
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CYIS1SM0250-AA
Package
Package with Glass
Note: All dimension in Figure 12. are measured in inches.
Figure 12. STAR250 Package Dimensions
Table 15. Package Specifications:
Type
JLCC-84
Material
Black Alumina BA-914
Thermal expansion coefficient
7.6 x 10-6 /K
Document Number: 38-05713 Rev. *B
Page 19 of 24
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CYIS1SM0250-AA
Die Alignment
Figure 13. Die Alignment
Parallelism in
X and Y within
+ 50 Pm
68 P
Pin 1
Center of Cavity
and of FPA
Center of
Silicium
A
Bonding Cavity:
0.508+0.051
Offset Between Center of
Silicium and Center of
Cavity:
X: 0
Y: 68 Pm
Die:
0.508+0.01
A
Glass Window:
1.0+/-0.05
Window Adhesive:
0.08+0.02
Die Cavity:
0.508+0.051
A-
Die Adhesive:
0.08+0.02
Section A
Drawing Not to Scale
The die is aligned manually in the package to a tolerance of ±50 µm and the alignment is verified after hardening the die adhesive.
All dimensions in figure 13 are in mm.
Document Number: 38-05713 Rev. *B
Page 20 of 24
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CYIS1SM0250-AA
Window Specifications
STAR250
Table 16. STAR250 Glass Cover Specifications:
Material
Fused Silica
Dimensions
25 x 25 mm +- 0.2 mm
Thickness
1 mm +- 0.05 mm
Anti reflective coating
No
Cavity fill
Air
STAR250BK7
Table 17. STAR250BK7 Glass Cover Specifications
Material
BK7G18
Dimensions
25 x 25 mm +- 0.2 mm
Thickness
1 mm +- 0.05 mm
Anti reflective coating
Yes
Cavity fill
N2
Document Number: 38-05713 Rev. *B
Page 21 of 24
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CYIS1SM0250-AA
Soldering and Handling
Use a soldering iron with temperature control at the tip. The
soldering iron tip temperature should not exceed 350°C.
Soldering and Handling Conditions
The soldering period for each pin should be less than five
seconds.
Take special care when soldering image sensors onto a circuit
board. Prolonged heating at elevated temperatures may result
in deterioration of the performance of the sensor. The following
recommendations are made to ensure that sensor
performance is not compromised during end users' assembly
processes.
Board Assembly
The STAR250 is very sensitive to ESD. Device placement onto
boards should be done in accordance with strict ESD controls
for Class 0, JESD22 Human Body Model, and Class A,
JESD22 Machine Model devices. Assembly operators need to
always wear all designated and approved grounding
equipment; grounded wrist straps at ESD protected
workstations are recommended including the use of ionized
blowers. All tools should be ESD protected.
Manual Soldering
When a soldering iron is used the following conditions should
be observed:
Reflow Soldering
Reflow soldering is not allowed.
Precautions and Cleaning
Avoid spilling solder flux on the cover glass; bare glass and
particularly glass with antireflection filters may be harmed by
the flux. Avoid mechanical or particulate damage to the cover
glass.
Use isopropyl alcohol (IPA) as a solvent for cleaning the image
sensor glass lid. When using other solvents, it should be
confirm whether the solvent will dissolve the package and/or
the glass lid.
RoHS (lead free) Compliance
This paragraph reports the use of Hazardous chemical
substances as required by the RoHS Directive (excluding
packing material).
Table 18. Chemical Substances in STAR250 Sensor
Any intentional content
If there is any intentional content, in which portion
is it contained?
Lead
NO
-
Cadmium
NO
-
Mercury
NO
-
Hexavalent chromium
NO
-
PBB (Polybrominated biphenyls)
NO
-
PBDE (Polybrominated diphenyl ethers)
NO
-
Chemical Substance
Information on Lead Free Soldering
The product cannot withstand a lead free soldering process.
Reflow or wave soldering is not allowed. Hand soldering only.
Solder 1 pin on each side of the sensor and let it cool down for
at least 1 minute before continuing
Note: "Intentional content" is defined as any material
demanding special attention is contained into the inquired
product by these cases:
1. A case that the above material is added as a chemical
composition into the inquired product intentionally in order
Document Number: 38-05713 Rev. *B
to produce and maintain the required performance and
function of the intended product
2. A case that the above material, which is used intentionally
in the manufacturing process, is contained in or adhered to
the inquired product.
The following case is not treated as "intentional content":
A case that the above material is contained as an impurity into
raw materials or parts of the intended product. The impurity is
defined as a substance that cannot be removed industrially, or
it is produced at a process like chemical composing or reaction
and it cannot be removed technically.
Page 22 of 24
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CYIS1SM0250-AA
Ordering Information
Part Numbers
FillFactory part number
Cypress Part number
Package
Glass Lid
Mono/Color
STAR250
CYIS1SM0250AA-HQC
84-pin JLCC
Quartz fused silica
Mono
STAR250BK7
CYIS1SM0250AA-HHC
84-pin JLCC
BK7G18
Mono
CYIS1SM0250-EVAL
84-pin JLCC
Quartz fused silica
Mono
Evaluation system
Evaluation kit
For evaluating purposes an STAR250 evaluation kit is
available. The STAR250 evaluation kit consists of a
multifunctional digital board (memory, sequencer and IEEE
1394 Fire Wire interface) and an analog image sensor board.
Visual Basic software (under Win 2000 or XP) allows the
grabbing and display of images from the sensor. All acquired
images can be stored in different file formats (8 or 16-bit). All
setting can be adjusted on the fly to evaluate the sensors
specs. Default register values can be loaded to start the
software in a desired state. Please contact us for more
information.
All products and company names mentioned in this document
may be the trademarks of their respective holders
Document Number: 38-05713 Rev. *B
Page 23 of 24
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYIS1SM0250-AA
Document History Page
Document Title: CYIS1SM0250-AA STAR250 250K Pixel Radiation Hard CMOS Image Sensor
Document Number: 38-05713
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
**
310213
SEE ECN
SIL
*A
603159
SEE ECN
QGS
Converted to Framemaker Format
*B
649360
SEE ECN
FPW
Title update + package spec label
Document Number: 38-05713 Rev. *B
Origination
Page 24 of 24
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