STAR1000
1M Pixel Radiation Hard CMOS Image
Sensor
Features
The STAR1000 sensor has the following characteristics:
■
Integrating 3-transistor Active Pixel Sensor.
■
1024 by 1024 pixels on 15 mm pitch.
■
Radiation tolerant design.
■
On-chip double sampling circuit to cancel Fixed Pattern Noise.
■
Electronic shutter.
■
Read out rate: up to 11 full frames per second.
■
Region of Interest (ROI) windowing.
■
On-chip 10-bit ADC.
■
Programmable gain amplifier.
■
Ceramic JLCC-84 package.
■
Available with BK7G18 glass and with N2 filled cavity
Sensor Description
The STAR1000 is a CMOS image sensor with 1024 by 1024
pixels on a 15 mm pitch. It features on-chip Fixed Pattern Noise
(FPN) correction, a programmable gain amplifier, and a 10-bit
Analog-to-Digital Converter (ADC).
All circuits are designed using the radiation tolerant design rules
for CMOS image sensors, to allow a high tolerance against total
dose effects.
Registers that are directly accessed by the external controller
contain the X- and Y- addresses of the pixels to be read. This
architecture provides flexible operation and allows different
operation modes such as (multiple) windowing, subsampling,
etc.
Three versions of sensors are available: STAR1000,
STAR1000BK7, and STAR1000SP. The STAR1000 has a quartz
glass lid, and the cavity between the die and the glass lid is filled
with air. The STAR1000BK7 has a BK7G18 glass lid, and the
cavity is filled with N2 which increases the temperature operating
range. The STAR1000SP is similar to the STAR1000BK7, it has
a BK7G18 glass lid, and a N2 filled cavity, but is also screened
and tested to space qualified device standards.
Cypress Semiconductor Corporation
Document Number: 38-05714 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 20, 2009
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STAR1000
Image Sensor Specifications
General Specifications
Table 1. General Specifications of the STAR1000 Sensor
Parameter
Specification
Comment
Detector technology
CMOS active pixel sensor
Pixel structure
3-transistor active pixel
Radiation-tolerant pixel design.
Photodiode
High fill factor photodiode
Using N-well technique.
Sensitive area format
1024 x 1024 pixels
Pixel size
15 x15 μm2
Pixel output rate
12 MHz
Windowing
X- and Y- addressing random programmable
Electronic shutter
Electronic rolling shutter.
Range - 1:1024
Integration time is variable in time steps equal to the
row readout time.
Total dose radiation
tolerance
> 250 Krad (Si)
Pixel test structures with a similar design have
shown total dose tolerance up to several Mrad.
Note: Dark current and DSNU are dependent of
radiation dose.
Speed can be altered for power consumption.
Proton radiation tolerance 2,4.1011 proton/cm2
At 60 MeV
SEU tolerance
> 127,8 MeV cm3 mg-1
Electro-optical Specifications
Table 2. Electro-optical Specifications of the STAR1000 Sensor
Value
Parameter
Spectral range
Comment
Typical Value
Unit
400-1000
nm
Quantum efficiency x fill
factor
20%
Average over the visual range. See spectral
response curve.
Full well capacity
135.000
e-
Saturation capacity to
meet non-linearity within
+ 5%
99.000
e-
Output signal swing
1.1
V
Conversion gain
11.4
μV/e-
kTC noise
47
e-
Dynamic range
69
dB
Fixed pattern noise
Local: 1σ < 0.30%
Global: 1σ <0.56%
of full well
Photo response
non-uniformity at Sat/
2 (RMS)
Local: 1σ < 0.67%
Global: σ <3.93%
of full well
Document Number: 38-05714 Rev. *C
Page 2 of 21
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STAR1000
Table 2. Electro-optical Specifications of the STAR1000 Sensor (continued)
Value
Parameter
Comment
Typical Value
Unit
Average dark current at
293K
223
ρA/cm2
Dark current signal
3135
e-/s
DSNU signal
Optical cross-talk
at 600 nm
1.055% of Vsat
DSNU rises 14 e-/s per Krad.
Vertical: 16%
Horizontal: 17.5%
Anti-blooming capacity
Output amplifier gain
x 1000
x1, x2.47, x4.59 and x8.64
Analogue input
bandwidth
Controlled by 2 bits.
9.5
MHz
0.1 to 4.9
V
10
bit
ADC Differential
Non-Linearity (DNL)
<= ±3.5
LSB
ADC Integral
Non-Linearity (INL)
<= ±5.8
LSB
5
V
<350
<100
mW
Analogue input signal
range
Dark current rises 425 e-/s per Krad.
Analog-to-Digital
converter
Supply voltage
Power dissipation
Document Number: 38-05714 Rev. *C
Radiation-tolerant version of the ADC on Ibis4 and
other image sensors.
Integral non-linearity of ADC is better than linearity
of image sensor.
Digital input signals are 3.3V compatible.
With internal ADC powered.
Without internal ADC powered.
Both values measured at nominal speed (12 MHz).
Page 3 of 21
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STAR1000
Spectral Response
Figure 1. Spectral Response Curve
0.16
QE 0.3
0.14
QE 0.2
Spectral response [A/W]
0.12
0.1
0.08
QE 0.1
0.06
QE 0.05
0.04
0.02
QE 0.01
0
400
500
600
700
800
900
1000
Wavelenght [nm]
Photo-Voltaic Response
Figure 2. Photo Voltaic Response Curve
Voltage swing at output [V]
1,2
1
0,8
0,6
0,4
0,2
0
0
20000
40000
60000
80000
100000 120000 140000 160000 180000
Number of electrons
Document Number: 38-05714 Rev. *C
Page 4 of 21
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STAR1000
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings STAR1000
Limits
Characteristics
Units
Remarks
Min
Max
Any supply voltage
-0.5
+7
V
Voltage on any input terminal
-0.5
Vdd + 0.5
V
0
+60
°C
Temperature range confirmed by
evaluation testing.
Storage temperature
-10
+60
°C
Not longer than 1 hour. Temperature range
confirmed by evaluation testing.
Sensor soldering temperature
NA
125
°C
Hand soldering only. The sensor’s
temperature may not rise above this limit.
Please read the Soldering and Handling
Conditions on page 18 for more
information.
Operating temperature
R
Table 4. Absolute Maximum Ratings STAR1000BK7 and STAR1000SP
Limits
Characteristics
Units
Remarks
Min
Max
Any supply voltage
-0.5
+7
V
Voltage on any input terminal
-0.5
Vdd + 0.5
V
Operating temperature
-40
+85
°C
Temperature range confirmed by
evaluation testing.
Storage temperature
-40
+85
°C
Temperature range confirmed by
evaluation testing.
-40
+120
NA
125
Sensor soldering
temperature
Maximum 1 hour.
°C
Hand soldering only. The sensor’s
temperature may not rise above this limit.
Please read the Soldering and Handling
Conditions on page 18 for more
information.
Table 5. DC Operating Conditions
Limits
Symbol
Parameter
Units
Min
Typ
Max
VDDA
Analog supply of the image core.
5
V
VDDD
Digital supply of the image core.
5
V
VDD_ADC_ANA
Analog supply of the ADC circuitry.
5
V
VDD_ADC_DIG
Digital supply of the ADC circuitry.
5
V
VDD_DIG_OUT
Power supply of ADC digital output stage.
5
V
VRES
Reset level for RESET signal.
5
V
VREF
Reset level for RESET_DS signal.
Document Number: 38-05714 Rev. *C
4
5
V
Page 5 of 21
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STAR1000
Table 5. DC Operating Conditions (continued)
Limits
Symbol
Parameter
Units
Min
Typ
Max
GNDA
Analog ground of the image core.
0
V
GNDD
Digital ground of the image core.
0
V
GND_ADC_ANA
Analog ground of the ADC circuitry.
0
V
GND_ADC_DIG
Digital ground of the ADC circuitry.
0
V
VIH
Logical '1' input voltage.
1.8
VDDD
V
VIL
Logical '0' input voltage.
0
1
V
VOH
Logical '1' output voltage.
4.25
VDDD
V
VOL
Logical '0' output voltage.
1
V
Document Number: 38-05714 Rev. *C
Page 6 of 21
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STAR1000
Architecture
Floor Plan
Figure 3. STAR1000 Floor Plan
1024
Reset
10
Pixel Array
1024 x 1024 pixels
Reset_DS
D0...D9
Rst
Vref
Ld_Y
10
Y Address
Decoder
and Logic
Col
10-bit ADC
Rst
1024
Clk_ADC
Rd
Latch
A0....A9
Rd
Ain
1024
10
S
R
Column Amplifiers
1024
Rst
1024
Sig
Progr. Gain
Amplifier
Multiplexer
1024
X Register
Clk_X
Buffer
Aout
1024
10
Ld_X
The image sensor contains five sections: the pixel array, the Xand Y- addressing logic, the column amplifiers, the output
amplifier and the ADC. Figure 3 shows an outline diagram of the
sensor, including an indication of the main control signals. The
following paragraphs explain the function and operation of the
different imager parts in detail.
Document Number: 38-05714 Rev. *C
Sel1
Sel0
Figure 4. Architecture of the 3T Pixel
T1
Read
Reset
T2
Column Bus
The photo diode is always in reverse bias. At the beginning of
the integration cycle, a pulse is applied to the reset line (gate of
T1) bringing the cathode of D1 to the reset voltage level. During
the integration period, photon-generated electrons accumulate
on the diode capacitance reducing the voltage on the gate of T2.
The real illumination dependent signal is the difference between
the reset level and the output level after integration. This
difference is created in the column amplifiers. T2 acts as a
source follower and T3 allows connection of the pixel signal
(reset level and output level) to the vertical output bus.
Ain1
Ain2
Ain3
The reset lines and the read lines of the pixels in a row are
connected together to the Y- decoder logic; the outputs of the
pixels in a column are connected together to a column amplifier.
Pixel Array
The pixel array contains 1024 by 1024 active pixels at 15 μm
pitch. Each pixel contains one photo diode and three transistors
(Figure 4).
G0f
G1
Blackref
Cal
Latch
X Address Decoder
T3
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STAR1000
Addressing Logic
The addressing logic allows direct addressing of rows and
columns. Instead of the one-hot shift registers that are often
used, address decoders are implemented. One can select a line
by presenting the required address to the address input of the
device and latching it to the Y- decoder logic. Presenting the
X- address to the device address input and latching it to the
X- address decoder can select a column.
A typical line read out sequence first selects a line by applying
the Y-address to the Y-decoder. Activation of the LD_Y input on
the Y-logic connects the pixel outputs of the selected line to the
column amplifiers. The individual column amplifier outputs are
connected to the output amplifier by applying the respective
X- addresses to the X- address decoder. Applying the appropriate Y- address to the Y- decoder and activating the “Reset”
input reset a line. The integration time of a row is the time
between the last reset of this row and the time when it is selected
for read out.
The Y- decoder logic has two different reset inputs: RESET and
RESET_DS. Activation of RESET resets the pixel to the Vdd
level; activation of RESET_DS resets the pixel to the voltage
level on the VREF input. This feature allows the application of
the so called dual slope integration. If dual slope integration is
not needed, VREF is tied to Vdd and RESET_DS must never be
activated.
Column Amplifiers
All outputs from the pixels in a column are connected in parallel
to a column amplifier. This amplifier samples the output voltage
and the reset level of the pixel whose row is selected at that
moment and presents these voltage levels to the output
amplifier. As a result, the pixels are always reset immediately
after read out as part of the sample procedure. Note that the
maximum integration time of a pixel is the time between two read
cycles.
Output Amplifier and Analog Multiplexer
The output amplifier combines subtraction of pixel signal level
from reset level with a programmable gain amplifier. Since the
Document Number: 38-05714 Rev. *C
amplifier is AC coupled, it also contains a provision to maintain
and restore the proper DC level.
An analog signal multiplexing feeds the pixel signal to the final
unity gain buffer, providing the required drive capability. Apart
from the pixel signal, three other external analog signals can be
fed to the output buffer. All these signals can be digitalised by the
on-chip ADC if the output of this buffer is externally connected to
the input of the ADC.
The purpose of the additional analog inputs (A_IN1, A_IN2, and
A_IN3) is to allow the possibility of processing other analog
signals through the image sensors signal path. These signals
can then be converted by the ADC and processed by the image
controller FPGA. The additional analog inputs are intended for
low frequency or DC signals and have a reduced bandwidth
compared with the image signal path.
ADC
The image sensor has a 10-bit ADC that is electrically separated
from the rest of the image sensor circuits and can be powered
down if an external ADC is used. The conversion takes place at
the falling edge of the clock and the output pins can be disabled
to allow operation of the device in a bus structure.
Timing and Control Signals
The pixels addressing is done by direct addressing of rows and
columns. This approach has the advantage of full flexibility when
accessing the pixel array: multiple windowing and subsampled
read out are possible by proper programming.
The following paragraphs clarify the timing for row and column
readout.
Row Selection and Reset Timing
Figure 5 on page 9 shows the timing of the line sequence control
signals. The timing constraints are presented in Table 6 on page
9
The address, presented at the address IO pins (A0…A9) is
latched in with the LD-Y pulse (active low). After latching, the
external controller already produces a new address.
Page 8 of 21
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STAR1000
Figure 5. Line Selection and Reset Sequence
A0......A9
Read Address
Reset Address
k
k
l
m
m
l
LD_Y
INTERNAL
Row Selected for Reset
Row Selected for Readout
a
b
S
c
d
f
g
d
RESET
e
b
R
h
i
CAL
(Once each
frame)
ROW
READOUT
Idle
Time Available for Readout of Row Y-1
Latching in a Y- address selects the addressed row and connects
the pixel outputs of that row to the column amplifiers. Through
the sequence of the S and R pulse and the reset pulse in
between the pixel output signal and reset level are sampled and
produced at the output of the column amplifier (to do the FPN
double sampling correction).
Time Available for X-readout of Row Y
At this time horizontal read out of the selected row is started and
another row is reset to effectuate reduced integration time
(electronic rolling shutter).
Table 6. Timing Constraints of Line Sequence
Symbol
Min
Typ
a
3.6 μs
Delay between selection of a new row and falling edge on S.
Minimal value: For maximum, speed a new row can already be selected
during X- read out of the previous row.
b
0.4 μs
Duration of S and R pulse.
c
0
d
200 ns
100 ns
Document Number: 38-05714 Rev. *C
Description
Delay between falling edge of S and rising edge of reset.
Minimum duration of reset pulse.
Page 9 of 21
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STAR1000
Table 6. Timing Constraints of Line Sequence
Symbol
Min
e
1.6 μs
f
0
Typ
Description
Delay between falling edge of reset and falling edge of R.
100 ns
g
g
Minimum delay between falling edge on LD_Y and rising edge of reset.
Minimum required extension of Y- address after falling edge of reset pulse.
h
100 ns
200 ns
Position of cal pulse after rising edge of S.
The cal pulse must only be given once per frame.
i
100 ns
1 μs
k
10 ns
Address set up time.
l
20 ns
Load register value.
m
10 ns
Address stable after load.
Duration of cal pulse.
Pixel Read Out Timing
Figure 6 on page 11 shows the timing of the pixel readout
sequence. The external digital controller presents a column
address that is latched by the rising edge of the LD_X pulse. After
decoding the X- address the column selection is clocked in the
X- register by CLK-X. The output amplifier uses the same pulse
to subtract the pixel output level from the pixel reset level and the
signal level. This causes a pipeline effect such that the analog
output of the first pixel is effectively present at the device output
terminal at the third rising edge of the X-CLK signal.
Document Number: 38-05714 Rev. *C
The ADC conversion starts at the falling edge of the CLK-ADC
signal and produces a valid digital output 20 ns after this edge.
The timing constraints are given in Table 7 on page 11
Important note: The values of the X shift-register tend to leak
away after a while. Therefore, it is very important to keep the
CLK_X signal asserted for as long as the sensor is powered up.
If the sensor sits idle and CLK_X is not asserted, the leakage of
the X shift-register causeq multiple columns to be selected at
once. This forces high current through the sensor and may cause
damage.
Page 10 of 21
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STAR1000
Figure 6. Column Selection and Read Out Sequence
Row Idle Time
A0......A9
X1
X2
X3
X5
X4
X6
X8
X7
LD_X
a
b
CLK_X
X1
X2
X3
Undefined Output Level
ANALOG
OUTPUT
X4
X5
X6
CLK_ADC
c
X1
D9......D0
X2
X3
X4
Table 7. Timing Constraints of Column Read Out
Symbol
Min
a
20 ns
Address setup time.
b
40 ns
Address valid time.
c
0
Document Number: 38-05714 Rev. *C
Typ
20 ns
Description
ADC output valid after falling edge of CLK_ADC.
Page 11 of 21
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STAR1000
Pin List
Figure 7 displays the pin connections of the STAR1000. The tables that follow group the connections by their functionality.
Figure 7. STAR1000 Pin Connections
Table 8. Pin List of the STAR1000 Sensor
Pin
Pin Name
Pin Type
1
A3
Input
2
A4
Input
3
A5
Input
4
A6
Input
5
A7
Input
6
A8
Input
7
A9
Input
8
LD_Y
Input
Document Number: 38-05714 Rev. *C
Pin Description
Digital Input. Latch address (A0…A9) to Y-register (0 = track, 1 = hold).
Page 12 of 21
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STAR1000
Table 8. Pin List of the STAR1000 Sensor (continued)
Pin
Pin Name
Pin Type
9
LD_X
Input
10
VDDA
Supply
Analog power supply of the imager (typical 5V).
11
GNDD
Ground
Digital ground of the imager.
12
GNDA
Ground
Analog ground of the imager.
13
CLK_X
Input
Digital input. Clock X-register (output valid & stable when CLK_X is high).
14
RESET_DS
Input
Digital input (active high). Resets row indicated by Y-address (see sensor
timing diagram).
RESET_DS is used for dual-slope integration (see FAQ).
GND is used for normal operation.
15
VDDD
Supply
16
RESET
Input
Digital input (active high). Resets row indicated by Y-address (see sensor
timing diagram).
17
S
Input
Digital input (active high). Control signal for column amplifier (see sensor
timing diagram).
18
R
Input
Digital input (active high). Control signal for column amplifier (see sensor
timing diagram).
19
NBIAS_DEC
Input
Analog input. Biasing of address decoder.
Connect with 100 kΩ to VDDA and decouple with 100nF to GND.
20
A_IN2
Input
21
A_IN3
Input
Additional analog inputs. For proper conversion with on-chip ADC, the
input signal must lie within the output signal range of the image sensor
(approximately +2V to +4V).
22
A_IN1
Input
23
A_SEL1
Input
24
A_SEL0
Input
25
NBIAS_OAMP
Input
Analog input. Bias of output amplifier (speed/power control).
Connect with 100 kΩ to VDDA and decouple with 100 nF to GND for 12.5
MHz output rate (lower resistor values yield higher maximal pixel rates at
the cost of extra power dissipation).
26
PBIAS
Input
Analog input. Biasing of the multiplexer circuitry.
Connect with 20 kΩ to GND and decouple with 100 nF to VDD.
27
G1
Input
28
G0
Input
Digital input. Select output amplifier gain value: G0 = LSB, G1 = MSB ('00'
= unity gain, '01' = x2, '10' = x4, '11' = x8).
29
CAL
Input
Digital input (active high). Initialization of output amplifier. Output amplifier
outputs BLACKREF in unity gain mode when CAL is high (1).
Apply pulse pattern (see sensor timing diagram).
30
OUT
Output
Analog Output Video Signal. Connected to the analog input of the internal
(pin 52) 10-bit ADC or an external ADC.
31
BLACKREF
Input
Analog input. Control voltage for output signal offset level. Buffered
on-chip, the reference level can be generated by a 100 kΩ resistive divider.
Connect to 2V DC for use with on-chip ADC.
32
VDDA
Supply
Analog power supply of image core (typical 5V).
33
VDDD
Supply
Digital power supply of image core (typical 5V).
Document Number: 38-05714 Rev. *C
Pin Description
Digital input. Latch address (A0…A9) to X-register (0 = track, 1 = hold).
Digital supply of the image sensor.
Selection of analog channel: '00' selects image sensor ('01' selects A_IN1,
'10' A_IN2, and '11' A_IN3).
Page 13 of 21
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STAR1000
Table 8. Pin List of the STAR1000 Sensor (continued)
Pin
Pin Name
Pin Type
Pin Description
34
GNDA
Ground
Analog ground of image core.
35
GNDD
Ground
Digital ground of image core.
36
NBIAS_ARRAY
Input
Analog input. Biasing of the pixel array. Connect with 1MΩ to VDDA and
decouple with 100 nF capacitor to GND.
37
n.c.
38
n.c.
39
n.c.
40
n.c.
41
n.c.
42
n.c.
43
n.c.
44
n.c.
45
n.c.
46
n.c.
47
n.c.
48
TESTPIXARRAY
Output
Analog output of an array of 20 x 35 test pixels where all photodiodes are
connected in parallel. Is used for electro-optical evaluation.
49
PHOTODIODE
Output
Plain Photo Diode (without circuitry). Area of the photodiode = 20 x 35
pixels. Is used for electro-optical evaluation.
50
NBIAS_ANA
Input
51
NBIAS_ANA2
Input
52
IN_ADC
Input
53
VDD_ADC_ANA
Supply
Analog power supply of the ADC (typical 5V).
54
GND_ADC_ANA
Ground
Analog ground of the ADC.
55
VLOW_ADC
Input
Low reference voltage of internal ADC. Nominal input range of the ADC
is between 2V and 4V. The resistance between VLOW_ADC and
VHIGH_ADC is approximately 1.5 kΩ. Connect with 1.5 kΩ to GND and
decouple with 100 nF to GND.
56
n.c.
57
PBIASDIG2
Input
Connect with 20 kΩ to GND and decouple with 100nF to VDDA.
Analog input. Analog biasing of the ADC circuitry. Connect with 100 kΩ to
VDDA and decouple with 100 nF to GND.
Analog input of the internal ADC. Connect to analog output of image
sensor (pin 30).
Input range (typically 2V and 4V) of the internal ADC is set between by
VLOW_ADC (pin 55) and VHIGH_ADC (pin 62).
58
BITINVERT
Input
Digital input. Inversion of the ADC output bits. 0 = invert output bits (0 =>
black, 1023; white, 0), 1 = no inversion of output bits (black, 0; white, 1023).
59
TRI_ADC
Input
Digital input. Tri-state control of digital ADC outputs (1 = tri-state, 0 =
normal mode).
60
D0
Input
ADC output bits.#D0 = LSB, D9=MSB.
61
CLK
Input
Digital input. ADC clock. ADC converts on falling edge.
Document Number: 38-05714 Rev. *C
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STAR1000
Table 8. Pin List of the STAR1000 Sensor (continued)
Pin
Pin Name
Pin Type
Pin Description
62
VHIGH_ADC
Input
High reference voltage of internal ADC. Nominal input range of the ADC
is between 2V and 4V. The resistance between VLOW_ADC and
VHIGH_ADC is about 1.5 kΩ.
Connect with 1.1 kΩ to VDDA and decouple with 100 nF to GND.
63
GND_ADC_ANA
Ground
Analog ground of the ADC circuitry.
64
VDD_ADC_ANA
Supply
Analog supply of the ADC circuitry (typical 5V).
65
VDD_ADC_DIG
Supply
Digital supply of the ADC circuitry (typical 5V).
66
GND_ADC_DIG
Output
Digital ground of the ADC circuitry.
67
VDD_DIG_OUT
Supply
Power supply of ADC digital output. Connect to 5V for normal operation.
Can be brought to lower voltage when image sensor must be interfaced
to low voltage periphery.
68
D1
Output
ADC output bits. #D0 = LSB, D9 = MSB.
69
D2
Output
70
D3
Output
71
D4
Output
72
D5
Output
73
VDDA
Supply
Analog supply of the image core (typical 5V).
74
GNDA
Ground
Analog ground of the image core (typical 5V).
75
GND_AB
Supply
Anti-blooming drain control voltage. Default: connect to ground where the
anti-blooming is operational but not maximal. Apply 1V DC for improved
anti-blooming.
76
VREF
Supply
Analog supply. Reset level for RESET_DS. Is used for extended optical
dynamic range. See FAQ for more details.
77
VRES
Supply
Analog supply. Reset level for RESET (typical 5V).
78
D6
Output
ADC output bits. #D0 = LSB, D9 = MSB.
79
D7
Output
80
D8
Output
81
D9
Output
82
A0
Input
83
A1
Input
84
A2
Input
Document Number: 38-05714 Rev. *C
Digital input. Address inputs for row and column addressing. A9 = LSB,
A0 = MSB.
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STAR1000
Packaging and Geometrical Constraints
Package Drawing
The detector is packaged in an 84-pin J-leaded package.
The detector is mounted into position with thermally and electrically conductive adhesive. The bottom plate of the cavity is
electrically connected to a ground pin.
The detector is positioned into the cavity such that the optical
center of the detector coincides with the geometrical center of
the cavity within a tolerance of ± 50 μm in X- and Y direction. The
tolerance on the parallelism of the detector is ± 50 μm in X- and
Y- direction.
Note: The dimensions in Figure 8 are in inches.
Figure 8. Package Drawing
Document Number: 38-05714 Rev. *C
Page 16 of 21
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STAR1000
Die Alignment
Figure 9. Die Alignment
Parallelism in
X and Y within
+ 50 mm
200 P
Y
Pin 1
Centre of Cavity
and of FPA
Centre of
Silicium
A
52 P
Bonding Cavity:
0.508+0.051
X
Offset Between Centre of
Silicium and Centre of
Cavity:
X: 52 Pm
Y: 200 Pm
Die:
0.508+0.01
A
Glass Window:
1.0+/-0.05
Window Adhesive:
0.08+0.02
Die Cavity:
0.508+0.051
A-
Die Adhesive:
0.08+0.02
Section A
Drawing Not to Scale
Glass Lids
There are 2 glass lid versions available:
■
STAR1000 - Quartz glass with air inside the cavity
■
STAR1000BK7 and STAR1000SP - BK7G18 glass with N2
inside the cavity
Document Number: 38-05714 Rev. *C
Page 17 of 21
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STAR1000
Soldering and Handling
Soldering and Handling Conditions
Take special care when soldering image sensors onto a circuit
board. Prolonged heating at elevated temperatures may result in
deterioration of the performance of the sensor. The following
recommendations are made to ensure that sensor performance
is not compromised during end users' assembly processes.
Use a soldering iron with temperature control at the tip. The
soldering iron tip temperature should not exceed 350°C.
The soldering period for each pin should be less than five
seconds.
Reflow Soldering
Reflow soldering is not allowed.
Board Assembly
The STAR1000 is very sensitive to ESD. Device placement onto
boards should be done in accordance with strict ESD controls for
Class 0, JESD22 Human Body Model, and Class A, JESD22
Machine Model devices. Assembly operators need to always
wear all designated and approved grounding equipment;
grounded wrist straps at ESD protected workstations are recommended including the use of ionized blowers. All tools should be
ESD protected.
Precautions and Cleaning
Manual Soldering
RoHS (lead free) Compliance
When a soldering iron is used the following conditions should be
observed:
This paragraph reports the use of Hazardous chemical
substances as required by the RoHS Directive (excluding
packing material).
Avoid spilling solder flux on the cover glass; bare glass and
particularly glass with antireflection filters may be harmed by the
flux. Avoid mechanical or particulate damage to the cover glass.
Use isopropyl alcohol (IPA) as a solvent for cleaning the image
sensor glass lid. When using other solvents, confirm whether the
solvent does not damage the package and/or glass lid.
Table 9. Chemical Substances in STAR250 Sensor
Any intentional content
If there is any intentional content, in which portion is
it contained?
Lead
NO
-
Cadmium
NO
-
Mercury
NO
-
Hexavalent chromium
NO
-
PBB (Polybrominated biphenyls)
NO
-
PBDE (Polybrominated diphenyl ethers)
NO
-
Chemical Substance
Information on Lead Free Soldering
The product cannot withstand a lead free soldering process.
Reflow or wave soldering is not recommended. Hand soldering
is needed for this part type. Solder 1 pin on each side and let the
sensor cool down for minimum 1 minute before continuing.
Note: "Intentional Content" is defined as any material
demanding special attention that is contained into the inquired
product by these cases:
1. A case that the above material is added as a chemical composition into the inquired product intentionally in order to produce
Document Number: 38-05714 Rev. *C
and maintain the required performance and function of the
intended product
2. A case that the above material, which is used intentionally in
the manufacturing process, is contained in or adhered to the
inquired product.
The following case is not treated as "intentional content":
A case that the above material is contained as an impurity into
raw materials or parts of the intended product. The impurity is
defined as a substance that cannot be removed industrially, or it
is produced at a process like chemical composing or reaction
and it cannot be removed technically.
Page 18 of 21
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STAR1000
Ordering Information
Table 10. Ordering Information
Part Number
Cypress Part Number
Package
Glass Lid
Mono/Color
STAR1000
CYIS1SM1000AA-HQC
84-pin JLCC
Quartz
Mono
STAR1000-BK7
CYIS1SM1000AA-HHC
84-pin JLCC
BK7G18
Mono
STAR1000SP
CYIS1SM1000AA-HHCS
84-pin JLCC
BK7G18
Mono
Disclaimer
Cypress image sensors are only warranteed to meet the specifications as described in the production data sheet.
Cypress reserves the right to change any information contained herein without notice.
Please contact your local sales agent for more information.
Document Number: 38-05714 Rev. *C
Page 19 of 21
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STAR1000
1M Pixel Radiation Hard CMOS Image
Sensor
APPENDIX A: STAR1000 Evaluation System
The STAR1000 evaluation kit consists of a multifunctional digital
board (memory, sequencer, and IEEE 1394 Fire Wire interface)
and an analog image sensor board.
images can be stored in different file formats (8 or 16-bit). All
settings can be adjusted dynamically to evaluate the sensors
specs. Default register values can be loaded to start the software
in a desired state.
Visual Basic software (under Windows 2000 or XP) allows the
grabbing and display of images from the sensor. All acquired
All products and company names mentioned in this document
may be the trademarks of their respective holders.
For evaluating purposes, a STAR1000 evaluation kit is available.
Cypress Semiconductor Corporation
Document Number: 38-05714 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 20, 2009
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STAR1000
Document History Page
Document Title: STAR1000 - 1M Pixel Radiation Hard CMOS Image Sensor
Document Number: 38-05714
Revision
ECN
Orig. of
Change
Submission
Date
**
310213
SIL
See ECN
*A
603177
QGS
See ECN
Converted to Framemaker Format
*B
649371
FPW
See ECN
Package spec label update + ordering information update
*C
2738591 FOSTMP2
See ECN
Bond diagram update + review
Description of Change
Initial Cypress release
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
psoc.cypress.com
clocks.cypress.com
Wireless
wireless.cypress.com
Memories
memory.cypress.com
Image Sensors
image.cypress.com
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05714 Rev. *C
Revised July 20, 2009
Page 21 of 21
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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