CYPRESS CY7C1062AV33

CY7C1062AV33
512K x 32 Static RAM
Features
pins (I/O0 through I/O7), is written into the location specified on
the address pins (A0 through A18). If Byte Enable B (BB) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23
and I/O24 to I/O31, respectively.
• High speed
— tAA = 8 ns
• Low active power
— 1080 mW (max.)
Reading from the device is accomplished by enabling the chip
(CE1, CE2, and CE3 LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (BA) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
Enable B (BB) is LOW, then data from memory will appear on
I/O8 to I/O15. Similarly, Bc and BD correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and CE3
features
• Available in non Pb-free 119-ball PBGA package
The input/output pins (I/O0 through I/O31) are placed in a
high-impedance state when the device is deselected (CE1,
CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (BA-D HIGH), or during a write
operation (CE1, CE2, and CE3 LOW, and WE LOW).
Functional Description
The CY7C1062AV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
The CY7C1062AV33 is available in a 119-ball pitch ball grid
array (PBGA) package.
Writing to the device is accomplished by enabling the chip
(CE1, CE2, and CE3 LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (BA) is LOW, then data from I/O
WE
CE1
CE2
CE3
OE
BA
BB
BC
BD
CONTROL LOGIC
Logic Block Diagram
512K x 32
ARRAY
OUTPUT BUFFERS
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFERS
I/O0–I/O31
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUMN
DECODER
Selection Guide
–8
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 38-05137 Rev. *F
•
–10
–12
Unit
8
10
12
ns
Com’l
300
275
260
mA
Ind’l
300
275
260
Com’l/Ind’l
50
50
50
198 Champion Court
•
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1062AV33
Pin Configurations[1, 2]
119-ball PBGA
(Top View)
1
2
3
4
5
6
7
A
I/O16
A
A
A
A
A
I/O0
B
C
D
E
F
G
H
J
K
L
M
N
P
I/O17
I/O18
I/O19
A
Bc
VDD
A
CE2
VSS
CE1
NC
VSS
A
CE3
VSS
A
Ba
VDD
I/O1
I/O2
I/O3
I/O20
VSS
VDD
VSS
VDD
VSS
I/O4
I/O21
VDD
VSS
VSS
VSS
VDD
I/O5
I/O22
VSS
VDD
VSS
VDD
VSS
I/O6
I/O23
NC
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O7
DNU
I/O24
I/O25
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O8
I/O9
VDD
VSS
VSS
VSS
VDD
I/O10
I/O27
VSS
VDD
VSS
VDD
VSS
I/O11
I/O28
VDD
VSS
VSS
VSS
VDD
I/O12
I/O29
A
Bd
NC
Bb
A
I/O13
I/O30
A
A
WE
A
A
I/O14
I/O31
A
A
OE
A
A
I/O15
R
T
U
I/O26
Notes:
1. NC pins are not connected on the die.
2. DNU pins have to be left floating or tied to VSS to ensure proper application.
Document #: 38-05137 Rev. *F
Page 2 of 9
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CY7C1062AV33
Maximum Ratings
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 0.3V
Industrial
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
–8
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[3]
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VOUT < VCC, Output
Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
–10
Max.
2.4
Min.
–12
Max.
2.4
0.4
Min.
Max.
Unit
2.4
V
0.4
V
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
0.4
2.0
VCC
+ 0.3
V
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
–1
+1
µA
–1
+1
–1
+1
–1
+1
µA
Com’l
300
275
260
mA
Ind’l
300
275
260
mA
70
70
70
mA
50
50
50
mA
Com’l/
Ind’l
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
8
pF
10
pF
AC Test Loads and Waveforms[5]
50Ω
VTH = 1.5V
OUTPUT
Z0 = 50Ω
30 pF
Including all Components
of Test Equipment
(a)
ALL INPUT PULSES
3.3V
90%
90%
10%
10%
GND
Fall time:
> 1 V/ns
Rise time > 1 V/ns
R1 317Ω
3.3V
*Including OUTPUT
Jig and
*
Scope
5 pF
(b)
R2
351Ω
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
(c)
Notes:
3. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document #: 38-05137 Rev. *F
Page 3 of 9
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CY7C1062AV33
AC Switching Characteristics Over the Operating Range[6]
–8
Parameter
Description
Min.
–10
Max.
Min.
–12
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC (typical) to the first access[7]
1
1
1
ms
tRC
Read Cycle Time
8
10
12
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1, CE2, or CE3 LOW to Data Valid
8
10
12
ns
tDOE
OE LOW to Data Valid
5
5
6
ns
8
3
[8]
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[8]
10
3
1
1
5
Low-Z[8]
tLZCE
CE1, CE2, or CE3 LOW to
tHZCE
CE1, CE2, or CE3 HIGH to High-Z[8]
3
3
3
ns
6
CE1, CE2, or CE3 LOW to
CE1, CE2, or CE3 HIGH to Power-down[9]
8
10
12
ns
tDBE
Byte Enable to Data Valid
5
5
6
ns
Byte Enable to
tHZBE
Byte Disable to High-Z[8]
Write
1
0
ns
tPD
tLZBE
0
ns
tPU
Low-Z[8]
0
ns
6
5
ns
ns
1
5
5
Power-up[9]
12
3
1
5
ns
1
5
ns
6
ns
Cycle[10, 11]
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE1, CE2, or CE3 LOW to Write End
6
7
8
ns
tAW
Address Set-up to Write End
6
7
8
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
ns
tSD
Data Set-up to Write End
5
5.5
6
ns
tHD
Data Hold from Write End
0
0
0
ns
Low-Z[8]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[8]
3
tBW
Byte Enable to End of Write
3
5
6
3
5
7
ns
6
8
ns
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
tCDR
VDR > 2V
3.0V
tR
CE
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started.
8. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
± 200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to
the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05137 Rev. *F
Page 4 of 9
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CY7C1062AV33
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE1,CE2,CE3
tACE
OE
tHZOE
tDOE
tLZOE
BA, BB, BC, BD
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
IICC
CC
50%
ISB
Notes:
12. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05137 Rev. *F
Page 5 of 9
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CY7C1062AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16, 17]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BA, BB, BC , BD
tSD
tHD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)[15, 16, 17]
tWC
ADDRESS
tSA
tBW
BA, BB, BC , BD
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Notes:
15. CE indicates a combination of all three chip enables. When ACTIVE LOW, CE indicates the CE1, CE2, and CE3 are LOW.
16. Data I/O is high-impedance if OE or BA, BB, BC, BD = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05137 Rev. *F
Page 6 of 9
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CY7C1062AV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BA, BB, BC, BD
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE1 CE2 CE3
I/O0–
I/O7
I/O8–
I/O15
I/O16–
I/O23
I/O24–
I/O31
OE
WE
BA
BB
Bc
BD
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Power Down
Mode
(ISB)
Power
H
X
X
H
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Power Down
(ISB)
X
X
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Power Down
(ISB)
L
L
L
L
H
L
L
L
L
Data Out
Data Out
Data Out
Data Out
Read All Bits
(ICC)
L
L
L
L
H
L
H
H
H
Data Out
High-Z
High-Z
High-Z
Read Byte A
Bits Only
(ICC)
L
L
L
L
H
H
L
H
H
High-Z
Data Out
High-Z
High-Z
Read Byte B
Bits Only
(ICC)
L
L
L
L
H
H
H
L
H
High-Z
High-Z
Data Out
High-Z
Read Byte C
Bits Only
(ICC)
L
L
L
L
H
H
H
H
L
High-Z
High-Z
High-Z
Data Out
Read Byte D
Bits Only
(ICC)
L
L
L
X
L
L
L
L
L
Data In
Data In
Data In
Data In
Write All Bits
(ICC)
L
L
L
X
L
L
H
H
H
Data In
High-Z
High-Z
High-Z
Write Byte A
Bits Only
(ICC)
L
L
L
X
L
H
L
H
H
High-Z
Data In
High-Z
High-Z
Write Byte B
Bits Only
(ICC)
L
L
L
X
L
H
H
L
H
High-Z
High-Z
Data In
High-Z
Write Byte C
Bits Only
(ICC)
L
L
L
X
L
H
H
H
L
High-Z
High-Z
High-Z
Data In
Write Byte D
Bits Only
(ICC)
L
L
L
H
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Selected,
Outputs
Disabled
(ICC)
Document #: 38-05137 Rev. *F
Page 7 of 9
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CY7C1062AV33
Ordering Information
Speed
(ns)
8
10
12
Ordering Code
CY7C1062AV33-8BGC
CY7C1062AV33-10BGC
CY7C1062AV33-10BGI
CY7C1062AV33-12BGC
CY7C1062AV33-12BGI
Package
Name
51-85115
Package Type
119-ball (14 x 22 x 2.4 mm) PBGA
Operating
Range
Commercial
Industrial
Commercial
Industrial
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05137 Rev. *F
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1062AV33
Document History Page
Document Title: CY7C1062AV33 512K x 32 Static RAM
Document Number: 38-05137
REV.
ECN NO.
Issue Date
Orig. of
Change
**
109752
02/27/02
HGK
New Data Sheet
*A
117059
09/19/02
DFP
Removed 15-ns bin and added 8-ns bin.
Changed CE2 TO CE2.
Changed CIN – input capacitance – from 6 pF to 8 pF.
Changed COUT – output capacitance – from 8 pF to 10 pF.
*B
119389
10/07/02
DFP
Updated ICC, Tsd, and Tdoe parameters.
Removed note 7 (IZ/hZ comment).
*C
120384
11/13/02
DFP
Final Data Sheet.
Removed note 2.
Added note 3 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd.
*D
124440
2/25/03
MEG
Changed ISB1 from 100 mA to 70 mA
*E
329638
See ECN
RKF
Removed CE2 waveform showing Active High signal timing on Page #5, and
included it with the CE1, CE3 waveform
Corrected Truth Table on page 7 with CE2 active low information
*F
492137
See ECN
NXR
Included note #1 and 2 on page #2
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated Ordering Information Table
Document #: 38-05137 Rev. *F
Description of Change
Page 9 of 9
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