CY7C1062DV33 16-Mbit (512K X 32) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3V ■ 2.0V data retention To write to the device, take Chip Enables (CE1, CE2, and CE3 LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A18). If Byte Enable B (BB) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). Likewise, BC and BD correspond with the IO pins IO16 to IO23 and IO24 to IO31, respectively. ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE1, CE2, and CE3 features ■ Available in Pb-free 119-Ball PBGA package To read from the device, take Chip Enables (CE1, CE2, and CE3 LOW), and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte Enable B (BB) is LOW, then data from memory appears on IO8 to IO15. Likewise, Bc and BD correspond to the third and fourth bytes. For more information, see Truth Table on page 9 for a complete description of read and write modes. The input and output pins (IO0 through IO31) are placed in a high impedance state when the device is deselected (CE1, CE2, or CE3 HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a write operation (CE1, CE2 and CE3 LOW, and WE LOW). OUTPUT BUFFERS 512K x 32 ARRAY SENSE AMPS A(9:0) ROW DECODER INPUT BUFFERS CONTROL LOGIC Logic Block Diagram IO0 – IO31 WE CE1 CE2 CE3 OE BA BB BC BD COLUMN DECODER A(18:10) Cypress Semiconductor Corporation Document Number: 38-05477 Rev.*D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 06, 2007 CY7C1062DV33 Selection Guide –10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration Figure 1. 119-Ball PBGA (Top View) [1] 1 2 3 4 5 6 7 A IO16 A A A A A IO0 B C D E F G H J K L M N P IO17 IO18 IO19 A Bc VDD A CE2 VSS CE1 NC VSS A CE3 VSS A Ba VDD IO1 IO2 IO3 R T U IO20 VSS VDD VSS VDD VSS IO4 IO21 VDD VSS VSS VSS VDD IO5 IO22 VSS VDD VSS VDD VSS IO6 IO23 NC VDD VSS VSS VDD VSS VSS VSS VDD VDD VSS IO7 NC IO24 IO25 VDD VSS VSS VDD VSS VSS VSS VDD VDD VSS IO8 IO9 VDD VSS VSS VSS VDD IO10 IO27 VSS VDD VSS VDD VSS IO11 IO28 VDD VSS VSS VSS VDD IO12 IO29 A Bd NC Bb A IO13 IO30 A A WE A A IO14 IO31 A A OE A A IO15 IO26 Note 1. NC pins are not connected on the die. Document Number: 38-05477 Rev.*D Page 2 of 11 CY7C1062DV33 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND [2] ....–0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State [2]................................... –0.5V to VCC + 0.5V DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V Range Ambient Temperature VCC Industrial –40°C to +85°C 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [3] VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage [2] –10 Min Unit Max 2.4 V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V +1 µA VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC –1 IOZ Output Leakage Current GND < VOUT < VCC, Output disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC IOUT = 0 mA CMOS levels 175 mA ISB1 Automatic CE Power Down Current — TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE Power Down Current —CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 25 mA Note 2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3 HIGH. Document Number: 38-05477 Rev.*D Page 3 of 11 CY7C1062DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT IO Capacitance Test Conditions Max Unit 8 pF 10 pF 119-Ball PBGA Unit 20.31 °C/W 8.35 °C/W TA = 25°C, f = 1 MHz, VCC = 3.3V Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board AC Test Loads and Waveforms The AC test loads and waveform diagram follows. [4] 50Ω OUTPUT Z0 = 50Ω R1 317 Ω 3.3V VTH = 1.5V OUTPUT 30 pF* R2 351Ω 5 pF* *Including jig and scope (a) *Capacitive Load consists of all components of the test environment 3.0V GND (b) All input pulses 90% 10% 90% 10% Fall Time:> 1V/ns Rise Time > 1V/ns (c) Note 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100µs (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document Number: 38-05477 Rev.*D Page 4 of 11 CY7C1062DV33 AC Switching Characteristics Over the Operating Range [5] Parameter Description –10 Min Max Unit Read Cycle tpower VCC (Typical) to the First Access [6] 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE Active LOW to Data Valid [3] 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low Z 10 [7] OE HIGH to High Z tLZCE CE Active LOW to Low Z [3, 7] tPU CE Deselect HIGH to High Z [3, 7] CE Active LOW to Power Up [3, 8] CE Deselect HIGH to Power Down tDBE Byte Enable to Data Valid Byte Enable to Low Z tHZBE Write tWC ns 5 tPD tLZBE ns 1 [7] tHZOE tHZCE 3 [7] Byte Disable to High Z 3 0 ns ns 10 ns 5 ns 1 [7] ns ns 5 [3, 8] ns ns 5 ns Cycle[9, 10] Write Cycle Time [3] 10 ns 7 ns 7 ns tSCE CE Active LOW to Write End tAW Address Setup to Write End tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Setup to Write End 5.5 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z [7] 3 ns tHZWE WE LOW to High Z [7] tBW Byte Enable to End of Write 5 7 ns ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads and Waveforms, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 200 mV from steady state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No.2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05477 Rev.*D Page 5 of 11 CY7C1062DV33 Data Retention Characteristics Over the Operating Range Parameter Conditions [3] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [11] Chip Deselect to Data Retention Time tR [12] Operation Recovery Time Min Typ Max 2 Unit V 25 VCC = 2V, CE > VCC – 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V 3.0V tR tCDR CE Switching Waveforms Figure 2. Read Cycle No. 1 [13, 14] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Notes 11. Tested initially and after any design or process changes that affects these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs 13. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL. 14. WE is HIGH for read cycle. Document Number: 38-05477 Rev.*D Page 6 of 11 CY7C1062DV33 Switching Waveforms (continued) Figure 3. Read Cycle No. 2 (OE Controlled) [3, 14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE BA, BB, BC , BD tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Figure 4. Write Cycle No. 1 (CE Controlled) [3, 15, 16, 17] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE t BW BA, BB, BC , BD tSD tHD DATA IO Notes 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE or BA, BB, BC, BD = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05477 Rev.*D Page 7 of 11 CY7C1062DV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 2 (WE Controlled, OE LOW) [3, 15, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BA, BB, BC , BD tHZWE tSD tHD DATA IO tLZWE Figure 6. Write Cycle No. 3 (BA, BB, BC, BD Controlled) [3] tWC ADDRESS tSA tBW BA, BB, BC , BD tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Document Number: 38-05477 Rev.*D Page 8 of 11 CY7C1062DV33 Truth Table CE1 CE2 CE3 OE WE BA BB Bc BD IO0–IO7 Mode Power H X X X X X X X X High Z High Z High Z High Z Power Down (ISB) X H X X X X X X X High Z High Z High Z High Z Power Down (ISB) X X H X X X X X X High Z High Z High Z High Z Power Down (ISB) L L L L H L L L L L L L L H L H H H Data Out Data Out Data Out Data Out High Z High Z High Z Read Byte A Bits Only (ICC) L L L L H H L H H High Z Data Out High Z High Z Read Byte B Bits Only (ICC) L L L L H H H L H High Z High Z Data Out High Z Read Byte C Bits Only (ICC) L L L L H H H H L High Z High Z High Z Data Out Read Byte D Bits Only (ICC) L L L X L L L L L L X L L H L L Data In Data In Data In Data In Write All Bits (ICC) H H Data In High Z High Z High Z Write Byte A Bits Only (ICC) L L L X L H L H H High Z Data In High Z High Z Write Byte B Bits Only (ICC) L L L X L H H L H High Z High Z Data In High Z Write Byte C Bits Only (ICC) L L L X L H H H L High Z High Z High Z Data In Write Byte D Bits Only (ICC) L L L H H X X X X High Z High Z High Z High Z Selected, Outputs Disabled (ICC) L L L X X H H H H High Z High Z High Z High Z Selected, Outputs Disabled (ICC) Document Number: 38-05477 Rev.*D IO8–IO15 IO16–IO23 IO24–IO31 Data Out Read All Bits (ICC) Page 9 of 11 CY7C1062DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1062DV33-10BGXI Package Diagram Operating Range Package Type 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Fee) Industrial Package Diagram Figure 7. 119-Ball PBGA (14 x 22 x 2.4 mm) 51-85115-*B Document Number: 38-05477 Rev.*D Page 10 of 11 CY7C1062DV33 Document History Document Title: CY7C1062DV33 16-Mbit (512K X 32) Static RAM Document Number: 38-05477 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance datasheet for C9 IPP *A 233748 See ECN RKF 1.AC, DC parameters are modified as per EROS (Spec # 01-2165) 2.Pb-free offering in the Ordering Information *B 469420 See ECN NXR Converted from Advance Information to Preliminary Removed –8 and –12 speed bins from product offering Removed Commercial operating Range Changed J7 Ball of PBGA from DNU to NC in the pinout diagram Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 2 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Changed tSD from 5.5 ns to 5 ns Added Data Retention Characteristics table and waveform on page 5. Updated the 48-pin FBGA package Updated the Ordering Information Table *C 499604 See ECN NXR Added note 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics Table on page 4 *D 1462583 See ECN VKN/AESA Converted from preliminary to final Updated block diagram Changed ICC spec from 150 mA to 175 mA Updated thermal specs Description of Change © Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05477 Rev.*D Revised September 06, 2007 All product and company names mentioned in this document are the trademarks of their respective holders. Page 11 of 11