CYPRESS CY2XF24FLXCT

PRELIMINARY
CY2XF24
High Performance LVPECL Oscillator with
Frequency Margining - I2C Control
Features
Functional Description
■
Low Jitter Crystal Oscillator (XO)
■
Less than 1ps Typical RMS Phase Jitter
■
Differential LVPECL Output
■
Output Frequency from 50 MHz to 690 MHz
The CY2XF24 is a high performance and high frequency Crystal
Oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed using the I2C Bus serial interface,
allowing easy frequency margin testing in applications.
■
Frequency Margining through I2C Bus
■
Factory Configured or Field Programmable
■
Integrated Phase-Locked Loop (PLL)
■
Pb-Free Package: 5.0 x 3.2 mm LCC
■
Supply Voltage: 3.3V or 2.5V
■
Commercial and Industrial Temperature Ranges
The CY2XF24 is available as a factory configured device or as
a field programmable device.
Logic Block Diagram
4
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
CLK
OUTPUT
DIVIDER
5
CLK#
PROGRAMMABLE
CONFIGURATION
1
SDA
I 2C
INTERFACE
2
SCL
Pinouts
Figure 1. Pin Diagram - 6 Pin Ceramic LCC
SDA 1
6 VDD
SCLK 2
5 CLK#
VSS 3
4 CLK
Table 1. Pin Definitions - 6 Pin Ceramic LCC
Pin
Name
I/O Type
Description
1
SDA
I/O
I2C Serial Data
2
SCLK
CMOS Input
I2C Serial Clock
4, 5
CLK, CLK#
LVPECL Output
Differential Output Clock
6
VDD
Power
Supply Voltage: 2.5V or 3.3V
3
VSS
Power
Ground
Cypress Semiconductor Corporation
Document Number: 001-53146 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2009
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PRELIMINARY
CY2XF24
Functional Description
Configuration Software
The CY2XF24 is a phase locked loop (PLL) based high performance clock generator. It uses an internal crystal oscillator as a
reference, and outputs one differential LVPECL clock. It has an
I2C Bus serial interface[1], which is used to change the output
frequency.
Cypress provides CyberClocks™ Online web-based software
that enables users to create data values for shifting into the
frequency words. This software is required because the
algorithm is too complicated to describe here.
The CY2XF24 comes configured for four different frequencies.
At power on, the four configurations are transparently loaded into
an internal volatile memory which in turn controls the PLL. The
user can switch between the four frequencies through the I2C
Bus. The user can also configure the CY2XF24 with new output
frequencies by shifting new data into the internal memory.
The user specifies the output frequency. The software then
calculates the bit stream. The bit stream is generic in the sense
that it can be shifted into any of the four Frequency Words. This
process is repeated for all frequencies of interest.
Frequency margining is a common application for this feature.
One frequency is used for the standard operating mode of the
device, while additional frequencies are available for margin
testing, either during product development or in system
manufacturing test.
Note that all configuration changes made using I2C are
temporary and are lost when power is removed from the device.
At power on, the device returns to its original state.
The configuration for a particular frequency is stored in a 6-byte
block of memory, known as a word. The CY2XF24 has four such
words, labeled Frequency Word 0 through Frequency Word 3.
An additional register byte contains a 2-bit field, which selects
one of the four frequency words. By writing to this Select Byte,
the user can switch back and forth between the four programmed
frequencies. The select byte is always defined to select
Frequency Word 0 at power on.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
I 2C
If more than four frequencies are needed, the
Bus can be
used to change any of the four frequency words. When writing
frequency words through I2C, users should not change the
currently selected word. Instead, write one of the three
unselected words before changing the select byte to select that
new word.
Figure 2 shows how the frequency words are arranged and
selected.
Figure 2. Frequency Words
10h – 15h
Frequency Word 0
00
16h – 1Bh
Frequency Word 1
01
1Ch – 21h
Frequency Word 2
10
22h – 27h
Frequency Word 3
Control
11
Sel
40h
Select Byte
Programming Description
The CY2XF24 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in a later section. Two
different device types are available, each with its own
programming flow. They are described in the follwing section.
Field Programmable CY2XF24F
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyberClocks Online Software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using a Cypress programmer.
Third party vendors manufacture programmers for small to large
volume applications. Cypress’s value added distribution partners
also provide programming services. Field programmable
devices are designated with an “F” in the part number. They are
intended for quick prototyping and inventory reduction. The
CY2XF24 is one time programmable (OTP).
Factory Configured CY2XF24
For customers wanting ready-to-use devices, the CY2XF24 is
available with no field programming required. All requests are
submitted to the local Cypress Field Application Engineer (FAE)
or sales representative. After the request is processed, the user
receives a new part number, samples, and data sheet with the
programmed values. This part number is used for additional
sample requests and production orders.
Programming Variables
Output Frequencies
Register
Address
Bits [1:0]
Default = 00
The software is located at www.cyberclocksonline.com.
PLL
The CY2XF24 is programmed with up to four independent output
frequencies, which are then selected using the I2C interface. The
device can synthesize frequencies to a resolution of 1 part per
million (ppm), but the actual accuracy of the output frequency is
limited by the accuracy of the integrated reference crystal.
The CY2XF24 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF24 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz, and
596 MHz to 617 MHz.
Note
1. The serial interface is I2C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped
to VDD, setup time, and output hold time.
Document Number: 001-53146 Rev. *A
Page 2 of 12
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CY2XF24
PRELIMINARY
Industrial Versus Commercial Device Performance
Industrial and Commercial devices have different internal
crystals. This has a potentially significant impact on performance
levels for applications requiring the lowest possible phase noise.
CyberClocks Online Software displays expected performance
for both options.
Table 4. Register 40h: Select Byte
Bits
Default Value
(binary)
7:2
000000
Reserved
1:0
00
Word Select Selects the Frequency
Word to determine the
output frequency. 00
selects Word 0; 01
selects Word 1; 10
selects Word 2; 11
selects Word 3
Phase Noise Versus Jitter Performance
In most cases, the device configuration for optimal phase noise
performance is different from the device configuration for optimal
cycle to cycle or period jitter. CyberClocks Online Software
includes algorithms to optimize performance for either
parameter.
Name
Description
Reserved. Always
write this value
Serial Interface Protocol and Timing
Table 2. Device Programming Variables
The CY2XF24 uses pins SDA and SCLK for an I2C Bus that
operates up to 100 kbits/sec in Read or Write mode. The
CY2XF24 is always a slave on this bus, meaning that it never
initiates a bus transaction. The basic Write protocol is as follows:
Variable
Output Frequency 0
Output Frequency 1
Output Frequency 2
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4 on page 5.
Output Frequency 3
Optimization (phase noise or jitter)
Temperature range (Commercial or Industrial)
Device Address
Memory Map
Five fields can be written through the I2C Bus. Four frequency
words define the output frequency. As shown in Table 3, each of
these words is a 6-byte field. When writing to a frequency word,
all six bytes should be written. They may be written either as
individual byte writes, or as a block write. The currently selected
frequency word should not be written to. All four words are
symmetrical, meaning that a 6-byte value that is valid for one
word is also valid for any of the other words, and produce the
same frequency.
The fifth field is the select byte, located at byte address 40h. The
value written into the two least significant bits determines the
active frequency word. The other bits of the byte are reserved
and should be written with the values indicated in the table.
Users should never write to any address other than the 25 bytes
described here.
Table 3. Frequency Words
Frequency
Word
Byte Addresses
(hex)
Word Select
(Select Byte 40h)
0
10h to 15h
00
1
16h to 1Bh
01
2
1Ch to 21h
10
3
22h to 27h
11
Document Number: 001-53146 Rev. *A
The device address is a 7-bit value. The default serial interface
address is 69H.
Data Valid
Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW as illustrated in Figure 5 on page 5.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 5.
START Sequence - Start Frame is indicated by SDA going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
STOP Sequence - Stop Frame is indicated by SDA going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During Write Mode, the CY2XF24 responds with an
Acknowledge (ACK) pulse after every eight bits. This is accomplished by pulling the SDA line LOW during the N*9th clock cycle
as illustrated in Figure 7 on page 6. (N = the number of bytes
transmitted). After the data packet is sent during Read Mode, the
master generates the acknowledge.
Page 3 of 12
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CY2XF24
PRELIMINARY
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (SDA = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (SDA = 0/LOW), and the master must end the
write sequence with a STOP condition.
the CY2XF24 receives the slave address with the R/W bit set to
a ‘1’, the CY2XF24 issues an acknowledge and transmits the
8-bit word. The master device does not acknowledge the
transfer, but does generate a STOP condition, which causes the
CY2XF24 to stop transmission.
Random Read
To write more than one byte at a time, the master does not end
the write sequence with a stop condition. Instead, the master can
send multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, just like after
the first byte, and accept data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the CY2XF24 internally increments the register address.
Through random read operations, the master may access any
memory location. To perform this type of read operation, first the
word address must be set. This is accomplished by sending the
address to the CY2XF24 as part of a write operation. After the
word address is sent, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next the master reissues the
control byte with the R/W byte set to ‘1’. The CY2XF24 then
issues an acknowledge and transmits the 8-bit word. The master
device does not acknowledge the transfer, but does generate a
STOP condition which causes the CY2XF24 to stop transmission.
Read Operations
Sequential Read
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action results in an incrementing of the internal address
pointer, and subsequently output of the next 8-bit data word. By
continuing to issue acknowledges instead of STOP conditions,
the master may serially read the entire contents of the slave
device memory. When the internal address pointer points to the
FFh register, after the next increment, the pointer points to the
00h register.
Writing Multiple Bytes
Current Address Read
The CY2XF24 has an onboard address counter that retains 1
more than the address of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation would return the value stored in location ‘n+1’. When
Figure 3. Data Transfer Sequence on the Serial Bus
SCLK
SDA
START
Condition
Address or
Acknowledge
Valid
Document Number: 001-53146 Rev. *A
Data may
be changed
STOP
Condition
Page 4 of 12
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CY2XF24
PRELIMINARY
Figure 4. Data Frame Architecture
SDA Write
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
8-bit
Register
Address
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+2)
1 Bit
Slave
ACK
8-bit
Register
Data
(FFH)
1 Bit
Slave
ACK
1 Bit
Slave
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
SDA Read
Current
Address
Read Start Signal
SDA Read
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 1 ACK
7-bit
Device
Address
1 Bit
Master
ACK
8-bit
Register
Data
Stop Signal
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
8-bit
Register
Address
(XXH)
1 Bit
Master
ACK
7-bit
Device
Address
+R/W=1
1 Bit
Master
ACK
8-bit
Register
Data
(XXH)
1 Bit
Master
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Master
ACK
8-bit
Register
Data
(FFH)
1 Bit
Master
ACK
1 Bit
Master
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Figure 5. Data Valid and Data Transition Periods
Data Valid
Transition
to next Bit
SDA
tDH
tSU
CLKHIGH
VIH
SCLK
VIL
CLKLOW
Figure 6. Start and Stop Frame
SDA
START
Document Number: 001-53146 Rev. *A
Transition
to next Bit
SCLK
STOP
Page 5 of 12
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CY2XF24
PRELIMINARY
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
+
START
DA6
DA5 DA0
+
R/W
ACK
RA7
+
RA6 RA1
RA0
ACK
D7
+
+
D6
D1
D0
ACK
STOP
+
SCLK
Absolute Maximum Conditions
Parameter
Description
Condition
VDD
Supply Voltage
VIN[2]
Input Voltage, DC
Relative to VSS
Non Operating
TS
Temperature, Storage
TJ
Temperature, Junction
ESDHBM
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
ΘJA[3]
Thermal Resistance, Junction to Ambient
0 m/s airflow
Min
Max
Unit
–0.5
4.4
V
–0.5
VDD+0.5
V
–55
135
°C
–40
135
°C
2000
V
64
°C/W
Operating Conditions
Parameter
VDD
Min
Typ
Max
Unit
3.3V Supply Voltage Range
Description
3.135
3.3
3.465
V
2.5V Supply Voltage Range
2.375
2.5
2.625
V
TPU
Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp
is Monotonic)
0.05
–
500
ms
TA
Ambient Temperature (Commercial)
0
–
70
°C
–40
–
85
°C
Condition
Min
Typ
Max
Unit
VDD = 3.465V, CLK = 150 MHz, output
terminated
–
–
150
mA
VDD = 2.625V, CLK = 150 MHz, output
terminated
–
–
145
mA
Ambient Temperature (Industrial)
DC Electrical Characteristics
Parameter
IDD[4]
Description
Operating Supply Current
VOH
LVPECL High Output Voltage
VDD = 3.3V or 2.5V, RTERM = 50Ω to
VDD – 2.0V
VDD – 1.15
–
VDD –
0.75
V
VOL
LVPECL Low Output Voltage
VDD = 3.3V or 2.5V, RTERM = 50Ω to
VDD – 2.0V
VDD – 2.0
–
VDD –
1.625
V
VOD1
LVPECL Output Voltage Swing
(VOH - VOL)
VDD = 3.3V or 2.5V, RTERM = 50Ω to
VDD – 2.0V
600
–
1000
mV
VOD2
LVPECL Output Voltage Swing
(VOH - VOL)
VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V
500
–
1000
mV
VOCM
LVPECL Output Common Mode
Voltage (VOH + VOL)/2
VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V
1.2
–
–
V
Note
2. The voltage on any input or IO pin cannot exceed the power pin during power up.
3. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
4. IDD includes ~24 mA of current that is dissipated externally in the output termination resistors.
Document Number: 001-53146 Rev. *A
Page 6 of 12
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CY2XF24
PRELIMINARY
DC Electrical Characteristics (continued)
Parameter
Description
Condition
Min
Typ
Max
Unit
–
–
0.1*VDD
V
0.7*VDD
–
–
V
–
–
0.3*VDD
V
–
–
115
μA
VOLS
Output Low Voltage (SDA)
VIH
Input High Voltage
VIL
Input Low Voltage
IIH0
Input High Current (SDA)
IIH1
Input High Current (SCLK)
Input = VDD
–
–
10
μA
IIL0
Input Low Current (SDA)
Input = VSS
–50
–
–
μA
IIL1
Input Low Current (SCLK)
Input = VSS
–20
–
–
μA
CIN0[5]
Input Capacitance (SDA)
–
15
–
pF
CIN1[5]
Input Capacitance (SCLK)
–
4
–
pF
IOL = 4 mA
Input = VDD
AC Electrical Characteristics[5]
Parameter
Description
Condition
Min
Typ
Max
Unit
50
–
690
MHz
TA = 0°C to 70°C
–
–
±35
ppm
TA = –40° to 85°C
–
–
±55
ppm
–
–
±15
ppm
F <= 450 MHz, measured at zero crossing
45
50
55
%
FOUT
Output Frequency[7]
FSC
Frequency Stability, commercial
devices[6]
FSI
Frequency Stability, industrial
devices[6]
AG
Aging, 10 years
TDC
Output Duty Cycle
F > 450 MHz, measured at zero crossing
40
50
60
%
TR, TF
Output Rise and Fall Time
20% and 80% of full output swing
200
400
600
ps
TLOCK
Startup Time
Time for CLK to reach valid frequency
measured from the time VDD = VDD(min)
–
–
10
ms
TLSER
Relock Time
Time for CLK to reach valid frequency from
serial bus change to select bits in register
40h, measured from I2C STOP
–
–
10
ms
TJitter(φ)
RMS Phase Jitter (Random)
fOUT = 106.25 MHz (12 kHz–20 MHz)
–
1
–
ps
Document Number: 001-53146 Rev. *A
Page 7 of 12
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CY2XF24
PRELIMINARY
I2C Bus Timing Specifications[5]
Parameter
Description
fSCLK
SCLK frequency
tHD:STA
Start mode time from SDA LOW to SCLK LOW
tLOW
tHIGH
Min
Max
Unit
100
kHz
4
μs
SCLK LOW period
4.7
μs
SCLK HIGH period
4
μs
tSU:DAT
Input data setup (SDA transition to SCLK rising edge)
1000
ns
tHD:DAT
Input data hold (SCLK falling edge to SDA transition)
0
ns
tHD:DO
Output data hold (SCLK falling edge to SDA transition)
tSR
Rise time of SCLK and SDA
tSF
Fall time of SCLK and SDA
tSU:STO
Stop mode time from SCLK HIGH to SDA HIGH
tBUF
Stop mode to Start mode
200
ns
300
ns
300
ns
4
μs
4.7
μs
Typical Output Characteristics
Figure 8. 2.5V Supply and Termination to VDD–1.5V, minimum VDD & maximum TA
0.9
1.40
0.8
0.7
VOCM (V)
Swing (V)
1.35
0.6
1.30
1.25
0.5
1.20
0.4
0
100
200
300
400
Frequency (MHz)
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Notes
5. Not 100% tested, guaranteed by design and characterization.
6. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
7. This parameter is specified in CyberClocks Online software.
Document Number: 001-53146 Rev. *A
Page 8 of 12
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CY2XF24
PRELIMINARY
Figure 9. 2.5V Supply and Termination to VDD–2V, minimum VDD & maximum TA
0.9
0.90
0.8
0.7
VOCM (V)
Swing (V)
0.85
0.6
0.80
0.75
0.5
0.4
0.70
0
100
200
300
400
500
600
700
0
100
200
Frequency (MHz)
300
400
500
600
700
Frequency (MHz)
Figure 10. 3.3V Supply and Termination to VDD–2V, minimum VDD & maximum TA
1.60
0.9
0.8
0.7
VOCM (V)
Swing (V)
1.55
0.6
1.50
1.45
0.5
0.4
1.40
0
100
200
300
400
Frequency (MHz)
Document Number: 001-53146 Rev. *A
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Page 9 of 12
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CY2XF24
PRELIMINARY
Measurement Definitions
Figure 11. Output DC Parameters
VA
CLK
VOD
VOCM = (V A + VB)/2
CLK#
VB
Figure 12. Duty Cycle Timing
CLK
TDC =
TPW
TPERIOD
CLK#
TPW
TPERIOD
Figure 13. Output Rise and Fall Time
CLK#
CLK
80%
80%
20%
20%
TR
TF
Termination Circuits
Figure 14. LVPECL Termination
VDD - 2V
(VDD = 3.3V)
50Ω
50Ω
50Ω
50Ω
50Ω
CLK#
Document Number: 001-53146 Rev. *A
CLK
BUF
BUF
CLK
VDD - 2V or VDD - 1.5V
(VDD = 2.5V)
50Ω
50Ω
50Ω
CLK#
Page 10 of 12
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CY2XF24
PRELIMINARY
Ordering Information
Part Number[8]
Configuration
Package Description
Product Flow
Pb-Free
CY2XF24FLXCT
Field Programmable
6-Pin Ceramic LCC SMD - Tape and Reel
Commercial, 0° to 70°C
CY2XF24FLXIT
Field Programmable
6-Pin Ceramic LCC SMD - Tape and Reel
Industrial, –40° to 85°C
CY2XF24LXCxxxT
Factory Configured
6-Pin Ceramic LCC SMD - Tape and Reel
Commercial, 0° to 70°C
CY2XF24LXIxxxT
Factory Configured
6-Pin Ceramic LCC SMD - Tape and Reel
Industrial, –40° to 85°C
Package Drawings and Dimensions
Figure 15. 6-Pin 3.2x5.0 mm Ceramic LCC LZ06A
0.50
1.30 Max
2.54 TYP.
SIDE VIEW
0.64 TYP.
TYP.
0.20 R REF.
5
4
0.32 R
INDEX
6
7
9
8
3
2
0.45 REF.
TOP VIEW
1
0.10 REF.
3.2
TYP.
1.2 TYP.
10
1.27
5.0
TYP.
0.10 R REF.
BOTTOM VIEW
Dimensions in mm
General Tolerance: ± 0.15MM
Kyocera dwg ref KD-VA6432-A
001-10044-**
Package Weight ~ 0.12 grams
.
Note
8. “xxx” is a factory assigned code that identifies the programming option.
Document Number: 001-53146 Rev. *A
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PRELIMINARY
CY2XF24
Document History Page
Document Title: CY2XF24 High Performance LVPECL Oscillator with Frequency Margining - I2C Control
Document Number: 001-53146
REV.
ECN NO.
Orig. of
Change
**
2704379
KVM/PYRS
*A
2718898
WWZ
Submission
Date
Description of Change
05/11/2009 New data sheet
06/15/09
Minor ECN to post data sheet to external web
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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Document Number: 001-53146 Rev. *A
Revised June 15, 2009
Page 12 of 12
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