ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS FEATURES 1 • • • Qualified for Automotive Applications 4000-V(peak) Isolation – UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1 – 50-kV/s Transient Immunity (Typ) Signaling Rate 0 Mbps to 150 Mbps – Low Propagation Delay – Low Pulse Skew (Pulse-Width Distortion) • • • • • Low-Power Sleep Mode High Electromagnetic Immunity Low Input Current Requirement Failsafe Output Drop-In Replacement for Most Optical and Magnetic Isolators DESCRIPTION The ISO721 is a digital isolator with a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, this device prevents noise currents on a data bus or other circuits from entering the local ground, and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc refresh pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. FUNCTION DIAGRAM DC Channel Isolation Barrier + _ OSC + PWM Vref _ + POR IN Input + Filter BIAS + _ Vref _ Filter Pulse Width Demodulation Carrier Detect POR Data MUX AC Detect 3-State Output Buffer OUT + AC Channel 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com DESCRIPTION (CONTINUED) The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching and allows fast transient voltage changes between the input and output grounds without corrupting the output. The small capacitance and resulting time constant provide for fast operation with signaling rates(1) from 0 Mbps (dc) to 100 Mbps. The device requires two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply, and all outputs are 4-mA CMOS. The device has a TTL input threshold and a noise-filter at the input that prevents transient pulses of up to 2 ns in duration from being passed to the output of the device. The ISO721 is characterized for operation over the ambient temperature range of –40°C to 125°C. (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). VCC1 1 IN 2 VCC1 3 GND1 4 Isolation D PACKAGE (TOP VIEW) 8 VCC2 7 GND2 6 OUT 5 GND2 ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) SOIC – D ORDERABLE PART NUMBER Reel of 2500 ISO721QDRQ1 TOP-SIDE MARKING IS721Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice: CA-5A Recognized under 1577 Component Recognition Program (1) File Number: 40016131 File Number: 1698195 File Number: E181974 (1) 2 Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 ABSOLUTE MAXIMUM RATINGS (1) VCC Supply voltage (2), VCC1, VCC2 –0.5 V to 6 V VI Voltage at IN or OUT terminal –0.5 V to 6 V IO Output current TJ Maximum virtual-junction temperature ESD (1) (2) (3) (4) ±15 mA 170°C Human-Body Model Electrostatic discharge rating (3) ±2 kV Charged-Device Model (4) ±1 kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms values are not listed in this publication. JEDEC Standard 22, Test Method A114-C.01 JEDEC Standard 22, Test Method C101 RECOMMENDED OPERATING CONDITIONS MIN MAX 3 5.5 (1) VCC Supply voltage IOH High-level output current IOL Low-level output current –4 mA tui Input pulse width 10 ns VIH High-level input voltage (IN) 2 VCC VIL Low-level input voltage (IN) 0 0.8 V TA Operating free-air temperature –40 125 °C TJ Operating virtual-junction temperature H External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9 certification (1) , VCC1, VCC2 UNIT V 4 See the Thermal Characteristics table mA V 150 °C 1000 A/m For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. IEC 60747-5-2 INSULATION CHARACTERISTICS (1) over recommended operating conditions (unless otherwise noted) PARAMETER VIORM VPR TEST CONDITIONS SPECIFICATIONS UNIT 560 V After Input/Output Safety Test Subgroup 2/3 VPR = VIORM × 1.2, t = 10 s, Partial discharge < 5 pC 672 V Method a, VPR = VIORM × 1.6, Type and sample test with t = 10 s, Partial discharge < 5 pC 896 V Method b1, VPR = VIORM × 1.875, 100 % Production test with t = 1 s, Partial discharge < 5 pC 1050 V Maximum working insulation voltage Input to output test voltage VIOTM Transient overvoltage t = 60 s 4000 V RS Insulation resistance VIO = 500 V at TS >109 Ω Pollution degree (1) 2 Climatic Classification 40/125/21 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 3 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 VCC1 supply current ICC2 VCC2 supply current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN at 2 V IIL Low-level input current IN at 0.8 V CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, No load VI = VCC or 0 V, No load TYP MAX 0.5 1 2 4 8 12 10 14 IOH = -4 mA, See Figure 1 VCC – 0.8 4.6 IOH = –20 µA, See Figure 1 VCC – 0.1 5 mA mA V IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 µA, See Figure 1 0 0.1 150 V mV 10 –10 15 UNIT µA 1 pF 50 kV/µs For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 5-V OPERATION over recommended operating conditions (unless otherwise noted) TYP MAX tPLH Propagation delay, low-to-high-level output PARAMETER See Figure 1 17 24 ns tPHL Propagation delay , high-to-low-level output See Figure 1 17 24 ns tsk(p) Pulse skew |tPHL – tPLH| See Figure 1 0.5 2 ns tsk(pp) (1) Part-to-part skew 0 3 ns tr Output signal rise time See Figure 1 1 tf Output signal fall time See Figure 1 1 ns tfs Failsafe output delay time from input power loss See Figure 2 3 µs 100-Mbps NRZ data input, See Figure 4 2 100-Mbps unrestricted bit run length data input, See Figure 4 3 tjit(PP) (1) 4 Peak-to-peak eye-pattern jitter TEST CONDITIONS MIN UNIT ns ns tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 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SLLS918 – JULY 2008 ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 VCC1 supply current ICC2 VCC2 supply current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN at 2 V IIL Low-level input current IN at 0.8 V CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, No load VI = VCC or 0 V, No load TYP MAX 0.5 1 2 4 4 6.5 5 7.5 IOH = –4 mA, See Figure 1 VCC – 0.4 3 IOH = –20 µA, See Figure 1 VCC – 0.1 3.3 mA mA V IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 µA, See Figure 1 0 0.1 150 V mV 10 µA µA –10 15 UNIT 1 pF 40 kV/µs For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) TYP MAX tPLH Propagation delay, low-to-high-level output PARAMETER See Figure 1 19 30 ns tPHL Propagation delay , high-to-low-level output See Figure 1 19 30 ns tsk(p) Pulse skew |tPHL – tPLH| See Figure 1 0.5 3 ns tsk(pp) (1) Part-to-part skew 0 5 ns tr Output signal rise time See Figure 1 2 tf Output signal fall time See Figure 1 2 ns tfs Failsafe output delay time from input power loss See Figure 2 3 µs 100-Mbps NRZ data input, See Figure 4 2 100-Mbps unrestricted bit run length data input, See Figure 4 3 tjit(PP) (1) Peak-to-peak eye-pattern jitter TEST CONDITIONS MIN UNIT ns ns tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 5 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 VCC1 supply current ICC2 VCC2 supply current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN at 2 V IIL Low-level input current IN at 0.8 V CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, No load VI = VCC or 0 V, No load TYP MAX 0.3 0.5 1 2 8 12 10 14 IOH = –4 mA, See Figure 1 VCC – 0.8 4.6 IOH = –20 µA, See Figure 1 VCC – 0.1 5 mA mA V IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 µA, See Figure 1 0 0.1 150 V mV 10 µA µA –10 15 UNIT 1 pF 40 kV/µs For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) TYP MAX tPLH Propagation delay, low-to-high-level output PARAMETER See Figure 1 17 30 ns tPHL Propagation delay , high-to-low-level output See Figure 1 17 30 ns tsk(p) Pulse skew |tPHL – tPLH| See Figure 1 0.5 3 ns tsk(pp) (1) Part-to-part skew 0 5 ns tr Output signal rise time See Figure 1 1 tf Output signal fall time See Figure 1 1 ns tfs Failsafe output delay time from input power loss See Figure 2 3 µs 100-Mbps NRZ data input, See Figure 4 2 100-Mbps unrestricted bit run length data input, See Figure 4 3 tjit(PP) (1) 6 Peak-to-peak eye-pattern jitter TEST CONDITIONS MIN UNIT ns ns tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 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SLLS918 – JULY 2008 ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 VCC1 supply current ICC2 VCC2 supply current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN at 2 V IIL Low-level input current IN at 0.8 V CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, No load VI = VCC or 0 V, No load TYP MAX 0.3 0.5 1 2 4 6.5 5 7.5 IOH = –4 mA, See Figure 1 VCC – 0.4 3 IOH = –20 µA, See Figure 1 VCC – 0.1 3.3 mA mA V IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 µA, See Figure 1 0 0.1 150 V mV 10 µA µA –10 15 UNIT 1 pF 40 kV/µs For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) TYP MAX tPLH Propagation delay, low-to-high-level output PARAMETER See Figure 1 20 34 ns tPHL Propagation delay , high-to-low-level output See Figure 1 20 34 ns tsk(p) Pulse skew |tPHL – tPLH| See Figure 1 0.5 3 ns tsk(pp) (1) Part-to-part skew 0 5 ns tr Output signal rise time See Figure 1 2 tf Output signal fall time See Figure 1 2 ns tfs Failsafe output delay time from input power loss See Figure 2 3 µs 100-Mbps NRZ data input, See Figure 4 2 100-Mbps unrestricted bit run length data input, See Figure 4 3 tjit(PP) (1) Peak-to-peak eye-pattern jitter TEST CONDITIONS MIN UNIT ns ns tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 7 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator (see Note A) VI 50 W VCC1 VI IO OUT VCC1/2 VCC1/2 0V tPHL VOH tPLH VO CL V (see Note B) O 90% 50% tr A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. 50% 10% VOL tf Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VCC1 0V IN ISOLATION BARRIER VI VCC1 VI OUT 2.7 V VO 0V tfs CL 15 pF ±20% VOH 50% VO VOL NOTE: VI transition time is 100 ns VCC1 IN VCC or 0V CI = 0.1 mF, GND1 ISOLATION BARRIER Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC2 OUT GND2 ±1% CL 15 pF ±20% VO VCM NOTE: Pass/fail criteria is no change in VO. Figure 3. Common-Mode Transient Immunity Test Circuit and Voltage Waveform 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 PARAMETER MEASUREMENT INFORMATION (continued) Tektronix HFS9009 Tektronix 784D PATTERN GENERATOR VCC1 In p u t 0V O u tp u t VCC2/2 J itte r NOTE: Bit pattern run length is 216 – 1. Transition Time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s. Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 9 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT L(101) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4.8 mm L(102) Shortest terminal to terminal distance across the Minimum external tracking (creepage) package surface 4.3 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112/VDE 0303 Part 1 ≥ 175 V Minimum internal gap (internal clearance) Distance through insulation 0.008 mm RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100°C >1012 Ω Input to output, VIO = 500 V, 100°C ≤ TA< TA max. >1011 Ω CIO Barrier capacitance, input to output VI = 0.4 sin (4E6πt) 1 pF CI Input capacitance to ground VI = 0.4 sin (4E6πt) 1 pF (1) Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER TEST CONDITIONS Basic isolation group Installation classification SPECIFICATION Material group IIIa Rated mains voltage ≤150 VRMS I-IV Rated mains voltage ≤300 VRMS I-III DEVICE I/O SCHEMATIC Equivalent Input and Output Schematic Diagrams Input Output VCC2 VCC1 VCC1 VCC1 1 MW 8W OUT 500 W IN 13 W 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 IEC SAFETY LIMITING VALUES Safety limiting is designed to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply, and without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum case temperature MIN MAX θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 100 θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 153 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. THERMAL CHARACTERISTICS (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Low-K (1) 263 High-K (1) 125 MAX UNIT θJA Junction-to-air thermal resistance θJB Junction-to-board thermal resistance 44 °C/W θJC Junction-to-case thermal resistance 75 °C/W PD Device power dissipation (1) VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty cycle square wave °C/W 159 mW Tested in accordance with the Low-K or High-K thermal metric definition of EIA/JESD51-3 for leaded surface-mount packages. 200 Safety Limiting Current − mA 175 VCC1, VCC2 = 3.6 V 150 125 100 75 VCC1, VCC2 = 5.5 V 50 25 0 0 50 100 150 200 o Case Temperature − C Figure 5. θJC Thermal Derating Curve Per IEC 60747-5-2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 11 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com FUNCTION TABLE (1) VCC1 PU PD (1) 12 VCC2 PU PU INPUT (IN) OUTPUT (OUT) H H L L Open H X H PU = powered up (VCC ≥ 3 V), PD = powered down (VCC ≤ 2.5 V), X = irrelevant, H = high level, L = low level Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 TYPICAL CHARACTERISTICS RMS SUPPLY CURRENT vs SIGNALING RATE RMS SUPPLY CURRENT vs SIGNALING RATE 15 10 VCC1 = 3.3 V, VCC2 = 3.3 V, o TA = 25 C, CL = 15 pF 8 VCC1 = 5 V, VCC2 = 5 V, o TA = 25 C, CL = 15 pF 14 13 ICC − Supply Current − (mARMS) ICC − Supply Current − (mARMS) 9 7 6 ICC2 5 4 3 ICC1 2 12 11 10 ICC2 9 8 7 ICC1 6 5 4 3 2 1 1 0 0 0 25 50 75 100 0 25 50 Signaling Rate (Mbps) 75 100 Signaling Rate (Mbps) Figure 6. Figure 7. PROPAGATION DELAY vs FREE-AIR TEMPERATURE PROPAGATION DELAY vs FREE-AIR TEMPERATURE 30 20 tPLH 18 tPLH 25 tPHL 16 20 15 10 VCC1 = 3.3 V, VCC2 = 3.3 V, CL = 15 pF, Air Flow at 7 cf/m 5 0 -40 -25 -10 5 20 35 50 80 65 95 Propagation Delay − ns Propagation Delay − ns tPHL 14 12 10 8 6 VCC1 = 5 V, VCC2 = 5 V, CL = 15 pF, Air Flow at 7 cf/m 4 2 0 -40 110 125 -25 -10 o 5 20 35 50 80 65 95 110 125 o TA − Free-Air Temperature − C TA − Free-Air Temperature − C Figure 8. Figure 9. INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE VCC1 FAILSAFE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE 2.92 1.4 5-V (VIT+) 2.9 1.3 3.3-V (VIT+) 1.25 1.2 Air Flow at 7 cf/m 1.15 5-V (VIT- ) 1.1 VCC1 Failsafe Voltage − V VIT − Input Voltage Threshold − V 1.35 Vfs+ 2.88 VCC = 5 V or 3.3 V, CL = 15 pF, Air Flow at 7 cf/m 2.86 2.84 2.82 Vfs- 2.8 1.05 3.3-V (VIT- ) 1 -40 -25 -10 5 20 35 50 80 65 95 110 125 2.78 -40 -25 o TA − Free-Air Temperature − C -10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − oC Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 13 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE -80 70 TA = 25 C -70 IOL − Low-Level Output Current − mA IOH − High-Level Output Current − mA o TA = 25 C o VCC = 5 V -60 -50 -40 VCC = 3.3 V -30 -20 -10 0 60 VCC = 5 V 50 40 30 VCC = 3.3 V 20 10 0 0 1 2 3 5 4 6 0 VOH − High-Level Output Voltage − V Figure 12. 14 1 2 3 4 5 VOL − Low-Level Output Voltage − V Figure 13. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 APPLICATION INFORMATION MANUFACTURER CROSS-REFERENCE DATA The ISO721 isolator has the same functional pinout as most other vendors, and it is often a pin-for-pin drop-in replacement. The notable differences in the product are propagation delay, signaling rate, power consumption, and transient protection rating. Table 1 is used as a guide for replacing other isolators with the ISO721 single-channel isolators. 6 OUT GND1 4 5 GND2 VI 2 VDD1 3 GND1 4 8 VDD2 VDD1 1 7 GND2 VI 2 6 VO * 5 GND2 3 GND1 4 IL710 8 VDD2 7 NC VDD1 1 VI 2 6 VO 5 GND2 NC 3 GND1 4 Isolation IN 2 VCC1 3 VDD1 1 Isolation 8 VCC2 7 GND2 Isolation VCC1 1 HCPL-xxxx ADuM1100 Isolation ISO721 8 VDD2 7 VOE 6 VO 5 GND2 Figure 14. Pinout Cross Reference Table 1. Competitive Cross Reference ISOLATOR PIN 1 PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 ISO721 (1) (2) VCC1 IN VCC1 GND1 GND2 OUT GND2 VCC2 VDD1 VI VDD1 GND1 GND2 VO GND2 VDD2 GND1 GND2 VO NC VDD2 GND1 GND2 VO VOE VDD2 ADuM1100 (1) (2) (3) (4) (1) (2) HCPL-xxxx VDD1 VI Leave Open (3) IL710 VDD1 VI NC (4) The ISO721 pin 1 and pin 3 are internally connected together. Either or both may be used as VCC1. The ISO721 pin 5 and pin 7 are internally connected together. Either or both may be used as GND2. Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO721, because the extra VCC1 on pin 3 may be left open circuit as well. Pin 3 of the IL710 must not be tied to ground on the circuit board, because this shorts the ISO721 VCC1 to ground. The IL710 pin 3 may only be tied to VCC or left open to drop in an ISO721. 20 mm (max) from VCC2 20 mm (max) from VCC1 VCC1 VCC2 0.1 µF Input 2 3 GND1 0.1 µF ISO721 8 1 4 7 IN OUT 6 5 Output GND2 Figure 15. Basic Application Circuit Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 15 ISO721-Q1 SLLS918 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com ISOLATION GLOSSARY Creepage Distance — The shortest path between two conductive input to output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance — The shortest distance between two conductive input to output leads measured through air (line of sight). Input-to-Output Barrier Capacitance — The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to-Output Barrier Resistance — The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit — An internal circuit directly connected to an external supply mains or other equivalent source which supplies the primary circuit electric power. Secondary Circuit — A circuit with no direct connection to primary power, and derives its power from a separate isolated source. Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials and is defined as the numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721-Q1 ISO721-Q1 www.ti.com ....................................................................................................................................................................................................... SLLS918 – JULY 2008 Insulation Operational insulation — Insulation needed for the correct operation of the equipment Basic insulation — Insulation to provide basic protection against electric shock Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation Double insulation — Insulation comprising both basic and supplementary insulation Reinforced insulation — A single insulation system that provides a degree of protection against electric shock equivalent to double insulation Pollution Degree Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence. Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation must be expected. Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs that becomes conductive due to condensation, which is to be expected. Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions. Installation Category Overvoltage Category — This section addresses insulation coordination by identifying the transient overvoltages that may occur and by assigning four different levels as indicated in IEC 60664. I: Signal Level — Special equipment or parts of equipment II: Local Level — Portable equipment, etc. III: Distribution Level — Fixed installation IV: Primary Supply Level — Overhead lines, cable systems Each category should be subject to smaller transients than the category above. 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